A Low Minimum Detectable Power, High Dynamic Range,

V-Band CMOS Millimeter-Wave Logarithmic Power Detector

Chien-Chang Chou, Wen-Chian Lai, Tzuen-Hsi Huang, and Huey-Ru Chuang
Department of Electrical Engineering,
National Cheng Kung University, Tainan, Taiwan, R.O.C

Abstract—This paper presents a V-Band logarithmic power de-

tector fabricated in 90-nm CMOS technology. The topology of RF RF
successive detection logarithmic amplifier (SDLA) is adopted for input AL AL AL AL output
high dynamic range. Instead of using traditional differential lim-
iting amplifiers, millimeter-wave (MMW) amplifiers are applied
for the gain cells to achieve the desired performance. A three-
stage SDLA test key was implemented. The measured results at
52 GHz show that the dynamic range is 50 dB and the logarith-
mic errors are within ±1.5 dB. From 50 to 62 GHz, the dynamic
range is better than 35 dB, and the logarithmic errors are within Limiting amplifier
±2 dB. The total power consumption and chip size are 20 mW Rectifier DC output
and 0.66 mm2, respectively. Compared to the previously reported (a)
millimeter-wave (MMW) power detectors, the proposed work
features a wider dynamic range and reasonably linear logarith-
mic curve response to RF input power. RF input Matching
network and Amp. #1
Matching
network and Amp. #2
Matching
network and Amp. #3
Conjugate
matching with
Index Terms—90-nm, CMOS, millimeter-wave, power detector, detector port #1 detector port #2 detector port #3 detector port #4

successive detection logarithmic amplifier (SDLA), V-band

I. INTRODUCTION
The spectrum range between 50–75 GHz (V-band) is suita-
ble for many applications including microwave radiometers,
thermal remote sensing and microwave sounding units. Espe-
cially the wireless personal network (WPAN) in unlicensed
57–64 GHz band for short-range communication is of special
interest for indoor high-speed data links [1]. Moreover, in the
recently developed millimeter-wave life detection system
(MLDS) by using waveguide components [2] and the integrat-
ed 60-GHz CMOS vital-signs radar sensor [3], a MMW power
detector is an essential component for clutter power monitor-
ing and automatic clutter cancellation. Hence, an on-chip V-
band power detector is desired to be fully-integrated in the
CMOS vital-signs Doppler sensor chip. In power detector de-
signs, diodes are widely used due to their exponential I-V be-
havior. However, the exponential transfer curve of diodes will
make power calibration difficult due to the small output volt-
age variation. The alternative for power detection is the use of
logarithmic amplifier, of which the advantage is the linear-in-
dB characteristic. The logarithmic amplifier can be imple-
mented by using different topologies, such as the operational
amplifier with trans-conductance feedback [4], the automatic-
gain control-based detector [5] and the successive detection
logarithmic amplifier [6]. In among, the successive detection
logarithmic amplifier (SDLA) [6] features a wide dynamic
range by using several limiting amplifiers and full-wave recti-
fiers to achieve piecewise linear approximation. However, the
limited bandwidth of gain cells, which lead to the dynamic
range problem with current design topology of logarithmic
detectors [7], is not easy to cover the V-band range applica-
tions of interest.
DC output
(b)
Fig. 1. Circuit block diagram: (a) the traditional successive detection loga-
rithmic amplifier, and (b) the proposed V-band logarithmic power detector.
The state-of-the-art MMW power detectors are reported in
[8]-[9]. In [8], an E-band multi-tanh power detector with 40-
dB dynamic range is presented. However, the transfer curve
linearity of DC output is not discussed and modelled. In [9], a
38 dB dynamic range and -30 dBm sensitivity are reported
with low power consumption. However, log-to-log DC trans-
fer curve will cause very small voltage difference in lower RF
input power, and resulting in the needs of high-precision DC
comparators and high-resolution analog to digital converters
(ADC’s).
To address the above problems, MMW amplifiers are
adopted for the whole gain stage in this work. Three MMW
amplification stages and four single-ended common-source
rectifiers with a voltage summation buffer are employed to
realize the SDLA. The measured results show that a V-band
logarithmic amplifier is implemented with high dynamic range,
sufficient log errors and low power consumption.
II. CIRCUIT DESIGN
A. Proposed MMW SDLA structure analysis
Fig. 1(a) shows the circuit block diagram of a traditional
SDLA, which consists of N rectifiers and N-1 gain cells. The
main principle of the SDLA is to use piecewise linear approx-
imation to get linear-in-dB function to let the gain (G) of

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 VDD 1000
1000 4
3 950 Simu. @ 52 GHz

DC output voltage (mV)

t

DC output voltage (mV)

980
2 Meas. @ 52 GHz
900

Log error (dB)

RF input To voltage summer Simu. @ 60 GHz
960 1
Meas. @ 60 GHz
t
0 850
940 -1
-2 800
920 Real curve of rectifier
Best-fit line -3
750
900 -4
-15 -12 -9 -6 -3 0
Vg RF Input power (dBm) 700

Fig. 2. (a) Schematic diagram of a rectifier, and (b) simulated dynamic range 650
600
Stage 1 Amplifier Stage 2 Stage 3 -55 -45 -35 -25 -15 -5 5
VDD1 VDD1 VDD1 VDD1 VDD1 RF Input power (dBm)
RF input
(a)
VGS1 VGS2 VGS3 VGS4 VGS5
6
5
VDD2 VDD2 VDD2 VDD2 4
3

Log error (dB)

2
1
0
-1
Vg Vg Vg Vg
Rectifier -2 Simu. @ 52 GHz
-3 Meas. @ 52 GHz
VDD3
-4 Simu. @ 60 GHz
-5 Meas. @ 60 GHz
Buffer DC output
-6
-55 -45 -35 -25 -15 -5 5
Fig. 3. Circuit schematic of the proposed V-band logarithmic power detector. RF Input power (dBm)

(b)
Fig. 5. Simulated and measured (a) DC output voltage (b) log errors.
the rectifier becomes active. It is because the rectifiers are in
shunt configuration in inter-stage matching networks to result
in additional power loss modelling as an insertion loss (IL).
Thus, the required gain of each amplification stage can be
evaluated by:
G = DRrectifier + IL . (dB) (1)

In practice, each shunt rectifier cell is designed together with

each inter-stage matching network, the matching condition of
the whole power detector will be changed and lead to the gain
Fig. 4. Chip micrograph (total chip size : 0.66mm2) .
degradation and the frequency-dependent log errors. There-
amplifiers remain as constant as possible within the dynamic fore, the optimal design of the rectifiers to minimize the inser-
range (DRrectifier) of the rectifiers. Differential limiting amplifi- tion loss is necessary.
ers are widely used as the gain cells for the SDLA. The band-
B. Design considerations of rectifiers and MMW gain cells
width of limiting amplifiers dominates the operating frequen-
cy range of the SDLA. Hence, many modified topologies of In the conventional SDLA design, limiting amplifiers are in
limiting amplifiers have been reported to enhance the band- differential operation. Hence, full-wave rectifiers are adopted
width, like in [6]. However, wideband limiting amplifiers are for handling differential output of limiting amplifiers. For rec-
usually with high power consumption, which is not suitable tifiers used in this proposed circuit design, the NMOS transis-
for low-power MMW SDLA detector designs. In this paper, tors, operated in saturation region with a single-ended com-
the circuit block diagram of our proposed MMW logarithmic mon-source configuration, are adopted. The schematic dia-
detector is shown in Fig. 1(b). The difference with the tradi- gram of a rectifier is shown in Fig. 2(a). Compared to the best-
tional topology is that the limiting amplifiers are replaced by fit linear curves, rectifiers have the linearity errors. Therefore,
MMW amplifiers. Hence, all matching conditions (including the linear response of the rectifier is an important design issue.
input, output and inter-stage matching) should be carefully As for the simulated transfer curve of the rectifier including
considered. The final gain cell is in conjugate matching with the summation buffer stage, the dynamic range (Fig. 2(b)) is
the last rectifier cell to enhance the detector sensitivity. The about 10 dB (from -10 to 0 dBm) and the log errors are within
input impedance of each amplifier stage becomes lower when ±1 dB.

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 TABLE I
PERFORMANCE COMPARISONS OF LOGARITHMIC AMPLIFIERS AND MMW POWER DETECTOR
Reference [4] [6] [7] [10] [8] [9] This Work
MTT 2008 IMS 2011 MWCL 2013 MTT 2016 EuMIC 2014 MTT 2015
Process 0.18-um 0.18-um 0.13-um 28-nm 0.13-um 55-nm 90-nm
CMOS CMOS CMOS CMOS SiGe BiCMOS CMOS
Topology OPA with trans- SDLA SDLA SDLA Different pair Common base / SDLA
conductance with RF input common gate
feedback balun detector
Bandwidth (GHz) 0.125–8.5 0.9–8 2–16 0.7–4 65–86 50–67 50–62
Center frequency (GHz) 5.5 8 < 14 16 --- 81 60 52 60
Input dynamic range (dB) 20 40 43 > 50 40 40 38 50 37
Min. detectable power (dBm) -25 -40 -35 -38 -35 -25 -30 -50 -35
Log error (dB) ±0.5 ±1 ±1 ±1.5 ±0.8 --- --- ±1.5 ±1.4
Power consumption (mW) 0.18 70 35.2 11.8 12 0.05–0.8 20
Chip size / Core size (mm2) --- / 0.013 0.98 / 0.55 0.75 / 0.45 --- / 0.15 0.504 / --- --- / 0.0064 0.66 / 0.38

III. MEASUREMENT RESULTS

1000
Meas. @ 50 GHz The proposed V-band logarithmic power detector is fabri-
950 Meas. @ 52 GHz
cated in a 90-nm CMOS process. Due to the limitation of pin
DC output voltage (mV)

Meas. @ 55 GHz
900 Meas. @ 57 GHz
numbers in the chip layout, VGS,1–VGS,5 are tied together for
Meas. @ 60 GHz
850 Meas. @ 62 GHz
doing the experiment. The total chip size including testing pad
800 is 0.66 mm2 and the core size is 0.38 mm2. The chip micro-
750 graph is shown in Fig. 4. For power detection measurement, a
700
signal generator (Agilent E8257D) is used to provide the
MMW input signal. A V-band fixed attenuator is adopted to
650
cover a lower input power level from -50 to -40 dBm. The
600 digital multimeter is used to measure the output DC voltage.
-35 -55-25 -45-15 -5 5
RF Input power (dBm) Fig. 5 shows the simulated and measured DC output voltages
Fig. 6. Measured output voltage vs. RF input power. and log errors at 52 and 60 GHz (with fixed VGS,1-5 = 0.6 V).
6 Simulation and measurement results show a reasonable
5 Meas. @ 50 GHz Meas. @ 57 GHz agreement to each other. The measured log responses and log
Meas. @ 52 GHz Meas. @ 60 GHz
4 Meas. @ 55 GHz Meas. @ 62 GHz errors from 50 to 62 GHz are shown in Figs. 6 and 7, respec-
3
tively. Table I summarizes the performance comparisons with
Log error (dB)

2
1 different reported technologies. This work achieves a lowest
0 minimum detectable power, high dynamic range and low log-
-1 error response at V-band MMW frequency. A 20-mW power
-2
-3
consumption due to the applied MMW amplifiers for the gain
-4 cells is observed for the achieved good performance.
-5
-6
-55 -45 -35 -25 -15 -5 5 IV. CONCLUSION
RF Input power (dBm)
Fig. 7. Measured log errors between the output voltage and linear-in-dB best This paper presents a successive detection logarithmic am-
fit curves. plifier (SDLA) using MMW amplifiers as the gain cells for the
As for the gain cells design, a cascade topology is adopted V-band CMOS logarithmic power detector. The power detec-
for avoiding excess gain cells. In the conventional limiting tor is successfully implemented in 90-nm CMOS with high
amplifier design, the gain is set to be equal to the dynamic dynamic ranges and low log errors, which are better than 35
range of the rectifiers. However, the gain values of MMW dB and within ±2 dB, respectively, from 50 to 62 GHz. At 52
amplifier cells are difficult to be unified due to the different GHz, the dynamic range is around 50 dB and the logarithmic
matching networks and matching loss. In the proposed circuit errors are within ±1.5 dB. The designed MMW power detector
topology, the middle gain cell is designed as a three-stage will be very useful for the applications of V-band received
common-source amplifier (as shown in Fig.3). signal strength indication, automatic-level control, and auto-
matic-gain control.

644 978-1-5090-6360-4/17/$31.00 ©2017 IEEE

 ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation
Center (CIC), Hsinchu, Taiwan, for supporting the TSMC
CMOS process and chip implementation.
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