IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO.
12, DECEMBER 2012 2241
Synthesis and Array Processor Realization of a 2-D
IIR Beam Filter for Wireless Applications
Rimesh M. Joshi, Student Member, IEEE, Arjuna Madanayake, Member, IEEE, Jithra Adikari, Member, IEEE,
and Len T. Bruton, Fellow, IEEE
Abstract—A broadband digital beamforming algorithm is
proposed for directional filtering of temporally-broadband
bandpass space-time plane-waves at radio frequencies (RFs).
The enhancement of desired waves, as well as rejection of un-
desired interfering plane-waves, is simulated. A systolic- and
wavefront-array architecture is proposed for the real-time imple-
mentation of second-order spatially-bandpass (SBP) 2-D infinite
impulse response (IIR) beam filters having potential applications
in broadband beamforming of temporally down-converted RF sig-
nals. The higher speed of operation and potentially reduced power
consumption of the asynchronous architecture of wavefront-array
processors (WAPs) in comparison to the conventional synchronous
hardware has emerging applications in radio-astronomy, radar,
navigation, space science, cognitive radio, and wireless com-
munications. Further, the bit error rate (BER) performance
improvement along with the reduced computational complexity
of the 2-D IIR SBP frequency-planar digital filter over digital
phased array feed (PAF) beamformer is provided. A nominal
BER versus signal-to-interference ratio (SIR) gain of 10–16 dB
compared to case where beamforming is not applied, and a gain of
2–3 dB at approximately half the number of parallel multipliers
to digital PAF, are observed. The results of application-specific
integrated circuit (ASIC) synthesis of the digital filter designs are
also presented.
Index Terms—Array processors, bit error rate (BER), digital
phased array feed (PAF), field-programmable gate array (FPGA),
multidimensional digital filters, spatial modulation, systolic, wave-
front, wireless.
I. INTRODUCTION
U LTRA-WIDEBAND (UWB) wireless communications
[1]–[4], cognitive radio [5]–[8], cooperative wireless
sensor networks [9], [10] require highly directional and elec-
tronically steerable smart antenna arrays capable of broadband
plane-wave (PW) filtering at RFs to improve the bit-error
rate (BER) caused due to interference from multiple users
Manuscript received May 25, 2011; revised September 05, 2011; accepted
October 13, 2011. Date of publication January 13, 2012; date of current version
August 02, 2012.
R. M. Joshi and A. Madanayake are with the Department of Electrical and
Computer Engineering, University of Akron, Akron, OH 44325-3904 USA
(e-mail: rmj17@uakron.edu; arjuna@uakron.edu).
J. Adikari is with the Department of Electrical and Computer Engi-
neering, University of Waterloo, Waterloo, ON N2L 3G1, Canada (e-mail:
jithra.adikari@uwaterloo.ca).
L. T. Bruton is with the Department of Electrical and Computer Engineering,
University of Calgary, Calgary, AB T2N 1N4, Canada (e-mail: bruton@ucal-
gary.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2011.2174167
1063-8210/$26.00 © 2012 IEEE
and multipath fading. These antenna arrays typically employ
beamforming using analog delay-and-sum networks, fractional
delay based delay-and-sum digital networks [1], digital phased
array feeds (PAFs) [11]–[13] and multi-dimensional finite-im-
pule response/infinte impulse response (FIR/IIR) digital filters
[5], [14]. Digital signal processing (DSP)-based broadband
smart antenna arrays have potential applications in UWB
wireless communications [1], [2], [15], cognitive radio [5]–[8],
software-defined radio [16], microwave imaging [17], space
science and radio astronomy [18]–[21], remote-sensing and
navigation [22], [23].
The systolic-array and scanned-array implementation of
2-D and 3-D IIR broadband frequency-planar filters for digital
beamforming have been proposed in [25]–[27]. These filters
are highly suitable for high-speed filtering of broadband ST
PWs based on their direction of arrivals (DOAs). For example,
a 2-D IIR beam filter has recently been practically verified for
balanced antipodal Viraldi antennas (BAVAs) [3], [28] using
non-real time software algorithms.
We propose a second-order 2-D IIR digital filter for the
directional enhancement of temporally-broadband bandpass ST
PWs [5], [29] (see Fig. 1). It is shown that the filter operates
at an intermediate frequency (IF) leading to lower-speed VLSI
circuits. We show that the proposed filters have lower computa-
tional complexity compared to the conventional delay-and-sum
beamformers (approximately 70% less number of multipliers
for similar performance [30], [31]) and are also of lower circuit
complexity compared to 2-D FIR beamformers such as fan
and trapezoidal filters [29], [32]–[34]. The lower computa-
tional complexity, closed-form design approach, broadband
performance, electronic steerability, and availability of rapidly
reconfigurable programming logic realizations make these
emerging 2-D ST digital filters attractive and promising for
cognitive radio applications [5]–[8].
A massively-parallel systolic-array and wavefront-array
architectures are proposed for the real-time VLSI implemen-
tations of the proposed digital filter. Systolic-array processors
are well-known for the implementation of real-time high
throughput beamforming algorithms [35]–[37]. These pro-
cessors have arrays of identical processors which are highly
modular, regular and highly interconnected, making them
suitable for VLSI realizations for high speed, especially RF,
applications [38].
This paper presents the BER performance of a second-order
2-D IIR spatially-bandpass (SBP) beam filter [39] and compares
with that of a digital PAF beamformer for a 16-element uni-
form linear array (ULA). The asynchronous implementations
2242 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012

which seek to address the design complexities, power consump-

tion and timing issues affecting modern digital circuits [40],
is also explored here by extending the direct-form-I realiza-
tion of a second-order 2-D IIR SBP beam filter using novel
clock-free asynchronous quasi delay insensitive (a-QDI) logic
devices [40]. The removal of the global clock in the design
leads to reduction in design complexity, lower chip area, lower
power consumption, and increased speed of operation compared
to the synchronous implementations [40]. The wavefront-array
[41]–[43] a-QDI architecture of the second-order IIR filter is
implemented on a Speedster SPD60 asynchronous field-pro-
grammable gate array (FPGA) from Achronix Semiconductor
[44], which uses so-called picoPIPE acceleration technology
[44], [45] to deliver an improved speed performance.
Consider a time varying signal propagating in the far field
in the 3-D space . This signal can be approximated
by a 4-D ST PW signal [46] which is of the form
given by

(1)

where is the unit vector specifying the DOA in

the 3-D space ,
is the 1-D temporal intensity function in the DOA and
ms is the speed of propagation. When a 4-D
continuous ST PW signal is received by a ULA of sensors,
spaced apart, it reduces to the 2-D ST PW signal
with spatial DOA defined by the angle between the normal
to the -axis and the normal to the 2-D wavefront as shown in
Fig. 1, where and . The time-synchro- Fig. 1. Second-order 2-D IIR spatially-bandpass digital beam filter for asyn-
nously sampled 2-D ST PW, sampled every seconds using chronous FPGA implementation [24] showing ULA of BAVAs [3] and SC block
an array of analog-to-digital converters (ADCs) clocked at at each antenna (consisting of LNA, local oscillator for down-conversion, LPF
for image rejection and ADC). The outputs from the SC blocks are fed to an
Hz, represented by [47] is given by asynchronous FPGA implementing an array of PPCMs (described in detail in
Figs. 8 and 10) for filtering a plane-wave having desired DOA ,
. Here, the uncertainty in the DOA is indicated by angle .

(2)
of interfering signals having DOAs , .
where and in the continuous domain, Therefore, the undesired signal can be expressed as
and represent desired ST PW and undesired inter-
ferences from multi-users with additive noise.
Let us consider Gaussian modulated cosine (GMC) signals
given by
(5)
(3)

where is the carrier frequency and is a constant which

is chosen such that the signal has the required bandwidth II. 2-D IIR SBP BEAM FILTER
(double-sided bandwidth is ). Therefore, the desired 2-D ST The second-order 2-D IIR SBP digital beam filter [39] has
PW signal is given by been proposed for implementation in RF smart antenna appli-
cations for filtering temporally-broadband bandpass signals ob-
tained from a down-converted (or bandpass sampled [48]) array
of antennas. These 2-D IIR filters have possible new applica-
(4) tions in wireless communication base-stations [49] due to their
high directional selectivity and temporal broadband nature, as
where is the DOA of the desired PW. well as being fully steerable and free from fractional delays.
Similarly, the undesired signals at the communication re- The digital implementation of the second-order 2-D IIR SBP
ceivers often contain noise and interference from frequency-planar filter is shown in Fig. 1. The broadband PWs
other signals. Let us denote be the number received by the linear array of sensors are low-noise amplified
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER 2243

C. Second-Order 2-D IIR SBP Beam Filter

The 2-D IIR SBP beam filter is an extension of a 2-D IIR
broadband frequency-planar filter [25] for carrier modulated
signals, capable of selectively enhancing broadband PWs
depending on their DOAs. The transfer function (TF) of a 2-D
IIR frequency-planar beam filter [25] based on a first-order
resistively terminated passive prototype network which are
practical bounded-input-bounded-output (P-BIBO) stable [50],
[51] is given by

(7)
Fig. 2. (a) 2-D frequency-domain ROS of the broadband bandpass plane-wave
and (b) the ROS of the plane-wave following down-conversion and down sam- where
pling, where spatio-temporal DOA (normalized to
).
(8)
(LNAd), bandpass filtered (BPFd), synchronously down-con-
verted to baseband and low pass filtered (LPFd), uniformly and for ; , and sets the selectivity of the
synchronously time-sampled and amplitude-quantized and then filter.
finally digitally processed using the 2-D IIR SBP beam filter. The 2-D frequency response of the IIR beam filter (7) has
Alternatively, we could employ bandpass sampling at the LNA a ROS along a line centered on the origin of 2-D frequency
output using a BPF, thereby removing the need for down-con- axis. The IF broadband beamforming applications, on the other
version [48]. hand require beam shaped 2-D passbands centered on a partic-
ular spatial frequency other than the 2-D frequency origin
A. ROS of the Space-Time Plane-Wave (0,0) (as in the case here for GMC PW signal). The TF of the
second-order 2-D IIR SBP filter [39] in partially separable form,
The region of support (ROS) of the 2-D frequency re- described later in (10), can therefore be obtained by applying
sponse of the ST PW lie along a line oriented at an angle spatial modulation to the impulse response of (7) multiplying
, passing though the center of the impulse response by , where is the desired
the 2-D space-time frequency , where and spatial shift from the center of the 2-D frequency spectrum [14],
are spatial and temporal frequencies, respectively [50]. [39].
The angle is referred to as the spatio-temporal Let be the impulse response of the
(ST) DOA of the PW. If there is certain uncertainty in the filter (7). Applying spatial modulation on the impulse response,
spatial DOA of the PW, say , then the 2-D ROS of the ST PW we get the desired impulse response of the spatially modulated
occupies a trapezoidal region as shown in Fig. 2, where is 2-D IIR filter
the variation in spatio-temporal DOA due to the uncertainty in
the spatial DOA . The temporal downsampling by a factor of (9)
causes the ST DOA to change to an angle given by
[29] -
Let be the TF of the
desired filter.
(6)
Using the linear system of modulated -transforms,
-
The trapezoidal ROS [29] of the broadband ST PW following for [48], where
-
down-conversion and down-sampling is shown in Fig. 2, where and , after
[39] is the spatial shift in the simplification, we obtain the TF of the second-order 2-D IIR
frequency of the PW (4). SBP frequency-planar beam filter [39] as

(10)
B. Shape of the 2-D Filter Passband
A double-trapezoidal 2-D FIR filter has been proposed in [5], for , and where
[29] for filtering temporally-broadband bandpass PWs (shown
in Fig. 2). These FIR filters achieve high performance direc-
tional enhancement of band-limited signals but are of very high (11)
order (typically 32 [5]), leading to a higher circuit complexity
compared to the proposed IIR counterparts.
The 2-D IIR ST digital beam filter encompasses the desired -
trapezoidal passband of the PW centered on as Here, 2-D discrete input
-
shown in Fig. 2(b), while achieving a much lower computational and 2-D discrete output ,
complexity compared to the FIR filters [5]. where , .
2244 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012

Fig. 4. 2-D magnitude frequency response of input signal containing desired

signal having spatial DOA 30 and two other interfering waves having DOAs
Fig. 3. Magnitude frequency response of second-order 2-D IIR SBP beam filter 10 and 60 .
for , , and . Here, is given by (6).

Therefore, the complete TF of the second-order 2-D IIR SBP

filter is given by

(12)
The filter coefficients and as computed in [14], [39]
are given by

Fig. 5. 2-D magnitude frequency response of the filtered output signal showing
the directional enhancement of the desired PW.

Therefore, the signal received (2) by the ULA (considering a

noise-free case for simplicity) is given by

(14)

(13) where
where we express the filter coefficients in terms of required
statio-temporal DOA (after down-sampling) and beam-width
(selectivity). Here, is the desired spatial frequency
shift from the origin of the 2-D frequency spectrum. and is the sample delay. The received signal (14) is
The magnitude frequency response of the second-order 2-D down-converted using oscillators at 1 GHz, low-pass
IIR SBP beam filter [39] as given by the TF (12) is shown in filtered for image rejection and down-sampled before feeding
Fig. 3, which encompasses the trapezoidal ROS of the desired the signal to the filter. Here, a down-sampling factor of
down-converted down-sampled (DCDS) PW shown in Fig. 2. is used which reduces the required clock frequency to
500 MHz , expanding the baseband
III. VERIFICATION: AN EXAMPLE OF BROADBAND spectrum of the input signal by 5 times as shown in Fig. 4.
INTERFERENCE REJECTION The 2-D magnitude frequency response of the resulting output
Let us consider a element ULA and a partially- signal from the second-order 2-D IIR SBP filter is shown in
broadband GMC PW signal (3) with amplitude Fig. 5 which shows the directional enhancement of the PW
at a carrier frequency of having spatial DOA having DOA , while suppressing PWs with other
, the single-sided bandwidth 250 MHz (double-sided DOAs.
bandwidth 500 MHz) and sampling frequency The temporal cross-correlation of the input and output signals
2.5 GHz. The chosen PW signal has a fractional with a reference Gaussian wave representing the ideal desired
bandwidth (FBW) of (50%). signal is shown in Fig. 6, which demonstrates the directional
Two other interfering PWs identical to the desired PW, except enhancement capability of the 2-D IIR digital beamformer. Ob-
for their spatial DOAs and , are consid- serve that PWs with DOA 10 and 60 have been attenuated
ered for the verification of the rejection of the undesired PWs. by 40 and 38.4 dB respectively, enhancing the PW with desired
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER 2245

Fig. 6. Temporal cross-correlation of the input signal (dashed line) and the fil-
tered output signal (solid line) with a reference Gaussian pulse showing the at-
tenuation of undesired signals.

DOA. This verifies the ideal performance of the 2-D IIR SBP
beam filter.
Fig. 7. Phased-array delay-sum beamformer implementation illustrating
IV. REVIEW OF DIGITAL PHASED ARRAY FEED BEAMFORMER transformation of the data at each sensor into frequency domain along with the
weighted combinations.
The delay-and-sum beamformer is based on the concept that
if we have a ULA with broadband antenna elements, then the output of each sensor is phase shifted prior to summation
the output of sensor at is differing only by a time [31].
delay . Therefore, if the output of each antenna is de- The time domain output of the digital delay-and-sum beam-
layed appropriately (with proper weight vector [31] applied) and former is given by
summed together, the effective radiation pattern of the array is
reinforced in the desired direction while suppressing the waves (17)
coming from other directions [31], [52].
The continuous-time output of the delay-and-sum beam-
former is given by [30], [47], [52], [53] where is the sampling period of the ADCs at each
sensor and is the spacing between the sensors
satisfying the Nyquist criterion [25].
(15)
The 1-D discrete Fourier transform (DFT) of (17) is given by

where (18)

(16)
where , are
the bin frequencies for the -point fast Fourier transform
and is the spatial DOA of the desired PW as shown in Fig. 7.
(FFT).
The delay-and-sum beamformer can be implemented in both
The digital PAF implementation for filtering a par-
time and frequency domain [54]. In time domain, the beam-
tially-broadband GMC PW is shown in Fig. 7. The phase
former works by performing time-based delay and sum opera-
compensation required at RF (before down-conversion) for
tions, delaying the incoming signal from each array element by
each FFT bins of the sensors for the beamformer is given by
a certain fractional amount of time and then finally adding them
together. The time domain beamformer requires fractional de-
(19)
lays, the digital implementation of which require accurate ap-
proximation of the fractional delays leading to high computa-
tional complexity of the digital fractional-delay based delay- The baseband frequency after down-conversion and down-
and-sum beamformer [14]. The temporal-frequency do- sampling becomes , where is the carrier
main delay-and-sum beamformer, on the other hand, applies frequency and is the down-sampling factor, while the phase
different complex phasor multipliers to each fre- remains the same as in RF
quency bin of the 1-D frequency response of the signal from
each sensors. The beamformer is steered to a specific direction (20)
by selecting appropriate phases for each sensor. The resulting
array and beamformer is termed a PAF beamformer [11] since where ; .
2246 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012

The 1-D frequency response of the output of the digital PAF

is therefore given by

(21)

Expressing the output frequency response in terms of fre-

quency bins and complex multiplier coefficients, we get

(22)

where

(23)
The time domain output of the digital PAF beamformer can be
obtained by taking the inverse fast Fourier transform (IFFT) of
(22). The frequency of operation of the -point digital PAF
beamformer circuit has been reduced from sampling frequency
to .
The BER performance of the digital PAF beamformer for a
GMC partially broadband PW and its computational complexity Fig. 8. Block diagram of a PPCM of the second-order 2-D IIR SBP beam filter
is compared with the proposed second-order 2-D IIR SBP beam with the CP shown. The block marked is reused in multiple realizations of
PPCMs with different CPs.
filter in Section VII.
as shown in Fig. 9. This leads to the systolic-array processor
V. HARDWARE ARCHITECTURE OF THE SECOND-ORDER 2-D implementation [35], [36] in which the 2-D non-separable
IIR SBP BEAM FILTER filter is implemented using an array of PPCMs and
The proposed filter having closed-form coefficients (13) can the separable 1-D component is imple-
be implemented in digital VLSI hardware employing the differ- mented trivially using a delay buffer and adder at the output of
ence equation, which is obtained by inverse 2-D -transform of . The normalized 2-D space-time difference equation
(12) under zero initial conditions (ZICs), and given by for the implementation of
is given by

(25)
Normalized to (24)

The architectural block diagram for implementing (24) in
direct-form-I implementation using a systolic interconnection
(see Fig. 1) of parallel processing core modules (PPCMs) is
shown in Fig. 8. A cascaded interconnection of the PPCM
blocks lead to the desired massively-parallel array proces-
sors for real-time RF throughputs. It should be noted that
the number of PPCMs for the filter circuit should equal the
number of sensors used in the implementation. Systolic-array
implementations allow a throughput of one frame per clock
cycle (OFPCC), unlike the throughput of one pixel per clock
cycle (OPPCC) in scanned-array implementations [25], [27].
Concurrent architectures for 2-D digital IIR filters proposed
in [38] utilize 1-D block processing for raster-scanned image
processing, and are suitable for video processing applications.
The modified direct-form-I implementation of the filter TF
(10) in partially-separable form, achieves lower computational
complexity in terms of number of adders in the design (13
adders compared to 19 adders in direct-form-I implementation)
The final filtered 1-D output signal using the modified direct-
form-I implementation of the filter is obtained by feeding the
output of the last PPCM in the array through a 1-D FIR filter
having TF and is given by
(26)
VI. SPEED OPTIMIZATION OF THE ARRAY PROCESSOR
The feed-forward path of (24) can be pipelined by adding
first-input first-output (FIFO) blocks in between combinational
logic blocks in order to increase the speed of operation of the
filter. Likewise, look-ahead (LA) optimization can be applied
for pipelining the feedback paths [55].
A. Intra- and Inter-PPCM Pipelining
The PPCMs can be pipelined in order to obtain critical paths
(CPs) equal to that of a single multiply operation. The intra-
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER 2247

Let us define 1-D -transforms

Therefore, (12) can be expressed in the form

(27)

where is the temporal feedback loop shown in Fig. 8

Fig. 9. Block diagram of a PPCM in modified direct-form-I implementation,

where is the temporal feedback loop as shown in Fig. 8.

PPCM pipelining consists of FIFO buffers in between the com-

binational logic blocks in the feed-forward signal paths
, , , and . double poles at
The pipelining latency for all the feed-forward paths is as
shown in Fig. 8. The depth of pipelining is increased until the
CP is determined by the temporal feedback loop in the PPCM.
The CP for the temporal feedback loop can also be reduced to
a single multiply operation using deep intra-PPCM pipelining
using LA discussed in Section VI-B.
The intra-PPCM pipelining of latency is complemented
by inter-PPCM pipelines, obtained by inserting FIFO buffer of
length at the inputs and . Similarly, FIFO buffer
of length at the inputs and length at the inputs
, . The pipeline compensation FIFO buffers
are also placed at the outputs of the PPCMs for aligning the
output of the 2-D filter.
B. Look-Ahead to 2-D Circuits
LA is an optimization technique for clocked 1-D IIR digital
filters in VLSI circuits [55]. In this paper, LA optimization tech-
niques for higher order IIR filters such as clustered LA (CLA)
and scattered LA (SLA) [25], [55], usually used for synchronous
logic, is used for the novel application in asynchronous feedback
loops. This helps reduce the critical path delay (CPD) by intro-
ducing extra pipelining stages in the feedback path, thereby in-
creasing the speed of operation. The original systolic-array im-
plementation of the 2-D IIR SBP beam filter is now converted
to a fully asynchronous massively-parallel processor architec-
ture, as shown in Fig. 1, where number of PPCMs are inter-
connected via FIFO pipelines, in order to realize the recursive
computation of the difference equation. Such asynchronous par-
allel processors are known as WAPs [41]–[43].
The 1-D LA optimization technique for higher-order TF [55]
has been extended here to the 2-D case despite the non-sepa-
rability of the input-output TF given in (12). The wavefront-
array implementation of the 2-D IIR filter, using interconnected
PPCMs, however allows 1-D LA optimization of non-separable,
practical-BIBO stable multi-dimensional filters [25], [39].
The second-order TF in (27) has double zeros at and
(since and
). Here, as given by (8) ensuring the poles are
within the temporal frequency unit circle , satisfying
the 1-D digital stability criteria [48]. The PPCMs are identical
to each other and have the same second-order TF which can be
optimized for speed using 1-D LA for higher order IIR filters.
1) Clustered LA Optimization: CLA pipelining [55] is based
on the addition of cancelling poles and zeros to the TF (27)
such that the coefficients of in the denomi-
nator of TF are zero for a -stage CLA pipelining. The output
of (24) can then be written in terms of two past out-
puts and for a second-order
filter, leading to a loop consisting of delay elements and a
single multiplication operation. The CLA pipelining of certain
order/delay could produce an unstable filter even if
the original filter (without LA) was stable at the first place. But,
it has been shown that CLA produces a stable filter at some crit-
ical delay such that the stability is assured for
[55]. So, if the desired CLA pipeline order does not produce
a stable filter, it should be increased to an order until a stable
filter is obtained [55].
a) CLA of Order 2 [24]: Multiplying both numerator and
denominator of (27) by , we get
(28)
where ; .
The single-delay feedback path of the feedback loop implied
by (12) which has a CP of multiply-then-add operation as
shown in Fig. 2 has now been reduced to a single multiplier
because of the additional delay it added to the feedback path,
thereby reducing the CP from
to [55]. In practice,
.
b) CLA of Order 3 and Higher [24]: The 3-stage CLA
optimized TF can be obtained by multiplying both numerator
2248 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012

where , are poles of . Here, .

The -stage SLA optimized TF can be described by [55]

(32)

It can be shown from (32) that 2-stage SLA leads to

(33)

Similarly, the 3-stage SLA optimized is given by

(34)

VII. FILTER PERFORMANCE IN A WIRELESS

COMMUNICATION SYSTEM
The multipath and interference suppression capabilities of
the 2-D IIR frequency-planar beam filter [25] in a multi-user
Fig. 10. CLA optimized PPCM hardware architectures of 2-D IIR spatially- environment has been described in [4] with potential applica-
bandpass beam filter in direct-form-I realization of stages 2, 3, and 4 corre-
sponding to (28)–(30), respectively [24]. For brevity, block is described in tions in UWB communication systems. Here, the performance
Fig. 8. of the second-order 2-D IIR SBP beam filter [39] for varying
levels of interferences was evaluated by conducting BER simu-
and denominator of (27) by and is given lations involving the filter and the element ULA. The
by ability of the filter to reject the undesired multi-user interfer-
ences and improve the signal-to-interference ratio (SIR) of the
(29) desired signal was assessed and the result was compared with
the delay-and-sum beamformer (implemented as a digital PAF
in the frequency-domain) and the non-beamformer case. The re-
where and . sult showed reduction in BER relative to both digital PAF beam-
This leads to an ideal CP of former (of similar computational complexity) and non-beam-
[55]. Similarly, multiplying both numerator and denominator former implying potential applications in wireless communica-
of (27) by , we get the LA tion basestations.
optimization of order given by A series of Monte Carlo simulations of the 2-D IIR SBP
frequency planar filter and the digital PAF beamformer were
(30) carried out for element sensor array. The test signal
considered here was a partially-broadband GMC pulse (3). The
where and , which composite signal received by the sensors constituted one desired
allows four levels of pipelining within the loop, leading to an PW with spatial DOA and four other interfering identical
ideal CP of [55]. partially-broadband PWs with spatial DOAs to which are
The resulting signal flow graphs (SFGs) of three 2-D IIR SBP bi-phase modulated (BPSK modulation) by random streams of
filter hardware circuits after implementing CLA optimization of data bits [49].
stage 2, 3, and 4, respectively are shown in Fig. 10 (stage 5 CLA The composite partially-broadband PW signal received by
not shown). the sensor array was first down-converted to intermediate base-
2) SLA Optimization: SLA pipelining [55] requires the de- band, then low-pass filtered for image rejection, down-sampled
nominator of the TF (27) to be transformed in a way that it con- and then finally applied to the 2-D IIR SBP beam filter to get
tains two terms and . The output of (24) the desired signal at the output. The resulting DCDS signal from
can then be written in terms of two past outputs each sensor is given by [15], [49]
and for a second-order filter. SLA optimization
always leads to stable realizations, provided that the original TF (35)
is BIBO stable.
We can express from (27) as
where is the total number of users, is the total
(31) number of symbols, is the number of samples per symbol
and is the random data streams for modulating
the input signals, . represents the
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER 2249

Fig. 11. BER curve for varying levels of SIR for different beamforming cases Fig. 12. BER curve for varying levels of SIR for different beamforming cases
for and . for and .

desired signal, while and represents the unde-

sired interference from other users. is the additive white
Gaussian noise (AWGN), at a level 18 dB relative to the
received signal, modeled for the effect of quantization noise at
the ADCs.

A. BER Simulation Example

Let us consider a 16-element ULA and a partially-broad-
band GMC PW signal (3) at a carrier frequency of 1
GHz having desired spatial DOA with the single-
sided bandwidth 500 MHz double-sided bandwidth
1 GHz (such that ). Let us consider four
other interfering identical partially-broadband PWs with spa-
tial DOAs to as 20 , 50 , 65 , and 80 , respectively.
Let us choose a sampling frequency of 3 GHz satis-
fying the Nyquist sampling frequency , a
down-sampling factor of reducing the clock frequency
to 1 GHz (which is equal to , allowing
the implementation at a lower clock frequency), and
samples per symbol having a bit rate of 50 Mbps. For Fig. 13. BER curve for varying levels of SIR for different beamforming cases
the detection, we used a cross-correlation detector at the output for and .
of the beam filter which is at the spatial location , while
the cross-correlation detector for the non-beamformer case was The BER performance of the IIR filter for a PW of 100%
used at the first sensor location . FBW but with different desired spatial DOAs 50 and 65 is
To compare the performance of the second-order 2-D IIR shown in Figs. 12 and 13, which shows almost similar perfor-
SBP filter against the conventional phased array beamformer, mance of the 2-D IIR filter compared to 8-point FFT digital PAF,
the simulations for the same number of element (i.e., 16 el- but a gain of 2 dB compared to the 4-point FFT digial PAF for a
ement) digital PAF beamformer (described in Section IV) for BER of . For the case of desired PW spatial DOA of 50 ,
-point and 8-point FFT were carried out. The simulated the interferers were chosen to have the spatial DOA of 20 , 35 ,
BER versus SIR plot for PW having FBW of 100% with de- 65 , and 80 . Likewise, the interfering PWs were chosen with
sired spatial DOA is shown in Fig. 11. It is observed spatial DOA of 20 , 35 , 50 , and 80 for a desired spatial DOA
from the figure that the gain due to second-order 2-D IIR SBP of 65 .
digital filter is approximately 17 dB compared to the non-beam- Similar sets of simulation for desired DOAs of 35 , 50 , and
forming case, while a gain of 4.5 and 4 dB compared to 4-point 65 were carried out for PWs having FBW of 50% ( 250
and 8-point FFT digial PAFs respectively for a BER of . MHz, 1 GHz at ). The corresponding BER
2250 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012

Fig. 14. BER curve for varying levels of SIR for different beamforming cases
Fig. 16. BER curve for varying levels of SIR for different beamforming cases
for and .
for and .

It is observed from Table I that as the desired DOA angle in-

creases, the gain of the beamformer reduces because of the high
steering angle of the beamformer which increases the warping
effect of the 2-D IIR beam filter [25]. On the other hand, the
BER performance of the beamformer is better for PWs having
smaller fractional bandwidth.
The BER for various practical combinations of finite internal
word lengths and ADC precisions for 2-D IIR beam filters with
TF (7) have been investigated in [56]. But here, for the pro-
posed second-order 2-D IIR SBP beam filter, the internal pre-
cision level of the processors have been chosen large enough
such that the effects on BER due to internal quantization noise
is negligibly small. The effects of lower precision on BER of
the proposed 2-D IIR SBP filter due to quantization effects is
therefore a topic for future research work.

Fig. 15. BER curve for varying levels of SIR for different beamforming cases
for and . beam filter [39] requires 13 multipliers per PPCM as described
versus SIR plots for various cases of beamforming (for PWs
with ) are shown in Figs. 14–16. From Fig. 14, it
is observed that the gain of the 2-D IIR filter is about 17 and 1
dB compared to non-beamformer and 4-point/8-point FFT dig-
ital PAF, respectively for a BER of . The BER performance
for PW with desired DOA of 50 and as shown in
Fig. 15 is similar to the case where and . tiplication and five real additions. Therefore, a 4-point FFT dig-
Whereas, the performance of the 2-D IIR filter for PW with de-
sired DOA of 65 at FBW of 50%, as shown in Fig. 16, is ob-
served to be similar to both 4-point and 8-point digital PAFs.
The gain of the beamformers for a bit error rate of , for
various cases of fractional bandwidth and desired DOA angle
described above is shown in Table I. The table clearly shows an
improved BER performance due to the 2-D IIR SBP beam filter.
B. Computational Complexity
The computational complexity of a circuit directly depends
on the number of adder and multiplier blocks it requires. The
direct-form implementation of the second-order 2-D IIR SBP
in Section V, totaling 208 multipliers for a 16-element ULA.
The digital PAF beamformer as described in Section IV requires
additional complex multipliers along with multi-
pliers for a -point FFT [48], per each element. The conven-
tional method of complex number multiplication requires four
real multipliers and two real additions. Note that the Gauss com-
plex multiplication algorithm [57] requires only three real mul-
ital PAF beamformer requires multipliers
per element.
The computational complexity in terms of the number of
multipliers for the above-mentioned beamformers is shown in
Table II, which shows that the second-order 2-D IIR SBP filter
has a better BER performance compared to the 4-point FFT
digital PAF with similar computational complexity. Whereas,
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER
TABLE I
BEAMFORMER GAIN FOR A BER OF FOR DIFFERENT CASES OF DESIRED DOA AND FRACTIONAL BANDWIDTH
TABLE II
NUMBER OF MULTIPLIERS PER EACH SENSOR FOR DIFFERENT BEAMFORMERS
the digital PAF beamformer implementing 8-point FFT has
a much higher computational complexity compared to the
2-D IIR SBP beam filter, but with a slightly poor or a similar
BER performance. A 2-D FIR trapezoidal filters [5] for fil-
tering temporally-broadband bandpass signals have very high
interference rejection ability but at a cost of larger number
of multipliers in the design. The 2-D IIR SBP beam filter,
on the other hand, still provides a significant reduction in the
interference signal with less number of multipliers and provides
a better BER performance compared to digital PAFs of similar
computational complexities.
VIII. ASYNCHRONOUS LOGIC REALIZATION
WITH ACHRONIX FPGA
FPGAs from Achronix Semiconductor [44] which employ
a-QDI logic [45] facilitate asynchronous implementation of
conventional circuits. The removal of the global clock in a-QDI
circuits result in reduced design complexity, lower power
consumption and higher speed of operation [40]. The clock in
a-QDI implementation using Achronix FPGA refers to the clock
present at the synchronous input/output (I/O) frame (as shown
in Fig. 1) which consists of synchronous to asynchronous con-
verters at the input and asynchronous to synchronous converters
at the output. Therefore, the design register transfer level (RTL)
does not need to be targeted to picoPIPE technology and is the
same for conventional synchronous implementations. It is the
core fabric of the Achronix FPGA that performs the a-QDI
implementation. The core contains large number of fine-grain
pico-pipeline stages called “picoPIPE” used for both logic and
routing [44], [45], which lead to high-throughput architectures.
Unlike in synchronous circuits where the global clock is used
to sequence the computation and for synchronization, the
sequencing and synchronization in asynchronous circuits are
achieved using local handshake protocol between adjacent
pipeline stages. Data are passed through the pipeline stages as
messages called “data tokens”. A three wire channel (two data
wires and one enable wire) is present in between the pipeline
stages which consists of “wire 0”, “wire 1”, and “enable” [40].
The data tokens are encoded in the wires such that setting “wire
0” represents “logic 0” and setting “wire 1” represents “logic
1”, while resetting both wires represent “no-data” state. The
third wire is an acknowledge signal used for the asynchronous
handshake protocol. The handshake protocol employed by the
a-QDI logic consists of the following four phases [40]:
2251
1) the sender sends the data by setting one of the data wires;
2) the receiver latches the data and lowers the “enable” wire;
3) the sender lowers all data wires;
4) the receiver raises the “enable” wire when it is ready to
accept new data.
The time required to complete one four-phase handshake is
referred to as cycle time of a pipeline stage and the inverse of
the cycle time represents the throughput which gives
the rate at which tokens travel through the pipeline, provided
the dataflow netlist is free from loops and reconvergent paths
[58]. Since the pipeline stages can contain a “no-data” state
along with conventional “logic 0” and “logic 1”, pipelining the
dataflow path does not affect the functionality of the design,
causing these a-QDI pipelines to be “slack elastic” [40], which
is in contrast to the conventional synchronous designs. When
pipeline stages are inserted they are initialized to “no-data” state
at global reset, whereas actual registers defined in RTL design
are initialized to either “logic 1” or “logic 0” based on the de-
scription.
The two constraints that determine the final operation speed
of a-QDI circuits are loops and reconvergent paths [58]. A loop
is a feedback path in the dataflow. IIR filter circuits such as the
proposed 2-D IIR SBP filter contains loops in the design. If loop
is the critical path, as in our case, the frequency of operation is
, where is the number of initialized
tokens within the loop and is the entire loop delay. In-
creasing causes increase in the speed of operation. A recon-
vergent path occurs in a fan-in node where one of the path has
fewer pipeline stages (shorter path) than the other (longer path).
In this situation, the data token that arrived earlier in the shorter
path has to wait for the coherent data token in the longer path,
making it a critical path. This can be eliminated by balancing
the pipeline stages in the two paths adding extra delay to the
shorter path. Achronix CAD environment (ACE) tool [58] al-
lows elimination of reconvergent paths by adding a constraint
to the place and route tool. The RTL design of the second-order
2-D IIR SBP filter is sent through ACE tool flow for final place
and route on the Achronix SPD60 FPGA, which is described in
Section IX-A.
IX. VHDL IMPLEMENTATION, SIMULATION, AND
VERIFICATION
Five prototype designs (with CLA up to stage 5) of the
second-order 2-D IIR SBP filter in direct-form-I realization,
consisting of PPCMs have been implemented using
VHDL. First, the difference equation of the filter for the
different CLA optimized designs (see Section VI) were im-
plemented using behavioral VHDL. The circuit employed 2’s
complement fixed-point binary arithmetic, with a precision of
and (where is the word length and is the
2252 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 12, DECEMBER 2012
TABLE III
SPEEDS OF SECOND-ORDER 2-D IIR SBP FILTER IN DIRECT-FORM-I [24]
position of binary point), chosen large enough to make quanti-
zation noise effects small [56]. The VHDL was then imported
into Simulink model using a blackbox implementation provided
by Xilinx system generator (XSG) design tool. The complete
design with five of these blackbox (for ) with necessary
ZICs was created in Simulink. Finally, a VHDL-mappable
bit-true cycle accurate Simulink models of the designs were
created using the XSG design tool, with all Xilinx specific opti-
mizations turned off. The resulting VHDL code would therefore
be generated using behavioral VHDL. These behavioral VHDL
designs were passed through synchronous and asynchronous
FPGA flows as well as to application-specific integrated circuit
(ASIC) synthesis to get the timing and power analysis.
A. FPGA Prototyping
The five prototype designs for CLA optimized a-QDI filter
circuits, employing PPCMs have been tested on an
SPC60 development board with a 65-nm CMOS Achronix
Speedster SPD60 asynchronous FPGA. The VHDL design is
passed through Mentor Graphics’ Precision Synthesis tool for
RTL synthesis and then the resulting post-synthesis netlist is
fed to ACE tool [58] for place and route on the asynchronous
fabric. A wrapper RTL for communication with PC through a
USB port is used to read the filtered output from the Achronix
FPGA.
To obtain a speed comparison of the asynchronous imple-
mentation on Achronix FPGA with conventional designs, the
five designs are also synthesized and placed and routed using
synchronous FPGA design tool for high capacity device of same
65-nm CMOS technology Xilinx Virtex-5 LX330FF1760-2
using the timing driven place and route algorithms (ensuring
the CP to be the tightest loop via pipelining). The results for
the synchronous and asynchronous implementations of the
second-order 2-D IIR SBP beam filter employing 5 PPCMs are
shown in Table III. We can observe a significant improvement
in speed with the asynchronous implementation using Achronix
FPGAs, for LA optimized designs, which are as high as 31%
for a CLA of order . leading to
The correct operation of the 2-D IIR SBP filter was veri-
fied for both synchronous and asynchronous implementation
by exciting the inputs of the filter by a 2-D unit impulse
function and measuring the impulse response
-
from the on-chip realizations.
A 2-D magnitude frequency response of
the measured filter output within the 2-D Nyquist square
, , 2, is shown in Fig. 17. For the ver-
ification of the synchronous implementation of the filter, the
design was realized in hardware using using a 90-nm CMOS
Fig. 17. Magnitude frequency response of 2-D IIR SBP beam filter, for
, , and , obtained from (a) closed form expressions
with infinite precision and (b) prototype FPGA implementation on the Xilinx
ML402 board for word size of 16 bits, for PPCMs. The response ap-
proaches the ideal case as the value of and word size is increased.
Xilinx Virtex-4 SX35FF668-10 synchronous FPGA, employing
the Xilinx ML402 board which facilitates on-chip hardware
co-simulation (HCS) with MATLAB/Simulink, while the same
65-nm CMOS Achronix Speedster SPD60 asynchronous FPGA
on a SPC60 development board was used for the verification of
the asynchronous implementation.
B. ASIC Realizations at 65- and 90-nm CMOS
The behavioral VHDL designs (conventional synchronous
design) of the 2-D IIR SBP filter circuits for PPCMs with
word size of 16 bits ( , ) were also synthesized
for ASIC in 65- and 90-nm CMOS technology. The ASIC syn-
thesis was performed with the Synopsys Design Compiler Ver-
sion D-2010.03 using DesignWare building block libraries
and TSMC TCBN65G standard-cell library version 140b and
TSMC TCBN90GHP standard-cell library version 210a for 65-
and 90-nm technology, respectively. The optimization goal was
to maximize the speed of operation of the filter. The global
operating voltage for both the technologies was 900 mV. The
results of the ASIC synthesis of the CLA optimized filter de-
signs for 65- and 90-nm technologies are shown in Table IV.
It can be seen that the speed of operation of the filter increases
as the CLA pipelining is increased (at the cost of added hard-
ware complexity thereby increasing cell area and power). But
once the CLA pipelining reaches a certain limit, there is no fur-
ther speed improvement in the filter circuit. For 65-nm CMOS
technology, CLA with was the limit beyond which the
speed of the filter remained the same (1.064 GHz). Similarly,
for 90-nm CMOS technology, the filter with CLA of
had the highest speed of 694 MHz.
We consider the equation ; for the area-time
complexity [59]. Since our optimization goal was to improve
the speed of operation of the circuit, we chose a higher value of
performance. Alternatively, for area
efficient designs, the performance can be compared among
various designs. The area-time complexity, total gate count and
power details of the prototype designs obtained from the ASIC
synthesis are also indicated in Table IV. It can be observed that
the circuit with CLA of is the optimum design in terms
of performance based on the synthesis results. For the
power analysis, a PW input (partially-broadband GMC pulse)
with one desired signal and four interfering signals including
noise (as used for the BER simulation in Section VII) was mod-
eled as test patterns. A switching activity information format
JOSHI et al.: SYNTHESIS AND ARRAY PROCESSOR REALIZATION OF A 2-D IIR BEAM FILTER
TABLE IV
RESULTS OF ASIC SYNTHESIS OF THE SECOND-ORDER 2-D IIR SBP FILTER CIRCUITS FOR 65-nm AND 90-nm CMOS TECHNOLOGIES
(SAIF) file was generated using 10 000 test vectors for the gate-
level simulation in Cadence NCSim version 06.11. Then the
SAIF file was back annotated with the gate level netlist. Finally,
Power Compiler was used to calculate power consumption in
the circuit. It can be seen in Table IV that as the CLA stages in
the design is increased, the total power consumption of the de-
sign also increases. Therefore, there exists a trade-off between
power-efficient and timing-efficient design and the choice of de-
sign is based on the specific requirements on speed or power.
X. CONCLUSION
A second-order 2-D IIR SBP beam filter is proposed for the
directional enhancement of a PW based on its DOA. The filter
is highly steerable, algebraically-defined in terms of the desired
DOA, computable, and is based on the impulse response mod-
ulation of a practical-BIBO stable 2-D IIR frequency-planar
beam PW filter. The performance of the 2-D IIR digital filter
for interference rejection is verified for PWs in the presence
of interfering PWs at different DOAs. Further, the BER versus
SIR performance of a phased array beamformer and the second-
order 2-D IIR SBP beam filter were studied and simulated for
a partially broadband PW. The performance improvement of
the second-order 2-D IIR SBP beam filter (which is based on
a systolic/wavefront array implementation) over a digital PAF
beamformer is proposed here. Also, a massively-parallel array
architecture of the filter is proposed for real-time implementa-
tions using synchronous and asynchronous FPGAs, which en-
able spatial filtering of broadband PWs at a very high throughput
having potential applications in wireless communications, cog-
nitive radio, radio-astronomy aperture-arrays, and radar. The
ASIC synthesis of the filter designs was also carried out for
65- and 90-nm CMOS technologies. The results show that the
speed of operation of the filter is as high as 1.064 GHz for a
stage CLA pipelined design for 65-nm CMOS tech-
nology. Higher order 2-D IIR filter and its performance im-
provement is a topic to be researched in future.
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Rimesh M. Joshi (S’10) received the B.E. degree in electronics and communi-
cation engineering from Tribhuvan University, Kathmandu, Nepal, in 2008, and
the M.S. degree in electrical engineering from the University of Akron, Akron,
OH, in 2011.
Arjuna Madanayake (M’03) received the B.Sc. degree in electronic and
telecommunication engineering from the University of Moratuwa, Moratuwa,
Sri Lanka, in 2002, and the M.Sc. and Ph.D. degrees in electrical engineering
from the University of Calgary, Calgary, Canada, in 2004 and 2008, respec-
tively.
He is a Tenure-track Assistant Professor with the Department of Electrical
and Computer Engineering, University of Akron, Akron, OH.
Jithra Adikari (M’07) received B.Sc. degree in electronic and telecommuni-
cation engineering from the University of Moratuwa, Moratuwa, Sri Lanka, in
2002, the M.Sc. degree in information technology from the Royal Institute of
Technology (KTH), Stockholm, Sweden, in 2005, and the Ph.D. degree in elec-
trical and computer engineering from the University of Calgary, Calgary, AB,
Canada, in 2010.
He is with Elliptic Technologies, Canada. He was with the University of Wa-
terloo, Waterloo, ON, Canada.
Len T. Bruton (F’81) is Professor Emeritus with the Department of Electrical
and Computer Engineering, University of Calgary, Calgary, AB, Canada.
Prof. Bruton was a recipient of many awards including the 2002 IEEE Circuits
and Systems Education Award, the 1994 IEEE Outstanding Engineering Award,
and the 1991 Manning Principal Award. In 1994, he was elected a fellow of the
Royal Society of Canada. He has been featured in the 1997 Great Canadian
Scientists by Barry Shell.