FACULTY OF ELECTRICAL ENGINEERING

UNIVERSITI TEKNOLOGI MARA

ADVANCE DIGITAL DESIGN AND COMPUTER ARCHITECTURE

(ELE654)

LAB REPORT

Lab Report No. 3 Experiment No. 3

Date Performed 23/10/2018
Date Submitted 13/11/2018
Title Testbench And FSM

Prepared by:
Name UiTM NO Group
AMMAR HAFIFFI BIN MOHAMAD ISA 2016479802 EE241E7A

Assessment:
Assessment Marks
Title
Objective
Literature Review
Methodology
Results & Discussion
Conclusion
Appendix
Total Marks

Lecture’ Name EN ABDUL KARIMI HALIM

Feedback Comment
1.0 OBJECTIVES

The objectives of Lab 2 experiments are :

a) To write the testbench’s Verilog code for a sequential module and simulate using
Modelsim.
b) To write the Verilog code of a FSM module and implement the design on FPGA board.

2.0 LITERATURE REVIEW

 Sequential Logic :
Every digital system is likely to have combinational circuits, most systems
encountered in practice also include storage elements, which require that the system be
described in term of sequential logic
a) Latch :
A latch is an example of a bistable multivibrator, that is, a device with exactly two
stable states. These states are high-output and low-output. A latch has a feedback path, so
information can be retained by the device. Therefore latches can be memory devices, and
can store one bit of data for as long as the device is powered. As the name suggests, latches
are used to "latch onto" information and hold in place. A D latch have 2 states, one is
opaque and transparent. A latch is in opaque state when the value of output is not to input
and is in transparent state when output is similar to input in real time.

2
 INPUT OUTPUT
S R Q ̅Q̅
0 0 Invalid
0 1 0 1
1 0 1 0
1 1 Invalid
Table 1 : Truth Table of SR Latch

S Q
LATCH
̅Q
R

Figure 1 : Block Diagram of SR Latch

The truth table of half adder above shows all the possible inputs and its resulting
outputs.To avoid having invalid states, the latch can be reconfigured to be a D latch where
R input is replaced with clock. This will enable opaque and transparent states.

b) Flip Flop :

A flip-flop is a device very much like a latch in that it is a bistable multivibrator,

having two states and a feedback path that allows it to store a bit of information. The
difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs
can change as soon as the inputs do (or at least after a small propagation delay). A flip-
flop, on the other hand, is edge-triggered and only changes state when a control signal goes
from high to low or low to high. This distinction is relatively recent and is not formal, with
many authorities still referring to flip-flops as latches and vice versa, but it is a helpful
distinction to make for the sake of clarity.

3
 There are several different types of flip-flop each with its own uses and
peculiarities. The four main types of flip-flop are : SR, JK, D, and T.

CLK

D FLIP FLOP S

RST

Figure 2 : The block diagram of D Flip Flop

4
3.0 METHODOLOGY :
Start

Design Statement / Problem Statement

Specifications

Behaviour

Truth Table

Simplified Boolean Expression

Logic Circuit

Implementation

Test Bench Verilog Pin Assignment /

Programming

5
 Flowchart above is the Design Flow used to design logic gates or modules such as adders,
demultiplexers, priority decoders, multiplexers from scratch untila verilog code is constructed and
test bench is simulated.This acts as a guideline for us to create, troubleshoot or debug any logic
gate or module.

a) EXPERIMENT 1 : DESIGN & SIMULATION OF A SEQUENTIAL MODULE

1. Design Statement / Problem Statement :

o Design a sequential module that can transfer 4-bit input datas at every positive
clock edge to the outputs.

2. Specification :

o Block Diagram :

Figure 3 : Block diagram of 4 bit sequential module

o Input : rst, clk, D0, D1, D2, D3.

o Output : Y0, Y1, Y2, Y3

6
3. Behavior :
o Tc = 10T, tsetup = 4T and thold = 6T.
o 4 bit inputs at positive clock edge (posedge).
o Data from input changes at every negative clock edge (negedge).
o Asynchronous sequential behaviour.
o If rst = 0, then Y0 = D0, Y1 = D1, Y2 = D2, Y3 = D3.

4. Truth Table :

INPUT OUTPUT

rst clk Y3 Y2 Y1 Y0
0 D3 D2 D1 D0

1 0

5. Implementation :

o Verilog :

Figure 4 : The Verilog code for DUT

7
o Testbench

8
9
Figure 5 : The Verilog code for Testbench

10
o Synthesized RTL viewer.

11
o Testbench model for sequential module

o Timing Diagram

12
o Output waveform generated from Modelsim

13
b) EXPERIMENT 2 : DESIGN AND SIMULATION OF A FSM MODULE

1. Design Statement / Problem Statement :

o design a FSM module using Moore architecture

2. Specification :

o Block Diagram :

Figure 6 :Block diagram of FSM module

o State Transition Diagram

o Input : SW0 – SW4

o Output : LEDR0 & LEDG0

3. Behavior :
o when SW2(clock) is toggled, data will change.
o when SW3(reset) is toggled, the LEDR0 switch ON. (initial ground position)
o when SW0(down) is toggled, the LEDR0 switch ON. (wait clock toggle)
o when SW1(up) is toggled, the LEDG0 switch ON. (wait clock toggle)

14
4. Truth Table :

o State Transition Table

CURRENT INPUT NEXT STATE
STATE (S) (S’)
Groundfloor Down Groundfloor
Groundfloor Up Firstfloor
Firstfloor Down Groundfloor
Firstfloor Up Firstfloor

o State Encoding Table

CURRENT BINARY
STATE (S) ENCODING (b)
Groundfloor 0
Firstfloor 1

o State Encoded Table

CURRENT So INPUT NEXT So’
STATE (S) STATE (S’)
Groundfloor 0 Down Groundfloor 0
Groundfloor 0 Up Firstfloor 1
Firstfloor 1 Down Groundfloor 0
Firstfloor 1 Up Firstfloor 1

15
 o State Output Table
CURRENT OUTPUT (LED)
STATE (S)
RED GREEN
Groundfloor ON OFF
Firstfloor OFF ON

o State Output Encoding Table

OUTPUT (LED) BINARY
ENCODING (b)
OFF 0
ON 1

o State Output Encoded Table

CURRENT OUTPUT (LED)
STATE (S) So
RED GREEN
Groundfloor 0 ON OFF
Firstfloor 1 OFF ON

5. Expression :
Simplified expressions for Next State Combinational Logic:
So’ = So (Input) + So(Input).

Simplified expressions for Output Combinational Logic:

LED Red = So == Groundfloor.
LED Green = So == Firstfloor.

16
6. Logic Circuit :
o Output Combinational Logic

o Next State Combinational Logic

o Moore FSM Architecture Logic Circuit

17
7. Implementation :
o Verilog :

Figure 7 :Verilog code for FSM

18
o Synthesized RTL viewer

o Pin Assignment :

19
5.0 DISCUSSION :

 EXPERIMENT 1 :

In Experiment 1, output waveform generated from Modelsim software are a result of

combining DUT verilog and Testbench verilog. DUT verilog are programmed in Quartus Prime
Lite software while Testbench verilog are programmed in Modelsim software. Based on the result,
we can see that when reset is HIGH, all outputs are LOW regardless of what the current input is,
This is because the verilog code is behavioural asynchronous. This means when reset triggers,
output overwrites any current data to LOW.

When reset is not triggered, it is set up in the verilog code that the output will follow the
input values. However, the data from inputs only transferred to outputs in the positive clock edge
of the clock cycle. This is set by the command line “always @ (posedge rst, posedge clk)”. A full
clock cycle is T = 10ns. For positive clock edge is T/2 = 5ns. Next, the Tsetup and Thold is
approximately ±10 % from T at the positive clock edge trigger. At this state the data must be stable.
In the verilog code, a change in data simulation is entered on each clock cycle from “0000” to
“1111”. In a nutshell, experiment 1 is successfully accomplished as generated waveform is
identical with expected timing diagram from design flow.

20
  EXPERIMENT 2 :

In Experiment 2, switches which is assigned as input devices and LED as output devices
on FPGA board and are programmed in Quartus Prime Lite software. The Verilog code used for
the DE2-115 board was generated manually by doing the design flow for FSM. The Verilog code
is written into the Quartus software and undergoes compilation to ensure no errors with the code.
Switches SW0 is down, SW1 is up, SW2 is clock, and SW3 is reset. For the output, LEDs LEDR0
is Red 0 for ground floor while LEDG0 is Green 0 for first floor. Each of the pins are individually
assigned in Pin Planner.

Figure 8 : When SW0 = 1, SW1 = 0, SW2 = 1 and SW3 = 0, the LEDR0 is turned ON

Based on the figure above, this is when the ground elevator button (SW0) is pressed. The
data enters and waits for the clock signal (SW2) to produce the output LEDR0 = 1 showing that
the elevator has arrived at ground floor. This is because the data can only be transferred on the
positive clock edge to the outputs.

21
 Figure 9: When SW0 = 0, SW1 =1, SW2 = 1 and SW3 = 0, the LEDG0 is turned ON.

Based on the figure above, this is when the first floor elevator button (SW1) is pressed.
The data enters and waits for the clock signal (SW2) to produce the output LEDG0 = 1 showing
that the elevator has arrived at ground floor. This is because the data can only be transferred on
the positive clock edge to the outputs.

22
 Figure 10: When SW0 = 0, SW1 =1, SW2 = 1 and SW3 = 1, the LEDR0 is turned ON.

Based on the figure above, this is when the reset elevator button (SW3) is pressed. The data
enters and does not wait for the clock signal (SW2) to produce the output LEDR0 = 1 showing
that the elevator has arrived at ground floor. This is because when the reset button is pressed, the
verilog code resets the current data to LOW, which in this case the initial position of the elevator
(ground floor).

23
6.0 CONCLUSION :

As a conclusion, based on the results obtained from Experiment 1 and 2, it can be

concluded that the objectives for this experiment have been achieved successfully. The inputs and
outputs on the FPGA board is properly set up and implemented. Then, logic circuits and boolean
expressions from the design flow method is correctly implemented into the Quartus software to be
downloaded into the FPGA board without errors. Modelsim simulation for testbench verilog was
also able to be properly set up and implemented. In addition, students have learnt the differences
between Quartus software and Modelsim software and what are the uses for each softwares.

24
7.0 REFERENCES :

[1] Harris , S. L., & Harris, D. M. (2016). Digital Building Blocks. In Digital Design and
Computer Architecture. MA: Elsevier Science & Technology.

[2] Field-programmable gate array (FPGA) – Wikipedia. Retrieved November 10, 2018, from
https://en.wikipedia.org/wiki/Field-programmable_gate_array

[3] Digital Circuits/Latches – Wikibooks. Retrieved November 10, 2018, from

https://en.wikibooks.org/wiki/Digital_Circuits/Latches

[4] Digital Circuits/Flip-Flops – Wikibooks. Retrieved November 10, 2018, from

https://en.wikibooks.org/wiki/Digital_Circuits/Flip-Flops

25