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SEQUENTIAL ELEMENTS
Ch. 7 Ch. 6
[Sorin Cotofana]
CLK = CK=φ
TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 6 sequential 8
Latches vs. Registers
Latch Register
Level-sensitive Edge-triggered
Transparent when clock Input and output isolated
is active
Sampling on 0 → 1 clock:
Clock active high: positive edge triggered
positive latch
Sampling on 1 → 0 clock:
Clock active low: negative edge triggered
negative latch
Safer
Faster, smaller
Static Dynamic
Operate through positive Store charge on
feedback (parasitic) capacitor
Preserve state as long as Charge leaks away (in
power is on milliseconds)
Can work when clock is Clock must be kept
off running (for periodic
refresh)
More robust
Faster, smaller
Vo1 =V i2
Vi1 Vo2
Vi2 = Vo1
o1
V
C
C: meta-stable point
§ 7.2.1
B
Vi1 = Vo2
S S R Q Q
& Q
S Q
S Q 1 1 Q Q
R Q 0 1 1 0
R
&
QQ 1 0 0 1
R 0 0 1 1 forbidden
§ 7.2.5
S Construction of D-latch
D R D-latch, D-register most common in
VLSI
& Q φ M6
M1
M8 φ
& M3
R
S M5 M7 R
φ = CK
Save 6 PMOS transistors and 2 NMOS
D-latch requires 7 x N, 3 x P (instead of 9xN, 9xP)
CLK
IN Restoration
CLK
Recirculating latch
Multiplexer
φ1 φ2
φ2
Quasi-static, static on one phase
Feedback restores value
Requires 4 x N, 4 x P, minimum size
(compare 7 x N, 3 x P, non-minimum size)
φ1 and φ2 inverse but should be non-overlapping
Can suffer from charge sharing (when φ not non-overlapping)
Cin and Cload form communicating vessels when Output connected
directly to input
φ1
φ1 φ2
φ2
Degraded 1 at X
Lower noise margin, higher delay, power
t loop
t
φ
D Q t
1 φ Q
master slave
§ 7.2.3 D Q
§ 6.1.4-5
clickable
link
Robust Design
Can eliminate I1 and I4, however, they make design
more robust (avoid charge sharing, robust input)
High Clock Load (8 x)
Vou t V OH
In Out
•Restores
Restoressignal slopes
signal slopes
VM– VM+ Vi n
Vin Vout
VM+
VM–
t0 t t0 + tp t
V DD
M2 M4
V in X V
out
M1 M3
5.0 6.0
4.0
4.0
3.0
Vou t (V)
VM+
V X (V)
2.0
2.0
VM-
1.0
0.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vin (V) Vin (V)
VDD
M4
M6
M3
In Out
M2
X
M5 V DD
M1
Background
Timing, terminology, classification
Static Flipflops
Latches
Registers
Dynamic Flipflops
Latches
Registers
Non-bistable elements
Schmitt Trigger
TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 6 sequential 33