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Transactions on Power Electronics
Abstract—A novel dual-mode control scheme is developed here Coss1
to enable synchronous buck con verters (S BC) to operate in a Iin iL IO
continuous conduction mode under heavy-load conditions and in a D1
discontinuous conduction mode under light-load conditions. MA L
When an S BC operates in a discontinuous conduction mode, a MB
VDC VGS1 CO RO
quasi-resonant valley switching technique can be employed to VO
Coss2
turn on a synchronous switch, perform zero-voltage switching at VGS2
main switches, and improve the light-load efficiency. The D2
proposed scheme does not require the addition of an auxiliary (a)
circuit in the S BC, providing it with the advantages of low cost
T
and easily built-in integrated circuits. To verify its feasibility, an
S BC equipped with the proposed control scheme is de veloped, iL
with output voltage and output power of 5 V and 25 W, 0 t
respectively.
VGS2
consumers have become increasingly concerned about the shown by the red dotted lines in Fig. 1(b). Specifically, the
usage duration of their electronics devices. Currently, such operation of SBCs under light-load conditions is inadequate
devices are powered by batteries, and the voltage supply to such due to the low conversion efficiency.
products tends to decrease gradually. Therefore, to extend the In order to address the drawbacks of SBC, hybrid mode
battery life, synchronous buck converters (SBC) have been control strategies based on different loading conditions from
widely used in personal and portable devices (Fig. 1(a)). several different studies have been proposed [2–14]. The most
Conventional SBCs are controlled using complementary popular technique of the dual mode control is to combine with
pulse-width modulation (PWM), as shown in Fig. 1(b). Under CCM and discontinuous conduction mode (DCM). Generally,
heavy-load conditions, the low conduction loss inherent in a dual-mode operations can be divided into fixed-frequency
switch, MB, is used to operate an SBC in a continuous mode and variable-frequency mode.
conduction mode (CCM), thus increasing the conversion In variable-frequency control, a PFM technique based on the
efficiency. However, when the mean load current is lower than hysteresis of the output voltage determines the timing for the
the inductance current associated with a boundary conduction turning on and off of a metal-oxide-semiconductor field-effect
mode, the reverse inductance current creates excess loss [1], as transistor (MOSFET) [2–5]. In other words, the output power
decreases, thereby decreasing the switching frequency.
Therefore, the light-load efficiency of the SBC increases. The
Manuscript received XXX. XX, XXXX; revised XXX. XX, XXXX; drawback of this control strategy is a much wider range of
accepted for publication XXX. XX, XXXX. This work was supported by the switching frequencies, making EMI filter design difficult. In
Ministry of Science and Technology of Taiwan through Grant numbers MOST
105-2221-E-150 -047, and MOST 102-2221-E-150 -023 -MY3. addition, the output ripple voltage for this control strategy is
J. M. Wang is with the Department of Vehicle Engineering, National higher than that for the PWM control strategy.
Formosa University, Taiwan, ROC (phone: x-886-5-6315692; fax: Another variable-frequency technique involves detecting the
x-886-5-6321571; e-mail: jmw@sunws.nfu.edu.tw). valley of the inductor current. If the inductor current reaches the
S. T . Wu, is with the Department of Electronic Engineering, National
T aiwan University of Science and T echnology, Taipei, 10607, Taiwan, ROC. valley, the main switch will be triggered on. Thus, the SBC can
Color versions of one or more of the figures in this paper are available be operated at the boundary between CCM and DCM. The main
onlineat http://ieeexplore.ieee.org.
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Transactions on Power Electronics
switch operated in this region has the characteristics of auxiliary switches or passive devices containing resistors,
zero-current-switching (ZCS) [6]. The quasi-resonant inductors, or capacitors (RLC) for the SBC main switches to
switching technique is similar to the aforementioned control achieve ZVS; only logic circuits and comparators are needed.
strategy [7–9]. This scheme involves resonance generated As a result, the proposed scheme possesses various advantages
through the parasitic capacitance and inductance of switches. such as low cost and easily built-in integrated circuits (IC).
To improve the efficiency, it turns on the MOSFET when the SBCs exhibiting a 40 kHz switching frequency, 25 W output
vds resonance reaches a valley. The above-mentioned control power, 12 V input voltage, and 5 V output voltage were
strategies still have problems related to a wider variation range employed to verify the advantages of the proposed control
of switching frequencies when the output power drops. technique.
Due to the aforementioned drawbacks of variable-frequency Table I shows a general comparison of the dual-mode control
control, some authors have opted for fixed-frequency PWM strategies. The SBC with the proposed control strategy exhibits
techniques [10–14]. These control methods need to detect the better performance than the other two strategies, especially
zero point of the inductor current. When the inductor current with regards to the efficiency. In addition, the switching
reaches zero, the synchronous switch is turned off to prevent an frequency is almost fixed. Therefore, it is a simple process to
inverse inductor current. Another control strategy is to emulate suppress EMI and audio noise.
the inductor current with an auxiliary circuit, and the result is The rest of this manuscript is organized as follows: Section II
the same as for the previous method [13]. In order to improve explains the concepts and operating principles of the proposed
the efficiency of SBCs under light-load conditions, Ref. [14] control scheme; Section III presents the design of the control
adopted the ZVS technique. The key point of the control circuit; Section IV gives details of the power loss analysis;
strategy is that the synchronous switch is turned on twice in a Section V presents design considerations for relevant devices;
complete switching cycle; therefore, the main switch has a ZVS Section VI presents experimental results; Section VII gives the
characteristic without considering the vds of the synchronous conclusions.
switch for the on-state. That is, the synchronous switch
generates extra switching losses at the instant that the switch is II. PROPOSED DUAL-MODE CONVERT ER ST RUCT URE AND
turned on. In order to overcome this drawback, this paper OPERAT ING PRINCIPLES
proposes a novel control strategy. Figure 2(a) presents the block diagram of the proposed
Previous studies have proposed the use of soft-switching control scheme, including a fixed-frequency PWM controller
techniques that comprise ZVS and ZCS to improve the and an LZC. To achieve ZVS while avoiding reverse
efficiency of buck converters. ZVS is commonly applied to inductance currents, an external current transformer and a
computer, communication, and consumer electronics products
zero-hysteresis comparator must be used when inductance
because it eliminates the need for the switch to be turned on, a current levels are less than zero in order to generate v Z1_O
process that causes capacitive loss. These techniques generally signals to turn off the synchronous switch (MB). In other words,
require external active auxiliary circuits, and main switch (i.e., in the proposed control scheme, the SBC operating mode can be
ZVS) operations are completed using resonance currents divided into a DCM and a CCM. The error signal v EAO is
generated by LC cells. Although these techniques result in good generated by comparing the feedback voltage vFB of the error
performance, they are associated with increased device volume compensation amplifiers with the reference voltage Vref. This
and circuit complexity, as well as elevated device stress [15– signal can be used to determine the duty cycle of the main
22]. Digital control techniques are also feasible solutions [23– switch. In addition, v ZCD is mainly supplied by an auxiliary
25]. However, they require complex mathematical algorithms winding for detecting the drain voltage of MB. Furthermore, the
and the adoption of digital signal processors. Furthermore, the negative-edge of vZ2_O triggers LZC to generate v pulse signals,
overall costs associated with such techniques are considerably which turn on MB and the rest of the PWM controller to
high. implement the valley switching of MB and ZVS of the main
This study proposes a novel dual-mode control technique switch MA . Here, Vref1 is close to VO /2.
combined with QR valley switching and ZVS. In the DCM Figure 2(b) shows the theoretical waveform of the proposed
region, a limit-frequency QR valley switching technique turns controller, which involves DCM and CCM operations. The
on the main switch to achieve ZVS to increase the efficiency of DCM operation is described as follows. When the inductance
the SBC. Furthermore, this novel limit-frequency ZVS current drops to zero, the vZ1_O signal changes from a high level
controller (LZC) maintains the switching frequency under to a low level in order to turn off MB and prevent the occurrence
light-load conditions. The method requires no external of a reverse induction current. Subsequently, the LZC begins to
T ABLE I COMPARISON OF SBC CONT ROL T ECHNIQUES
Operation Mode Efficiency Load Range Output Voltage Ripple Audio Noise EMI filter design Line/load regulation
CCM/DCM Good Wide Large Medium Hard Good
(Variable-Frequency)[2–9]
CCM/DCM Medium Wide Small Small Easy Good
(Fixed-Frequency)[10–13]
CCM/DCM Good Wide Small Small Easy Good
(Fixed-Frequency)[14]
CCM/DCM Very Good Wide Small Small Easy Good
(Novel)
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Transactions on Power Electronics
detect valley voltages created by inductance and parasitic becomes feasible following MB valley conduction. During
capacitance (Coss) resonance. To prevent the switching CCM operation, the LZC enters a conventional synchronous
frequency from reaching a higher frequency, LZC generates a rectification control mode.
control signal, v pulse, for valley switching of MB based on the
frequency of v osc. When MB turns on after Δt, the PWM III. CIRCUIT IMPLEMENT AT ION
controller restarts to achieve ZVS of MA for the next switching QR control strategy usually has a problem about much
cycle. higher switching frequency. This drawback is typically
vZCD resolved by limiting the highest switching frequency, which
vds_MA
Coss1 iO can be done by adding a minimum off-time (during which
D1 L
vZ1 energy is transmitted to an output load) to a switching cycle [26,
Rsense iL
MA CT
R1 27]. Although this technique can prevent an increase in the
VDC is CO RO VO
MB frequency, it requires the addition of blanking time circuits and
VGS1 VGS2
vds_MB R2 time delay circuits, rendering the overall control circuit design
Driver
D2 Coss2 more complex. Instead, this study proposes an LZC that only
requires one additional pulse generator circuit to limit the
vZ1 vZ1_O vFB maximum frequency of the QR mode (Fig. 3). Additionally, MA
vPWM vEAO Voltage Loop
Limit-Frequency Comparator
Compensator Vref has characteristics of ZVS.
Zero-Hysteretic
Comparator
ZVS Controller Sawtooth When the inductance current iL drops to zero, the v Z1_O signal
vZCD Oscillator turns off MB through the AND gate. In the QR mode, Coss
vZ2_O vpulse
RZCD vZ2 vosc PWM Controller
induces resonance with L, as shown in Fig. 3(b). When the
Vref1 Hysteretic
Comparator vds_MB voltage resonance reaches a valley, the v ZO_2 signal
(a) immediately changes from a positive potential to a negative
Transient
Operation Region potential, and processing this signal using a differentiator and a
VO resistive divider (Rth1 and Rth2 ) yields an adjustable pulse signal
vp_th. To limit the maximum frequency, the PWM IC oscillator
Light Load Heave Load iO signals v osc and v p_th must be composed for comparison with
The control signal and the inductor
current waveforms operated in DCM
Tdelay The control signal and the inductor
current waveforms operated in CCM VTH to determine the valley switching timing (Fig. 3(a)). If the
Δt
iL TS vsoc_p signal (vsoc_p = v p_th + v soc_p, where vp_th = Vp_h ) is lower
than VTH , then the v pulse signal is maintained at a low potential
ΔIL
t t
without influencing the operation of the oscillator. This
MA operating mode is repeated until t0 is achieved.
VGS1
At t0 , vds_MB reaches the valley in resonance. At this moment,
t t
VGS2
MB vsoc_p is higher than VTH . Hence, v pulse changes from a low to a
high level. During this transient state, MB and Q are turned on
vZ1_O
t t simultaneously. This causes the oscillator to discharge rapidly
t t
and the inductor starts to store energy. After t1, MB and Q are
vds_MB turned off simultaneously. Thus, the PWM controller restarts to
VDC 2VO VDC change the designed oscillation frequency. As mentioned above,
t t
vds_MA the frequency of the PWM controller increases if v p_th is higher.
VDC
t
VDC
t
Conversely, the frequency of the PWM controller will decrease.
vZCD Vref1
t
Vref1 These results indicate that v p_th can be adjusted according to the
t
maximum switching frequency. Furthermore, the energy stored
vZ2_O in the inductor in the previous state causes the parasitical
t t capacitor to discharge, forcing MA to achieve ZVS in the
vpulse
subsequent switching cycle. The following circuit design is
vosc
t t divided into two parts—the ZVS of MA and valley switching of
VH
MB.
VL
t VCC
t
DCM Operation Region CCM Operation Region Rp1 vosc
Differential
vp
(b) vZ2_O Q1
Circuit
Rth1
vp_th vosc_p
Q C T RT PWM
Fig. 2. (a) Proposed dual mode control scheme and (b) key waveforms of the Rth2
vp1 Monostable vpulse
Controller
CMP trigger
proposed controller circuit
VTH
vosc
The CCM operation is described as follows. As the output
power increases, the operating mode of the SBCs is changed vPWM
MB
driver
VGS2
from DCM to CCM. Concurrently, the synchronous switch and vZ1_O vZCD
the main switch are turned on complementarily. This willnot be vPWM Delay time
VGS1
MA
influenced by v Z1_O. In conclusion, the controllers in the
Limit-Frequency ZVS Control Circuit
proposed control scheme can operate SBCs in the DCM under
(a)
light-load conditions. In addition, the MA ZVS operation
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Δt Tdelay vds_MA
VGS1 Coss1 D1 L iL iO
Quasi-Resonant
Mode Region MA
t VDC
VGS2 VGS1 D2 CO RO VO
VGS2 vds_MB
t
iL MB Coss2
t VDC 2VO
vds_MB
t
VDC 2VO
VTH
t
vds_MA Vp_h
VDC
vZCD Vref1
t
vosc_p t
tp
t TS
Fig. 5. SBC valley switching timing
vZ2_O
B. ZVS of M A
t
T delay and Δt of v pulse need to be considered if ZVS of MA is
achieved. Figure 6 presents the SBC-equivalent circuit when
vp_th Vp_h MA is turned off and MB is turned on. The voltage across the
t
inductance L is −VO . The inductance current iL is expressed as
VL follows:
vosc −V
t
𝑖 𝐿 (𝑡) = L O (t − t 0) (4)
VTH To ensure that the MA parasitic capacitance is fully discharged
in order to achieve ZVS, the stored inductor energy EL must be
vosc_p t greater than the energy stored in parasitic capacitors, ECoss1. The
vpulse
energy storage equation is expressed as follows:
t 2
t0 t1 (𝑖 𝐿𝑝 ) × L ≥ COSS1 × (VDC )2 (5)
(b) where iLp is the peak value of the inductance current.
Fig. 3. (a) The proposed LZC logic circuit and (b) Theoretical waveforms of Through Eqs. (2) and (3), the pulse time can be determined
proposed LZC driver under light-load condition.
as
√LCOSS1 ×VDC
∆t (min) ≥ (6)
A. QR valley switching of MB VO
Figure 4 shows an SBC-equivalent circuit in resonance This mode is completed when MB is turned off.
intervals. In this circuit, iL(t) and vds_MB(t) can be calculated as: vds_MA
V
𝑖 𝐿 (t) = − O sin(𝜔t) (1) Coss1 D1 L iL iO
𝑍
𝑣𝑑𝑠_𝑀𝐵(t) = VO − VO cos(𝜔t) (2) MA
1 L VDC D2
where 𝜔 = and Z = √ C,C= COSS1 + COSS2. VGS1 CO RO VO
√ LC
Figure 5 depicts the valley switching timing, where T S and T r VGS2 vds_MB
represent the switching cycle and the resonance cycle, MB Coss2
respectively. In this study, the conduction time of MB was
designed to be close to the switching cycle; therefore, the Fig. 6. SBC equivalent circuit in Δt intervals
controller reset time was set to tp . The magnitude of Vp_h can be
determined as follows: In this study, the monostable trigger circuit generates a PWM
V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 signal vpulse. As shown in Fig. 7, the RC circuit determines the
Vp_h = VTH − R C (TS − Tr ) (3) width of Δt by using the charging and discharging behavior.
T T
where V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 is the peak voltage (V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 = 3V) of the Therefore, Δt can be expressed as
sawtooth waveform generated from a TL494 oscillator, V
Δt = −RC𝑙𝑛 (1 − VTH1) (7)
CC
TS = 2𝜋√LC, and VTH = 4.8 V.
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where VTH1 is the high-level input voltage of the NOR gate. The where T r is the rise time and f s is the switching frequency. In
capacitance of Cp can be determined using Eqs. (2) and (7): addition, the loss of MB is similar to that of MA [29], and
VTH1 √LCOSS1 ×VDC therefore,
−R p Cp 𝑙𝑛 (1 − )≥ (8) VF+1.1R𝑑𝑠,MB×I O T
VCC VO 𝑇𝑟𝑎𝑑. ) × I O ) × r × 𝑓𝑠.
P𝑆𝑤𝑖𝑡𝑐ℎ_MB = (VF × I O + ( 2 2
The technique of using a monostable trigger circuit to
determine the pulse width of the v pulse signal is thus feasible. (13)
Monostable trigger circuit
VCC vp1 t
VGS1 (1-D)TS t
vp1 Cp Rp
vpulse vA t
vA vB VTH DTS
VGS2 t
vB t
vpulse t ΔiL
Δt IO
ids,MA t
Fig. 7. Structure and control sequence of a monostable trigger circuit.
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(b)
Fig. 11 (a)Key ZVS-related waveforms; (b) Enlargement of ZVS-related
waveforms
(a)
(a)
(b)
Fig. 10 (a) Light-load control signals and inductance currents; (b) Heavy-load
control signals and inductance currents
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Fig. 16. Efficiency comparison between the novel and conventional scheme
VII. CONCLUSION
(b)
Fig. 14. Output voltage transient response (a) with light-load (10%) changed to In this study, a novel dual-mode control scheme suitable for
heavy-load (100%); (Vo: 100 mV/div., Vpulse: 10 V/div., and time: 10 synchronous buck converters (SBC) was developed, and the
ms/div.); (b) with heavy-load (100%) changed to light -load (10%); (Vo: 100 operating principle of this strategy was explained. It was then
mV/div., Vpulse: 10 V/div., and time: 10 ms/div.)
analyzed to demonstrate its efficiency. The novel control
scheme mainly integrates a continuous conduction mode and a
discontinuous conduction mode (DCM). In particular, when the
SBC was operated in the DCM, the second synchronous switch
conduction that occurred before the main switch conduction
contributed to the zero-voltage switching (ZVS) of the main
switch. In addition, composing the pulse and sawtooth
waveform signals prompted the synchronous switch to achieve
valley switching under limited frequency conditions. This
scheme possesses the following advantages. First, it is
integrated with a synchronous rectification technique to reduce
Fig. 15 shows the line regulation and load regulation of the proposed control
scheme. the conduction losses of the converter and improve the
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efficiency of the overall circuit. Second, operating an SBC in of the output voltage causes vds of the synchronous to increase.
the DCM can achieve ZVS in the main switch without requiring If the synchronous switch is not turned on at the valley, the
additional auxiliary switches or passive devices comprising a switching losses will be more serious. This result is the
resistor, an inductor, and a capacitor. The simple pulse disadvantage of Ref. [14].
generators are employed to limit the highest switching DCM Region
(Stage 1) (Stage 2)
frequency of the quasi-resonant mode. Finally, in Appendix, a VGS1 VGS2 VGS1 VGS2
comparison between the proposed control method with variable
switching frequency and the control method with constant
switching frequency presented in [14] is provided. t
APPENDIX B
The purpose of this paper and Ref. [14] is to improve the vds A
t
efficiency when the SBC operates under light-load conditions. VTH
The analysis of the control strategy is described when the SBC
operates under light-load conditions. Figure 17(a) shows the vosc t
TS
waveforms of key control signals and v ds of the synchronous TS
(a)
switch for the SBC control strategy [14]. This technique utilizes
DCM Region
the fixed-frequency control strategy. In state1, in order to (Stage 1) (Stage 2)
VGS2
VGS1 VGS2 VGS1
achieve ZVS of the SBC main switch, the synchronous switch
has to turn on at point A. In the same switching period, when
the load condition changes from state1 to state2, the v ds of the
synchronous switch changes with the variation of loading as t
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Transactions on Power Electronics
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