FIELD PROGRAMMABLE GATE ARRAY
Shah Siddhi S
Dept.:-Electronics and Communication
Nirma University
Ahmadabad ,India
11bec177@nirmauni.ac.in
Abstract—Field Programmable Gate Arrays (FPGA's) have rapidly
grown in acceptance and use over the last few years. Infect, some
aspects of FPGA's are preventing this growth from being much
more rapid than it is now. Particularly there is a need for closing
part of the gap between the performance of FPGA's and the
performance of traditional approaches to ASIC design in the areas
of gate density, clock rate, and ease of use. FPGA chips contain
tens to hundreds of thousands of logic gate with programmable
interconnects and are available to the users for their custom
hardware Programming. This design style provides a means of fast
prototyping and also cost effective chip design, especially for low
volume applications. It consists of I/O buffers, an array of
configurable logic blocks (CLBs) and programmable interconnects
structure.
Keywords— FPGA, AND-LUT, PLA, LUT, ORCA, CLBs.
Introduction
ASIC designers had two basic options for implementing their
designs in 1980s. Highly complex designs for which a large
unit volume was expected were designed as cell based ASIC's,
and simpler or lower volume circuits were used as Gate
Arrays. As illustrated in Figure 1. It changed when FPGA's
became available. Currently FPGA's offer a reliable option for
designers of ASIC's with low volume needs of up to 10K gates
and for somewhat higher volumes with lower gate counts.
Figure 1: Complexity vs production volume for three types
of ASIC circuits.
The reason FPGA's are limited to the lower left corner of
Figure 1 is that FPGA's still lag behind both Gate Array and
Cell Based designs in three key areas. These are gate density,
system clock speed, and ease of use. With improvements in
these three areas, FPGA use will extend well into the mid-
range of the Gate Array Market.
The Optimized Reconfigurable Cell Array (ORCA) is a new
SRAM based FPGA architecture which makes FPGA's
attractive in applications that which were previously reserved
for Gate Arrays. The ORCA has an architecture that assures
dense layout of all major types of functionality needed
including data path, random logic, and SRAM. High density
data paths are obtained through a completely nibble oriented
structure for both routing and functionality. Good random
logic packing results from a novel approach to interconnect
that simplifies software and reduces transistor count, coupled
with a powerful and flexible functional unit. All SRAM bits
that are associated with Look Up Tables (LUT's) gives good
SRAM density. High speed is assured with high speed
arithmetic circuits, low resistance interconnect lines, and
special low skew clock lines.
To make the ORCA easy to use, the entire architecture was
designed so that it could be efficiently used with simple,
straightforward algorithms. This eliminates the need for the
manual manipulation of FPGA placement and routing that has
made working with FPGA’s a challenge. Apart from that a
new approach is taken to automatic timing design that
automatically reallocates Routing and other resource for
critical signals so that fast routing paths can be saved for it.
FPGA programmed with SRAM technology are usually based
on Look-Up Tables (LUTs). For implementing random logic
circuits in LUT based FPGA, the cost of LUTs increases
exponentially according to the inputs of circuits. So LUT is
suitable for low fan-in logic circuits.
2. A Hybrid FPGA Architecture
2.1. Symmetrical FPGA architecture
The diagram of symmetrical FPGAs is Shown in Figure 2. It
consists of programmable logic clusters, Connection Boxes
(CBs) and Switch Boxes (SBs). The connection box of the
symmetrical FPGA, illustrated in Figure 3, is fully-populated,
which connects signal between routing channel tracks and
logic clusters.
 Figure 2 : Symmetrical FPGA Architecture.

Figure 4: Wire-and CB

Detailed architecture of the wire-and CB is presented in

Figure 5. A pull-up resistor is used in every wire-and line. Two
serial NMOS pass transistors draw the wire-and line to the
ground when the SRAM bit and channel input are both at
logic “1”. Keep the SRAM bit to logic “0” when the channel
input is not in use. If the CB works in the LUT mode, the
channel input signal is routed though the inverse input of the
MUX and set corresponding SRAM bit to logic “1” while
other SRAM bits in the same wire-and line are kept at logic
“0”. In contrast to the LUT mode, several SRAM bits of the
same wire-and line may be set to logic “1” when the CB is
used in the PLA mode.

Figure 3 : Connection Box.

Figure 3. shows the internal structure of connection box

which contains vertical channel and the horizontal channels are
used to connect the routing channels with left and right
clusters. It consists of SRAM and Mos transistor connected
between horizontal and vertical channels.

2.2. A new hybrid FPGA architecture

The new hybrid FPGA architecture is based on symmetrical

FPGA, which utilizes existing CBs in implementing logic
functions. Its logic tiles can be configured as either PLAs or
LUTs. In the PLA mode, CBs are employed to implement the
AND plane and LUTs are used to realize the OR plane. While
in the LUT mode, it can be configured as LUT, which is the
same as general LUT-based FPGA. Figure 4 shows the CB Figure 5 : Detailed CB Architecture.
structure used in the hybrid FPGA. A 2 to 1 MUX with an
inverse input is used because both input and inverse input are 3. An on-line reconfigurable FPGA architecture
needed simultaneously in AND plane. So the number of PLA
inputs is 16, half of the channel width. Signals from routing FPGAs are widely used for prototyping of digital systems. A
channel can be programmably connected to the cluster major problem of current FPGA architectures is that if a there
inputs. All the connected signals to a cluster input are wire- is a fault in a single combinational logic block (CLB), it may
and connected and regarded as a product term. take a significant amount of time to find an alternative,
mapping of the circuit to bypass the faulty block. Thus, there
is a need for new type FPGA architectures that allow rapid
recovery from internal faults in a FPGA. Currently only the
detection of permanent faults in logic blocks, and on their
interconnections are considered in FPGA-based systems.
Reconfigurable FPGA architecture
An FPGA architecture to accommodate on-line error detection
and replacement of faulty CLBs by fault-free CLBs has been
proposed. Fig. 6 .shows the implementation of the CLB. Each
multiplexer has both normal and the complement value of its
data and control inputs, and its outputs are also
complementary.
Thus, a 2-to-1 multiplexer has six inputs and two outputs, and
a 4-to-1 multiplexer has twelve inputs and two outputs. The D
flip-flop also generates both normal output and its
complement. In the presence of a single fault in any of its
components, a CLB produces either 00 or 11 as output,
otherwise the outputs are 01 or 10. The CLBs are grouped into
a matrix of cells. Each cell contains four CLBs , three of
which can be interconnected to perform a logic function. The
fourth CLB is a spare, and is used to replace any of the other
three CLBs if any of these has a fault. Fig.6 shows the
structure of a cell. A cell has four inputs , all of which or a
subset of these can be routed to the inputs of a CLB. In
addition, a CLB can transfer data to or receive data from any
other CLB in the cell. For example , the outputs of CLBs A a
and B can be connected to the inputs of CLB C by enabling
links 5 and 1 I. Subsequently if one of the CLBs fails, it can be
replaced by the spare CLB S. Thus, as long as there is not
more than one faulty CLB in a cell , it can have three possible
configurations of CLBs. Each configuration of the three fault-
free CLBs can implement the original function.
Fig.6 Implementation of a CLB
Let us illustrate the fault tolerant capability of a cell by
implementing the following four-variable function using three
CLBs in a cell as shown in Fig. 3(a).
F (a,b,c,d) = afl + cfz
Where J=abd+ 6 c d + a c 2
And,
h = bfl + Ff,
Let us assume next that CLB C is faulty. An alternate
configuration of the CLBs that implements the original
function is shown in Fig.7. Note that in this configuration
spare CLB S replaces CLB C. Since the critical path delay in
a cell is equivalent to the propagation delays of any two CLBs
in series, the replacement of a faulty CLB by the spare does
not affect the critical path delay of a cell. In other words, the
rerouting of signals to achieve fault tolerance does not change
the timing of a circuit implemented using a cell of any two
CLBs in series, the replacement of a faulty CLB by the spare
does not affect the critical path delay of a cell. In other words,
the rerouting of signals to achieve fault tolerance does not
change the timing of a circuit implemented using a cell. Three
cells can be interconnected as shown in Fig. to form a super
cell. The spare CLBs if not used, can be interconnected to
form a spare super cell. Thus, if none of the cells in a super
cell has a faulty CLB the spares CLBs are utilized for normal
data processing. In addition to the cells, a supercell contains
an additional CLB; only a 440-1 multiplexer in this CLB is
used to transfer the output of one of the four possible
constituent cells to the output of the supercell. Normally the
select inputs of the multiplexer are set such that the output of
the supercell is derived from the output of cell C. This is
because cell C may use up to four CLBs in series ( the longest
path in a supercell ) to implement a certain function. It should
be clear from the configuration of a supercell that in the
absence of a faulty CLB, the supercell can make a 100%
utilization of all 12 CLBs in it. In the worst possible situation
i.e. the presence of a single faulty CLB in each of the
constituent cells, the CLB utilization in a supercell reduces to
75%.
Figure 7: Implementation of the Function.
\
Figure 8: Alternate Implementation.
4. FPGA Architecture.
FPGA contains tens of hundreds of thousands of gate s with
programmable interconnects, are available to the user for their
custom hardware programming. These design style provides a
means of fast prototyping and cost-effective chip design,
especially for low volume applications. FPGA consists of I/O
Buffers, an array of configurable logic blocks (CLBs), and
programmable interconnect structure. The programming of the
interconnects is accomplished by programming of RAM cells
whose output terminals are connected to the gates of the MOS
pass transistor. The CLBs offers significant flexibility of
implementing a wide range of functions, with up to nine input
variables. The complexity of a FPGA chip is typically
determined of the same by the number of CLBs it contains.
The largest advantage of FPGA based design is the very short
turn around time, i.e., the time required from the start of the
design process until a functional chip is available. The typical
price of FPGA chips is usually higher than other alternatives
of the same design style, but for small volume production of
ASIC chips and fast prototyping , FPGA offers a very valuable
option.
Figure 9: FPGA Architecture
5. Conclusion:
This paper include an FPGA architecture which is composed
of large matrix of programmable cells. Each cell contains
four configurable logic blocks (CLBs) out of which Three
CLBs in a cell can be interconnected to perform a logic
function. The fourth CLB is a spare, and is used to replace any
of the other three CLBs if any of these has a fault. Four cells
are grouped together to form a super cell. A CLB is designed
such that it is self-checking for any single ( permanent or
transient) fault in itself. If a cell has a faulty CLB, the
interconnecting links among the CLBs are reprogrammed such
that the faulty CLB is replaced with the spare. The new
configuration implements the original function. This technique
can be used in applications where on-line fault detection is
extremely important.
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