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Interrupts are important because they allow a system to respond asynchronously to an event and deal with the event
while in the middle of performing another task. An interrupt is the occurrence of a condition that causes a temporary
suspension of a program while the condition is serviced by another program.
The program that deals with an interrupt is called an interrupt service routine (ISR) or interrupt handler. The ISR
executes in response to the interrupt and generally performs a task to deal with the cause of the interrupt.When an
interrupt occurs, the main program temporarily suspends execution and branches to the ISR. The ISR executes,
performs the desired operation, and terminates and return from interrupt.
Main program
ISRx ISRy
Interrupt Handler
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or
external source meets a valid interrupt condition, the associated interrupt-pending flag is set to 1.These interrupt
flags are “level sensitive” in that if the flag is not cleared in the ISR by either hardware or software, the interrupt will
trigger again, even if the event that originally caused the interrupt did not occur again. All interrupts are disabled
after a system reset and enabled individually by software.
In the event of two or more simultaneous interrupts or an interrupt occurring while another is being serviced, there is
both a fixed priority order and two programmable priority levels to schedule the interrupts.
Each of the interrupt sources is individually enabled or disabled through the IE, EIE1 and EIE2 SFRs.
In addition to individual enable bits for each interrupt source, there is a global enable/disable bit, EA (IE.7) that is
cleared to disable all interrupts or set to turn on all enabled interrupts. Typically, two bits must be set to enable an
interrupt: the individual enable bit the global enable bit. Some interrupts need more than two bits to enable.
Example 1
Configure A C8051F120 mixed signal processor to have i) T0 interrupt enabled ii) T2 interrupt enabled iii) T0,
T1 and T2 interrupt enabled iv) EX0 and EX2 enabled.
(i) 1 0 0 0 0 0 1 0 IE |= 0x82;
(ii) 1 0 1 0 0 0 0 0 IE |= 0xA0;
(iii) 1 0 1 0 1 0 1 0 IE |= 0xAA;
(iv) 1 0 0 0 0 1 0 1 IE |= 0x85;
Example 2
Configure A C8051F120 mixed signal processor to have i) ADC0 window comparator interrupt enabled ii)
Programmable Counter Array interrupt enabled.
Example 3
Configure A C8051F120 mixed signal processor to have i) T4 ii) T3 iii) ADC0 iv) T3 and ADC0 interrupts
enabled.
Example 4
A C8051F120 mixed signal processor having an 3.0625 MHz internal clock is to be used to generate a 0.2 second
time delay. Pin 6 of the port 1 (P1^6 ) is to be toggled every 0.2 second.
(i) Using timer 0, determine the mode and the base number that must go into TH0 and TL0;
(ii) Write a C code to implement the (i) using timer interrupt;
(iii) Using timer 2, determine the mode and the base number that must go into RCAP2H and RCAP2L;
(iv) Write a C code to implement the (iii) using timer interrupt.
(i)
(i) Using timer 2, determine the mode and the base number that must go into RCAP2H and RCAP2L;
(ii) Write a C code to use Timer2 interrupt to generate the waveform.
(i)
Example 6
Use a C8051F120 mixed signal processor having a 3.0625 MHz internal clock is to sample a signal on Ain0.0 at 10
KHz (use values calculated in example 5) and put the results (ADC0H and ADC0L) on the P1 and P0 respectively.
Write a C code to use Timer 2 interrupt to sample the signal.
1. Repeat Use a C8051F120 mixed signal processor having a 3.0625 MHz internal clock is Write a suitable C
program to configure the ADC0 to send the conversion DAC0 with :-
i) An0 single ended, left justified, continuous tracking, and starts conversion with T2 interrupt every
1 mS;
ii) An0 and A1 as differential pair , left justified, continuous tracking , and start conversion with T3
interrupt every 2 mS.
3. Using the C8051F120 data sheet, determine the maximum sampling frequency that can be used with the
ADC0 for problem 1.