C8051F120 Interrupts

Interrupts are important because they allow a system to respond asynchronously to an event and deal with the event
while in the middle of performing another task. An interrupt is the occurrence of a condition that causes a temporary
suspension of a program while the condition is serviced by another program.

The program that deals with an interrupt is called an interrupt service routine (ISR) or interrupt handler. The ISR
executes in response to the interrupt and generally performs a task to deal with the cause of the interrupt.When an
interrupt occurs, the main program temporarily suspends execution and branches to the ISR. The ISR executes,
performs the desired operation, and terminates and return from interrupt.

Main program

ISRx ISRy

Main Main Main

The C8051F120 supports 22 interrupt sources, including:

• 4 external interrupts (/INT0, /INT1, Interrupt 6 and Interrupt 7)

• 5 timer interrupts (Timer 0 through 4 Overflow)
• 2 serial port interrupts (UART0, UART1)

Interrupt Handler
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or
external source meets a valid interrupt condition, the associated interrupt-pending flag is set to 1.These interrupt
flags are “level sensitive” in that if the flag is not cleared in the ISR by either hardware or software, the interrupt will
trigger again, even if the event that originally caused the interrupt did not occur again. All interrupts are disabled
after a system reset and enabled individually by software.

In the event of two or more simultaneous interrupts or an interrupt occurring while another is being serviced, there is
both a fixed priority order and two programmable priority levels to schedule the interrupts.

Each of the interrupt sources is individually enabled or disabled through the IE, EIE1 and EIE2 SFRs.
In addition to individual enable bits for each interrupt source, there is a global enable/disable bit, EA (IE.7) that is
cleared to disable all interrupts or set to turn on all enabled interrupts. Typically, two bits must be set to enable an
interrupt: the individual enable bit the global enable bit. Some interrupts need more than two bits to enable.

Note the following when using interrupts :-

♦ The RESET interrupt (interrupt 0) cannot be turned off, and always the highest priority;
♦ Each interrupt source can be individually programmed to one of two priority levels, low or high, through an
associated interrupt priority bit in the IP, EIP1 and EIP2 SFRs;
♦ These three SFRs are cleared after a system reset to place all interrupts at low priority by default;
♦ The two priority levels allow an ISR to be interrupted by an interrupt of higher priority than the current one
being serviced;
♦ A low priority ISR is pre-empted by a high priority interrupt;
♦ A high priority interrupt cannot be pre-empted.;
♦ Having two priority levels is useful because some events require immediate action, while some other events
can tolerate some delay in the response time.

M518 – Mixed Signal Processors : Hassan Parchizadeh Page 1

Interrupt Sources and Vectors

Source Vector Priority Flag Enable Flag Priority Control

Reset 0000 Top None Always Enabled Always Highest

External Interrupt 0 (/INT0) 0003 0 IE0 (TCON.1) EX (IE.0) PX0 (IP.0)
Timer 0 Overflow 000B 1 TF0 (TCON.5) ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/INT1) 0013 2 IE1 (TCON.3) EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 001B 3 TF1 (TCON.7) ET1 (IE.3) PT1 (IP.3)
RI0 (SCON0.0)
UART0 0023 4 ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
Timer 2 Overflow 002B 5 TF2 (T2CON.7) ET2 (IE.5) PT2 (IP.5)
Serial Peripheral Interface 0033 6 SPIF (SPI0CN.7) ESPI0 (EIE1.0) PSPI0 (EIP1.0)
SMBus Interface 003B 7 SI (SMB0CN.3) ESMB0 (EIE1.1) PSMB0 (EIP1.1)
PWADC0
ADC0 Window Comparator 0043 8 AD0WINT (ADC0CN.2) EWADC0 (EIE1.2)
(EIP1.2)
CF (PCA0CN.7) CCFn
Programmable Counter Array 004B 9 EPCA0 (EIE1.3) PPCA0 (EIP1.3)
(PCA0CN.n)
Comparator 0 Falling Edge 0053 10 CP0FIF (CPT0CN.4) ECP0F (EIE1.4) PCP0F (EIP1.2)
Comparator 0 Rising Edge 005B 11 CP0RIF (CPT0CN.5) ECP0R (EIE1.5) PCP0R (EIP1.5)
Comparator 1 Falling Edge 0063 12 CP1FIF (CPT1CN.4) ECP1F (EIE1.6) PCP1F (EIP1.6)
Comparator 1 Rising Edge 006B 13 CP1RIF (CPT1CN.5) ECP1R (EIE1.7) PCP1F (EIP1.7)
Timer 3 Overflow 0073 14 TF3 (TMR3CN.7) ET3 (EIE2.0) PT3 (EIP2.0)
ADC0 End of Conversion 007B 15 AD0INT (ADC0CN.5) EADC0 (EIE2.1) PADC0 (EIP2.1)
Timer 4 Overflow 0083 16 TF4 (T4CON.7) ET4 (EIE2.2) PT4 (EIP2.2)
ADC1 End of Conversion 008B 17 AD1INT (ADC1CN.5) EADC1 (EIE2.3) PADC1 (EIP2.3)
External Interrupt 6 0093 18 IE6 (P3IF.6) EX6 (EIE2.4) PX6 (EIP2.4)
External Interrupt 7 009B 19 IE7 (P3IF.7) EX7 (EIE2.5) PX7 (EIP2.5)
RI1 (SCON1.0) TI1
UART1 00A3 20 ES1 (EIE2.6) PS1 (EIP2.6)
(SCON1.1)
External Crystal OSC Ready 00AB 21 XTLVLD (OSCXCN.7) EXVLD (EIE2.7) PXVLD (EIP2.7)

Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described below. Here we look at
IE(Interrupt Enable) , EIE1 (Extended Interrupt Enable 1) , and EIE2 (Extended Interrupt Enable 2) registers for
enabling/disabling interrupts and IP (Interrupt Priority), EIP1 (Extended Interrupt Priority 1) and EIP1 (Extended
Interrupt Priority 2) for setting priority level of individual interrupts.

M518 – Mixed Signal Processors : Hassan Parchizadeh Page 2

IE: Interrupt Enable

Example 1
Configure A C8051F120 mixed signal processor to have i) T0 interrupt enabled ii) T2 interrupt enabled iii) T0,
T1 and T2 interrupt enabled iv) EX0 and EX2 enabled.

(i) 1 0 0 0 0 0 1 0 IE |= 0x82;

(ii) 1 0 1 0 0 0 0 0 IE |= 0xA0;

(iii) 1 0 1 0 1 0 1 0 IE |= 0xAA;

(iv) 1 0 0 0 0 1 0 1 IE |= 0x85;

M518 – Mixed Signal Processors : Hassan Parchizadeh Page 3

EIE1: Extended Interrupt Enable 1

Example 2
Configure A C8051F120 mixed signal processor to have i) ADC0 window comparator interrupt enabled ii)
Programmable Counter Array interrupt enabled.

(i) 0 0 0 0 0 1 0 0 EIE1 |= 0x04;

1 0 0 0 0 0 0 0 IE |= 0x80;

(ii) 0 0 0 0 1 0 0 0 EIE1 |= 0x04;

1 0 0 0 0 0 0 0 IE |= 0x80;

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EIE2: Extended Interrupt Enable 2

Example 3
Configure A C8051F120 mixed signal processor to have i) T4 ii) T3 iii) ADC0 iv) T3 and ADC0 interrupts
enabled.

(i) 0 0 0 0 0 1 0 0 EIE2 |= 0x04;

1 0 0 0 0 0 0 0 IE |= 0x80;

(ii) 0 0 0 0 0 0 0 1 EIE2 |= 0x01;

1 0 0 0 0 0 0 0 IE |= 0x80;

(iii) 0 0 0 0 0 0 1 0 EIE2 |= 0x02;

1 0 0 0 0 0 0 0 IE |= 0x80;

(iv) 0 0 0 0 0 0 1 1 EIE2 |= 0x03;

1 0 0 0 0 0 0 0 IE |= 0x80;

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IP: Interrupt Priority

EIP1: Extended Interrupt Priority 1

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EIP2: Extended Interrupt Priority 2

Example 4
A C8051F120 mixed signal processor having an 3.0625 MHz internal clock is to be used to generate a 0.2 second
time delay. Pin 6 of the port 1 (P1^6 ) is to be toggled every 0.2 second.

(i) Using timer 0, determine the mode and the base number that must go into TH0 and TL0;
(ii) Write a C code to implement the (i) using timer interrupt;
(iii) Using timer 2, determine the mode and the base number that must go into RCAP2H and RCAP2L;
(iv) Write a C code to implement the (iii) using timer interrupt.

(i)

If SCA1 = SCA0 = 0, then

Timer clock = internal oscilator / 12 = 3.0625MHz / 12 = 0.2552 MHz
Timer cycle time = 1/0.2552MHz = 3.918 uS
Delay Count = Delay Time/ Timer Cycle Time
= 0.2 S / 3.918 uS = 51046 ( nearest whole number )

Therefore 16–bit , mode 1

Base Number = 65535 – 51046 = 14489

TH0=38 and TL0 = 99

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(ii)
1 #include <c8051f120.h> // SFR declarations
2
3 sbit LED = P1^6; // green LED: '1' = ON; '0' = OFF
4 //------------------------------------------------------------------------------------------------
5 // Initialisation and other functions
6 //------------------------------------------------------------------------------------------------
7 void PORT_Init (void){
8 P1MDOUT |= 0x40; // enable P1.6 (LED) as push-pull output
9 XBR2 = 0x40; // Enable crossbar and weak pull-ups
10 }
11
12 void T0_init(void){
13 TCON = 0x00; // Stop Timer0; Clear TF0;
14 TMOD = 0x01; // use SYSCLK/12 as timebase
15 TH0 = 0x38; // set to 0.2 s
16 TL0 = 0x99;
17 ET0 = 1; // enable Timer0 interrupts
18 TR0 = 1; // start Timer3
19 }
20 //------------------------------------------------------------------------------------------------
21 // Interrupt Service Routines
22 //------------------------------------------------------------------------------------------------
23 void Timer0_ISR (void) interrupt 1 {
24 TH0 = 0x38; // set to reload immediately
25 TL0 = 0x99;
26 LED = ~LED; // change state of LED
27 }
28
29 //------------------------------------------------------------------------------------------------
30 // MAIN Routine
31 //------------------------------------------------------------------------------------------------
32 void main (void) {
33 WDTCN = 0xde; // disable watchdog timer
34 WDTCN = 0xad;
35
36 SFRPAGE = CONFIG_PAGE; // Switch to configuration page
37 PORT_Init();
38
39 SFRPAGE = TIMER01_PAGE; // Switch to Timer 0 page
40 T0_init();
41
42 EA = 1; // enable all interrupts
43
44 SFRPAGE = LEGACY_PAGE; // Page to sit in for now
45 while (1) {} // spin forever
46 }

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(iii)

TnM1 and TnM0: Timer Clock Mode Select Bits.

00: SYSCLK/12
01: SYSCLK
10: EXTERNAL CLOCK/8 (Synchronized to the System Clock)
11: SYSCLK/2

Clock and base number is as before, therefore :- RCAP2H = 38 and RCAP2L = 99

(iv) 1 #include <c8051f120.h> // SFR declarations

2
3 sbit LED = P1^6; // green LED: '1' = ON; '0' = OFF
4 //-------------------------------------------------------------------------
5 // Initialisation and other functions
6 //-------------------------------------------------------------------------
7 void PORT_Init (void){
8 XBR2 = 0x40; // Enable crossbar and weak pull-ups
9 P1MDOUT |= 0x40; // enable P1.6 (LED) as push-pull output
10 }
11
12 void T2_init(void){
13 RCAP2L = 0x4C; // Timer 2 reload values
14 RCAP2H = 0x9C;
15 TR2 = 1; // switch on timer 2
16 ET2 = 1; // enable Timer3 interrupts
17 }
18 //-------------------------------------------------------------------------
19 // Interrupt Service Routines
20 //-------------------------------------------------------------------------
21 void Timer2_ISR (void) interrupt 5 {
22 LED = ~LED; // change state of LED
23 }
24
25 //-------------------------------------------------------------------------
26 // MAIN Routine
27 //-------------------------------------------------------------------------
28 void main (void) {
29 WDTCN = 0xde; // disable watchdog timer
30 WDTCN = 0xad;
31
32 SFRPAGE = CONFIG_PAGE; // Switch to configuration page
33 PORT_Init();
34
35 SFRPAGE = TMR2_PAGE; // Switch to timer 2 page
36 T2_init();
37
38 EA = 1; // enable all interrupts
39
40 SFRPAGE = LEGACY_PAGE; // Page to sit in for now
41 while (1) {} // spin forever
42 }

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Example 5
Use a C8051F120 mixed signal processor having a 3.0625 MHz internal clock is to be used generate the following
waveform on the DAC0 output. The DAC0 samples are applied at 10 KHz intervals.

(i) Using timer 2, determine the mode and the base number that must go into RCAP2H and RCAP2L;
(ii) Write a C code to use Timer2 interrupt to generate the waveform.

(i)

TnM1 and TnM0: Timer Clock Mode Select Bits.

00: SYSCLK/12
01: SYSCLK
10: EXTERNAL CLOCK/8 (Synchronized to the System Clock)
11: SYSCLK/2

Timer clock = internal oscilator / 12 = 3.0625MHz / 12 = 0.2552 MHz

Timer cycle time = 1/0.2552MHz = 3.918 uS
Delay Count = Delay Time/ Timer Cycle Time
= 0.1 mS / 3.918 uS = 25 ( nearest whole number )

Therefore 16–bit , mode 1

Base Number = 65535 – 25 = 65510
therefore :- RCAP2H = FF and RCAP2L = E6

(ii) 1 #include <c8051f120.h> // SFR declarations

2 int i;
3 //-------------------------------------------------------------------------
4 // Initialisation and other functions
5 //-------------------------------------------------------------------------
6 void DAC_init(){
7 SFRPAGE = DAC0_PAGE;
8 REF0CN = 0x03; // Enable ADC/DAC internal Bias Generator,
9 DAC0CN = 0x80; // enable DAC0, and update on T2 overflow
10 }
11
12 void T2_Init() {
13 SFRPAGE = TMR2_PAGE; // Switch to timer 2 page
14 TMR2CF = 0x00; // system clk/12, no toggle, count up
15 RCAP2L = 0xE6; // Timer 2 reload values
16 RCAP2H = 0xFF;
17 TMR2H = 0xFF; // start with reload values
18 TMR2L = 0xE6;
19 ET2 = 1;
20 TR2 = 1; // switch on timer 2
21 }
22
23 //-------------------------------------------------------------------------
24 // Interrupt Service Routines
25 //-------------------------------------------------------------------------

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 26 void Timer2_ISR (void) interrupt 5 {
27 SFRPAGE = DAC0_PAGE; // Switch to timer 2 page
28 DAC0L = i % 256;
29 DAC0H = i / 256;
30 i++;
31 if(i==4094) i=0;
32 }
33
34 //-------------------------------------------------------------------------
35 // MAIN Routine
36 //-------------------------------------------------------------------------
37 void main (void) {
38 WDTCN = 0xde; // disable watchdog timer
39 WDTCN = 0xad;
40
41 T2_Init();
42 DAC_init();
43
44 EA = 1; // enable all interrupts
45 i=0;
46 SFRPAGE = LEGACY_PAGE; // Page to sit in for now
47 while (1) {} // spin forever
48 }

Example 6
Use a C8051F120 mixed signal processor having a 3.0625 MHz internal clock is to sample a signal on Ain0.0 at 10
KHz (use values calculated in example 5) and put the results (ADC0H and ADC0L) on the P1 and P0 respectively.
Write a C code to use Timer 2 interrupt to sample the signal.

1 #include <c8051f120.h> // SFR declarations

2
3 //-------------------------------------------------------------------------
4 // Initialisation and other functions
5 //-------------------------------------------------------------------------
6 void Port_IO_Init(){
7 SFRPAGE = CONFIG_PAGE; // set SFR page
8 P0MDOUT = 0xFF; // P0 as push-pull output
9 P1MDOUT = 0xFF; // P1 as push-pull output
10 XBR2 = 0x40; // Enable Xbar and hence P0 and P1
11 }
12
13 void ADC_Init() {
14 SFRPAGE = ADC0_PAGE; // set SFR page
15 REF0CN = 0x03; // Enable ADC/DAC internal Bias Generator,
16 // and internal VREF output buffer
17 AMX0CF = 0x00; // AIN0.0 as single-ended input
18 AMX0SL = 0x00; // AIN0.0 ADC Input selected
19
20 ADC0CN = 0x8C; // enabled, normal tracking, conversions are
21 }
22
23 void T2_Init() {
24 SFRPAGE = TMR2_PAGE; // Switch to timer 2 page
25 TMR2CF = 0x00; // systemclk/12, no toggle, count up
26 RCAP2L = 0xE6; // Timer 2 reload values

M518 – Mixed Signal Processors : Hassan Parchizadeh Page 11

 27 RCAP2H = 0xFF;
28 TMR2H = 0xFF; // start with reload
29 TMR2L = 0xE6;
30 ET2 = 1;
31 TR2 = 1; // switch on timer 2
32 }
33
34 //-------------------------------------------------------------------------
35 // Interrupt Service Routines
36 //-------------------------------------------------------------------------
37 void Timer2_ISR (void) interrupt 5 {
38 SFRPAGE = ADC0_PAGE; // Switch to timer 2 page
39 P1 = ADC0H; // high byte to P1
40 P0 = ADC0L; // low byte to P0
41 }
42
43 //-------------------------------------------------------------------------
44 // MAIN Routine
45 //-------------------------------------------------------------------------
46 void main (void) {
47 WDTCN = 0xde; // disable watchdog timer
48 WDTCN = 0xad;
49
50 Port_IO_Init();
51 ADC_Init();
52 T2_Init();
53
54
55 EA = 1; // enable all interrupts
56
57 SFRPAGE = LEGACY_PAGE; // Page to sit in for now
58 while (1) {} // spin forever
59 }

Exercises : Showing the C code for each :-

1. Repeat Use a C8051F120 mixed signal processor having a 3.0625 MHz internal clock is Write a suitable C
program to configure the ADC0 to send the conversion DAC0 with :-

i) An0 single ended, left justified, continuous tracking, and starts conversion with T2 interrupt every
1 mS;
ii) An0 and A1 as differential pair , left justified, continuous tracking , and start conversion with T3
interrupt every 2 mS.

2. Repeat the above for DAC1.

3. Using the C8051F120 data sheet, determine the maximum sampling frequency that can be used with the
ADC0 for problem 1.

4. Repeat 3. For DAC0.

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