C8051F120 Digital to Analogue Converters (DACs)

The C8051F12x devices include two on-chip 12-bit voltage-mode DACs. Each DAC has an output swing of 0 V to
(VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The DACs may be enabled/disabled via
their corresponding control registers, DAC0CN and DAC1CN. The voltage reference for each DAC is supplied at
the VREFD pin. If the internal voltage reference is used it must be enabled in order for the DAC outputs to be valid.

DAC Output Scheduling

Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and
supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0,
but DAC1 operation is identical. The DACs output update could be done in two ways as follows :-

i ) Update Output On-Demand

In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” on a write to the high byte of
the DAC0 data register (DAC0H). It is important to note that writes to DAC0L are held, and have no effect on the
DAC0 output until a write to DAC0H takes place. Data is latched into DAC0 after a write to the corresponding
DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is
required.

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ii ) Update Output Based on Timer Overflow

DAC output update, can be initiated by a Timer overflow. This feature is useful in systems where the DAC is used
to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and
instruction execution on the timing of the DAC output. When the DAC0MD bits (DAC0CN.[4:3]) are set to ‘01’,
‘10’, or ‘11’, writes to both DAC data registers (DAC0L and DAC0H) are held until an associated Timer overflow
event (Timer 3, Timer 4, or Timer 2, respectively) occurs, at which time the DAC0H:DAC0L contents are copied to
the DAC input latches allowing the DAC output to change to the new value.

DAC0CN: DAC0 Control register

DAC Output Scaling/Justification

In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data
within the DAC input registers. This action would typically require one or more load and shift operations,
adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting feature
provides a means for the user to program the orientation of the DAC0 data word within data registers
DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data
word orientations as shown in the DAC0CN register definition.

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Reference Configuration on the C8051F120
On the C8051F120, the REF0CN register allows selection of the voltage reference source for ADC0 and ADC2. Bits
AD0VRS and AD2VRS in the REF0CN register select the ADC0 and ADC2voltage reference sources, respectively.
Three voltage reference input pins allow each ADC and the two DACs to reference an external voltage reference or
the on-chip voltage reference output (with an external connection). ADC0 may also reference the DAC0 output
internally, and ADC2 may reference the analogue power supply voltage, via the VREF multiplexers shown below.

REF0CN: Reference Control Register C8051F120

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Example 1

Configure DAC0 of A C8051F120 mixed signal processor for 12-bit operation with :-

a) The LSB in DAC0L with update occurring on i) write to DAC0H, ii) Timer 3 overflow iii) Timer 4
and iv) Timer 2 over flow.

b) The MSB in DAC0H with update occurring on i) write to DAC0H, ii) Timer 3 overflow iii) Timer 4
and iv) Timer 2 over flow.

a) (i) DAC0CN = 0x80; (ii) DAC0CN = 0x88; (iii) DAC0CN = 0x90; (iv) DAC0CN = 0x98;

b) (i) DAC0CN = 0x84; (ii) DAC0CN = 0x8C; (iii) DAC0CN = 0x94; (iv) DAC0CN = 0x9C;

Example 2
Write a suitable C program to generate a saw-tooth wave on the DAC0 output.

#include "c8051F120.h"
void main (void) {
char convHigh, convLow;
int i;

WDTCN = 0xde; // disable watchdog timer

WDTCN = 0xad;

SFRPAGE = DAC0_PAGE;
DAC0CN = 0x80; // enable DAC0, and update on write to DAC0H

REF0CN = 0x03; // Enable ADC/DAC internal Bias Generator

// and internal VREF output buffer
while (1) {
for(i=0; i<4093; i++) {
convHigh = (char) i/256; // calculate the value for DAC0 High byte
convLow = (char) i%256; // calculate the value for DAC0 Low byte
DAC0L = convHigh; // set the low byte
DAC0H = convLow; // set the high byte and update DAC0 output
}
}
}

Exercises : Showing the C code for each :-

1. Configure DAC0CN to have DAC0H and DAC0L data format as :-

i) ii)

iii) iv)

2. Modify the program in example 2, to generate a Square waveform.

3. Modify the program in Exercise 2, to use data format in iv) Exercise 1.

4. Modify the program in Exercise 3, to generate a triangular waveform.

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