EC1031 VLSI Design Lab: Course Description

Academic Course Description

SRM University
Faculty of Engineering and Technology
Department of Electronics and Communication Engineering

EC1031 VLSI Design Laboratory

Seventh Semester, 2016-17 (odd semester)

Course description
This course provides an introduction to the design and implementation of VLSI circuits for complex digital
systems using Verilog HDL. An idea about synthesis and timing analysis of a design can be performed using
Xilinx Tool and ModelSim for simulation of HDL design.

Compulsory/Elective course: Compulsory for ECE students

Credit hours: 2 credits

Laboratory
DSP Lab, Room No.TP9L3,
VLSI Simulation Lab, Room No.TP11L4

Course coordinator(s):
Mrs.A.Maria Jossy , Assistant Professor (OG), Department of ECE
Instructor(s)

Class Office Office Email (domain:

Name of the instructor Consultations
handling location phone @ktr.srmuniv.ac.in)
[Day Order 2
- P13 - P14]
Mr.A.V.M.Manikandan [Day Order 1
- P8 - P9]
[Day Order 2
- P13 - P14]
Mrs.E.Chitra [Day Order 3
- P28 - P29]
[Day Order 3
- P28 - P29]
Mrs.V.Sarada [Day Order 5
- P48 - P49]
[Day Order 1
- P3 - P4]
Mrs.P.Radhika [Day Order 4
- P38 - P39]
[Day Order 4
- P38 - P39]
Mrs.A.Mariajossy [Day Order 1
- P3 - P4]
Mrs. K. Ferents Koni [Day Order 4
- P33 - P34]
Jiavana [Day Order 2

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 EC1031 VLSI Design Lab: Course Description
Class Office Office Email (domain:
Name of the instructor Consultations
handling location phone @ktr.srmuniv.ac.in)
- P18 - P19]

[Day Order 5
- P43 - P44]
Mrs.J.Kasturibha [Day Order 2
- P18 - P19]
[Day Order 5
- P43 - P44]
Mr.B.Srinth [Day Order 3
- P23 - P24]
[Day Order 5
- P48 - P49]
Mr.S.Nivash [Day Order 3
- P23 - P24]
[Day Order 1
- P8 - P9]
Mr.R.Prithviraj [Day Order 4
- P33 - P34]

Relationship to other courses

Pre-requisites: EC1010 – Digital Systems Lab
Co-requisites: EC1029 - VLSI Design
Assumed knowledge: EC1010- Digital Electronics

Following courses: Nil

Text book(s) and/or required materials: Lab manual; additional materials posted on SRM web.

References
1. LAB MANUAL, Department of ECE, SRM University.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL”, Prentice Hall Higher Education,
2010,
3. Edition 2.
4. Bhaskar J, “A VHDL Primier”, Prentice Hall, 3rd Edition, 1999.
5. Douglas L.Perry, “VHDL:Prigramming by Example”, McGraw-Hill, 2002.
6. Charles H.Roth, Lizy Kurian John, “Digital systems design using VHDL”, Thomson, 2008.
Computer usuage
Xilinx and Modelsim is used to synthesis and simulate the design and to verify the
functionality.
Hardware Laboratory Usage
Each laboratory station is equipped with computer with the simulation software
loaded. Students work individually and maintain individual laboratory notebooks and submit
individual reports.

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 EC1031 VLSI Design Lab: Course Description
Class / Lab schedule: one 105 minutes lab session per week, for 14-15 weeks
Batch Schedule
Y4 Day 1 (2,3), TP9L3
X3 Day 1 (6,7), TP9L3
X4 Day 2 (2,3), TP9L3
Y8 Day 2 (6,7), TP9L3
Y1 Day 3 (2,3), TP9L3
X6 Day 3 (6,7), TP9L3
X7 Day 4 (2,3), TP9L3
Y5 Day 4 (6,7), TP9L3
Y9 Day 5 (2,3,), TP9L3
X5 Day 5 (6,7), TP9L3
Y2 Day 1 (2,3),TP11L4
X1 Day 1 (6,7),TP11L4
X2 Day 2 (2,3),TP11L4
Y1 Day 2 (6,7),TP11L4
Y10 Day 3 (2,3),TP11L4
X9 Day 3 (6,7),TP11L4
X10 Day 4 (2,3),TP11L4
Y3 Day 4 (6,7),TP11L4
Y11 Day 5 (2,3),TP11L4
X8 Day 5 (6,7),TP11L4
Professional component
General - 0%
Basic Sciences - 0%
Engineering sciences & Technical arts - 0%
Professional subject - 100%

Broad area: Communication | Signal Processing | Electronics | VLSI | Embedded

Mapping of Instructional Objectives with Program Outcome

Correlates to
This course provides the foundation education in circuit analysis. Through Student
lecture, laboratory, and out-of-class assignments, students are provided Outcome
learning experiences that enable them to:
H M L

1. To apply concepts and methods of digital system design techniques

b,c,d,f,k
as discussed in the class (EC1029) through hands-on experiments.

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 EC1031 VLSI Design Lab: Course Description

2. Learn to design combinational and sequential digital systems starting

from a word description that performs a set of specified tasks and
functions. b,c,d,f,k

3. To analyze the results of logic and timing simulations and to use

these simulation results to debug digital systems. b,c,d,f,k

4. Develop skills, techniques and learn state-of-the-art engineering

tools (such as HDL, Xilinx / Altera tools) to design, implement and b,c,d,f,k
test digital systems on FPGAs / CPLDs.

H: High correlation, M: Medium correlation, L: Low correlation

List of Experiments:

No. Lab Experiments Sessions

0 Tutorial Lab 1
1 Design Combinational logic circuit 2
Design Sequential logic circuit
2 2
Design of VLSI multipliers
3 2
Design of Multiply-Accumulate circuits
4 1
Design of Digital Filters
5 1
Design of State Machines
6 1
7 Design of microprocessor parts (Mini Project) 2

Mapping of Instructional Objective with experiments:

Lab Experiments IO #1 IO #2 IO #3 IO #4
1 Design Combinational logic circuit X X X X
Design Sequential logic circuit
2 X X X X
Design of VLSI multipliers
3 X X X X
4 Design of Multiply-Accumulate circuits X X X X

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 EC1031 VLSI Design Lab: Course Description

Design of Digital Filters

5 X X X X
Design of State Machines
6 X X X X
7 Design of microprocessor parts X X X X

Evaluation methods
Internal Assessment Marks: 60 End Semester Examination Marks: 40

Carrying out lab work & Report : 30 Design Procedure : 15

Attendance : 05 HDL Code : 15
Mini Project : 05 Result : 05
Model Exam : 20 Viva-Voce : 05

Laboratory Policies and Report Format

Reports are due at the beginning of the lab period. The reports are intended to be a complete
documentation of the work done in preparation for and during the lab. The report should be complete so
that someone else familiar with digital design could use it to verify your work. The prelab and postlab
report format is as follows:

1. A neat thorough pre-lab must be presented to your Staff In-charge at the beginning of your scheduled
lab period. Lab reports should be submitted on A4 paper. Your report is a professional presentation of
your work in the lab. Neatness, organization, and completeness will be rewarded. Points will be deducted
for any part that is not clear.

2. In this laboratory students will work and prepare the lab report individually. Please use the following
format for your lab reports.
a. Cover Page: Include your name, Subject Code, Section No., Experiment No. and Date.
objectives: Enumerate 3 or 4 of the topics that you think the lab will teach you. DO NOT REPEAT the
wording in the lab manual procedures. There should be one or two sentences per objective. Remember,
you should write about what you will learn, not what you will do.
c. Design and simulation: This part contains all the steps required to arrive at your final stage. This
should include all input and output waveforms, explanations, etc. This section should also include a clear
and error free program description of your design process. Simply including a circuit schematic is not
sufficient.
e. Questions: Specific questions(Prelab and Postlab) asked in the lab should be answered here. Retype
the questions presented in the lab and then formally answer them.
3. Your work must be original and prepared independently. However, if you need any guidance or have
any questions or problems, please do not hesitate to approach your staff in-charge during office hours.

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 EC1031 VLSI Design Lab: Course Description
Copying any pre-lab /post-lab will result in a grade of 0. The incident will be formally reported to the
University and the students should follow the dress code in the Lab session.
4. Each laboratory exercise (simulation results) must be completed and demonstrated to your Staff In-
charge in order to receive working design model credit. This is the procedure to follow:
a. Design model works: If the design model works during the lab period (2 hours), call your staff in-
charge and he/she will sign and date it. This is the end of this lab, and you will get a complete grade for
this portion of the lab.
b. Design model does not work: If the Design model does not work, you must make use of the open
times for the lab room to complete your experiment. When your design model is ready, contact your
staff in-charge to set up a time when the two of you can meet to check your simulation.
5. Attendance at your regularly scheduled lab period is required. An unexpected absence will result in
loss of credit for your lab. If for valid reason a student misses a lab, or makes a reasonable request in
advance of the class meeting, it is permissible for the student to do the lab in a different section later in
the week if approved by the staff in-charge of both the sections. Habitually late students (i.e., students
late more than 5 minutes more than once) will receive 5 point reductions in their grades for each
occurrence following the first.
6. Final grade in this course will be based on laboratory assignments. All labs have an equal weight in the
final grade. Grading will be based on pre-lab work, laboratory reports, post-lab and in-lab performance
(i.e., completing lab, answering laboratory related questions, etc.,).The Staff In-charge will ask pertinent
questions to individual members of a team at random. Labs will be graded as per the following grading
policy:
Pre-Lab Work 05 Marks
In-Lab Performance 10 Marks
Post Lab Work 05 Marks
Laboratory Report 10 Marks
7. Reports Due Dates: Reports are due one week after completion of the corresponding lab.
8. Systems of Tests: Regular laboratory class work over the full semester will carry a weight age of 60%.
The remaining 40% weightage will be given by conducting an end semester practical examination for
every individual student if possible or by conducting a 1 to 1 ½ hours duration common written test for
all students, based on all the experiment carried out in the semester.

Prepared by: Mrs.A.Maria Jossy, Assistant Professor, Department of ECE

Dated: 29th June 2016 Revision No.: 00 Date of revision: NA

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 EC1031 VLSI Design Lab: Course Description
Addendum

Student Outcomes of B.Tech ECE program:

(a) an ability to apply knowledge of mathematics, science, and engineering
(b) an ability to design and conduct experiments, as well as to analyze and interpret data
(c) an ability to design a system, component, or process to meet desired needs within realistic constraints
such as economic, environmental, social, political, ethical, health and safety, manufacturability, and
sustainability
(d) an ability to function on multidisciplinary teams
(e) an ability to identify, formulate, and solve engineering problems
(f) an understanding of professional and ethical responsibility
(g) an ability to communicate effectively
(h) the broad education necessary to understand the impact of engineering solutions in a global, economic,
environmental, and societal context
(i) a recognition of the need for, and an ability to engage in life-long learning
(j) a knowledge of contemporary issues
(k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

Program Educational Objectives

PEO1: Graduates will perform as a successful professional engineer in related fields of Electronics and
Communication Engineering.
PEO2: Graduates will pursue higher education and/or engage themselves in continuous professional
development to meet global standards.
PEO3: Graduates will work as a team in diverse fields and gradually move into leadership positions.
PEO4: Graduates will understand current professional issues, apply latest technologies and come out with
innovative solutions for the betterment of the nation and society.

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 EC1031 VLSI Design Lab: Course Description

Course Teachers Class Signature

[Day Order 2
- P13 - P14]
Mr.A.V.M.Manikandan [Day Order 1
- P8 - P9]
[Day Order 2
- P13 - P14]
Mrs.E.Chitra [Day Order 3
- P28 - P29]
[Day Order 3
- P28 - P29]
Mrs.V.Sarada [Day Order 5
- P48 - P49]
[Day Order 1
- P3 - P4]
Mrs.P.Radhika [Day Order 4
- P38 - P39]
[Day Order 4
- P38 - P39]
Mrs.A.Mariajossy [Day Order 1
- P3 - P4]
[Day Order 4
Mrs. K. Ferents Koni - P33 - P34]
Jiavana [Day Order 2
- P18 - P19]
[Day Order 5
- P43 - P44]
Mrs.J.Kasturibha [Day Order 2
- P18 - P19]
[Day Order 5
- P43 - P44]
Mr.B.Srinth [Day Order 3
- P23 - P24]
[Day Order 5
- P48 - P49]
Mr.S.Nivash [Day Order 3
- P23 - P24]
[Day Order 1
- P8 - P9]
Mr.R.Prithviraj [Day Order 4
- P33 - P34]

Course Coordinator Academic Coordinator Professor In-Charge HOD

(A.Maria Jossy) (Mrs. N. Saraswathi) (Dr. B. Ramachandran) (Dr.T. Rama Rao)

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