2220 IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 33, NO.

4, DECEMBER 2018

A New Diode-Clamped Multilevel Inverter With

Balance Voltages of DC Capacitors
Shunji Shi , Xiangzhou Wang, Shuhua Zheng , Yanxi Zhang , and Dongyuan Lu

Abstract—This paper proposes a new diode-clamped multilevel

inverter that can effectively balance the voltages of dc capacitors.
For the proposed inverter, the inductors are inserted between the
diodes and the main switches. Also, the voltage balance of the
dc capacitors can be guaranteed by controlling the opening time
of the corresponding main switches in particular modes. Thus,
the parallel circuits on the dc side in the conventional inverters
are canceled. Consequently, the proposed topology requires fewer
switches, diodes, and capacitors, although it adds the compensation
currents to the corresponding main switches. Both the simulation
and experimental results demonstrate the suitability and applica-
bility of the proposed topology.
Index Terms—Compensating current, diode-clamped, inserted
inductor, multilevel inverter, voltage balance.

I. INTRODUCTION
ITH the increase in the output power density of power
W inverters, multilevel inverters have become the subject
of extensive research [1], [2]. Multilevel inverters have the
following advantages over conventional two-level inverters:
high-quality waveforms, low switching losses, high-voltage
capability and low electromagnetic interference (EMI) [3],
[4]. In general, multilevel inverters can be classified into three
types: diode-clamped multilevel inverters (DCMLIs), flying
capacitor multilevel inverters and cascaded multilevel inverters
with separated DC sources [10]–[12].
Among these inverters, the DCMLI has attracted the most at-
tention because its DC capacitors are easily precharged [5], [6];
moreover, it offers simple switch control and a low-complexity
protection circuit [13]–[15]. Unfortunately, the output voltage Fig. 1. Method to install the parallel circuit on the DC side of the inverter.
imbalance of a DCMLI occurs when number of its output voltage (a) Conventional chopper. (b) Three-level flying capacitor-based chopper.
levels exceeds three. Therefore, maintaining a balance between (c) Voltage-balancing circuit on an RSCC. (d) Parallel switch-based chopper
circuit.
the DC capacitor voltages is essential for the DCMLI to function
properly [16].
switches [17], [18]. However, this approach requires a com-
Two approaches are proposed to maintain the balance of
plex control system. The second approach involves installing
the DC capacitor voltages. The first approach is changing the
a parallel circuit on the DC side of the inverters [7]–[9]. In
switching pattern and optimizing the control methods of the
this approach, four schemes are proposed: a conventional chop-
per circuit (Fig. 1(a)), a flying capacitor-based chopper circuit
Manuscript received January 6, 2018; revised May 25, 2018; accepted July 19, [16] (FCBC) (Fig. 1(b)), a circuit based on resonate switched-
2018. Date of publication August 6, 2018; date of current version November 21,
2018. This work was supported by the Natural Key Technology Support Program capacitor converter (RSCC) [19]–[21] (Fig. 1(c)), and a parallel
of Ministry of Science and Technology, China, under Grant 2014BAF08B06. switch-based circuit (PSBC) (Fig. 1(d)) [22]. However, all these
Paper no. TEC-01031-2017. (Corresponding author: Shuhua Zheng.) schemes require many extra devices. When used in a five-level
The authors are with the School of Automation, Beijing Institute
of Technology, Beijing 100081, China (e-mail:, 18001322660@163.com; inverter, the conventional chopper circuit requires four switches
wangxiangzhou@bit.edu.cn; zhengshuhua@bit.edu.cn; 2624590984@qq.com; and two inductors, and the peak voltage of the extra switches is
15652360430@163.com). twice that of the main switches. The FCBC can reduce the peak
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. voltage to the same as that of the main switch but requires dou-
Digital Object Identifier 10.1109/TEC.2018.2863561 ble the switches and two additional capacitors. Furthermore, its
0885-8969 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
SHI et al.: NEW DIODE-CLAMPED MULTILEVEL INVERTER WITH BALANCE VOLTAGES OF DC CAPACITORS
Fig. 2. Conventional diode clamped five-level inverter. (a) Conventional
topology. (b) Conventional modulation strategy.
control system is very complex. The RSCC reduces the number
of extra capacitors and inductors on the basis of the FCBC. The
PSBC requires only three switches and has a simplified control
system; however, it requires three diodes and an inductor.
This paper proposes a new diode-clamped multilevel inverter
that balances the voltages of the DC capacitors. The proposed
topology requires no parallel circuit on the DC side and no com-
plex control system. Instead, it simply inserts inductors between
the diodes and main switches and extends the opening time of
some of the main switches in some particular modes. There is no
need for additional switches, diodes, capacitors or drive circuits,
although the currents through some of the switches slightly in-
crease. Hence, the cost can be greatly reduced. The simulation
and experimental results validate the proposed topology.
II. ANALYSIS OF CAPACITOR-VOLTAGE-IMBALANCE
IN DCMLIS
Before introducing the new topology, the cause of voltage
imbalance in DCMLIs is analyzed. For a five-level inverter
(Fig. 2(a)), the modulation method shown in Fig. 2(b) is ap-
plied. By taking point n as the neutral reference, the following
assumptions can be made to simplify the theoretical analysis:
1) All the switches and diodes are ideal.
2) All the capacitors are ideal, and C1 = C2 = C1 = C2
= C.
3) All the inductors are ideal, and L1 = L1 = L.
4) The load is a resistor R.
In Fig. 2(a), the input voltage on the DC side is Vdc . The
expected voltage through each capacitor is Vdc /4. Fig. 3 shows
five different modes of a conventional inverter. The output volt-
ages corresponding to i0 , i1 , i2 , i1 , and i0 are Vdc /2, Vdc /4, 0,
−Vdc /4 and −Vdc /2, respectively.
In mode (a), the output voltage is Vdc /2, and the output cur-
rent is i0 = Vdc /2R. i0 is divided into i01 and i02 . i02 discharges
capacitors C1 and C1 , and i01 charges capacitors C1 and C2 .
Similarly, in mode (e), the output voltage is −Vdc /2, and the
absolute value of the output current is |i0 | = Vdc /2R. The direc-
tion of the output current is shown in 3(e). i0 is divided into i01
2221
Fig. 3. Corresponding output current in five different modes (a), (b), (c), (d),
and (e).
and i02 . i01 discharges capacitors C1 and C2 , and i02 charges
capacitors C1 and C2 . As C1 = C2 = C1 = C2 , i01 = i02 =
i01 = i02 = Vdc /4R. Because the capacitor’s charge current is
equal to its discharge current, voltage imbalance does not occur
in modes (a) and (e).
In mode (c), voltage imbalance does not occur because the
output voltage and current are zero.
In mode (b), the system can be analyzed in the same manner.
i1 is divided similarly to i0 in mode (a). Capacitors C1 , C3 and
C4 are charged by i11 , and capacitor C2 is discharged by i12 . In
contrast to mode (a), the output voltage is Vdc /4, and the output
current is i1 = Vdc /4R. Similarly, in mode (d), the output volt-
age is −Vdc /4, and the absolute value of the output current is
|i1 | = Vdc /4R. Fig. 3(d) displays the direction of the output cur-
rent. Capacitor C2 is discharged by i11 . Capacitors C1 , C2 and
C1 are simultaneously charged by i12 . Current i1 is composed
of i11 and i12 . i11 = i12 = 3i11 = 3i1 /4 = 3Vdc /16R, and
i12 = i11 = i1 /4 = Vdc /16R. The calculation results above il-
lustrate that the charge and discharge currents of the capacitors
are not equal in one cycle. As a result, the voltages across C2
and C2 decrease, and the voltages across C1 and C1 increase.
The voltage deviation ΔU of the capacitor in one cycle is given
by
i1 t1 t1 Vdc
ΔU = = (1)
C 4CR
where t1 is the duration of i1 , which is shown in Fig. 2(b).
III. COMPENSATION PRINCIPLE OF THE PROPOSED TOPOLOGY
The proposed topology and its modulation method are shown
in Fig. 4. As shown in Fig. 4(b), switch S1 must be turned on
for an additional finite time tb when the output voltage is Vdc /2.
Similarly, switch S4 must be turned on for time tb when the
output voltage is −Vdc /2. In this manner, the capacitor voltages
can be balanced.
The mode of output voltage Vdc /2 can be used as an example.
As shown in Fig. 5(a), when switch S1 is on, the voltage across
inductor L1 is VL 1 = VC 1 = Vdc /4. Current iL 1 flows through
switches S1 − S4 and S1 and increases from 0 A. Current iL 1
is divided into iL 11 and iL 12 . iL 11 discharges capacitor C2 ,
and iL 12 charges capacitors C2 , C3 and C4 . Therefore, iL 11 =
3iL 1 /4 and iL 12 = iL 1 /4.
Fig. 5(b) depicts the complementary mode of Fig. 5(a). Switch
S1 is turned off, so the inductor current iL 1 flows through the
2222 IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 33, NO. 4, DECEMBER 2018

Fig. 7. Proposed topology of (2n + 1)-levels. (a) Circuit diagram. (b) Mode
of output current im . (c) Mode of output current im . (d) Mode of compensating
current iL m .

Fig. 4. Proposed topology and the modulation method. (a) New topology. pensation operation is given as follows:
(b) Modulation method.
(tb + tr ) × IM L 1 t2 Vdc
QL = = b (2)
2 6L1

The compensated voltage across one capacitor is given by

QL Vdc t2b
ΔUb1 = = (3)
C 24L1 C
There are two compensation opportunities during one cycle.
The total compensated voltage increment is given by
Vdc t2b
ΔUb = 2ΔUb1 = (4)
12L1 C
The capacitor voltages can be balanced when ΔUb = ΔU .
Then,
t2bm R
L1 = (5)
3t1
Fig. 5. Proposed topology. (a) State of circuit at tb . (b) State of circuit at tr .
Moreover, the restricting conditions are
t b + t r < t1 (6)
Vdc
LM L 1 + < IM (7)
2R
where IM is the maximum current of the main switch.
Because the total voltage across C1 and C2 is invariant in
one cycle, only maintaining the voltage across capacitor C2 at
Vdc /4 is sufficient. Fig. 6(b) shows the control strategy of the
proposed topology.

IV. APPLICABILITY OF THE PROPOSED TOPOLOGY

Fig. 6. Proposed topology. (a) Compensating current waveform.

(b) Controlling strategy.
antiparallel diodes of switches S2 − S4 . The voltage across L1
is VL 1 = −3VC 1 = −3Vdc /4. Next, current iL 1 begins to de-
crease. As shown in Fig. 6(a), tb is the compensating time, and
tr is the time during which current iL 1 declines. The relation-
ship between tb and tr is tr = tb /3. In this mode, iL 1 reaches
the peak of tb Vdc /4L1 . The charge QL obtained from one com-
The proposed topology can be used for not only a five-level
system but also a (2n + 1)-level system, as shown in Fig. 7(a). A
comparison of the number of additional devices required for the
different schemes is presented in Table I. The proposed topology
decreases the number of additional devices significantly. This
advantage becomes more prominent as the number of levels
increases.
The compensation strategy for a (2n + 1)-level system is
similar to that of a five-level system. The following assumptions
can be made to simplify the theoretical analysis:
SHI et al.: NEW DIODE-CLAMPED MULTILEVEL INVERTER WITH BALANCE VOLTAGES OF DC CAPACITORS 2223

TABLE I
THE NUMBER OF EXTRA DEVICES IN DIFFERENT SCHEMES WHEN
USED IN A (2n+1)-LEVEL INVERTER

Fig. 9. Strategy of the proposed topology.

TABLE II
Fig. 8. Proposed topology of (2n + 1)-levels. (a) Output voltage waveform. SIMULATION PARAMETERS
(b) Compensating current waveform.

1) The output of the (2n + 1)-level inverter is assumed to be

as shown in Fig. 7(a).
2) Corresponding inductors (for example, L1 and L1 ) have
the same value. During one cycle, there are two opportunities to compensate
Similar to the five-level inverter, in the (2n + 1)-level inverter, for m = 1 and four opportunities to compensate for m > 1.
currents i0 and i0 shown in Fig. 7(b) and (c) do not cause volt- Then,
age imbalance. When output voltage VO M = mVdc /2n (0 < (2n − m + 1) Rt2bm
m < n), output current im is divided into im 1 and im 2 . im 2 Lm = , m=1 (11)
4 (2n − m) (n − m) tm
discharges capacitors Cm +1 − Cn , and im 1 charges the other
(n + m) capacitors. Complementarily, when output voltage (2n − m + 1) Rt2bm
Lm = , m>1 (12)
VO M = −mVdc /2n, output current im is divided into im 1 and 2 (2n − m) (n − m) tm
im 2 . im 1 discharges capacitors Cm  
+1 − Cn , and im 2 charges Equations (9), (11) and (12) show the relationships between
the other (n + m) capacitors. Lm , tbm and IM L m . If a lower IM L m is desired, Lm and tbm
Then, im 1 = im 2 = (n − m)im /2n and im 2 = im 1 = (n + must be higher. However, the following limitations of Lm , tbm
m)im /2n. Therefore, the voltage imbalance caused by im and and IM L m must be satisfied:
im in one cycle is
2mtm im 2 (n − m) mtm tbm + tr m < tm −1 (13)
Um = = Vdc (8)
nC 2n2 CR (n − m) Vdc
IM L m + < IM (14)
The corresponding compensating current iL m is shown in 2nR
Fig. 7(d). iL m can be divided into iL m 1 and iL m 2 . iL m 1 The strategy of the proposed topology is shown in Fig. 9.
discharges C1 − Cm , and iL m 2 charges the other (2n − m) Because the compensation current iL m charges capacitors
capacitors. Therefore, iL m 1 = (2n − m)iL m /2n and iL m 2 = Cm +1 − Cn and C1 − Cn , the compensation time tb1 is ad-
miL m /2n. The waveform of current iL m is shown in Fig. 8(b). justed first, followed by tb2 , and so on.
In tbm , the voltage across conductor Lm is Vdc /2n. The peak
current of iL m is V. SIMULATION RESULTS
Vdc tbm
IM L m = (9) The proposed topology used in the five-level inverter is simu-
2nLm lated for comparison with the theoretical results. The simulation
parameters are listed in Table II.
Because tbm : tr m = (2n − m) : 1, the compensated voltage
Fig. 10 shows that the output voltage is that of a five-level
across one capacitor is
inverter with a slight distortion of 17.33% THD. The output

1 m (2n − m + 1) t2bm Vdc voltage of a three-level inverter, shown in Fig. 14 has a dis-
Ubm = iL m 2 dt = (10)
C 8n2 (2n − m) Lm C tortion of approximately 74% THD. The THD of the five-level
2224
Fig. 10. Simulation result of the output waveform of five-level inverter.
Fig. 11. Simulation result of the voltage of one capacitor.
Fig. 12. Simulation result of compensating time tb .
Fig. 13. Simulation result of compensating current Im L .
inverter is considerably lower than that of the three-level in-
verter. The heat loss and unbalanced torque of the motor can
be greatly reduced when the five-level inverter is applied to the
motor control. The stability and efficiency of the motor can be
improved. The voltage across one capacitor, which is stable in
one cycle, is shown in Fig. 11. Fig. 12 shows the compensating
time tb , which is adjusted to balance the voltages of the capac-
itors. Fig. 13 shows the compensating current iL 1 on inductor
L1 , which is triangular and compensates for the voltages of the
capacitors. Table III presents the comparison of the theoreti-
cal and simulation results, which shows that the simulation is
consistent with the theoretical analysis.
IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 33, NO. 4, DECEMBER 2018
TABLE III
SIMULATION RESULTS
Fig. 14. Simulation result of the output waveform of three-level inverter.
Fig. 15. Simulation result of the voltages of four capacitors.
TABLE IV
SIMULATION PARAMETERS
The robustness of the system can be tested by assigning the
four capacitors C1 − C4 different values of 1.0, 1.3, 1.6 and
2.0 mF, respectively. The simulation results in Fig. 15 demon-
strate that the capacitor voltages are stabilized at 7.5 V even
though the capacitor values are not the same. This result indi-
cates the robustness of the controlling strategy.
The most practical performance of the proposed topology
is its applicability, as can be verified by simulating a seven-
level inverter based on the proposed topology. The values of the
parameters employed in the simulation are listed in Table IV.
The output voltage is that of a seven-level inverter with a slight
distortion, as shown in Fig. 16. The voltage across one capacitor
is balanced in one cycle, as shown in Fig. 17. The compensating
time tb1 and tb2 are shown in Figs. 18 and 20, respectively,
and are the extended opening times of the particular switches in
particular modes. The compensation opportunity of tb2 is twice
that of tb1 . Figs. 19 and 21 show the compensating currents
iL 1 and iL 2 , which are triangular and balance the voltages of
the capacitors. A comparison of the theoretical and simulation
SHI et al.: NEW DIODE-CLAMPED MULTILEVEL INVERTER WITH BALANCE VOLTAGES OF DC CAPACITORS
Fig. 16. Simulation result of the output waveform of seven-level inverter.
Fig. 17. Simulation result of the voltage of one capacitor.
Fig. 18. Simulation result of compensating time tb 1 .
Fig. 19. Simulation result of compensating current IM l 1 .
results is shown in Table V. The simulation results are similar
to the theoretical results, implying that the proposed topology
is applicable.
VI. EXPERIMENTAL RESULTS
The performances of the proposed topology are verified ex-
perimentally. Fig. 22 demonstrates a hardware prototype based
on the proposed topology.
The parameters of the five-level inverter are listed in Table II.
The output voltage shown in Fig. 23 is that of a five-level in-
verter, as expected. The voltage across one capacitor is stable in
one cycle, as shown in Fig. 24, which verifies the effectiveness
2225
Fig. 20. Simulation result of compensating time tb 2 .
Fig. 21. Simulation result of compensating current IM L 2 .
TABLE V
SIMULATION RESULTS
of the compensation method. Fig. 25 shows the compensating
time tb , which is the extended opening time of S1 , when the
output voltage is Vdc /2. Fig. 26 shows the compensating cur-
rent iL 1 , which compensates for the voltages of the capacitors.
A comparison of the experiment and simulation results is pre-
sented in Table VI, demonstrating that the experimental results
are similar to the simulation results.
An experiment on a seven-level inverter is performed to verify
the applicability of the proposed topology. The parameters are
listed in Table IV.
Fig. 27 shows that the output voltage is that of a seven-
level inverter and is slightly distorted. The voltage across one
capacitor, which is stable in one cycle, is shown in Fig. 28.
Equation (9) shows the relationship between tb1 , tb2 , IM L 1 and
IM L 2 . By adjusting tb1 and tb2 , the peaks of iL 1 and iL 2 can be
modified. Therefore, the compensating voltage Ub across one
capacitor changes. The stable values of compensating time tb1
and tb2 are shown in Figs. 29 and 31, respectively. They are the
extended opening time of particular switches in particular mo-
des. Further, the compensation opportunities of tb2 is twice that
of tb1 , which is consistent with the theoretical analysis. Figs. 30
and 32 show the stable waveforms of compensating currents
iL 1 and iL 2 , which are the key to balancing the voltages of the
capacitors. A comparison of the experimental and simulation
results is presented in Table VII. The deviation between the
2226 IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 33, NO. 4, DECEMBER 2018

Fig. 22. The picture of prototype

Fig. 23. Experiment result of the output waveform of five-level inverter. Fig. 25. Experiment result of compensating time tb .

Fig. 24. Experiment result of one capacitor.

Fig. 26. Experiment result of compensating current iL 1 .

results is small, thus verifying the applicability of the proposed TABLE VI

topology. SIMULATION AND EXPERIMENTAL PARAMETERS
In addition to the suitability of the proposed topology, the
experiments on the five- and seven-level inverters demonstrate
that the relationships between the compensating time tbm, peak
of the compensating current IM L m and the inserted inductor Lm
are consistent with Equations (9), (11) and (12). For a constant
power, lower IM L m , larger Lm and longer tbm . Because of the
limitation of tm −1 , tbm cannot be overly long. Small values of
IM L m cause Lm to increase rapidly because Lm is inversely between the inductor Lm and current IM L m is required for
2
proportional to IM L m . Therefore, consideration of the balance parameter optimization.
SHI et al.: NEW DIODE-CLAMPED MULTILEVEL INVERTER WITH BALANCE VOLTAGES OF DC CAPACITORS 2227

Fig. 30. Experimental result of compensating current iL 1 .

Fig. 27. Experiment result of the output waveform of seven-level inverter.

Fig. 31. Experiment result of compensating time tb 2 .

Fig. 28. Experiment result of one capacitor.

Fig. 32. Experiment result of compensating current iL 2 .

VII. CONCLUSION
In this paper, a new DCMLI is proposed to solve the voltage
imbalance for the multilevel inverter. The proposed topology
Fig. 29. Experiment result of compensating time tb 1 . requires the inductors to be inserted between diodes and main
switches, which can extend the opening time of some main
switches under particular modes. Although the currents through
TABLE VII some of the switches are increased, the fewer switches, diodes,
SIMULATION AND EXPERIMENTAL RESULTS capacitors and drive circuits are needed. Thus, the cost is sig-
nificantly reduced. Moreover, the control system is simplified.
Finally, both simulation and experimental results are given to
demonstrate that the proposed topology is suitable when ap-
plied to multilevel inverter. In addition, the applicability of the
topology is also verified.
2228
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Shunji Shi received the M.Sc. degree from the School
of Automation, Beijing Institute of Technology,
Beijing, China, in 2018.
His research interests include dc/dc inverters and
dc/ac inverters. He is currently working on the prod-
uct development of automobile power management
systems.
Xiangzhou Wang received the Ph.D. degree from the
School of Automation, Beijing Institute of Technol-
ogy, Beijing, China, in 1996.
He is currently a Professor with the School of
Automation, Beijing Institute of Technology. His re-
search interests include mobile controls, dc/dc invert-
ers, dc/ac inverters, and testing of the control compo-
nents and systems.
Shuhua Zheng received the Ph.D. degree from the
School of Automation, Beijing Institute of Technol-
ogy, Beijing, China, in 2013.
She is currently a Lecturer with the School of
Automation, Beijing Institute of Technology. Her re-
search interests include electric power system con-
trols and testing of the control components and sys-
tems.
Yanxi Zhang received the B.Sc. degree from the
School of Astronautics, Harbin Institute of Technol-
ogy, Harbin, China, in 2016. He is currently working
toward the M.Sc. degree at the School of Automation,
Beijing Institute of Technology, Beijing, China.
His main research interest includes wireless power
transfer.
Dongyuan Lu received the B.Sc. degree from the
School of Automation, Beijing Institute of Technol-
ogy, Beijing, China, in 2016. He is currently working
toward the M.Sc. degree at the School of Automation,
Beijing Institute of Technology.
His research interests include wireless power
transfer technology and power electronics in EVs.