MOS

SHARP
1986
SEMICONDUCTOR DATA BOOK
(MOS Edition)
General Information 11 ~
4-Bit 1-Chip Microcomputers ~
8-Bit 1-Chip Microcomputers [!

8-Bit Microprocessor and Peripheral LSls ~
16-Bit Microprocessor and Peripheral LSls ~
Peripheral LSls for Microcomputers ~
Support Tools for Microcomputers[ZJ

Memories [!
LSls for Telephone ~

MOS ICs/LSls ~
Preface
In recent years, the seemingly unlimited

progress seen in integrated circuits technology
has brought about phenomenal growth in elec-
tronic products for consumer and industrial
use. As electronics continues to expand -in the
future, we will direct our efforts at carefully
researching trends and supplying our custom-
ers with products that meet their needs and
contribute to the betterment of their way of
life.
We have now completed the "Sharp Semicon-
ductor Data Book - - MOS Edition", which
we present to you here how.
This data book lists the microcomputers,
memories and MOS LSIs produced and sold by
Sharp, which have a wide range of applicabil-
ity. We hope you will find this data book useful
and will contact Sharp if you have any ques-
tions.
The information contained in the databook isin-
tended to be a general product description. Sharp
reserves the right to make change in specifications
at any time and without notice.
Sharp does not assume any responsibility for use
of any circuitry described; no circuit patent
licenses are implied.
CONTENTS·
1. General Information ................................................. ;. 1

Products Lineup ...........................•... ; .................... 2
Package Outline .................................................... 12
Quality Assurance ................................................. 25

2. 4-Bit I-Chip Microcomputers ..................................... 35
3. 8-Bit I-Chip Microcomputers .................................... 165
4. 8-Bit Microprocessor and Peripheral LSIs ........ · .......... ·209
5. I6-Bit Microprocessor and Peripheral LSIs ................... 313
6. Peripheral LSIs for Microcomputers ........ · .................... 459
7. Support Tools for Microcomputers .... · ........ · .. · ............ ·561
8. Memories .............................................................. 581
9. LSIs· for Telephone .................................................. 731
10. MOS ICs/LSIs ......................................................... 795
General Information
Products Lineup
.--.-...r.-..-.--.-..-.-..-..-..-..--.-..-..-..-..-..-...r
. . .
Products Lineup
• 4-Bit 1-Chip Microcomputer
Supply ClnTent Sub·
Cycle colEUlllPlion Instruc- ROM RAM
Model Process voltage TYP.(mA) lions routine Package Remarks Page
ime. (f' s (bit) (bit)
(V) [operating] nesting
External RAM
SM-3A 10 -15 12 57 2268X8 128X4 2 60QFP 36
expandable
SM-100 10 -9 10 58 1134X8 64X4 2 28DIP 40
SM-105 10 -9 10 58 1134X8 64X4 2 28DIP 40
SM-ll0 10 -9 13 90 2032X9 128X4 6 60QFP 8-bit A/D conversion 44
SM-115 10 -9 13 90 2032.X9 128X4 6 60QFP 8-bit AID conversion 44
SM-111 PMOS 10 -9 13 90 4064X9 192X4 6 60QFP 8-bit AID conversion 49
SM-116 10 -9 13 90 4064X9 192X4 6 60QFP 8-bit AID conversion 49
8-bit AID conversion
SM-114 10 -9' 20 90 4064X9 192X4 6 60QFP Remote control 54
signal receiver
SM-120 10 -9 20 54 1536X8 64X4 2 44QFP External ROM 59
External ROM/REM
SM-200 NMOS 10 -5 32 100 3072X9 128X4t16 3 60QFP Automatic 64
display circuit
SM-4A 6)1 -3 0.05 54 2268X8 96X4 1 60QFP External RAM 69
SM-5A 61' -3 0.05 51 1827X8 65X4 1 60QFP 74
SM-5L 61 -3 0.05 51 1827X8 65X4 1 60QFP 79
SM-500 61 -2 0.02 52 1197X8 40X4 1 48QFP 84
SM-510 61 -3 0.06 49 2772X8 128X4 2 60QFP 89
Melody generator
SM-511 61 -3 0.04 55 4032X8 128X4 2 60QFP 93
circuit
External RAM
SM-520 11 -5 1.5 93 3072X10 160X4+ l6X2 4 64DIP Automatic 98
display circuit
External RAM
SM-525 11 -5 0.6 93 3072X10 160X4+ 16X2 4 64DIP Automatic 103
display circuit
Clock counter circuit
SM-530 91.6 -1.5 0.012 49 2016X8 88X4 1 80QFP Melody generator 108
circuit
Clock counter circuit
SM-531 91.6 -1.5 0.01 45 1260X8 52X4 1 60QEP Melody generator 113
circuit
SM-540 CMOS 16 -4.5 0.23 57 2016X8 128X4 2 60QFP Dot matrix 118
using
8-bit serial
SM-550 1.6 3-5 1 94 1024X8 80X4 RAM 48QFP 123
110 function
area
using
8·bit serial
SM-555 3.3 3-5 1 94 1024X8 80X4 RAM 48QFP 123
I/O function
area
using
8-bit serial
SM-551 1.6 3-5 1 94 2048X8 128X4 RAM 60QFP 128
110 function
area
using
8· bit serial
SM-556 3.3 3-5 1 94 2048X8 128X4 RAM 60QFP 128
110 function
area
2
Products Lineup
.'-'---------------------------
(Continued)
using
8-bit serial
SM-552 L6 3-5 1 94 4096X8 256X4 RAM 60QFP 133
I/O function
area
using
8-bit serial
SM-557 3_3 3-5 1 94 4096X8 256X4 RAM 60QFP 133
I/O function
area
using
8-bit serial
SM-5E3 L6 3-5 1 97 4096X8 256X4 RAM 80QFP 138
I/O function
area
CMOS using
8-bit serial
SM-563 6_6 3-5 0-4 93 4096X8 l28X4t32X4 RAM 64QFP 139
I/O function
area
SM-572 2 3-5 1-5 93 2032X9 128X4 6 64QFP 8-bit AID conversion 144
64DIP 8-bit AID conversion
SM-578 2 3-5 1-5 94 4064X9 192X4 6 150
64QFP 8-bit Serial 110 function
64DIP 8-bit AID conversion
SM-579 2 3-5 1-5 94 6096X9 256X4 6 151
64QFP 8-bit serial 110 function
SM-590 2 3-5 0_5 41 508X8 32X4 4 20DIP 16DIP, 18DIP 152
SM-591 2 3-5 0_5 41 1016X8 56X4 4 20DIP 16DIP, 18DIP 156
• 8-Bit 1-Chip Microcomputer

Supply Current
Cycle time I/O ROM RAM
Model voltage consumption Package Remarks Page
MIN- (JLs) pins (bit) (bit)
(V) MAX_(mA)
LH0801 1-5 5±5% 180 32 2,048X8 144X8 40DIP Z8601MCU 166
LH0802 1-5 5±5% 180 32 144X8 64DIP Z8602MPD 180
LH0803 1-5 5±5% 180 32 - 144X8 40PBP Z8603MPE 182
LH0811 1-5 5+5% 180 32 4,096X8 144X8 40DIP Z8611MCU 184
LH0812 1-5 5±5% 180 32 - 144X8 64DIP Z8612MPD 186
LH0813 1-5 5±5% 180 32 - 144X8 40PBP Z8613MPE 189
LH0881 1-5 5±5% 180 24 - 144X8 40DIP Z8681MCU 191
• 8-Bit CMOS 1-Chip Microcomputer

Supply Current
Cycle time I/O ROM RAM
Model voltage consumption Package Remarks Page
MIN- (JLs) pins (bit) (bit)
(V) MAX.(mA)
40DIP
SM-803 2.2 5±10% 32 4,096X8 144X8 - 195
44QFP
64DIP
SM-812 1 3-5 48 2,048X8 128X8 - 198
64QFP
64QFP
SM-813 1 3-5 48 4,096X8 192X8 - 201
64DIP
64QFP
LU810V1 1 3-5 48 - 128X8 - 204
64DIP
--------------SHARP -..-.---------.-.
3
.....,----------...
ProduotsLineup'
• a-Bit Microprocessor and Peripheral LSls

-~--,.- .......................,......~
.~
Supply Current Clock

Function MOdel Process voltage consumption fequency Package Remarks Page
(V) MAX.(mA) (MHz)
LH0080 150 2.5 Z80 CPU 210
CPU LH0080A ' NMOS 5±5% 200 4 40DIP Z80A CPU 210
LH0080B 200 6 Z80B CPU 210
Parallel LH0081 2.5 Z80 PIO 235
input/output LH0081A NMOS 5±5% 100 4 40DIP Z80A PIO 235
controller LH0081B 6 Z80B PIO 235
t80082 2.5 Z80 CTC 245
Counter / Timer
.L80082A NMOS 5±5% 120 4 28DIP Z80A CTC 245
controller
L80082B 6 Z80B CTC 245
L80083 150 2.5 Z80 DMA 255
DMA controller NMOS 5±5% 40DIP
LH0083A 200 4 Z80A DMA 255
L80084 2.5 Z80 SIO/O 270
LH0084A 100 4 40DIP Z80A SIO/O 270
LH0084B 6 Z80B SIO/O 270
LH0085 2.5 Z80 SIO/1 270
Serial input/output
LH0085A NMOS 5±5% 100 4 40DIP Z80A SIO/1 270
controller
LH0085B 6 Z80B 510/1 270
L80086 2.5 Z80SI012 270
LH0086A 100 4 40DIP . Z80A SIO/2 270
LH0086B 6 Z80B 510/2 270
Floppy disk LH0110 .170 2.5 ~
279
NMOS 5±5% 40DIP
controller LH0110A 180 4 ~
279
LH5080 2.5 ~
296
40DIP
CPU LH5080L CMOS 5±10% 10(TYP.} 2.5 ~
296
LH5080LM. 2.5 44QFP - 296
Parallel LH5081 2.5 - 302
40DIP
input/output LH5081L CMOS 5±10% 2(TYP.) - 2.5 - 302
.controller LH5081LM 2.5 44QFP - 302
LH5082 2.5 - 307
Counter /Timer 28DIP
LH5082L CMOS 5±10% 2.5(TYP.) 2.5 - 307
controller
LH5082LM 2.5 44QFP - 307
-~~-'----SI-iARP'---'-'-'----------
4
-------------------------
• 16-Slt Microprocessor and Peripheral LSls
Products Lineup
Supply Current Clock

Function Model Process voltage consumption fequency Package Remarks Page
(V) MAX.(mA) (MHz)
LH8001 4 Z8001 CPU 314
320 48DIP
LH8001A 6 Z8001A CPU ,314
CPU NMOS 5±5%
LH8002 4 Z8002 CPU 314
320 40DIP
LH8002A 6 Z8002A CPU 314
Memory LH8010 4 Z8010 MMU 332
NMOS 5±5% 300 48DIP
control unit LH8010A 6 Z8010A MMU 332
Serial communication LH8030 4 Z8030 SCC 342
NMOS 5±5% 250 40DIP
controller LH8030A 6 Z8030A SCC 342
CounterITimer parallel LH8036 4 Z8036 CIO 356
NMOS 5±5% 200 40DIP
input/ output unit LH8036A 6 Z8036A CIO 356
FIFO input/output LH8038 4 Z8038 FlO 377
NMOS 5±5% 200 40DIP
interface unit LH8038A 6 Z8038A FlO 377
FIFO buffer unit and
LH8060 NMOS 5±5% 200 4 28DIP Z8060 FIFO 396
Z-FIFO expander
Serial parallel LH8071 -- 402
NMOS 5±5% 250 4 40DIP
combination controller LH8072 -- 413
GPIB controller LH8073 NMOS 5±5% 250 4 40DIP -- 421
Multitask support
LH8075 NMOS 5±5% 250 4 40DIP -- 423
processor
LH8090 4 Z8090 UPC 434
NMOS 5±5% 250 40DIP
LH809QA 6 Z8090A UPC 434
LH8091 4 Z8091 ~:~f~~pment 451
250 64DIP
LH8091A 6 Z8091A ~:~~~~pment 451
NMOS 5±5%
Universal LH8092 4 Z8092 ~:~i~~pment 453
250 64DIP
peripheral LH8092A 6 Z8092A ~:~fi~pment 453
controller LH8093 4 Z8093 ~~~t~~k 455
250 40PBP
LH8093A 6 Z8093A ~::'JI:."~~k 455
NMOS 5±5%
LH8094 4 Z8094 ~~~ff~~k 457
250 40PBP
LH8094A 6 Z8094A ~~Ou'l':.:~k 457
5
Products Lineup
~~~"" __ ~-II!IIf:_""""""""'''''' __''_'':'''''''''''
• Peripheral LSls for Microcomputers
Supply ,Current Clock
Function Model Process voltage consumption ,fequency Package Remarks Page
(V) MAX.(mA) (MHz)
Serial communication LH8530 4 28030 SCC 460
NMOS 5±5% 250 40DIP
controller LH8530A 6 , 28030A SCC 460
CounterITimer parallel LH8536 4 28036 CIO .474
NMOS 5±5% 200 40DIP
input/output unit LH8536A 6 28036A CIO 474
Serial parallel LH8571 NMOS 5±5% 250 4 40DIP -- 49,1
combination controller LH8572 NMOS 5±5% 250 4 40DIP -- 502
GPIB controller LH8573 NMOS 5±5% 250 4 40DIP -- 511
Multitask support
LH8575 NMds 5±5% 250 4 40DIP -- 513
processor
LH8590 4 28090 UPC 525
NMOS 5±5% 250 .40DIP
LH8590A 6 28090A UPC 525
LH8591 4 28091*1 542
NMOS 5±5% 250 64DIP
LH8591A 6 28091A *1 542
I
LH8592 4 28092*1 544
NMOS 5±5% 250 64DIP
LH8592A 6 28092A *1 544
Universal LH8593 4 28093*2 546
NMOS 5±5% 250 40PBP
peripheral LH8593A 6 28093A *2 546
controller LH8594 4 28094*2 548
NMOS 5±5% 250 40PBP
LH8594A 6 28094A *2 548
Key-encoder and
LH8661 NMOS 5±5% 180 8 40DIP -- 550
data transmitter receiver
*1 Development device
*2 Protopack emulator
. ; Microcomputer Development Support System

Model Function Page
LH8DH11 0 Development Support System SM-D-8000 n; SM Series 28, 280, Z8000 development device 562
LH8DH130 Development Support System SM-D-8100; 28, 280, 28000 development device 564
LH8DH140 Development Support System SM-D-8200; 28, 280, 28000 development device 566
LH8DH312 280B In-circuit Emulator, for SM-D-8000 n 569
LH8DH321 Z8 In-circuit Emulator n, Stand-alone type 571
LH8DH330 28000 Evaluation Board, Stand-alone type 572
LH8DH340 28000 In-circuit Emulator SM-E-8100, Stand-alone type 573
LH8DH403 PROM Writer SM-E-8000 n 575
LU4DH200 SM Series Emulator Device SME-20, Stand-alone type 576
LUXXXH2 SM Series Evaluation Board 578
~~~----'-'---SHARP ---.-..-.------~---
6
Products Lineup
~~.-..-.~~.-..-..-..-..-.~.-..-..-.~.-.~
• Mask ROM
Bit Access Supply Power
Capacih Cycle time
Model Process composition time voltage consumption Package Remarks Page
(bit) MIN.(ns)
(bit) MAX.(ns) (V) MAX.(mW)
LH2331 450 450 5S2
32K
LH2331A
NMOS 4,096XS
350 350
5±5% 5S0 24DIP
582
LH2332 450 450 r-s86
LH2332A 350 350 r-s86
LH2362B 250 250 S40 24DIP 590
NMOS 5±5%
LH2367 250 250 420 2SDIP "594
64K LH5366A S,192XS 2,500 4,000 5±10% 30 599
LH5366S CMOS 6,000 12,000 3±0.5V 3.5 44QFP '602
LH5367 450 750 5±5% 60 605
LH5396 6,000 7,500 35 60S
4.5±0.5V
96K LH5396A CMOS 12,2SSXS 3,000 4,500 60 44QFP 608
LH5396S 15,000 1S,000 3±0.4V 10 ill
LH23126 NMOS 250 250 5±1O% 440 2SDIP 615
12SK
LH53127
16,3S4XS
250 350 5±10% 44 2SDIP rsl8
LH53129 CMOS 6,000 7,500 4.5±O.5V 35
44QFP
~
LH53129A 2,500 3,500 5±1O% SO ~
LH23257 NMOS 250 250 440 28DIP 630
256K LH53256
CMOS
32,76SXS 800 900 5±10% 55 44QFP ~
LH53257 250 250 165 2SDIP '638
512K LH53512 CMOS 65,536XS 3,000 4,400 5±IV 9 24S0P 642
1M LH531000 CMOS 131,072 X8 SO - 5 - 2SDIP 646
102M
LH53012
Series
CMOS 103,680X12 250 250 5 -. 40DIP 647
• EPROM
Capacit) Cycle time
Model Process compositiontime voltage consumption Package Remarks Page
(bit) MIN.(ns)
(bit) MAX.(ns) (V) MAX.(mW)
LH5764j-20 200 -- 6"50
LH5764j-25
S,192XS
250 - 2SDIP ~
64K CMOS 5±10% 150
LH5764j-30 300 - (Ceramic) ~
LH5764j-45 450 - ~
LH57128]-20 200 - 651
12SK
LH57128]-25
CMOS 16,3S4XS
250 -- 5±10% 150
2SDIP ~
LH57128]-30 300 - (Ceramic) . '651
LH57128j-45 450 -- ~
LH57256]-20 200 -- 652
LH57256]-25 250 - 2SDIP '652
256K
LH57256]-30
LH57256]-45
CMOS 32,76SXS
300
450
-
--
5±10% 150
(Ceramic) rrn-
rrn-
7
Products ,Lineup
'
................_ _. ._ _................ .........._ _ _. ._ _
~
~
.
-
.
.
r
• StaticRAM
,Bit
Access Supply Power
Capacih Cycle time
Model frocess composition
time voltage consumption Package Remarks Page
(bit) MIN.(ns)
(bit)
MAX;(ns) (V) MAX.(mW)
., LH5101-30 300 300
5±10% 140
653
LH5101-45 450 450 653
LH5101 800 800 658
1K CMOS 250X4 5±5% 145 22DIP
LH5101L3 650 650 658
LH5101S 3,000 3,500 3±OAV 45 602
LH5101W 800 800 5±10% 150 666
LH5102 1,200 1,200 670
5±5% 145
2K LH5102-8 CMOS 512X4 800 900 22DIP 670
LH5102W 1,200 1,200 5±10% 150 675
LH2114L-20 NMOS 200 200 400 680
1,024X4 5±10% 18DIP
4K LH5114-4 CMOS 450 450 110 684
LH5104-4 CMOS ' 4,096X 1 450 450 5±.10% 85 18DIP 688
LH5116-15 150 150 118 pin CS 693
LH5116-20 200 200 20 pin OE 693
LH5117-15 150 150 118 pin GE, ~
16K CMOS 2,048X8 5±10% 220 24DIP
LH5117-20 200 200 20 pin CEI 698
LH5118-15 150 150 118 pin CE, 703
LH5118-20 200 200 20 pin CEI 703
• Dynamic RAM
Capacity Cycle time
Model Process composition time voltage consumption Package ' Remarks Page
'(bit) MIN.(ns)
(bit) MAX.(ns) (\1) MAX.(mW)
LH2164-15 150 270 708
248
LH2164-20 200 330 708
64K NMOS 65,536X1 5±10% 16DIP
LH2164A-15 150 260 717
275
LH2164A-20 200 330 717
, LH2464-10 100 - 726
r-------'--
LH2464-12 120 - Page mode 726
r-------'--
LH2464-15 150 - 726
NMOS 65,536X4 5±10% 267.5 18DIP
LH2465c10 100 - 726
r-------'--
LH2465-12 -
120 Nibble mode
~
LH2465-15 150 - 726
256K LH21256-10 100 200 467.5 728
r-------'--
LH21256-12 120 230 440 Page mode 728
LH21256-15 150 260 385 rns
LH21257-10 100 200 467.5 728
LH21257-12 NMOS 262,144X 1 120 230 5±10% 440 16DIP Nibble mode rm-
LH21257-15 , 150 260 385 rns
LH21258-10 100 200 467.5 728
LH21258-12 120 230 440 Byte mode rm-
LH21258-15 150 260 385 c-m--
8
.............................. ......................... .........................
~ ~
Products Lineup
• Tone Dialer
Power Operating Oscillating
Tone
Model Processsupply current frequency Oscillater Mute output Remarks Package Page
output
lvoltage(V) TYP.(mA) (MHz)
LR4087 CMOS 3.5-10 1 3.58 Crystal bipolar output Complementary 16DIP 732
LR4089 CMOS 3.0-10 1 3.58 Crystal bipolar output N-channel open drain 16DIP 735
LR4091 CMOS 3.0-10 1 3.58 Crystal bipolar output N-channel open drain
Op amplifier
output
18DIP 738 1
LR4092 CMOS 3.5-10 1 3.58 Crystal bipolar output Complementary 16DIP 741
• Pulse Dialer
Power Operating Oscillating Make Pluse
Pluse Mute
Model Process supply current frequency Oscillator rate ratio Remarks Package Page
output output
r-roltage(V) MAX.(mA (kHz) (%) (pps)
LR40981A CMOS 2.5-6 0.15 480 Ceramic 33/39 10 Positive Negative 16DIP 744
LR40982 CMOS 2.5-6 0.15 480 Ceramic 33/39 10 Negative Negative 16DIP 748
LR40991 CMOS 2.5-6 0.15 4 CR 34/40 10/20 Negative Positive 18DIP 752
LR40992 CMOS 2.5-6 0.15 4 CR 34/40 10/20 Negative Negative 18DIP 756
LR40993 CMOS 2.5-6 0.15 4 CR 34/40 10/20 Negative Negative Key signal 18DIP 760
LR40994 CMOS 2.5-6 0.15 4 CR 34/40 10120 Negative Negative Key. signal 18DIP 764
• Pulse / Tone Dialer

Power Operating Oscillating Make Pluse
Abbrevication Redical
Model Process supply current frequency Oscillator rate ratio Package Page
memory function
voltage(V) TYP.(mA) (MHz) (%) (pps)
18 digits 18 digit last
.LR480lD CMOS 2-6 2 3.58 Crystal 40 10/20 18DIP 768
X9 stations number
LR4802 CMOS 2-6 2 3.58 Crystal 32 10/20 18DIP 773
X9 stations number
LR4803 CMOS 2-6 2 3.58 Crystal 40 10/20 18DIP 778
~
X9 stations number
32 digit last'
LR4804 CMOS 2-6 2 3.58 Crystal .40 10120 -- 20DIP 783
numger
32 digit last
LR4805 CMOS 2-6 1 3.58 Crystal 32 10120 -- 20DIP 788
number
LR4806B CMOS 2...,.6 1 3.58 Crystal 33/37 10/20 28DIP 793
X 20 stations number·
---~------SHARP~------~----
9
.....,.-..........
·Products Lineup
• MOS Ie / LSI
.---..... .-~~ ..... ...............................
.-
F'unction Model Process Features Package Page

LH5010 CMOS 6-circuit signal non-inversion type, INHIBIT input 16DIP. 908
LH5011 CMOS 6-circuit signal inversion type, INHIBIT input 16DIP ·908
kH5010D CMOS 7-circuit signal non-inve(sion type, INHIBIT input 18DIP 911
LH5011D CMOS 7-circuit signal iIiversion.type, INHIBIT input 18DIP 911
Driver
LH5012 CMOS 7-circuit signal non-inversion. type 16DIP 914
LH5013 CMOS 7 -circuit signal inversion type 16DIP 914
LH5012D CMOS 8-circuit signal ·non-inversion type, 18DIP 917
LH5013D CMOS 8-circuit signal inversion type 18DIP 917
LR3428 CMOS Analog clock, alarm, oscillator: 4.19 MHz crystal 8DIP 920
LR3429 CMOS Analog clock, alarm, oscillator: 4.19 MHz crystal 8DIP 923
LR3464 CMOS Analog clock, alarm, oscillator : 32kHz crystal 8DIP 926
LR3468 CMOS Analog clock, alarm, oscillator: 32kHz crystal 8DIP 929
Analog clock, melody generating function oscillator:
Clock/ LR3465 CMOS 22DIP 932
32kHz crystal
TImer
(Hour, min) LCD display, timecast, alarm, snooze function,
LR3441 CMOS 48QFP 936
oscillator: 32kHz crystal
(Hour, min) Fluorescent display tube indication,
LR3419 CMOS 48QFP 94i
power failure display, oscillator 50/~0 Hz or 32kHz crystal
(Hour, min) Fluorescent display tube, 6-program-a-week
LR3472 CMOS 48QFP 945
reservation, oscillator: 32kHz crystal
LH5008 CMOS 7-segment and 14-segment ·display, display RAM: 128 bits 60QFP 838
5 X 7 -dot matrix display (master), display RAM:
LH5003 CMOS 60QFP 899
240 bits, character generator: 125 types
5 X 7-dot matrix display (slave), display RAM:
320 bits, character generator: 128 types
Dot matrix display (master), display RAM:
1280 bits, common output: 20 lines, segment output: 44 lines
Dot matrix display (master), display RAM:
Dot matrix display (master), display RA.M :
Dot matrix display (slave), display RAM:
LCD driver LH5826 CMOS 80QFP 884
1280 bits, segment output: 64 lines
LH5030 CMOS Dot matrix display (common), common output: 80' lines 96QFP 892
LH5031 CMOS Dot matrix display (common), common output;. 32 lines 44QFP 896
Dot matrix display (segment), display RAM:
LH5035A CMOS 96QFP 889
Dot matrix display (segment), display RAM:
LH5036A CMOS 96QFP 889
LH5006A CMOS Dot matrix display, common output or segment output: 40 lines 60QFP 866
LH5021A CMOS Dot matrix display, common output or segment output: 80 lines 100QFP 870
LH5022 CMOS Dot matrix display, common output or segment output: 80 lines 100QFP 870
LR3691A CMOS Dot matrix controller, max display capacity: 163,840 dots 60QFP 844
LR3692 CMOS Dot matrix controller, max display capacity: 640 X 256 dots 80QFP 853
Vacuum LI2048 PMOS 5 X 7-dot matrix display, character generator: 128 types 60QFP 835
fluorescent Grid drive, output voltage (MAX.): -50V,
LH1001 PMOS 36QFP 905
display driver output current (MAX.): 20mA
10
~---------
•
.....---....---....------.......-.------------.....
MOS Ie / LSI (continued)
Products Lineup
Function Model Process Features Package Page

8-output, N-channel, output voltage (MAX.): 300V,
LZI008AD DMOS 18DIP 804
output current (TYP.): 35mA
LZI016AD DMOS 28DIP 807
High LZI032AM DMOS 44QFP 811
voltage 8-output, P-channel, output voltage (MAX.): 300V,
LZll08AD DMOS 18DIP 815
MOS
16-output, P-channel, output voltage (MAX.): 300V,
LZ1116AD DMOS 28DIP 818
32-output, P-channel, output voltage (MAX.): 300V,
LZ1132AM DMOS 44QFP 821
LR3617 CMOS Up I down counter with LCD decoder driver 48QFP 964
Audio &
LR3727 CMOS VTR data hack 36QFP 969
Video
LR3652 CMOS PLL synthesizer for AM I FM radio 22DIP 977
56-channel remote-controlled transmitter,
LR3715M CMOS 36QFP 952
Remote oscillator: 455 kHz ceramic
control 56-channel remote-controlled transmitter,
LU59001 CMOS 20DIP 957
oscillator: 455 kHz ceramic
8-melody generation with accompaniment,
Voice LR3461 CMOS 22DIP 824
Electromagnetic speaker driver, CR oscillation
Synthesizer /
LR3462 CMOS 8-melody generation, piezo·electric drive, CR oscillation 18DIP 827
Melody
Speech synthesizer, Waveform coding system,
generator LR3681 CMOS 48DIP 831
Built-in 32K-bit data ROM, Base frequency: 4.19MHz
CCD image sensor, dynamic range (TYP.): 54dB, 24DIP
CCD . LZ2020 CMOS 799
Transfer efficiency more than 99.996% (Ceramic)
Gate array LZ92 Series CMOS Gate array, 300-5000 gates, 2.8ns/gate -- 796
11
......
Package Outljoe
~.,
Package Outline (Unit: mm)

8 5
8DIP
14DIP
16DIP 16 9
12
.-..-..-.
iSDIP
.....-..-.....
.-..-~ ...-.-............ ........ -
Package Outline
7.62 TVP.
1 ;;==
;;
20DIP 20 11
'~-~f:*)
1 24.5±o.25 10 :;;
+1
....
",
..;
7.62TYP.
22DIP
10.16 TYP .
13
.
PackageOuUine
......,.--.
24DIP
......-------_...........
-~ . _-_..................-
CD
"
Normal
13.2±o.2s
Shrink
6.35±O.2
® 31.0±O·3 22.0±O.2S
® 15.24TYP. 7.62TYP.
® 4.25±O·2 3.45±O.2
® 5.1±o.2 4.2±O·2
® p~.54TYP. P-i, 778 TYP.
(J) 0.5±O.1 0.46±O.1
®
Normal Shrink
28DIP CD 13.2±o.25 8.6±O.2
® 36.0±O·3 25.5±O..25
® 15.24 TYP: 10. 16 T¥P.
® 4.25±O.25 3.85±O.2
® 5.1 ±O.2 4.4±O.2
® p-2.54T¥P. P-l, 778TYP.
(J) O.5±O.1 O.46±O·1
Normal Shrink
30DIP 3~ r"l t"J I'i fI t"J t"J ~ r"l r"l t"J t"J J'l r"1 ~6 CD 13.2±o.25 8.6±O.2
- 1----.
-$-
--+-----$-
. I
I
e
®
®
®
®
36.0±O.3
4.25±o.25
S.l ±O.2
27.2±O.25
lS.24 TYP . 10. 16 TYP.
3.85±o.2
4.4±O.2
p-2.54 TYP. P-l, 778 TYP.
\-IV V V V V V ! 'vi V V V V VL ®
(J) 0.5±O·1 O.46±O·1
1 ® 15
~
@ (§)
~
1
~
P-
,~
,,"
-H
on
""
.,.;
~
- ~
~.-.------~--SHARP-.-.~~-.-.--
14
Package Outline
~.-..-..-.-..-..-.-..-.-~.-.-.--.-..-.-.
40DIP
21
42DIP
48DIP
15
P~kage. Outline . .
. - . - . - . - . - . . . . . , . - -..._ ..._~.-.:..._ _illr.. . . . ....,.IIiiIIIIiiiIif.....
640lP 64 33
42.0MAX.
24 DIP (Ceramic) :....-------------t~1
24 13
I _~ n ~L
~
J
- Hjt:=chip ---+---
12
. 11 14.0TYI'·
M
.,;
+1
;2) >=
N t..
~~~~~=t~
.
J O.25±o.05
\: 15.24TYP ·
~
.1
28 DIP(Ceramic)
16
Package Outline
~~~"",~~"",~....,....,.--r~...., _________
40PBP 8.9 TYP .

40 21
( Ceramic )
Piggyback ~
~
'"0'
c::i
+\ +1
_ M '"
to: ~
~ .,.:
........
50.8±o.8
;;. I
ti. ';;,
20 '"0 0;
>-
~------------~--------------~~ ~
~ r--:
,
J~0~46±O.1 '"
.,;
...
+1
8S0P
JJ
- - r-
-'"
C>
: -u;
II
~j ~ II. 0.15±o.05
14S0P
'::' --+-------'- '"~

..,., '" ~IIE 0.15±O.05
ci
6T1iirfIDriB
~~----~~----------~~ ~
'" .,;
""
o~ ....
o
17
16S0~ .
8
o
...
on on on
~irini$nririC ~ <00
o~
o
24S0P
IS.4 0 0.2 o
~I 3
II eO.IS±O.05
on on
~-~ :
~ttl~:
32QFP
O.8S±O.2
1.45±O.2
16.0±O"
O.ITYP.
-------~---~-~SHARP,-~~-.--------
18
.-..-..-.~.-..-.~.-.~~~.-.~~~.-. .....----
Package Outline
36QFP p-o.8 TYP• 36 -0.38±o.1 0.15±o.o5
n7~-------' ~----
~
.,;
++1--E""'a::Il
N ..
o 0
~1=E=-88
<=> cD
............
0.85±0.2
10.0±O.2
1.45±O.2
16.0±O.4 o.rrvp
44QFP _liE 0.15-{l.tl5
J-.-
- -
0.85-°·2
1.45- 0 . 2
16.0,,0.4
. . . - - . - - - - - , . . . . - - $ H A R p . - - - - - - - - - - -..........
19
Paokage, Outline
........--.~...,...,.-. . ..-..-.. . .....r.-...........~......_
48QFP
p-o.75 TYP ,
24
N ~
__ +I
o 0
+i
<:> <:>
~~
13
16.01: 0 .4
O.I TYP ,
60QFP
0.15 ±0.05
N ~
, 0
00
---111==~3- ~ -r-~
o
""
1.0±0.2
1.9±0.2 .
20.3±0 .• O.FYP' '
20
.-..-..-..... .-..-. .......-....................-........-..-..-........ - Package Outline
64QFP 64-0.4±O.!
64
1
I 20.0±O.2
O.9±O.2
\ . 24.3±o.. I
,.
1. 95±o.2
-1'--1iE-O-.I ±o.os
-t6r;-fulunJ1tU1 rfilil-
~~ (21.9)._ _ _ _ _~-~
76QFP
P-O.8 T¥P.
I
--r'---
,
22.0±0.4 O.I±O.!
21
p,i1~kage Outline
80QFP p-0.8 TYP. O.15±0.01
~----- +-----
I
1.25±0.2
18.0±0.2
2.4±0.2
22.0±0.4 O.1't:O.1
I"
80QFP 1'-0.8 TY I'· 0.15±o.05
I 0.9±O.,
20.0±0.2
1.95±0.2
, 24.3±0.4
0.1±0.1
_ _ ~~-----~-SHARP~------"--'----"""'-
22
.-..-..-. ......-..-.......-.................-.................-.......-.
Package Outline
96QFP p-O.FYP' O.15±O.05

"II" .
,
I
~---+-----
,
I
I
i
18.0±o.2
1.25±o.2
2.4±O.2
22.0±O.'
O.l±O.!
lOOQFP
23
44PLCC
;>1 I,E
6' , 40
!" \
29
16.6.tO·2
28
(17.5)
DIP : Dual-In-Line Package

QFP : Quad Flat Package
SOP: Small-Outline Package
PBP : Piggyback Package
PLCC : Plastic-Leadless-Chip-Carrier
24
.-.,.-.,.-., ..... .-.,.-., ..... ..... ..... ..... ..... ..........
.-., .-., .-., .-.,
Quality Assurance
.-.,
Quality Assurance
1. Quality Assurance System
Sharp develops and manufactures a wide range

of consumer and industrial-use semiconductor pro-
1 ;;=;:;
ducts, including ICs and LSIs.
=
In recent years, the applications of ICs and LSIs
have expanded significantly, into fields where ex-
tremely high levels of quality are critical.
In response, Sharp has implemented a total qual-
ity assurance system that encompasses the entire I--_ _ _ Evaluation of functions
production process from planning to after-sales and performance
service. This system ensures that reliability is a
priority in the planning and manufacturing stages,
I--_ _ _ Eva!uation of quality
and guarantees product quality through rigorous and mass producibility
reliability testing. We will introduce a part of
this system here.
Sharp's quality and reliability assurance activi-
f----Evaluation of reliability
ties are based on the following guidelines:
(1) All personnel should participate in quality
assurance by continually cultivating a higher
level of quality awareness. 1 - - - - - Decision to mass
produce
(2) In the developmental stage of new products,
create designs that consider reliability in ev-
ery respect.
(3) In addition to quality control in all manufac-
Fig. 1 New Product Development Steps
turing processes, all working environments,
materials, equipment, and measuring devices marily for their ability to function and their per-
should be carefully monitored to ensure quali- formance.
ty and reliability from the very beginning of Next, ES (engineering samples) are made and ev-
the process. aluated to determine whether the functions, per-
(4) Confirm long-term reliability and obtain a formance and quality aimed for in the design stage
through understanding of practical limits can be guaranteed under the existing manufactur-
through reliability testing. ing conditions. These ES are also evaluated in
(5) Continually work to improve quality through quality and reliability tests to determine whether
application of data from process inspections, their long-term reliability can be guaranteed.
reliability testing, and market surveys. After this, mass producibility is evaluated using
CS (commercial samples) obtained from a trial mass
2. Quality and Reliability Control in New
production, and the decision to mass produce or
Product Development not is made. Fig. 1 shows the steps in the de-
The development of new products begins with a velopment of new products.
thorough understanding of the product specifica- 3. Quality and Reliability Control in Mass
tions and quality that will satisfy the purpose for
Production
which the product is intended and with develop-
mental planning that carefully considers pricing, (1 ) Quality Control of Materials
quantity and the time of introduction to the market.
The quality and reliability of a product is
In the design stage, reliability is designed into
affected by its component materials as well as the
the product based on test data, process capability,
manufacturing processes and conditions.
and field data, and experimental models are
The quality control of purchased component
made. These experimental models are referred to
. materials is ensured by material qualification and
as TS (technical samples), and are evaluated pri-
inspection upon receipt.
.-....----~.------SHARP.---------~
25
Q,uality Assurance
.....,.....,....., ........,.....,.... ..-.. .....
Table 1
~- ....,.....,
Examples of items considered in material approval
.....,.....,.....,....., ...........
Material Wafers Resins Lead frames .Bonding wire
Crystal growth method Composition Composition Purity
,Crystal orientation Electrical characteristics Electrical characteristics Appearance
Doping Thermal characteristics Thermal characteristics Dimensions
Oxygen content Formability Physical characteristics Strength
Items Dislocation density Process characteristics Appearance ' Elongation character-is-
Diameter Reliability evaluation Dimensions tics
Thickness Reliability characteris Processing a~cl,lracy Process characteristics
Parallelism tics Plating characteristics
Specific resistance by elements used Process characteristics
Process Control items C
Purchase of material .
Silicon
wafers
Inspection upon receipt Appearance, dimensions, Eliminate items with incorrect dimensions;
specific resistance scratches; and crystal defects and assure
resistance values.
, Oxidation
Appearance, film thickness Confirm the absence of pin

holes and assure film thickness.
On line QC Surface cleanliness Check the cleanliness of surfaces.
Photolithography
Visual inspection Development, etching Check the suitability of development and

~tching.
On line QC Wire width Control the wire width.
Ion implantation
Chip electrical inspection Electrical. characteristics Eliminate items with unsuitable electrical
characteristics.
Dicing
Breakage screening
Die inspection Appearance Confirm the absence of breakage and

chips.
Die bonding
Die bonding inspection Appearance, bond strength Check quality of die bond.
Wire bonding
Wire bonding 'inspection Appearance, tensile strength Ch.eck position and shape of bond and
assure sufficient tensile strength.
Fig .. 2 Example of process quality control

! '
.-----~-----SHARP,-~-.---.-.-..-.-
26
.-..-..-. ......-..-.......-.................-............-..-........... Quality Assurance
Table 1 shows examples of material qualification agement.

items. The inspections performed upon receipt of We perform a final inspection of all finished pro-
materials use criteria compiled from the purchase ducts as well as further quality assurance inspec-
specifications and approval drawings, and employ tions through sampling to fully ensure quality.
sampling inspection methods that conform with Detects found in these inspections are promptly
MIL-STD-105D. reported to the design and production sections, and
(2) Control of Manufacturing Environment improvements made' in the processes to upgrade
Environmental conditions in the manufacturing our uniform quality capabilitieS.
process - such as temperature, humidity, and dust
- significantly affect the finished quality of semi· Assembly process
conductor products.
Temperature is especially critical in maintaining
the accuracy of the measurement of electrical char- Electrical
All items
acteristics and the accuracy of various devices. characteristics
Humidity control is important for the prevention of
moisture penetration into a device and the preven-
tion of static electricity. Temperature and humid- Appearance All items
ity are thus strictly maintained at constant levels.
A dust-free environment is vital in the manufac-
ture of refined semiconductor circuits, as dust can Eiectrical
characteristics, Judge lot
be the critical determining factor in their quality appearance ' by sampling
and reliability. Thus, the cleanliness of every-
thing from air conditioning equipment to work ben- -----------,
I
ches to work clothes and office items is carefully
controlled. Reliability tests Sampling
Sharp is also concerned about creating an en- _ _ _ _ _ _ _ _ _ JI
vironment conducive to error-free high-precision
work, and so provides background music and in-
terior colors appropriate for specific tasks.
(3) Control of Manufacturing Equipment and
Measuring Devices
Shipment
Tremendous technological innovation and prog-
ress has been made in s~miconductors themselves Fig. 3 Product inspection system
and in the processes and equipment by which they Fig. 3 Shows the product inspection system.
are produced. Fig. 4 Shows an example of process quality
T,o achieve even higher levels of product uni- control.
formity and quality, Sharp is continually further-
(5) Reliability Assurance
ing the automation of its processes, strictly manag-
ing the maintenance of its manufacturing equipment, To guarantee the long·term reliability of our pro-
and carefully monitoring the accuracy of all ducts, we periodically sample products and subject
measuring devices through daily and periodic in- them to reliability testing such as life tests and en-
spections. vironmental tests.
In addition, reliability tests are performed
(4) Process Quality Control and Product in-
whenever process changes have been made.
spections
Based on the fundamental concept of ensuring
quality and reliability throughout the manufactur-
ing process, we check at each stage to determine
whether the prescribed characteristics are being
obtained and to prevent defective items from going
on to the next stage. We do this through strict
monitoring, inspection of all items, sampling in-
spections, and other standardized methods of man-
---...-..--.----SHARP-.--~-- ........ -
27
Q.uatity~sslM'anc'i.l·
,..-.r~~ .. ..r....__. .
~ ~~ .....~......-..r.~. .~..........__~..........
SHARP
Manufacturing Quality control Quality assurance Design ' Business, planning
Investigation
Development plan decision (New production planning collferen~e)
sample/Engineering, sample
General evaluation (New product debut conference)
Pilot production
production go - ahead conference)

=
.~
""
"C
o
&::
Fig.4 (a) Quality assurance system (SHARP side)
28
_
.................... .............................. .....................
Customers
_ Quality Assurance
-
Design dept.
1 Parts dept. 1 '
Manufacturing dept., Quality
dept. Assurance I Service dept.
End user
C Equipment
discussionS' )-~------------------~------~o~·----o
r Parts
seleciion )
Confirmation of\.
specifications
Equipment
( design
I Design
\.. sample
r Purchase
specifications }--(
Parts
approval )-
\
0 0 0 0 0
r Speeificatjons
approval
'\
\.. ./
r Mounting
\. approval
~
( Design review )
• "\ r f
( Sample
planning
../ \
Pilot
production
"\
\.
Sample
test )
l
( General evaluation )
+
J' Quality "\
evaluation ./
\...
Process quality
1 "\
Assembling
control
J'
\.
•
l.n s pections
/Aging
"\
./
r Reliability
)
\. evaluation
0
r Evaluation
/Analysis
"\ J' Operation
)
\.. ../ \.
Fig. 4 (b) Quality assurance system (User side)
.-.-.--.-----SHARP-----.-.---
29
Qua.lityAssurance
............... ~ ..............r.....AIIiIIIIIir.............,___ .....,~...................... - .
associations such as the International Electronics

4. Reliability Tests Commission (IEC), and the U. S. Military Specifica-
In addition to determining the extent to which tions (MIL). Sharp standardizes all
specifications to
product reliability can be assured, the objectives of conform with these standards.
reliability testing il1clude getting an understanding Table 2 shows a representative reliability test.
of design limitations and the catastrophic failure Durability testing of semiconductor products
mode, and predicting reliability in the field. places the greatest emphasis on high temperature
The major categories of reliability testing are operation tests. Priority in the testing of plastic
durability tests, thermal environmental tests, and m'olded products is on high temperature, high
mechanical test~. The standardized test .methods humidity storage (operation) tests.
used are those prescribed by official standards or
Table 2 Reliability test for semiconductor products
Type Test item Test condition Test objectives
High temperature T,tg(max.) Evaluate resistance to high temperatures in
storage longterm storage.
High temperature Top, (max.) Evaluate resistance to long, term thermal and
operation power supply voltage (max.) electrical stress.
High temperature, .60t 90% RH Evaluate resistance to high temperatures and
Durability high humidity 85t 85% RH high humidity in long-term storage.
tests storage Pressure cooker at l20t and
2 atmospheres
High temperature, 60t 90% RH 'Evaluate resistance to long-term thermal, humid,
high humidity 85t 85% RH ity and electrical stress.
operation
Low temperature T,tg(min.) Evaluate resistance to low temperatures in long-
storage term storage.
Temperature T,tg (max.)-T,tg (min.) Evaluate resistance to sudden extreme tempera-
cycling test ture changes.
Thermal Heat shock test ot -lOOt (liquid) Evaluate resistance to sudden extreme tempera-
environ- ture changes.
mental Temperature and -lOt to+65·C 90% RH Evaluate resistance to extreme temperature
tests humidity cycling changes at higgh humidity.
test
Solder heat 260t lOs Evaluate resistance to thermal stress during
resistance soldering.
Shock test 1,500G, 0.5 ms ±X, ±Y,±Z Evaluate structural and mechanical resistance to
strong shocks.
Variable-frequency 20G, 20-2,000 Hz, X, Y, Z Evaluate resistance to vibration during trans-
vibration test port and use.
Pin strengeth Tensile strength : holds fixed load Evaluate resistance to mechanical stress applied
for 10 seconds to pins.
Bending strength: bend once 90 iu
forward and reverse directions
Mechanical (Load is determined based on piu
tests shape and the surface area of pin
section.)
Air-tightness ' Test for minute leaks using helium Evaluate hermetic sealing.
gas and large leaks using foaming.
Salt spray test Spray 5% salt solution Evaluate resistance to corrosion in salt spray
at Ta=35 t for 24 hours environment.
'Solderability 230 tfor 5 seconds (with flux) Evaluate solderability of pins.
Solvent resistance Dip in isopropanol and acetone fo Evaluate resistance to pitting.
30 seconds at Ta=25t
30
Quality Assurance
.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-
offered and assure the products'long-life service,
5. After-sales Service please refer to this manual to help in designing sys-
If a product malfunctions after shipment, we tems that make best use of their capabilities.
have the customer return the product for detailed (1) Maximum Ratings
analysis. We also obtain complete information con- It is generally known that the failure rate of
cerning conditions of use, frequency of occurrence, semiconductor products increases as the tempera-
and symptoms. ture increases. It is necessary, of course, that the
When the cause has been determined, we report ambient temperature be within the maximum rated
findings concerning the design, manufacturing pro- temperature. Further it is desirable from the stand-
cess, or method of use to the departments con- point of reliability that the ambient temperature be
cerned for preventive action against recurrence of lowered as much as possible. The voltage, current,
the malfunction. We then submit a report to the and electric power used are also factors that signi-
customer. ficantly influence the life of semiconductor pro-
This process of tracking the performance of our ducts. Voltage or current- that exceeds the rated
products in actual use is an extremely effective level may damaged, the semiconductor product;
way to enhance product reliability. We direct a lot even if applied only momentarily and the unit con-
of energy forwards its full imprementation. tinues to operate properly, excessive voltage or
Fig. 5 shows the routes through which accidents current will likely increase the failure rate.
and malfunctions outside of the company are hand- Therefore, in actual circuit design, it is impor-
led, and Fig. 6 shows the procedures used in their tant that the semiconductor products used have a
analysis. certain degree of allowance with respect to the vol-
tage, current and temperature. conditions under
6. Handling Precautions which they will be used. The greater this allo-
All of the semiconductor products listed in this wance, the fewer the failures that will occur.
data book were manufactured based on exacting To keep failures to a minimum, the circuit should
designs and under comprehensive quality control. be designed so that under all conditions to absolute
However, to take full advantage of the features maximum, the ratings are not exceeded even
I
I
Complaint : Reply
I
I
I
Report of : Investigation
complaint I report
I
I
,-
I
I
Quality assurance
--,I
Request for I I Request for
corrective action I Report Report I
I I corrective action
I I
I I
I I
Instructions
Design and
Manufacturing
technology
Request for
corrective action
Fig. 5 Routes through which malfunctions
outside the company, are handled
----------------SHARP .----.--~-----
31
quality Assurance
,....-r..... -................~-.,.-.-....... - .................................
momentarily and so that the maximum values for that will prevent stress, frolll being applied to the
any two' or more items are not achieved simul- base of the wires should be used.
taneously. In addition, remember that the circuit To prevent the input terminals of semicondudor
functions of semiconductor products are gua'ran- products on c()mpleted printed circuit boards from
teed' within the operating temperature'range (To.,) becoming open during storage or transport, the ter-
of the absolute maximum ratings, but that storage minals oilhe circuit board should be'shortcircuited
temperature (Tstg) is the range in a nonoperating or the entire circuit board itself should be wrapped
condition. in aluminum foil.
(2) Transportation and Storage (4) Soldering and Cleaning
Semiconductor products are susceptible to high' When using a soldering iron or solder bath, keep
temperature and high humidity. Please store them the temperature below 260t the .time and within
in a dry place as near to room temperature as 10 seconds. If using a soldering'iron, use one with
possible. no leakage from the soldering tip. An A class
During shipping and storage, keep semiconduc- soldering iron with an insulation resistance of less
tor products in the packaging they were delivered than 10 Mil is recommended. When using a solder
in to prevent damage due to static electricity. If re- bath, it should be grounded to prevent its having
moved from tlIeir packaging, the terminals must be an unstable electric potential.
shortcircuited with a conductive material or the en- Using a strongly acidic or alkaline flux for
tire units wrapped in aluminum foil. Also remem- soldering can cause corrosion of the lead wires. A
ber that nylon and plastic containers build up elec- resin flux is ideal for this type of soldering.
trostatic charges easily and so should not be used To assure the reliability of a system, removal of
for storage or transportation. the flux used in soldering, is generally required.
Mechanical vibration and shock should also be Freon TE, a freon cleaning fluid, or difron solvent
kept to a minimum. S3-E is recommended for use as the cleaning fluid.
(3) Assembly To prevent stress on semiconductor products
When attached ,to printed, circuit boards, semi- and circuit board w'hen using ultrasonic cleaning, a
conductor products are removed from a conductive cleaning method must be used that will shadow the
container, so electrical equipment, work benches, main unit from the vibrator and keep cleaning time
and operators must be grounded to protect the pro- to less than 30 seconds.
ducts fmm static electricity. It is good to use (5) Adjustment and Tests
grounded metal plating on the surf(ices of work When the set is to be adjusted and tested upon
benches. Grounding metal rings and watch bands is completion of the printed circuit board, the printed
a convenient method for grounding operators. The circuit board must, be checked to ensure that there
grounding of operators is required to prevent elec- are no solder bridges or cracks ,before the power is
tric shock due to current leaks from electrical turned on. Also, if the marked rated voltage and
equipment, so it must be performed through a re- ~urrent are to be used, it is wise'to use a current
sistance of 1 Mn. limiter.
Working attire made of synthetic fabrics should Whenever a printed circuit board is to be re-
be avoided in favor of fabrics such as cotton that moved or mounted on a socket, the power must be
do not easily generate static electricity. turned off.
Keeping the relative humidity in working areas When testing with a probe, care must taken to
around 50% will 'also help to prevent the genera- assure that the probe does to' come in contact with
tion of static electricity. other signals or the power supply. If the test loca-
Current leakage from electrical equipment is not tion has been decided beforehand, it is wise to set
desirable from the standpoint of safety. All equip- , up a specially designed test pin for testing.
ment'should therefore be, checked periodically for When testing in high· and low temperatures, the
, current leakage. constant temperature bath must be groundeq and
When forming the lead wires of semiconductor measures taken to protect the set inside the bath
products to be mounted, forceps or a similar tool from static electricity.
32
Quality Assurance
Report
r--""]
'--- ....
Test is applied only to a hermetic sealed package.
Fig. Failure analysis procedure
33
4-Bit 1-Chip Microcomputers [g
. PMOS 4-Bit 1-Chlp Microcomputer SM-3A
SM-3A PMOS 4-Bit I-Chip Microcomputer

• Description • Pin Connections
The SM-3A is a 4-bit single chip PMOS micro-
computer with 2,268 bytes of ROM, and 128
words of RAM. It is well suited for low cost sys-
tems requiring many I/O control ports. K~ P
KEa 1
KE2
KE,
AD .. 0
• Features
1. PMOS process
2. ROM capacity 2,268 X 8 bits
3. RAM capacity 128 X 4 bits
4. Instructions 57
5. Subroutine nesting 2 levels
6. Input ports 8 bits
7. Output ports 37 bits
8. Input/Output ports 4 bits Top View
9. On-chip clock generator circuit
10. High voltage outputs (-38V) 27 bits
11. Single power supply -15V (TYP.)
12. Instruction cycle lOps
1a. 60-pin quad-flat package
36
PMOS 4-Bit 1-Chip Microcomputer SM-3A
• Block Diagram
Output Port
ROM
36x63x8
Frequency
Control
Clock RAM
2
8x16x4
Output 31
Port
'----------------------yr----------------------
Output Port
Symbol description
ALU : Arithmetic logic unit RC : Stack register of program counter
Acc : Accumulator Bu, BM, BL : RAM address register
C : Carry F/F X : Temporary register
PB, PU,PM, PL : Program counter S : Flag F/F
SC : Stack register of program counter DISP : Display F/F
37
PMOS 4-Bit t-Chip Microcomputer SM-3A
• ,. Pin Description
Pin I/O Type of circuit Function_
KE j -KE 4 I Pull clown Acc+--KEI-KE~
a, fJ, AK, 'TAB I Pull down Possible to test 4 bits independently
DIO j -DI0 4 I/O Complementary 3 states Acc+--DIOj -DI0 4
Rj -R 7 ci Open drain Segment output or R register output
Rs -R 22 0 Open drain R register output
F j -F 4 0 Open drain F j-F 4+--Acc
ADI-AD IO 0 Open drain BL decode output or external RAM address output
Possible to set, reset and test by command
IDF 0 Open drain
(Suitable for printer motor drive signal)
OD, R/W 0 Complementary External RAM control output
T I Pull down For test (usually connected to VDD)
ACL I Auto clear
~2 0 Complementary Synchronizing signal terminal
VI, SYNC Frequency control terminal
Vs• Power source for external RAM connection
VDD, GND Power source for logic circuit
• Absolute Maximum Ratings

Parameter Symbol Rating Unit Note
VDD -20-+0.3 V 1
Vs -20-+0.3 V 1
Pin voltage VIN -20-+0.3 V 1
VOUTI -20-+0.3 V 1,2
.
VOUT2 -40-+0.3 V 1,3
Operating temperature Topr -10-+60 "C
Storage temperature -55-+150 "C
T s ."
Note 1: The maximum applicable voltage on any pin with respect to GND.
Note 2: Applicable pins include: R/W, DIOI·DIO., OD, ADI-ADlO
Note 3: Applicable pins include : RI-R2~, FI-F4, IDF
• Electrical Characteristics (V DD =-15.0V±10%, VN=-38V, Ta=,-10-+60"C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

VIHI -2.5 V
4
V1Ll VDD =-13.5V -10.0 V
Input voltage
VIH2 -0.8 V
5
VjL2 VDD =-13.5V -10.0 V
VOH! Io =-2mA -2.0 V
6
VOLI RL = 50k il connected to VN VN+I V
VOH2 Io =-8mA -3.5 V
Output voltage 7
VOL2 RL=50kilconnected to VN VN+I V
VOH3 Io=-lmA ~L.O V
8
VOL3 R,L =50kil connected to VDD VDD+l V
Supply current IDD VDD =-15.0V -12 mA
Cycle time tc 10 f's
Note 4: Applicable pins ~, AK, TAB, KEI - KE.
Note 5: Applicable pins ACL, Vc SYNC
Note 6: Applicable pins RI- R7, FI"':F., IDF
Note 7: Applicable pins Rs- R22
Note 8: Applicable pins ADl- ADIO
38
PMOS 4-Bit 1-Chip Microcomputer SM-3A
• Applications
1. Electronic cash register
2. Hard-Hold electronic calculator with printer
3. POS terminal
4. Electronic scale
5. Vending machine
6. Microwave oven controller
- 7. Electronic sewing machine
8. Controllers of game machines
9. Others electronic appliance controller~
• System Configuration (for VTR program timer)
Control signals For channel selection
Fluorescent tube display
Rl~------;---------------f
+15V 56kO 56kO
-20V
lOOkO
Key matrix
~'-'------SHARP-'-'---------
39
PMOS 4-Bit 1-Chip Microcomputer SM-1 00/SM-1 05
SM-IOO/SM-I05 PMOS 4-Bit I-Chip

Microcomputer
The SM-100/SM-105 isa 4-bit single chip
PMOS microcomputer with 1,134 bytes of ROM;
and 64 words of RAM. It is well suited for low
cost systems requiring many I/O control ports.
• Features
1. PMOS process
2. ROM capacity 1,134X8 bits
4. Instructions 58
8. Input/Output ports 1 bit
(only SM-100)
11. Single power supply - 9V(TYP.)
12. Instruction cycle 10 ps
13. 28-pin dual-in-line package
------------~-SHARP------ ............ - - - -
40
PMOS 4-Bit 1-Chip Microcomputer SM-1 00/SM-1 05
• Block Diagram
ACL Oscillator
Output Instruction
Port 1 - - - - - - - - - - 1 Decoder
~---------v~-------~
Output Port
Symbol description
ALU : Arithmetic logic unit RC : Stack register of program counter
Acc : Accumulator DIV : Frequency divider
ACL : Auto clear CG : Clock generator
C : Carry F/F X : Temporary register
PC : Program counter ADC : RAM address register
SC : Stack register of Program counter S : Flag F/F
• Pin Description
Pin name I/O Circuit type Function
KE 1-KE 4 I Pull down Acc -KE 1-KE 4
IDF I/O Mid voltage * open drain Can be set, reset, and tested by instructions
R1-R7 0 Mid voltage * open drain Segment output or R register output
R8 -R 13 0 Mid voltage * open drain R register output
R14 -R 17 0 Mid voltage * open drain R14-R17-Acc or R register output
T I For test (Connected to V DD normally)
ACL I Auto clear
OSCIN, OSC OUT For clock oscillation
V DD , GND Power supply for logic circuit
* For SM-IOO
--.-.--.--.-..--SHARP . . . - - . - - - - - - - - - -
41
PMOS4-Bit 1-Chip Microcomputer .SM'-100/SM-1 05

Parameter Symbol Ratings Unit Note
Voo -12-+0.3 V 1
Pin voltage VIN -12-+0.3 V 1,2
VOUT -40-+0.3 V 1,3
Operating temperature Topr -10-=--+50 t
Storage temperature T S' 2
-55-+150 t
Note 1: The .maximum .illm!icable voltage on any pin with respect to GND.
Note 2: Apply to pins ACL, K,-K4, T, OSCIN, OSCOUT.
Note 3: Apply to pins RI-RI7, !DF..
• Recommended Operating Conditions

Parameter Symbol Ratings Unit
Supply voltage Voo -8.1--9.9 V
Oscillator frequency fosc 400 (TYP.) kHz
• Electrical Characteristics (V oo =-9.0V±10%, V N=-38V, Ta=25·C)

VIH1 -1.8 V
4
VILl Voo +l V
Input voltage
VIH2 -0.8 V
5
VIL2 Vo~+1 V
VOH1 IouT =-lmA -1.0 V
I SM-I00 VOLl Connect RL =50k'o' to VN
V N+l
V
6
I SM-I05 Voo +l
Output voltage VOH2 IOtJT =-8mA -1.0 V
I SM-I00 VOL2 Connect RL =50k'o' to V N
V N+.1
V
7
I SM-I05 Voo +l
Current consumption [00 10 rnA
Oscillator frequency fose 400 kHz 8
Note 4: Applied to pins KEI-KE~.
Note 5: Applied to pins ACL, T, !DF.
Note 6: Applied to pins Rl - R7, !DF.
Note 7: Applied to pins R8-R17.
Note 8: Reference oscillation: 10 ,us/cycle at 400 kHz
OSC OUT OSC 'N
42
PMOS 4-Bit 1-Chip Microcomputer SM-110/SM-115
PMOS 4-Bit I-Chip

SM-II0/SM-115 Microcomputer
The SM-1I0/SM-1I5 isa 4-bit single chip r-- . . .
I p
Nm~U')tl:lZ.t--oom ........................
PMOS microcomputer with 2,032X9 bits of ROM, ~ N N N N NIN 0 N N'N N N N N
41 31
128 words of RAM, and AID converter. It is well
suited for low cost systems requiring many I/O
control ports.
• Features
1. PMOS process
4. Instructions 90
8. InputlOutput ports 4 bits
10. Interrupt function
External interrupt 1
Timer interrupt 1
11. 8 bits AID conversion
12. Internal divider (1/50 or 1160)
13. High voltage outputs
(-35V) 21bits (only SM-lIO)
15. Instruction cycle lOps
16. 60-pin quad-flat package
~--'--------SHARP-----~--'-----
44
PMOS 4-:Bit 1-Chip Microcomputer SM-100/SM-105
• Applications
1. Various types of mechanical controllers for
video players, vending machines, etc.
2. Game machines
• System Configuration (Video timer)
Sun MOD Tue Wed Thu Fri Sat

AM n 0 0
PM I_I I_I 0
R14 Memory indicator

SM-Ioo/SM-I05
Rr5 Power-on indicator
R8
Clock Timer 50/60
----.-----.---~-SHARP --.-.~---.-.-.
43
• Block Diagram·
Input Input/Output
Port Port Output Port
~~/~ __ ~ ________ ~ __________ -JA~ ______________________ ~
Analog
Input
Port
Stack
Register ROM
(6Ievels) (2,032X9
Control
and Judge RAM
Interrupt (l28X4)
TF CG
IF
HF
15i}--------------------------{:~ U
'-v--'VDD ACL '--y----/2.5kHz "-v---"
GND Input Port Pulse Output Oscillator
Symbol description
ALU : Arithmetic logic unit PC : Program counter DA D/ A convert er
Acc : Accumulator CG : Clock generator X Temporary register
ACL : Auto clear DIV : Divider CF Comparater
C : Carry F/F BM, BL : RAM address register
45
PMOS .4-Bit l-Chip Microcomputer SM-110/SM-1.15
• Pin Description
KE 1 -KE 4 I Pull down Acc +-KE 1 -KE 4
KH I Pull down HF flag set on t ; reset by instruction
KI I Pull down IF flag set on t ; reset by instruction
KT I Pull down External timer signal input (50 or 60Hz)
KC 1 -KC 4 I Analog input or Acc +-KC 1 - KC 4
P 1 -P 4 I/O Open drain P 1 -P 4 +-Acc
QI-Q4 0 Mid voltage * operi drain Q1-Q4- Acc
Z I - Z I4 0 Mid voltage * open drain Z register output
T I For test (Connected to V00 normally)

ACL I Auto clear
F 0 2.5 kHz pulse output (System clock· 100kHz)
0 Sync' signal output
"'2+
CLio CL 2 For clock oscillation
VR, AGND AID conversion standard power supply
Voo, GND Power supply for logic circuit
* For SM-llO, ZI pin only is high voltage

Voo -12-+0.3 V 1
VIN Voo -0.3-+0.3 V 1,2
Pin voltage
VOliTI Vj)j)-0.3-+0.3 V 1,3
VOllT2 -37-+0.3 V 1,4
Storage temperature T$t~ -55-+150 "C
Note 2: Applied to pins KHI-KEI, KCI-KCI, P,-P" Kl,-KIl, KT.
Note 3: Applied to pins F, P,-P" Z,-Z,.
Note 4: Applied to pins QI-Q" RI-RI6, z,.

Parameter Symbol MIN. TYP. MAX. Unit
Supply yoltage V[)o -9.9 -8.1 V
Reference voltage VR 5/9 VDD -O.2 -4.5 V
-~-""""---'-"SHARP-~------------
46
• Electrical Characteristics (V oo =-9V±10%, VN (MAX.)=-35V, Ta=-10-70'C)

VIIIl -2 V 1
VILl Voo +2 V 1
Input voltage
VIII 2 -0.8 V 2
VIL2 -4.5 V 2
VOHl Io =-10mA -2.5 V 3
I SM-110 VaLl Connect RL=50kO to VN • VN +l V 3
VOH2 Io=-lmA -0.2 V 4
Output voltage I SM-110 VOL2 Connect RL = 50k 0 to VN. VN +l V 4
VOIU Io=-0.5mA -1 V 5
VOH4 Io=-0.2mA -1 V 6
VOL4 10= 10 /LA Voo +l V 6
lIIi VIN=OV 180 450 /LA 7
Input current
IR V R=-5V 900 1200 /LA 8
Output current IOL:) Vo=Voo -1 /LA 5
Current consumption 100 13 30 rnA 10
Oscillator frequency fosc 400 kHz 11
VR=-5V
AID conversion linear error ±3 LSB
Vo[)=-9V
VR=-5V
AID conversion zero error ±3 LSB
V[)[)=-9V
I
VR =-5V
AID covers ion full scale error ±3 LSB
V[)[)=-9V
V R=-5V
AID conversion overall error ±3 LSB
V o[)=-9V
Reset time tACL At power up 20 ms 12
Note 1: Applied to pins KE,-KE" P,-P" KI, KH, KT __
Note 2: Applied to pins KC,-KC1. (When used as a digital input), ACL.
Note 3: Applied to pins RJ(;-R"
Note 4: Applied to pins RR-R" Q,-Q" Z,.
Note 5: Applied to pins PI-P" Z,,-Z,
Note 6: Applied to pins F.
Note 7: Applied to pins KE,-KEI, KI, KH, KT.
Note 8: Applied to pins YR. (current flowing into ladder resistance for AID conversion).
Note 9: Applied to pins R,b-R" P,-P" Q,-Q" Z,,-Z1.
Note 10: Measured in no· load condition.
Note 11: Externally connected to oscillation circuit.
CF : Ceramic oscillator
KBR-400B(made by Kyocera Corp.)
R, : 1MO
C,: 220pF,C,: 220pF
l,uF /16
ALCo---~------~
56kO
Note 12: The time for reset of "Low" signal that is applied to the ACL terminal after supply voltage returns to rated level.
----.--------SHARP---~.--.----
47
PMOS 4-Bit1-Chip Microcomputer SM..:nO/SM~f15
. . . . . . . . ._ . . ._ . . . . . . .. . - .. . . . . . . ......"........ - . . - ...................:11. _ r i...~··~.....
•. Applications
1. Microwave oven controllers
2. Blood pressure monitors
3. Controllers for home appliances and audio
equipment
• ' System Configuration (Microwave oven controllers)

.Fluorescent tube display
III" n ,-,
III'd/U
Vnn
r--~J.....;:.;;:::';'::'::""-:f--:::L-....::...-~----,Crystal 220 F
400kHz P
Key matrix CL11--1_--11---,
Q--- }-........-\zs
CL2 .........~~,tF--1--;
I
I ACL tE-_-"V'.rv-~
I
I
}-.......-\Z14 SM-llO/SM-1l5
L----:-~KE4
\ V,," 1----.----<>---<> -9 V
'--------'--tKEJ
50/60Hz GNDt---t----.
signal --r--->I
AGND
48
PMOS 4-Bit I-Chip

SM-lll/SM ... 116 Microcomputer
The SM-lll1SM-116 is a 4-bit single chip Q
r--. ... N ~ ..,. It:! ~ Z t-- GO 0) ..............
PMOS microcomputer with 4,064 X 9 bits of ROM, ::<:NNNNNN(,!lNNNNNNN

41 3 3 31
192 words of RAM, and AID converter. It is well
F·
suited for low cost systems requiring many 110 KC, 7
control ports. KC,
KC 2
KC,"
VR 51
• Features
1. PMOS process
2. ROM capacity 4,064 X 9 bits I (62+
3. RAM capacity 192 X 4 bits , CL2
4. Instructions 90
1 2 3 4 5 6 7 8 91 11 1 3 4 5
6. Input ports 11 bits ~ ~ ~ ~ r:J cE c:.~ ~
(,!l (,!l
aa a a ~Id<
7. Output ports 35 bits < Top View
8. Input/Output ports 4 bits
Timer interrupt 1
11. 8 bits AID conversion
12. Internal divider (1150 or 1160)
13. High voltage outputs (-35V) 21bits (only
SM-ll1)
16. 60-pins quad-flat package
- - - - - - - - - - S H A R P .-..---------~------
49
PMOS 4-Bit1-Chip Microcomputer SM-t111SM-116
• Block Diagram
Output Port
r -____~----~--~----~----~A~----------------------------~
Analog
Input
Port
Stack
Register
(6 levels)
Control
and Judge RAM
Interrupt (192X4)
TF
IF
HF
'-v---" 2.5kHz '--y--'

Input Port Pulse, Output Oscillator
Symbol description
ALU : Arithmetic logic unit PC ,: Program counter DA D/ A converter
Ace : Accumulator CG : Clock generator X Temporary register
ACL : Auto clear DIV : Divider CF Comparater
50
• Pin Description
Pin name 110 Circuit type Function
KE 1 -KE 4 I Pull down Acc -KE 1 -KE 4
KH I Pull down HF flag set on t ; reset by instruction
KI I Pull down IF flag set on t ; reset by instruction
KT I Pull down External timer signal input (50 or 60Hz)
KC 1 -KC 4 I Analog input or Acc-KCj-KC j
P j -P 4 110 Open drain P I -P 4 -Acc
Qj-Q4 0 Mid voltage * open drain QI-Qj-Acc
ZI-ZI4 0 Mid voltage * open drain Z register output
T I For test (Connected to VI>I> normally)
ACL I Auto clear
F 0 2.5 kHz pulse output (System clock·100kHz)
1>2+ 0 Sync signal output
CLio CL 2 For clock oscillation
YR. AGND AID conversion standard power supply
VDI>. GND Power supply for logic circuit
* For SM-1l1, ZI pin only is high voltage.

VDI> -12-+0.3 V 1
VIN VDD -0.3-+0.3 V 1,2
Pin voltage
VOlITl VI>D-0.3-+0.3 V 1,3
VOllT2 -37-+0.3 V 1,4
Operating temperature Topr -10-+70 ·c
Storage temperature Tst~ -55-+150 t
Note 2: Applied to pins KEI-KEI, KCI-KCI, PI-PI, Kl, KH, KT.
Note 3: Applied to pins F, PI-PI, Z2-ZI.
Note 4: Applied to pins QI-QI, RI-RI6, ZI.

Supply voltage VDI> -9.9 -8.1 V
Reference voltage VR 5/9 VDD -O.2 -4.5 V
---.-.-..-.--------SHARP - - - - - - - - - - - - -
51
PMOS 4.:.Bit 1-Chip Microcomputer SM-111/SM-116
• Electrical Characteristics (V DD =-9V±10%, VN (MAX.)=-35V, Ta=-.10-70·C)

VIlli -2 V 1
VII. I Vllll +2 V 1
Input voltage'
VIm -0.8 V 2
V IL2 -4.5 V 2
VOIII Io =-10mA -2.5 V 3
I SM·111 VOL! Connect RL = 50kO to VN. V N+l V 3
VOlI2 Io =-lmA -2 V 4
Output voltage I SM·l11 VOL" Connect RL = 50k 0 to V N. V N+l V 4
VOIU Io=-0.5mA -1 V 5
VOII.1 Io=-0.2mA 1 V 6
Vou Io =10,uA V1)[)+1 V 6
lIN VIN=OV 180 450 ,uA 7
Input current
IR V R =-5V 900 1200 ,uA 8
Output current IoL:) VO=VDD -1 ,uA 5
Current consumption Ill[) 13 30 rnA 10
Oscillator frequency fosc 400 kHz 11
V R =-5V
AID conversion linear error ±3 LSB
V Dn =-9V
V R =-5V
AID conversion zero error ±3 LSB
V"n= -9V
V R =-5V
AID coversion full scale error ±3 LSB
VllI)=-9V
V R =-5V
AID conversion overall error ±3 LSB
V DD =-9V
Reset time t ACL . At power up 20 ms 12
Note 1: Applied to pins KE,-KEI, P,-P" KI, KH, KT
Note 2: Applied tu pins KC,-KCI. (When used as a digital input), ACL.
Note 3: Applied to pins R'6- R9
Note 4: Applied to pins RR-RI, QI-QI, Z,.
Note 5: Applied to pins PI-PI, ZII-ZI
Note 6: Applied to pin F.
Note 7: Applied to pins KEI-KEI, KI, KH, KT.
Note 8: Applied to pin YR. (current flowing into ladder resistance for AID conversion).
Note 9: Applied to pins Rlo-RI, P,-PI, Q,-QI, Z1I-Z,.
Note 10: Measured in no· load condition.
Note 11: Externally connected to oscillation circuit.
CF : Ceramic oscillator
KBR-400B(made by Kyocera Corp.)
Rf: 1MO
CI: 220pF,C2: 220pF
l,uF/16
ACL 0---+-----,
56kO
Note 12: The time for reset of "Low" signal that is applied to the ACL terminal after supply voltage returns to rated level.
52
PMOS 4-Bit 1';"Chip Microcomputer SM-114
SM-114 PMOS 4-Bit I-Chip Microcomputer

The SM-1l4 is a 4-bit single chip PMOS micro-
computer with 4,064X9 bits of ROM, 192X4 bits
of RAM, 8-bit A/D converter, timer/counter and Z14
remote control signal receiver.
It is best suited to controllers which measure
temperature and humidity of analog value from a
sensor.
• Features
1.
PMOS process R20 '
2.
ROM capacity 4,064 X 9 bits AGND
3.
RAM capacity 192X4 bits
4.
Instructions 92
5.
Subroutine nesting 6 levels
6.
Input ports 8 bits
7.
Output ports 17bits
8.
Input/Output ports 24 bits
9.
Timer/counter
7-bit 1
8-bit 1
10. Interrupt functions
Timer interrupt 2
11. 8-bit A/D conversion
12. Remote control signal receiver
13. Single power supply -9V(TYP.)
14. Instruction cycle 10 ps (TYP.)
15. 60-pin Quad-flat package
54
PMO$4-Bit 1-Chip Microcomputer SM-11~/SM-116 '
• Appli~a:tions
1. Microwave oven controllers
2. Blood pressure monitors'
3. Controllers for home applia,nces and audio
equipment
• System Configuration (Microwave oven controllers)
I I I / ' ,-,,-,I
LII "LlU
Vuu
Key matrix
0---
I
}-..e---\Zs
CL2r-+-~~~-+-,
I
I
I ACL IE--.--IIM---'
I
}-+----\Z14 SM-lll /SM-116
'-------:---.>-IKE 4
lkO
VI>I)I---1'--~-o-9V
\
'---------~KEI
SO/60Hz GNDf---+'-----.
signal----1o---+I
AGND
lOOkO iOOkO lOO'kO
53
PMOS 4-Bit 1-Chip Microcomputer SM-114
• Block Diagram
.
Input' Output Port
Output
Port ,
Symbol description Input Port
ALV : Arithmetic logic unit PC Program counter RCV Remote control unit
A .... : Accumula tor Stack register of program counter D/A D A converter
SR
ACL : Auto clear
SP Stack pointer COMP Comparator
C : Carry F F
CY : Over flow F F INT Interrupt control unit DIV Divider
B : RAM address register CG Clock generator VR Reference Voltage
------~.--SHARP.-----~--.-..---
55
PMOS.4-Bit 1-Chip Microcomputer ·SM-H4
• Pin Description
KC o -KC:1 I Analog input or Acc-KCo-KC:l
KL I Pull down* .' For optical remote control circuit
KI, KH I Pull
. *
down. IF, HF flag set on t -.
KT I Pull down* • External timer signal input
PO-P:l
QO-Q3 110 Open drain/Pull down * Acc-
!PO""'P:l
QO-Q:l RO, R1, R3-RAM
RO(;-R3:1 RO,R1,R3
ZO-ZI5 0 Open dra{n/Pull down * Can be set, reset individually
F 0 Sound output
TA,TB I Pull down For test (Connected to VDD normally)
ACL I Auto clear
~ 0 System clocj{ output
CLl> CL 2 For clock oscillation
VR, AGND A/D coversion standard power supply
Voo , GND Power supply for logic circuit
* Mask option

Voo -12-+0.3 V
Pin voltage VIN (Voo-0.3)-+0.3 V 1
VOllT (V 00-0.3)- +0.3 V
. Operating temperature Topr -10-+70 ·C
Storage temperature TSt2 -50-+150 "C

Supply voltage Voo -9.9 -8.1 V
Reference voltage VR -4.5 . 5/9VDD-O.2 V
56
• Electrical Characteristics (V ee =-9V±10%, Ta=-10-70'C)
Ratings
Parameter Symbol Conditions Unit Note
MIN. TYP. MAX.
VIHI -1 V'
1
VILl Voo +1 V
VIII2 -2 V
Input voltage 2
VIL2 Voo +1 V
VIII :l -0.8 V
3
VIL:l Voo +1 V
VOH! lo=-2mA -1 V
4
VaLl 10=20 pA Voo +1 Voo +1.5 V
OutJ'Ut voltage
VOH2 Io =-2rnA -1 V
5
VOL2 RL =50kO Voo +1 V
Inll VIN=OV 180 pA 6
Input current
IR VR =-5V 500 900 pA 7
Current consumption 100 20 rnA 8
AID conversion linear error V R =-5V ±3 LSB
AID conversion zero error VR =-5V ±3 LSB
AID conversion full scale error VR =-5V ±3 LSB
Note 1: Applied to pins
RO:l-ROo, RIa-RIo, R2:l-R20, R3:l-R30, POI-PO, Q:l-Qo
KI, KH, KL, KT
Note 3: Applied to KC:.- Keo (when used as a digital input), ACL.
pins
RO:l-ROo, Rl:!-RIo, R2:l-R20, R3:l-R30, POI-PO, Q:l-Qo, Z,,-Zo, F
(when an internal pull-down resistance is attached to R, P, Q, and Z)
Note 5: Applied to pins RO:l-ROo, Rl:!-RIo, R2:l-R20, R3,,-R30, P,,-Po, Q:l-Qo, ZI'-ZO
(when an internal pull-down resistance is not attached).
Note 6: Applied to pins RO,,-ROo, Rl:!-RIo, R2,,-R20, R3:I-R30, P,,-Po, Q,,-Qo, KI, KH, KL, KT
(when an internal pUll-down resistance is attached)
Note 7: Applied to pin V. (current folwing into ladder resistance for AID conversion)
Note 8: Measured in no-load condition_
Note 9: Externally connected to oscillation circuit
Rr=lMO
CI = 220pF
C2=220pF
57
PMQS, 4-Bit 1-Chip Microcomputer . SM-:-114
• System Configuration (Controllers)
Control signals Control signals

, - -_ _~A , ~
R33 - R30 R23 - .R2o Zo - Z9
----:----1Rl, ZlS.-------,
I
P3 k - - - - '
------I RIo P2i------'
....---.---IR0 3 Pli-------~
Control signals I Po~-----~---'
--......c.--IRO o
+-:--:---IQ3 KTt+---
KI t - - - - } Sensor input 1
I
KHk----
------IQo
-------IF KC 3 }
Optical remote ~ \ Sensor input 2
control input o------IKL KColE---- (analog input)
, - - - - - - - 1 AGND
.------IGND
TB
TA V»»
C+-~- 1:~
To VDD
56k!l ,--1_M_!l-4_ _
220pF I
58
SM-120 PMOS 4-Bit I-Chip Microcomputer

The SM-120 is a 4-bit single chip PMOS micro-
computer with 1,536 bytes of ROM, 64 words of
RAM, and a 17-stage divider. It is well suited for
low cost systems requiring many 110 control ports.
• Features
1. PMOS process
4. Instructions 54
8. External ROM expandable (512 X 8 bits)
10. Internal 17-stage divider with reset (timer cir-
cuit)
11. Alarm sound generator circut
14. Instruction cycle 10 p.s
59
• Block Diagram
Output 'Port Output Port

~ __ ~A ___ ~
Port
Input Port
'--v-" Voo
GND
Symbol description
ALU Arithmetic logic unit SRI, SR, Stack register of program counter
Ace Accumulator DIVo, DIVI, DIV2 Divider
ACL Auto clear CG Clock generator
PC Program counter H,L RAM address register
60
• Pin Description
Pin lIO Type of circuit Function
P IO -P I3 I Pull down Aee-PlO-PI3
P 2O -P 23 I Pull down Aec -P 20 - P 23
PI I Pull down PI flag set by t, reset by command
BIO -B I3 0 Pull down BlO-BI3+-Ace
R 0 Pull down Possible to set, reset, or CE signal output
0 0 Pull down Possible to set and reset
Display segment signal output or internal ROM
So-5 7 0 Open drain
data output
0 0-0 10 0 Open drain Display digit signal output
F 0 Pull down Alarm sound output
T I Pull down For test
ACL I Pull down Auto clear
OSCIN, OSCOUT Clock oscillation
VDD, GND Power source for logic circuit

VDD -20-+0.3 V 1
VIN -20-+0.3 V 1,2
Pin voltage
VOUTl -20-+0.3 V 1,3
VOUTZ -40-+0.3 V 1,4
Operating temperature Toor -10-+65 "C
Storage temperature TstQ -55-+150 "C
Note 2: Applicable to inputs
Note 3: Applicable Pins BIO- Bt:l, a, aSCOlIT, R, F
Note 4: Applica.ble Pins Do- DlO, SO-S7
• Operating Conditions
P¥ameter Symbol Specified value Unit Note
Supply voltage V DD -8.1--9.9 V
Oscillator frequency fose 300-800 kHz 5
Note 5: Frequency supplied to aSCIN Pin.
61
......-.-....-:--,..-..-.-.-.-.-.-..-.-....... -
PMOS4-Bit1-Chip Microcomputer
;~---
'SM-120
• Electrical Characteristics (V DD =-9.0±10%. V N=-36V, Ta=-10":"+65"C)

ViHl -3.5 V
6
V ILl -7.0 V
Input voltage
VIH2 -1.5 V
7
V IL2 -7.0 V
:IIHl VIN=GND 200 pA
8
IILl VIN=V DD ' -10.0 pA
IIH2 VIN='GND 700 pA
Input current 9
IIL2 VIN=VDD -10.0 pA
IIH3 VIN=GND 5.0 pA
10
IIL3 VIN=VDD -10.0 pA'
VOHl IoH =-6.0rnA -2;5 V
11
VOLl RL =50kO connected to V N V N+1.0 V
VOH2 IoH =-2.0rnA -2.0 V
12
VOL2 RL =50kO connected to V N V N+1.0 V
VOH3 IOH=-0.5mA -3.0 V
VOL3 IoL =50 pA V DD +1.5 V
Output voltage ' V'OL3 IoL =200pA V Do +3.0 V
VOH4 IoH =-1.0mA -1.5 V
YOL4 IOL=50pA V Do +1.5 V 14
Y'OL4 IOL=200pA V Do +3.0 V
VOHS IoH =-1.0rnA -1.5 V
VOLS IOL=100pA V DD +1.5 V 15
V'OLS, IOL=300pA V Do +3.0 V
Current consumption IDD 20 rnA
Note 6: Applicable pins PIO- PI3, P20- P':J
Note 7: Applicable pins PI, ACL, aSCIN, T
Note 8: Applicable pins PIO-PIS, P'O-P'3, PI, T
Note 9: Applicable pin ACL
Note 10: Applicable pin asclN ,
Note 11: Applicable pins DIO-DI3
Note 12: Applicable pins SO-S7
Note 13: Applicable pins BIO- B13, F
Note 14: Applicable pins R,a
Note 15: Applicable pin aSCOl1T
• Applications
1. VTR timer
2. Electronic home appliance controller
3. Game machine
• System Configuration (for 5 X 7 dot matrix fluorescent display tube drive)
5 x 7 dot matrix fluorescent display tube
r-------------~-- --------------
27kO 27kO lOkO IOkO
Power for display Crystal -36VO--"I/VIr-T
-36V 524.288kHz -36V
2.2kO 470pF
~--+--IDo Sot---~+-+I Ao
SM-120 ( Ll2048
) (Dot matrix driver)
I
I
I
I
--------6
Key matrix
---.-------SHARP.-.--...-.----
63
.....----. ~-- -
..... ....................,,----..........,..... -
SM:..200
SM-200 NMOS 4-Bit I-Chip Microcomputer

The SM-200 is 4-bit single .chip NMOS micro- Q
computer with 3,072X9 bits of ROM, 132 words of 22 r... d: rE d: ~ ~ rE ~ ~.:2~ ll~'
RAM, automatic display circuit, and a 16-stage
OSCIN"
divider. It is well suited for low cost systems re- SCOUT 7
qlliring many 110 control ports. CT 8
aD
• Features
1. NMOS process
3. RAM capacity 128X4+ 16 bits
4. Instructions 100
7. Output ports 37 bits Top View
9. Enable 8 bits parallel input/output
10. Externally ROM/RAM expandable
11. External interrupt function
12. Internal 16-stage divider ·with reset
(timer circuit)
13. Serial interfaces 8 bits
15. Single power supply 5V (TYP.)
16. Instruction cycle 10 p.s
64
NMOS 4-Bit 1-Chip Microcomputer SM-200
• Pin Description
Pin I/O Type of circuit Function
Ko-K 3 I Pull down ACCI-Ko-Ka
1. I Set by t, reset of after test instruction execution
h I Internal clock period type, test possible
CT I Open For pulse count per unit time
Pull down ACCI-PIO-PI3, Instruction code input for external
P IO -P I3 I
ROM
Acc2-P20-P2:j, Instruction code input for external
P 2O -P 23 I/O Pull down for input
ROM data transter from/to RAM for external RAM
Set, reset by instruction; chip select for external ROM
RW 0
Connected to RW pin for external RAM
Set, reset by instruction; Instruction code input for
OD 0
external ROM; connected to OD pin for external RAM
Eo-E 3 0 Eo-E3-Accl
BIO -B I3 0 BlO-BI3-Accl ,
B20 -B 23 0 B2o-B23-AcC2
0 1 -0 3 0 Set, reset by instruction
Display digit signal output; Address signal output for
Do-D l l 0
external ROM, RAM
0 0 -0 7 0 Display segment signal output
F 0 Alarm sound output ,
INT I Pull down Set of INT F/F by t

OSC IN, OSCOUT Clock oscillation
VDD, GND Power supply for logic circuit

VDD -0.5-+7 V
Pin voltage 1
VIN -0.5-V DD +0.3 V
Storage temperature T st• -55-+150 "C
Note 1: The maximum applicable voltage on any pin with respect to Vss (GND)
Parameter Symbol Specified value Unit
Supply voltage VDD 4.5-5.5 V
Oscillator frequency fosc 262.144 kHz
--------------SHARP---.----------
66
NMOS 4-Bit 1-:-Chip Microcomputer SM... 200
,...."~I1fIfIfIIII'....,,,..,~.,.,,,;•.•~~'-~"""~..tIIIIIIIII!IP....-.r~"""""""A!IIIIIIIIW
• Block Diagram
Divided
Display Segment Output Display Digit Output
r - __________ ~A~ ____________ ~
Osci- { 46
Bator 47
Pulse
Input
Asynchronous
Input
Symbol description
ALU : Arithmetic logic unit CG : Clock generator
Acc,. Acc2' : Accumulator DIV : Divider
ACL : Auto dear H.L : RAM address r,!'gister
C : Carry F/F SD : Segment decoder
PC : Program counter DD : Digit decoder
SR,. SR2. SR3 : Stack register of program counter X.Y : Temporary register
65
NMOS 4-Bit 1-Chip Microcomputer SM-200
• Electrical Characteristics (VI)I)=5V, Vss=GND, fosc =262kHz, Ta=25"C)

VIlli 2.4 5 V
2
VILI 0 0.5 V
Input voltage
VIII2 2.4 5 V
3
VIL2 0 0.6 V
11111 VIN =5V 15 50 pA
4
IlL I VIN=GND -1 -10 pA
11112 VIN =5V 1 10 pA
5
Input current IIL2 VIN=GND -1 -10 pA
1m3 VIII =5V 5 25 pA 6
11114 15 50 pA
7
hL4 pA
VOIll IOH=10pA 3.6 5 V
V'OIll 101l=0.2mA 2.4 5 V 8
VOLI I 10L I =0.15mA 0 0.5 V
VOH2 IOIl-25pA 3.6 5 V
V'01l2 IOIl=0.6mA 2.4 5 V 9
VOL2 I 101. I =0.25mA 0 0.5 V
VOll3 1011 =10 pA 3.6 5 V
V'OIl3 1011 = O.4mA 2.4 5 V 10
VOL3 I 10L I =0.3mA 0 0.5 V
Output voltage VOll4 IOII=10pA 3.6 5 V
V'01l4 IOIl=0.3mA 2.4 5 V 11
VOL4 I IOL I = 0.3mA 0 0.5 V
VOIIS 1011 =10 pA 3.5 5 V
V'OH5 IOH=0.3mA 2.4 5 V 12
VOLS I IOL I =50 pA 0 0.5 V
VOH6 IOH=0.2mA 2.4 5 V
13
VOL6 I IOL I =0.25mA 0 0.5 V
VOH7 IOII=0.15mA 2.4 5 V
14
VOL7 I IOL I =0.15mA 0 0.5 V
VOH8 IOH=50pA 3.6 5 V
15
VOL8 I IOL I =50 pA 0 0.5 V
Current consumption 100 Open all input and output" pins 32 56 rnA
Note 2: Applicable pins PIO-PI3, h-]2, INT, CT, ACL, P20- Note 9: Applicable pins So- S7
P23 in input mode, OD in input mode. Note 10: Applicable pin RW
Note 3: Applicable pins Ko- K3 Note 11: Applicable pin F
Note 4: Applicable pins PIO-PI3, Ko-K3, 11,]2, INT, P20-P23 Note 12: Applicable pins Do-[hl-
in input mode, OD in input mode Note 13: Applicable pin OD in output mode
Note 5: Applicable pin CT Note 14: Applicable pins P20-P23 in output mode
Note 6: Applicable pin OSC IN Note 15: Applicable pin OSCOUT
Note 8: Applicable pins BIO-BI3, B20-B23, Eo-E3, 01-03
• Applications
1. General·purpose program timer 6. Copy machine controller
2. Controllers for electronic home appliances, 7 . Vending Machine
Audio equipment, Office machines 8. Radio cassette tape recorder and PLL controller
3. Door chime, Home security system 9. TV remote control and channel controller
4. Hand-held calculator with printer
5. Cash register
- - - - - - - - - S H A R P -----.-.---------.-..-.-
67
~I • 'I·~·'
-I
;;;: ;;;: en
~ ~;;;: >ri en
I "" _....,c:: }Key input '<
en
d
CD
MK output 3
I FU output (2)
:::0
~
oo
-...
::::J
I I~
E2 t----->-
(Output level reverses on each FU input) "-
;;;: cO'
EI I - - MT output c::::
'0-"
I FU output OD
INT
Eo
03
02
PC5 output Melody output
Radio ON/OFF
~
'"~.
~
o
::::J
...,
I o~
II
g.
I DC
+ 5V output
77r
Counter control
VDD
RW
J2
SM·200
01
B23
o
....
s
E.
I
B22
I
K3 K2 KI
A JI
ACL
Dl1
Dlo
B21
B20
BI21MUTE
ON/OFF SQ r'l'1' '"'
-5'
~
....
'0
oC/)
Cb
'I
~ 'og."'
D9 Bl1
~
DB
D, (GND)
BIO
s, P L L shift register term inal
....
2. I
I
. il6 il6 D. il6 n, DI il6 Vss 80 81 82 83 8. 85 86 :;;
.:::!-.
I
I
I
I
II
I I
I I
I
I U
CMOS 4:-Bit 1-Chip, Microcomputer SM-4A
SM-4A CMOS 4-Bit I-Chip Microcomputer

The SM-4A is a 4-bit single chip CMOS micro- ~~~~~~~~~~~:~::
computer with 2,268 bytes of ROM, 96 words of 0000000"0000000
RAM, a 15-stage divider and 68-segment liquid

crystal driver circuits. It is well suited for ap-
plications of low power hand-held equipment with
many liquid crystal display segments.
• Features
1. CMOS process
3. RAM cap~city 96 X 4 bits
1 2 3 4 5 6 7 I! 9 1 11 1 13 41
4. Instructions 54
5. Subroutine nesting 1 level
....
0000:':
SSSS
M N ...... ~ c:tl.Q N ~ ..,. z
z:'::'::':U'
" C/lU
5'"''"'
r- ... N
6. Input ports 6 bits o ~ Top View

9. On-chip 50-stage divider with reset
(timer circuit)
. 10. External RAM driver (256 X 4 bits)
11. Direct LCD driver circuits (3V, 112 duty,
112 bias and 68 segments MAX.)
12. Standby mode (10 fJ-A current consumption)
13. Single power supply - 3V (TYP.)
14. Instruction cycle 61 fJ-S
- . - . - - - . - - - S H A R P ........ .-..---~---
69
CMds 4-Bit 1-Chip Microcomputer . SM-4A
..............................._ .........,.............AIIIIiiIIIiF.....'...._ . ....""....
• Block Diagram
Segment Output
r-___________________________________ ________________________________
~A~ ~
Segment
Output
Segment
Output
'---v--" '-v-'~ ~~
I/O Port Asynchronous Input Port Oscillator Test
Input
Symbol description
ALU : Arithmetic logic unit BM. BL : RAM address register
AI'c : Accumulator DIV : Frequency divider
ACL : Auto clear PLA : Programable logic array
C : Carry F/F CG : Clock generator
Cx. CA. Pu. PL : Program counter WI-W,. Wl';...W. : Static shift·register
Cs. SUo SL : Stack register of program counter
70
CMOS 4-Bit 1-Chip Microcomputer SM-4A
• Pin Description
Pin 110 Type of circuit Function
K1 -K 4 I Pull down Acc+-K l -K 4
a I Pull down Set by t, reset after test instruction execution
f3 I Pull down Input signal is held for 1 instruction, test possible
DIO I -DI0 4 110 3-state output Acc-DIO I - DI0 4
Rl -R 4 0 Complementary Rl -R 4 +-Acc
01l-048 Output of Wand W' registers' content; used for LCD
0
OSlo OS2 segment output
3-state level output possible, used for LCD common
Hb H2 0
output
BA I Pull up For low voltage detection circuit
Tlo T2 I For test (usually connected to V00)
ACL I Auto clear
OSC lN , OSC OllT For clock oscillation
VM Power supply for LCD driver
GND, Voo Power supply for logic circuit

Voo -,3.5-+0.3 V
Pin voltage VM -3.5-+0.3 V 1
VlN V00-0.3- +0.3 V
Operating temperature T oDr -5-+55 "C
Storage temperature Tst2 -55-+150 "C
Note 1: The maximum applicable voltage on any pin witb respect to GND.
Supply voltage VM Voo/2 (TYP.) V
Oscillator frequency fose 32.768 (TYP.) kHz
'-'-~-----"'--'--SHARP -----..--,-~----..--~
71
CMOS 4-Bit 1-Chip Microcomputer 'SM-4A
• Electrical Characteristics (V oo =-3.2--2.6V, Ta=25"C)

V UIl • -0.6 V
2
V ILl Voo+0.6 V
Input voltage
Vmz -0.3 V
3
V IL2 V nn +0.3 V
VOHI louT-50 pA to Voo -0.5 V
4
VOLl IOllT =5,uA to GND . V nn +0.5 V
VOH2 IOllT=50 pA to Vno -0.5 V
5
VOL2 loUT = 30 pA to GND Voo+0.5. V
VOII:l IOUT=50 pA to Vnn -0.5 V
Output voltage 6
VOL:l IOlIT=50 pA to GND Vnn +0.5 V
VOA No load -0.3 V
VOB Voo =-3.0V -1.5 V 7
Voc V M =-1.5V -2.7 V
Iso VOllT =-0.2V 100 'pA
Ou.tput curreBt 8
ISIN VOllT=Vno+0.2V 100 pA
InA In full- range operation 50 100 pA
Current consumption
Ins When system clock is stationary 10 20 pA
Note 2: Applicable pins KI, K2, K3, K" a, f3
Note 3: Applicable pin ACL '
Note 4: Applicable pins 0'8-0ll, Osl, OS2
Note 5: Applicable pins DIOI-DIO,
Note 6: Applicable pins R2, R3, R,
Note 7: Applicable pins HI, H2
Note 8: Applicable pin RI
72
• Applications
1. Hand-held calculator with clock function
2. High-quality clock
3. Cash register
4. General-purpose timer
5. Electronic scale
6. Game machine
7. Vending machine
8. Controllers for electronic home appliances
and audio equipment
• System Configuration (for radio PLL controller)
LCD
DC voltage cutout O.02JlF

r---:~~.....J._--:::--.......Ji...--'32. 768kHz 22 pF
Band selection OSCOUTI--+----I
r~-~BA
Tape stop
GND~-~~~~Nr~~~_,
Various controls { SM-4A V y. J--+_---,

220kO
PLL latch DIal V[)~-~~~+-----'
PLL shift register' clock DI0 2 O_33,uF
PLL shift register data DI0 3 ACL
MUTE DIO.
a P
047-----;~
046---~
045---~
04'---~
043-----;~
O.2-----;~
038--~
.-.----------SHARP-.-.-------
73
.---....--.... ........
CMOS 4-Bit 1-Chip Microcomputer
-...., .-- -.".-~
.. ....- ....-
/' SM-SA
SM-SA CMOS 4-Bit I-Chip Microcomputer

The SM-5A is a 4-bit single chip CMOS micro-
crystal driver. circuit. It is well suited for ap-
• Features
1. CMOS process
4. Instructions 51
8. On-chip 15-stage divider with reset·
(timer circuit)
9. Direct LCD driver circuit
(3V, 112 duty, 112 bias and 72 segments
MAX.)
10. On-chip crystal-controlled oscillator
(32.768kHz)
11. Standby mode (10 pA current consumption)
74
• Block Diagram
Segment ______________________
r -____________________ Output
--JA~ ~
Segment
Output
fl 5
. Segment
Output
,)-------{23 22:)-------------'
~ '--v---' ~ '--v--'
Output Asynchronous Input Port Oscillator
Port Input
Symbol description
ALU : Arithmetic logic unit CF : Carry F/F
Acc : Accumulator CA, CB, Pu, PL : Program counter
CG : Clock generator Cs, Su, SL : Stack register of program counter
ACL: Auto clear WI-W4, WI' -W4' : Static shift register
DIV : Frequency divider BM,BL : RAM address register
C : Carry flag
75
-~ ............... .. ...... .......... .. .... .. ..... ..........
CMOS 4-:-Bit 1-Chip MicrOComputer
~ ~ ~ ~ ~ ~ ~ ~
SM-5A
• Pin Oescription
K1 -K 4 I Pull down Acc-K 1 -K 4
a ,{J I Pull up Independent test possible
0 11 -0 48 Output of cont!!nts of Wand W' registers; used for out-'
0
OSI-0S4 ,put oLLCD segment
3,-state, level output possible; used for LCD common
H},H2 0
output
- -
R1 -R 4
R 1 -R 4-Acc, R 1 --·,Control output or alarm sound
0
output
Tp I For test (usually open)
T}, T2 I For test (usually connected to GND)
ACL I Auto clear
,
OSCIN, OSCOUT For clock oscillation
Voo• GND Power supply for logic circuit

Voo -3.5-+;0.3 V
Pin voltage VM -3.5-+0.3 V 1
VIN VDo -0.3-+0.3 V
Operating temperature Topr -5-+50 'C
Storage temperature To,,, -55-+150 'C
Note 1: The maximum applicable voltage on any pin with respect. to GND (GND=OV)
Supply voltage VM Voo/2 (TYP.) V
Oscillator frequency lose 32.768 (TYP.) kHz
....... -------~--SHARP'.-.----.-.--.--. ......... -

76
• Electrical Characteristics (V oo =-3.0V±10%,GND=OV, Ta=25t)

VIH -0.6 V
Input voltage 2
VIL Voo+0.6 V
IlHl VIN=OV 15 pA
3
IlLl VIN =-3.0V 1.5 pA
Input ,current
IIH2 VIN=OV 1 pA
4
IlL2 V lN =-3.0V 1 pA
VOHl IouT=30 pA to Voo -0.5 V
5
VOLl IouT= 10 pA to GND Voo+0.5 V
VOH2 IouT=100 pA to Voo -0.5 V
6
Output voltage VOL2 IouT= 100 pA to GND Voo+0.5 V
VOA -0.3 0 V
VOB No load VM =-1.5V -1.8 -1.5 -1.2 V 7
Vc -3.0 -2.7 V
lOA In full-range operation 50 100 pA
Current consumption 8
Ios When system clock is stationary 10 20 pA
Oscillator start time Tosc 2 5 s 9
Note 2: Applicable pins Kl, K2, K3, K4, a, fJ, ACL
Note 3: Applicable pins Kl, K2, K3, K,
Note 4: Applicable pins a, fJ
~ -----VOH
Note 5: Applicable pins ~I,..QS'!......O~ OSI, all ----------VOA
Note 6: Applicable pins RI, R2, R:l, RI
Note 7: Applicable pins HI, H2
Note 8: Mean current consumption at 32.768 kHz ------Voc
Note 9: Oscillating circuit constant
• Oscillator circuit
Oscillator circuit constant

Co=C G =15- 20.u F
---'--------SHARP------....-.--
77
CMOS 4-Bit 1-Chip Microcomputer SM-SA
• Applications
1. Hand-held electronic calculator with clock
2. High-quality clock
3. Cash register
4. Hand-held electronic culculator with printer
5. pas terminal
6. Electronic scale
7. Game machine
8. Vending machine
9. Controller for electronic home appliances and
audio equipment
• System Configuration (for LCD game machine)
AMI D·DD
PM U'UU
LCD
DC voltage cutout O.02,uF
r---'-~-"------'--"""32.768kHz 20pF
0" OSConJ-....,..--i
Piezoelectric buzzer =
Left Right
-------~------SHARP----.-----
78
CMOS 4-Bit 1-Chip Microcomputer SM-5L
SM-SL CMOS 4-Bit I-Chip Microcomputer

The SM-5L is a 4-bit single chip CMOS micro-
computer with 1,827 bytes of ROM, 65 words of o
~~;;"'MN_~
0 0 :.: :.: :.: :.: "
d Ie:. . uN-
'" <:!:I. ..: z >>
crystal driver circuit. It is well suited for ap-
• Features
1. CMOS process
3. RAM capacity 65X4 bits
4. Instructions 51 100 '"
5. Subroutine nesting 1 level ooooooozooooooo
.... .., In In It) IJ') \CO ID t-- r-- l'- I'-
6. Input ports 6 bits " Top View

(timer circuit)
9. Direct LCD driver circuit (3V, 112 duty, 112
bias and 72 segments MAX.)
10. On-chip crystal controlled oscillator
(32.768kHz)
11. Standby mode (2.5 pA current consumption)
79
CMOS 4-Bit ~1-Chip M i c r o c o m p u t e r ' SM:~5L
' ..................................... ----~ .................,...........................
• Block Diagram
Segirient ______________________
r -____________________ Output
~A~ ~
Segment
Output
~ '-----y--/ '--y---J '>--y-/

Output Asynchronous Input Port Oscillator
Port Input
Symbol description
ALU : Arithmetic logic unit CA, CD, Pu, PL : Program c.ounter
Acc : Accumulator Cs, Su, SL : Stack register of program counter
CG : Clock generator WI-W4, WI' c--W.' : Static shift resister
ACL : Auto clear BM,BL : RAM address register
DIV : Frequency divider DDe : LCD supply voltage generator
C : Carry F/F
80
• Pin Description
K1 -K 4 I Pull down Acc+-K 1 -K 4
a,p I Pull up Independent test possible '
0 11 -0 48 Output of contents of Wand W' registers; used for out-
0
OSI-0S4 put of LCD segment
3-state level output possible; usep for LCD common
HI> H2 0
output
- - R 1 - R4+- Ace, RI "'Control output or alarm sound
RI -R 4 0
output
Tp I For test (usually open)
TI> T2 I For test (usually connected to GND)
ACL I Auto clear
OSC IN , OSCOUT For clock oscillation
VDD , GND Power supply for logic circuit

VDD -3.5-+0.3 V
Pin voltage 1
VIN VDD -0.3-+0.3 V
Note 1: The maximum applicable voltage on any pin with respect to GND (GND=OV)
'. Operating Conditions'

Supply voltage V DD -3.3--2.7 V
-"'-''--~''''''''---SHARP'-~---~---
81
• Electrical Characteristics (Voo= -3.0V± 10%, GND=OV, Ta='25°C)

, ,
Parameter Symbol Conditions MIN. , TYP. MAX. Unit Note

V IH -0.6 V
Input voltage 2
V 1L V oo +0.6 V
IIH! 15 pA 3
Input current IIL2 1 pA 4
IIH3 3 pA 5
V OHl louT=30 pA to Voo -0.5 V
6
V OLI IOllT= 10 pA to GND Voo+0.5 V
VOH2 louT=100 pAtoVoo -0.5 V
7
Output voltage V OL2 IOlJT=100 pA to GND Voo+0.5 V
V OA -0.3 V
V OB No load V M= -1.5V -1.8 -1.2 V 8
Voc -2.7 V
VM C 1 =C 2 =0.1 pF -1.8 -1.5 -1.2 V 9
100 In Full-range operation 50 100 pA
10 When system clock is stationary 2.5 5 pA
Oscillation start time Tosc 2 5 s 11
Note 2: Applicable pins KI- K" a, fJ, ACL
Note 3: Applicable pins KI - K,
Note 4: Applicable pins a, fJ
Note 6: Applicable pins ~I --::QSI, Oi, (i = 1- 4, j = 1 - 8) • Waveform of Hlo H2
Note 7: Applicable pins RI- RI
__________ V""
~ ------ Vo "
-
Note 8: Applicable pins HI, H,
Note 9: Applicable pin VM
Note 10: Mean current consumption at 32.768kHz ------ Vile
Note 11: Oscillating circuit constant Ce, CD= 15-22pF
• Oscillation circuit, Intermediate potential

generator circuit
wJ'
OSC" OSCOt:T
1rlDi~1 1 er :1:.,
Cc
'T2 PF "t2PF lr o.l ttF o.l tt

pC
-----------SHARP - . - - - - - - - - - - -
82
• Applications
1. Digital watch
2. Game machine
3. Controller for electronic home appliances and
audio equipment
4. Hand -held electronic calculator with clock
• System Configuration
LCD
~tt==~---------
I r- DC voltage
.-t-±",-"""-1cutout O.02}lF
.--...J.._--....:.....-.1.---,Crys~al 22 pF
HI aj; (36 lines) aSCol'TH-l11---.
22 pF
H2 ascI~ '--'---R~
Rt ACL
SM-5L
VDD
Key matrix
- - - - . -.......... ------SHARP--~--------
83
CMOS 4-Bit 1-Chip Microcomputer SM-SOO
. . . . .. - . -_ _ _ _ _ _ _. . . .. -. . . .. - . -___ ~_~ _ _............._r......
SM-500 CMOS 4-Bit I-Chip Microcomputer

The SM-500 is a 4-bit single chip CMOS micro- Cl
,computer with 1,197 bytes of ROM, 40 words of. 86686~668666

RAM, a 15-stage divider and 40-segment liquid 3 a
O~2
crystal driver circuits. It is well suited for applica-
tions of low cost, low-power hand-held equipment
with liquid crystal display.
ose""
• Features VillI
K.
1. CMOS process
K.
2. ROM capacity 1,197X8 bits K2
4. Instructions 52
<5 <5 ci! c>: c>: Ii ~ I... 0>. ~ d ~
5. Subroutine nesting 1 level " <
6. Input ports 6 bits Top View
' 8. Input/Output ports 8 bits
9. On-cp.ip 15-stage divider with reset
(timer circuit)
(32.768kHz)
84
CMOS 4-Bit 1-Chip Microcomputer SM-500
• Block Diagram
Segment Output
ROM
(1,197 X8) I/O Port
'---y-/ ACL '--y--/

Oscillator Common Output
Symbol description
ALU : Arithmetic logic unit WI - W4, WI' - W4' : Static shift register
Acc : Accumulator BM, BL : RAM address register
ACL : Auto clear Bp : Backplate signal generator circuit
C : Carry F/F KF : Hit F/F
CA, CB, Pu, PL : Program counter Ks : 4-bit F/F
C~, Su, SL : Stack register of program counter S : 4-hit F/F (status register)
CG : Clock generator K : Key input F/F
DIV : Frequency divider
-..-.---------SHARP-----------
85
CMOS 4-Bit 1-Chip Microcomputer 8M-500
• Pin Description
K1 -K 4 I Pull down Acc+-K 1-K 4
a,f3 I Pull up Independent test possible
Output of contents of Wand W' registers or input/out·
0 11 -0 41 I/O
put to/ from KF register
Output of contents of Wand W' registers or i.nput/out·
. OSI-OS4 110
put to/from Ks register
Output of contents of Wand W' registers; Used for
0 12 -0 46 0
LCD segment output
3·state level output possible; used for LCD common
HI> H2 0
output
R1 -R 4 0 R1-R 4-Acc
T I Pull up For test (usually connected to GND)
OSCIN , OSCOUT For clock oscillation
• Absolute .Maximum Ratings

?arameter Symbol Rating Unit Note
Voo -4.0-+0.3 V
VM Voo -+0.3 V
Pin voltage 1
VIN VDD -0.3-+0.3 V
VOUT VDo -0.3-+0.3 V
Operating temperature T_ -10-+70 t
Storage temperature T stg -55-+150 t
Note 1: The maximum applicable voltage on aity pin with respect to GND.
Voo -3.3--2.7 V
Supply voltage
VM V00/2 (TYP.) V
'-'-~'---------SHARP ...--...--,.--------
86
CMQS 4-Bit1-Chip Microcomputer SM-SOO
• Electrical Characteristics (Voo=-3.0V±10%, GND=OV, Ta=25'C)

V IH -0.6 V
Input voltage 2
V1L Voo+0.6 V
IHl V1N=OV 15 pA 3
Input current IH2 V1N=OV 3 pA 4
IL3 VIN=Voo 1 pA 5
VOA -0.3 V
Output voltage Vos No load VM=VOOI2 V M-0.3 V M+0.3 V 6
Voc Voo+0.3 V
10HI VoUT =-0.5V 30 pA
7
lOLl VOUT=Voo+0.5V 10 pA
IOH2 VouT =-0.5V 100 pA
Output Current 8
IOL2 VouT=Voo+0.5V 10 pA
103 Vos=0.3V 100 pA 9
104 Vos=0.5V 100 pA 1-0
lOA In full·range operation 20 pA
los When system clock is stationary 3 pA
Note 2: Applicable pins Kl-KI, a, p, ACL, 011-041, 051-0SI • H},H2 waveform
Note 3: Applicable pins Kl-K" 011-011, OSI-051
U _______::::
-u-J"C.--.====~=
Note 5: Applicable pins a, p
Note
Note
Note
6: Applicable pins HI, H2
7: Applicable pins Oi, (i= 1-4, j=2-6)
8: Applicable pin Oll -041, OSI -051
- IL
• Oscillator circuit
Voc
Note 9: Applicable pin Rl
c~fD~'"
Note 10: Applicable pins Rz, R3, R,
Note 11: Current consumption under no load conditions at fosc=32.768kHz
Oscillator circuit constant

C"=C,,=22,,F
'-'-~-------""--'----SHARP ---~-----
87
....,-.........,
.
• . Applications
~-.....
OMOS 4-Bit l-Chip Microcomputer'
...................--....,-......
1. Digital watch
2. Game machine
3: pas terminal
4. Electronic scale
5. Controlle~ for electronic home appliances
and audio equipment
• System Configuration (for digital watch)
12 H/24 H Cl-----i
KI~---------------'
K,!E-------------,
K31E-------,
1-----IOSC0 1:T K.
22pF /3 R, R3 R. OSI OS2 a", 0 54
For
control
Mode switch
88

The SM-510 is a 4-bit single chip CMOS micro-
Q
~ :;~;.Q :..Q~:~:;..Q:~:
RAM, a 15-stage divider and 132-segrnent liquid 1 3 3 3 31
crystal driver circuits. It is well suited for ap-

plications of low cost, low power hand-held equip-
ment with liquid crystal display.
• Features
L CMOS process
3_ RAM capacity 96X4+32X4 bits
4_ Instructions 49
6_ Input ports 6 bits
7_ Output ports 47 bits
(timer circuit)
9. DirectLCD driver circuit (3V, 1/4 duty, 1/3
(32.768kHz)
1 L Standby mode (10 pA current consumption)
12. Single power supply -3V (TYP_)
~~-------SHARP"-------""'-~--""
89
• Block Diagram
~ Seliment
________________________ ~A~Output
________________________~
Display RAM
(32X4)
RAM
(96X4)
Segment
Output
Parallel
Output
Port
Test ' - - y - - / ACL Input "---v-' Voo '-v-'

Parallel GND Oscillator-
Input
Port
Symbol description
ALU : Arithmetic logic unit W : 8-bit shift register
C : Carry F/F Bp : Backplate signal generator circuit
Pu, PM, PL : Program counter H,L, Y : Hit F/F
Su, SM, SL : Stack register of program counter R : 2-bit F/F
Ru, RM, RL : Stack register of program counter K : Key input F/F
DIV : Frequency divider CG : Clock Generator
- , - - - - - - - - - - - - - - S H A R P , - - . - . '......... ------------'"......-
90
• Pin Description
K I -K 4 I Pull down Acc-K I -K 4
SA, PIN I Pull up Independent test possible
aI-aIS, b I -b I6 Output of contents of display RAM as LCD segment
0
bs signal
4-state level output possible; used for LCD common
HI -H 4 0
output
SI- S8 0 Output of contents of W register
Rr. R2 0 For piezo-electric buzzer direct drive
T I For Test (usually connected to V00)
OSCIN, OSCOUT For clock oscillation

Voo -3.5-+0.3 V
Pin voltage 1
VIN V oo -+0.3 V
Operating temperature T oDr 0-+50 t
Storage temperature T st• -55-+150 t
• Electrical Characteristics (V oo =-3V±10%, Ta=25t)

VIllI -0.6 V
2
V ILI Voo+0.6 V
Input voltage
VIII2 -0.3 V
3
V OL2 Voo+0.3 V
IIII VIN=OV 3 15 pA 4
Input current
IlL VIN=VOO 3 15 pA 5
VOH IOlJT=50 pA to Voo -0.5 V
6
VOL IOUT=5 pA to GND Voo+0.5 V
VOA -0.3 0 0 V
Output voltage
VOB V oo =-3.0V -1.3 -1.0 -0.7 V
7
Voc No load -2.3 -2.0 -1.7 V
Voo -3.0 -3.0 -2.7 V
Iso VouT=-0.2V 100 pA
Output current 8
ISIN VouT=Voo+0.2V 100 pA
lOA In full-range operation 60 pA
los When system clock is stationary 10 pA
Note 2: Applicable pins KI - K., PIN Note 6: Applicable pins SI -S8
Note 3: Applicable pins ACL, BA Note 7: Applicable pins al-al6, bl-blG, b8, HI-H,
Note 4: Applicable pins KI - K, Note 8: Applicable pins RI, R2
Note 5: Applicable pin PIN Note 9: Current consumption when fosc is 32.768kHz (TYP.) and
- 3.0V of V DISP is applied
--~------SHARP'--~---~--
91
GMQS:4-Bit 1-Chip Microcomputer
• AppHcations
1. Hand-held electronic calcuator with multi-digit
display and clock
2. High-quality clock:
3. Handy game machine'
4. Equipment that. need mUltiple LCD display seg-
ments
• System Configuration (Hand-held electronic caleuator with clock)
LCD
DC voltage cutout
O.02.uF
08C Ol"T I---<r---I
15pF
SM-510
Piezoelectric
5,
buzzer
88
'-----y----'
Key matrix'
92
S M- 511 CMOS 4-Bit I-Chip Microcomputer

Q .
computer with 4,032 bytes of ROM, 128 words of ..Q:~;~~~~
,
RAM, a 15-stage divider, melody generator and
136-segment liquid crystal driver circuits. It is
well suited for low cost, low power hand-held 8,
equipment with liquid crystal displays. H.
H,
• Features
1. CMOS process
3. RAM capacity 96X4+32X4 bits
4. Instructions 55
(timer circuit)
9. Melody generator circuit
10. Direct LCD driver circuit (3V, 1/4 duty, ~
1/3 bias and 136 segments MAX.)
(32.768kHz)
~-------SHARP----'----'---------
93
I
GMOS4-Bit 1-Chip Microcomputer . . . . . .'. SM-511
.-......~~.-._~.-.~~~.-...-..r~~~~~ I,
• Block Diagram
Segment Output
r-------------------------J~~------------------------~
Display RAM
(32X4)
RAM
(96X4)
Segment
Output
Parallel
Output
Port
12 13 14 15
Test '--y---' ACL Input '--y--I Voo '-y--.I Input Melody~
Parallel GND Osci. Output Segment
Input lIator Output
Port
Symbol description
ALU : Arithmetic logic unit W : 8·bit shift register
ACL : Auto clear Bp : Backplate signal generator circuit
C : Carry F/F H, L, X, Y : 4·bit F/F
Pu, PM, PL : Program counter K : Key input F/F
Su, SM, SL : Stack register of program counter CG : Clock generator
Ru, RM, RL : Stack register of program counter
DIV : Frequency divider
94
CMOS 4-Bit1-Chip Microcomputer
• Pin Description
Pin 110 Type of circuit Function
KI -K 4 I Pull down Acc+-K I -K 4
BA, {3 I Pull up Independent test possible
al-aI6, Output of contents of display RAM as LCD segment
0
b l -b l6 signal
bS I 0 LCD segment or LCD flashing output
bS2 0 Input of X register contents as LCD segment signal
4-state level output possible ; used for LCD common
HI -H 4 0
output
Sl-SS 0 Output of contents of W register
R 0 Melody output
T I For Test (usually connected to VDD)
OSC IN, OSC OUT For clock oscillation
VDD , GND Power supply for logic circuit

V DD -3.5-+0.3 V
Pin voltage 1
VIN V DD -+0.3 V
Operating temperature Toor 0-50 "C
Storage temperature T st • -55-+150 "C
Note 1: The maximum applicable voltage on }any pin with respect to GND (GND=OV)
Supply voltage V DD -3.2--;-2.6 V
---.-..-.-------SHARP . - . - - - - - - - - - - - -
95
...........
•
----.....
CMOS'4-Bit 1-Chip Microcomputer
Electrical Characteristics
.-- ............. .-~--. ..................................
SM-'511
(V 00= - 3V ±10 %, Ta= 25'C)

VIH1 -0.6 V
2
VIL1 Voo+0.6 V
Input voltage
VIH2 -0.3 V
3
V IL2 Voo+0.3 V
IIHI VIN=OV 3 15 /LA 4
Input current
IIH2 VIN=Voo 3 15 /LA 5
VOH IouT =50,uA to Voo -0.5 V
6
VOL IouT =5,uA to GND Voo+0.5 V
VOA -0.3 0 V
Output voltage
VOB Voo =-3.0V -1.3 -1.0 -0.7 V
7
Voc No load -2.3. -2.0 -1.7 V
Vo~ -3.0 -3.0 -2.7 V
Iso . VouT=-0.2V 100 ,uA .-
Output current 8
ISIN VouT=Voo+0.2V 100 ,uA
IOAI In full-range operation 40 60 ,uA
Iosl When system clock is stationary 10 .20 ,uA
IOAI In full-range operation 25 35 ,uA
Ios2 When system clock is stationary 10 20 ,uA
Note 2: Applicable pins KI-K" P
Note 3: Applicable pins ACL, BA
Note 4: Applicable pins KI- K,
Note 5: Applicable pin P
Note 6: Applicable pins SI - S8
Note 7: Applicable pins ai-alB, bl-bl6, bSl, b.s2, HI-H.I
Note 8: Applicable pin R .
Note 9: When melody circuit is inoperative with Voo at -3.0V and system clock at 16.384kHz.
Note 10: When melody circuit is inoperative with Voo at -3.0V and system j:lock at 8.192kHz.
~-----~---~SHARP .....--....-.--....-.-.--~
\ . .
96
• Applications
1. Hand-held electronic calculato'r with multidigit
display and clock
2. Hand-held electronic calculator with function
calculation capability
3. Hand-held game machine
4. Equipment that need multiple LCD display seg-
ments
• System Configuration (for melody alarm, watch, and hand-held electronic calculator with game func-
tion)
LCD
DC voltage cutout
O.02JlF
Crystal
32.768 kHz
OSCOl'T I-~--I
General {
purpose output 15pF
SM-511
...------1 S3
R Piezoelectric
buzzer
'---v------I
Key matrix
97
. '1 ~ ,
·. . . . .~~~~.-.~.....,. . . .. - . . . . ,...............,AIiIIIiIIIIr.-'~. . . . .
- '
S M- 5 20 CMOS 4-Bit I-Chip Microcomputer

computer with 3,072 X 10 bits of ROM, 168 words
GND
of RAM, a 15-stage divider, and automatic display
circuit. It is well suited for applications with aSCot'T
many control ports. VIH)
ACL
P 7
PE
• Features
MP3 I
1. CMOS process
3. RAM capacity 160 X 4 + 16 X 2 bits
(including 16 X 2 bits for display)
4. Instructions 93
(timer circuit)
11. External RAM expandable (1,704 X 4 bits)
12. Clock generator circuit
14. Standby mode (50 f.1-A current consumption)
15. Single power supply -5V (TYP.) Top View
16. Instruction cycle 11 f.1-s
17. 64-pin dual-in-line .package
98
• Block Diagram
Digit
and
Input { 7
External
RAM
Osci-
Bator
{2 Address
Output
Input { 9
Segment
Output
~------~v~------~
Register Output I/O Port
Symbol description
Acc : Accumulator DB, DP : Registers for automatic display use
ALU : Arithmetic logic unit W;j : Shift register
PC : Program counter 10 : DID control F/F
SR : Stack register C : Carry F/F
BM, BL : RAM address counter SD : Segment decoder
SB : RAM address counter stack IF : Interrupt flag F/F
X, SX : Temporary registers E : Interrupt mask F/F
ST : T output control register DIV : Divider
TC, J! : Counters for automatic display use CG : Clock generator
99
G,MOS 4-Bit 1-Chip Microcomputer
• Pin Description
..
KE 1 -KE 4 I Pull down Acc+-KEI - KE4
a, f3, PE, Q 1 I Pull down Test possible by separate input
DI0 1 -DI0 4 I/O Pull down Acc-DI0 1 - DI0 4
MG register output, on-the-way stage signal output o~
MP 1 -MP4 I/O
dividei- o~ Acc+- MP,- MP.
To-TIl 0 Digit signal or external RAM address signal output
R1 -R IO 0 W register content output
SI-S9 0 Segment signal output ,
F I -F 5 0 Can be set or reset independently
Q2 0 Can be set or reset .
TEST l TEST z I Pull down For test (usually connected to VDO)
Rf, Cf For system clock oscillator
OSCIN, OSCOUT For clock oscillator

VOD -6.0-+0.3 V 1
Pin voltage VIN VoD -0.3-+0.3 V 1,2
VOUT Voo -·0.3-+0.3 V 1,3
Operating temperature T= -10-+60 t
Storage temperature T stg . -55-+150 t
N9te1: The maximum applicable voltage on any pin with respect to GND (GND=OV)
Note 2: Applicable to inputs
Note 3: Applicable to outputs
Parameter Symbol Conditions Specified value Unit Note
-5.5--4.5 V
Operating voltage Voo In "Low" clock -5.5--3.5 V· 4
Note 4: When the clock frequency (c is lowered to 118 of that in normal operation
.,
CMOS 4-Bit1-Chip Microcomputer SM-520
• Electrical Characteristics (V oo =-5.0± 10%, Ta=25"C)

V lln -1.5 V
5
V ILI Voo + 1.0 V
Input voltage
V IH2 -0.3 V
6
V IL2 Voo+0.3 V
VOHI IOllT= -250 p.A -0.6 V
7
VOLl IOUT=30 p.A Voo+0.6 V
VOH2 IOllT=-250p.A -1.0 V
8
VOL2 IOUT=50p.A Voo+0.6 V
VOHa lOUT = - 500 p.A -1.0 V
9
VOL:l IOllT=50p.A Voo+0.6 V
Output voltage
VOH4 lOUT = -LOrnA -2.5 V
10
VOL4 IOUT=50p.A Voo+0.6 V
VOH5 IOUT= -100 p.A -0.6 V
11
VOL5 IOllT=50 p.A Voo+0.6 V
VOH6 louT=-150 p.A -0.6 V
12
VOL6 lOUT = 150 p.A Voo+0.6 V
1001 In normal operating 1.5 rnA 13
Current consumption
1002 When clock is stationary 50 150 p.A 14
fc 90 kHz
Clock frequency 15
fCL In "Low" clock 11.2 kHz
Oscillator frequency fCRY 32.768 kHz 16
Note 5: Applicable pins ACL, a, p, PE, QI, KEI-KE" DIOI-DIO., MP,-MP.
Note 6: Applicable pin C,
Note 7: Applicable pins To-Tll R,
Note 8: Applicable pins SI-S9, FI, Fa-F" Q2
Note 9: Applicable pins R.-R,o
Note 10: Applicable pins MPI-MR" F2
Note 11: Applicable pins DIOI - DIO,
Note 12: Applicable pin Rf
Note 13: No-load state (internal CG out attached capacity C = 15pF) Fig. 2
Fig. 1
Note 14: VDD =-3.5V, No-load state ( .. )
Note 15: For C and R elements out-attached to internal CG, C=15pF±2%, R=82kO ±2%, they are connected as shown in Fig.1
Note 16: For connection of out-attached element of crystal oscillator, see Fig. 2.
101
............................. ..._..._.............................................
CMOS 4-Bit 1-Chip Microcomputer
.-:
SM:"S20
• Applications
1. Cash register
2. Hand·held electronic calculator with printer
3. Electrical copy machine
4. Microwave oven
5. Vending machine
6. Game machine
7. POS terminal
8. Electronic scale
9. Controller for electronic and electric home
appliances
• System Configuration (for VTR timer)
~ Fluorescent tube display
U ~~;::::+;=~~--o-30V
lkO
SM-520
OSCH 1
V PIJ GND \OSC 1\

Crystal
lkO lkO 32.768 kHz
22pF
1000
lkO
+5V
lkO
~
Input signals
102

computer with 3,072 X 10 bits of ROM, 168 words
Rll
of RAM, a 15-stage divider and automatic display aSCI:, 2
circuit. OSCon 3
It is well suited for applications with fluorescent
display tube (VFD), due to built-in high voltage ACL 5
outputs.
• Features
1. CMOS process
(including 16 X 2 bits for dis-
play)
4. Instructions 93
9. High voltage outputs (- 30V) 21 bits
(timer circuit)
12. External RAM expandable (1,704X4 bits)
13. Clock generator circuit
15:Standby mode (50 Jl-A current consumption)
16. Single power supply -5V (TYP.) Top View
17. Instruction cycle 11 Jl-S
'-~------SHARP---'---""'-'-''-
103
CMOS A-Bit 1-Chip Microcomputer. , SM ..525
................-.......... .-~.-.-.- .....................-.-:__,.IIIIiI.
• Block Diagram
Clock Power supply

~ Output for display Test
r-----------------~--------~------------_Q4 48
Digit and
External
RAM'
Address
Output
RAM Address
Decoder
Segment
Output
y
Register Output
Symbol description
Ace : Accumulator DB,DP: Registers for automatIc display use
ALU : Arithmetic logic unit W,' : Shift register
l'C : Program counter DIO : DIO control F F
SR : Stack register C : Carry F F
B\I,BI.: RAM address counter SO : Segment decoder
SB : RAM address counter stack IF : Interrupt £lag F/F
X,SX : Temporary registers E : Interrupt mask F IF
ST : T output control register DIV : Divider
TC, £ : Counters for automatic display use CG : Clock generator
104
• Pin Description
KE I -KE 4 I Pull down Acc-+KEI - KE4
a, {J, PE, QI I Pull down Can be tested on individual input
010 1 -010 4 110 Pull down Acc +-+ 010 1 -010 4
MG register output or
MP I -MP 4 110 divider middle stage signal output or
Acc +- MP I -MP 4
To-T l l 0 Digit signal or external RAM address signal output
RI-R lO 0 W register output
SI-S9 0 Segment signal output
F I -F 5 0 Can be set or reset individually
Q2 0 Can be set or reset
TEST,TEST 2 I Pull down For test (Connected to V~)D normally)
Rf, Cf For system clock oscillation
OSC IN , OSC OliT For clock oscillation

-6-+0.3
Voo
~
VPR -12-+0.3 1,3
Pin voltage
VIN V oo -:0.3-+0.3 V r-t4
r-------'-----
VOllT1 Voo -0.3-+0.3
~
VOllT~ -35-+0.3 1,7
;-70
Output current
IOllT1
IOllT2 -15 rnA
r-2&-
5,8
IOllT3 4 ~
Storage temperature T stg -55-+150 "C
Note 2: Applied to pin VDn. .
Note 3: Applied to pin TEST IVrR. ;
Note 4: Applied to pins ACL, a, {3, PE, Q, DIOI-DIo." KE.-KE., MP.-MP., Cf.
Not~ 5: Applied to pins DIOI-DIO., MP.-MP., F.-FT:;, RI-RIO, Q,.
Note 6: Applied to pin Rf.
Note 7: Applied to pins To-Til, SI-S9
Note 8: Total high level output current
Note 9: Total low level output current

VDD During normal operation -5.5 -4.5
Supply voltage V
VDDL During low clock -5.5 -3 'iO
Auxiliary voltage VI'R -9.9 -8.1 V 11
Display voltage VN -30 VDD V
Note 10: Condition in which the clock frequency fc has been dropped to 118 of that during normal operation.
Note 11: The auxiliary voltage V!'R is applied from the TEST/V!'R pin. V~
~TEST/V"
r19V
(Example of circuit with V PR externally attached)
_....-..-.-_.-.--$HARP - - - - - - . - - - - - - -
105
C~OS 4-Bit 1-Chip Microcomputer SM-525
,• Electrical Characteristics (V DD =,="5V±10%, V PR =-9V±10%, V N =-30V,f=90kHz, Ta=25t)
Parameter SY{llbol Conditions MIN. TYP. MAX. Unit Note

VIHI -1.5
V 12
VILI VDD +0.6
VUI2 -2.3
Input voltage V 13,
VIL2 VDD +0.6
VUI3 -0.3
V 14
VIL3 V DD +0.3
Input current lUI V 1 =OV 5 35 pA 15
VOHl lo=-17mA -1.8
V 16
VOLI Connect RL =50kO to VN V N +1
VOH2 lo=-2mA -2
V 17
VOL2 Connect RL =50kO to VN ,V N +l
VOH :! lo=-250pA -1
V 18
VOLa 10=100pA VI>D+ 0.6
VOII4 10=-250pA -1
V 19
VOL4 10=300pA VI>D+ 0.6
Output voltage VOll5 10=-2mA -2.5
V 20
VOL5 10=50 pA V",,+0.6
VOll6 10=-1.5mA -2.5
V 21
VOL6 lo=100pA V"D+0.6
VOll7 lo=-100pA -0.6
V 22
VOL7 10=100pA VI>D+ 0.6
VOII8 10 =-150 pA -0.6
V 23
VOL8 10=150pA V I)Jl+0.6
I"DI During normal operation 600 pA 24
Current consumption
IDD2 During clock stop 50 150 pA 25
fc 90
Clock frequency kHz 26
fCL During low clock 11.2
Crystal oscillator frequency fCRY 32.768 kHz 27
Npte 12: Applied to pins ACL, a, fJ, PE, QI, DIO,- DIO I, MP,- MP I
Note 13; Applied to pins KEI-KE,
Note 14: Applied to pin Cf
Note 15: Applied to pins a, fJ, QI, KEI-KEI, Dial-Dia" MPI-MPI, F2 (during floating condition)
Note 16: Applied to pins To-T'l
Note 17: Applied to pins S,-S"
Note 18: Applied to pins FI, F:l, F5
Note 19: Applied to pins RI - R6, Q2, F I
Note 20: Applied to pins R,-RJO
Note 21: Applied to pins MPI-MPI, F2
Note 22: Applied to pins DIOI-DIO,
Note 23: Applied to pin Rf
Note 24: No·load condition
Note 25: No·load condition, VOll= -3.5V, internal CG with externally attached capacitance C= 15pF
Note 26: Internal circuit with externally attached CG
Note 27: Circuit with externally attached crystal oscillator
C,
pJ'
C
r
R=82kO Cl=330pF Rl=200kO
C=15pF C2=150pF CG=lOpF
Rl=lMO Co=33pF
• When a ceramic oscillator is used, the operating Crystal: KF-38G
voltage VDD is limited to -5.5 to -4.5V. R2 =5600
• Oscillation starting voltage becomes larger than the Ceram ic oscillator : KB R - (made by Kyocera Corp.)
CR oscillation. , (made by Kyocera Corp.)
~'-''---'---SHARP------'-'~-'--~
106
• System Configuration (for VTR timer)
M 8.2V
U~
~~---r~:f::~::~::~:;::~C:::::::::::~---------o-30V
IkO IkO
SM-525
OSCOCT
KE, - KE, DIO, - DIO, F, - F; MP, - MP. GND OSC"
Crystal
s.... --- S
....
c: ___ S
"'...." ""
00
32.768kHz
~ ~
Input signals ' - y - I Input signals
Control signals
1000
lkO
+5V
Key matrix
lkO
'----y---'
Input signals
.----.-...-.------'--SHARP ----------....-.-----
107
CMQS 4-Bit 1-Chip .Microcomputer •. SM~530

cOlI).puter with 2,016 bytes of ROM, 88 words of
RAM, melody generator circuit and 96-segment
LCD driver circuit. It is well suited for low cost,
low power systems with many LCD segments.
• Features
1. CMOS process
2. ROM capacity 2,016X8 bits
3. RAM capacity 64 X 4 + 24 X 4 bits
4. Instructions 49
7, Output ports !i8 bits Top Vi~w
8. Timer/Counter
(On-chip 15-stage divider with reset, 10-
second counter and 11100-second counter) /
(32.768kHz)
12. Standby mode (1.5 p.A current consumption)
13. Single power supply -1.5V (TYP.)
14. Instruction cycle 91.6 p.s
108
• Block Diagram
~
Segment Output
______________________________ ________________________________
~A~ ~
Segment
Output
ROM
(2,016 X 8)
RAM'
(4X16x4)
Pu(5) PL(6) Parallel
Output
Port
Battery
Alarm
Parallel
Input
Melody 12 Port
Output
'--v-'
Oscillator
Symbol description
ALU : Arithmetic logic unit DDC : LCD supply voltage generator
ACL : Auto clear CG : Clock generator_
C : Carry F/F BA : Battery alarm circuit
Pu. PL : Program counter BM, BL : RAM address register
Su, SL : Stack register of program counter
109
..............-.---.... .............-:-----..... -........
,
CMOS 4-Bit 1-Chip Microcomputer SM~530
-~
• PIn Description
Kl -K 4 I Pull down Acc -Kl-K,j
KE l -KE 4 I Pull down Acc - KEl - KE4
OlO- 0 4B 0 Display RAM contents output as LCD segment signals
Tri-value output capability;
. Hl -H 2 0
used for LCD common output
F l -F 4 0 F l -F 4 -Acc
Sl-S4 0 Sl-S4 - Acc
So 0 Melody output
BA I For Iiatter,y alarm
Test I Pull down For test (Connected to Voo normally)
OSC1N, OSC OUT For clock oscillation
Voo, Vee, DDC LCD driv~ power supply
VM,GND Power supply for logic circuit

VM -2.0-+0.3 V 1
Voo -4.0-+0.3 V 1,2
Pin voltage
VINl VM-0.3-+0.3 V 1,3
V1N2 VoD -0.3-+0.3 V 1
Operating temperature T oDr -10-+60 t
Storage temperature T st• -55'-+150 t
Note 2: Applied to pins Kl-Kl, KE1-KE1, Sl-S." Fl-FI, SO, Test, DDC, BA. ACL,
OSCIN, OSCollT
Note 3: Applied to pins O;j(i= 1-4, j=O-B)HI, H2, Vc

VM -1.2--1.8 V
Supply voltage
VOD -2.3--3.6 V
Oscillation start voltage Vose -1.4 V
Oscillator frequency fose 32.768(TYP.) kHz
-------~--SHARP.-.-.--·------
110
CMOS 4-Bit 1-Chip Microcomputer SM-S30
• EI,ectrical Characteristics (V M =-1.45-1.55V, V oo =-2.9--3.1V, Ta=25"C)

V IH -0.5 V
Input voltage 4
V1L VM +0.5 V
IIHI V1N=OV 0.155 3 pA 5
Input current
IIH2 V1N=OV 1.55 30 pA 6
V OO1 VM =-1.55V, RL =5Mn -2.80 V
Boost output voltage 7
V OO2 VM =-1.30V, RL =5Mn -2.30 V
10l Vos=0.5V 10 pA 8
102 Vos=0.5V 60 pA 9
103 Vos=0.5V 60 pA 10
104 Vos=0.5V 120 pA 11
10HI VOLJT =-0.5V 160 pA
Output current 12
lOLl VOllT =V M +0,5V 10 pA
IOH2 VOlJT =-0,5V 10 pA
13
IOL2 VOllT =V M +0.5V 1.5 pA
IOH3 VollT =-0,5V 100 pA
14
IOL3 VOllT =V M +0.5V 3 pA
105 Vos=0.5V 100 pA 15
100 During all operation 12 pA
los During system clock stop 1.5 pA
Oscillation start time Tosc 10 s 17
Note 4: Applied to pins KI-K" KEI-KEI, Test, ACL, OSC'N
Note 5: Applied to pins KI-K" KEI-KEI, ACL
Note 6: Applied to pin Test
Note 7: Applied to pin VDO
Note 8: Applied to pins 0" (i= 1-4, j =O-B)
Note 9: Applied to pins H" H,
Note 10: Applied to pin DDC
Note 11: Applied to pin Vc
Note 12: Applied to pin SO
Note 13: Applied to pins SI -S,
Note 14: Applied to pin F I
Note 15: Applied to pins F, - F I
Note 16: Current consumption during 32.768kHz
Note 17: Oscillation circuit constant, Cr;= 15pF, Cp=22pF
~ ------- V"
------------GND
--------V,,"
eH"H2 Waveform Cc;=ISpF, C,,=22pF
e Oscillation circuit e Boost circuit
- - - - - - - - S H A R P - - - - - - -1". .-
- j""
.....
....................., ....,.....,
CMOS 4-8it 1-Chip Microcomputer
..... .............
......,~
..
~.-. ................,.........
. .. 'SM"':530
• Applications
1. Digital watch
2. Game machine
3. Digital clock
equipment
5. Calculator with d9Ck
• System Configuration Example (Caluculator watch)
.
III
Test
FJ
"
"8 F2
i:!0 F3
"...
0 F,
~
SO
R
Key matrix
112
CMOS 4-Bit I-Chip Microcomputer

... z
The SM-531 is a 4-bit single chip CMOS micro- ~
uuQ~Qu 00
computer with 1,260 bytes of ROM, 52 words of ~""--MU)CJ)ZUCQU""_N
OOO:C:':oo,,<>Q>:':OO
RAM, melody generator circuit and 80-segment 1 3 3 3 31
LCD driver circuit. It is well suited for low cost,

low power applications with many LCD segments_
• Features
1.
CMOS process
2.
ROM capacity 1,260 X 8 bits
RAM capacity 32 X 4 + 20 X 4 bits
3.
4.
Instructions 45
5.
Subroutine nesting 1 level
6.
Input ports 6 bits
Output ports 42 bits
7.
8.
Timer/Counter
(On-chip 15-stage divider with reset, 1/100-
second counter)
9. Direct LCD driver circuit (3V, 1/2 duty, 112
10. On-chip crystal controlled cscillator
(32.768kHz)
12. Standby mode (1.5 p.A current consumption)
13. Single power supply -1.5V (TYP.)
14. Instruction cycle 91.6 p.s
------------SHARP----..-,----
113
CMOS 4-Bit 1-Chip Microcomput~r SM-531
• Block Diagram
~
Segment Output
_____________________ ____________________
A~ ~
common{ 3
Output (2)----...r--"'L---~---...;;;..;...-------r----'
Segment
ROM Output
DDC (1.260xS)
RAM
(2X16X4)
PutS) PL(6)
Parallel
\ Input
Port
Melody { 9
Output 'ID
'--v-' VM Test '-v--'

GND Oscillator
Symbol description
ALU : Arithmetic logic unit Suo SL : Stack register of program counter
Acc : Accumulator DDC : LCD supply voltage generator
ACL : Auto clear DIV : Frequency divider
C : Carry F/F CG : Clock generator
,Pu. PL : Program counter BM. BL : RAM address register
114
• Pin Description
K1 -K 4 I Pul1 down Acc - K I -K 4
KEh KE2 I Pul1 down Acc - KEh KE2
0 10 -0 49 0 Display RAM contents output as LCD segment signals
Tri·value output capability;
Hh H2 0
used for LCD common output
SOh S02 0 Melody output
Test I Pul1 down For test (Connected to VM normal1y)
ACL I Auto clear
OSCIN, OSCO\JT For clock oscillation
VDD , , Vee, DOC LCD driver power supply
V M, GND Power supply for logic circuit

VM -2.0-+0.3 V 1
VDD -4.0-+0.3 V 1
Pin voltage
V INI V M -0.3-+0.3 V 1,2
V IN2 VDo -0.3-+0.3 V 1,3
Storage temperature T st" -55-+150 "C
Note 2: Applied to pins KI-KI, KEI, KE" Sal, SO" Test, DOC, ACL, OSCIN, OSCQlTT
Note 3: Applied to pins O,j(i= 1-4, j=O-9), HI, H" Vc

VM -1.8-1.2 V
Supply voltage
Voo -3.6-2.3 V
Oscillation start voltage Vase -1.4 V 4
Note 4: Oscillation ciruit constant CG= 15pF, CD= 22pF
Oscillation start. time : within 10 seconds .
.-----------SHARp.-..--------....-.
115
CMOS4-Bit 1-Chip Microcomputer SM"531
• Electrical Characteristics (V M =-1.45--:-1.55V, Voo=-2.~--3.1V; Ta=25"C)
Parameter Symbol Conditions MIN. TyP. MAX. Unit Note

VIH -0.5 V
Input voltage 5
VIL VM +0.5 V
IIHI VIN=OV 0.155 3 pA 6
Input current
IIH2 VIN=OV 1.55 50 pA 7
VOOI VM =-1.55V, RL-5MO -2.80 V
Boost output voltage 8
V002 VM =-1.30V, RL =5MO -2.30 V
101 Vos=0.5V 10 pA 9
102 Vns =0.5V 60 pA 10
Output current 103 Vos=0.5V 60 pA- II
104 Vos=0.5V 120 pA 12
105 Vos=0.5V 900 pA 13
100 During all operation 10 pA
los During system clock stop 1.5 pA
Oscillation starting time Tosc 10 s 15
Note 5: Applied to pins KI-K" KEI, KE2" ACL, OSCIN • Hl,Hz Waveform
Note 6: Applied to pins KI-K" KEI, KE2, ACL
Note 7: Applied to pin Test
~---------
--------------GND
Note 8: Applied to pin VOD
Note 9: Applied to pins 0" (i= 1-4, j=0-9) V~I
Note 10: Applied to pins HI, H2
------------ VIlIl
Note 11: Applied to pin DOC
Note 12: Applied to pin Vc
Note 13: Applied to pins Sal, SO, • Oscillation circuit, Boost circuit
Note 14: (::urrent consumption at 32.768kHz
Note 15: Oscillation circuit constant CG=15pF, Co=22pF
~---'--'---'-----SHARP .-------------,---
116
• Applications
1. Digital watch
2. Game machine
equipment
4. Calculator with clock
• System Configuration (for melody alarm watch)
LCD
DC voltage cutout
O.02,uF
~~--~--~~~--,
o ij (40Iines)
15pF
1/.1F
+
SM-531 1.5 V
V,,"
DDC
Vc
ACL
ACL
----------SHARP--------
117
CMOS 4-Bit 1:"Chip Microcomputer , SM-S40
SM-S40 CMOS 4':'Bit I-Chip Microcomputer

RAM, a 15-stage divider and a 256-segment liq-
uid crystal driver circuit. It is well suited for
low power applications with 16 X 16 dot-matrix liq-
uid crystal display_
• Features
L CMOS process
2. ROM capacity 2,016 X 8 bits I Vuu 5
ALM
4. Instructions 57
(timer circuit)
9. Direct LCD driver circuit (4_5V; 1/8 duty,
113 bias and 256 segments MAX.)
1 L Standby mode (1 pA current consumption)
12. Single power supply -4_5V (TYP.)
-~-----~'---SHARP''''''-''''-'-'-~'-'-~
118
• Block Diagram
Segment Output
ROM
(2,016X8)
Segment Segment
Driver Output
Backplate Common
Control Output
}-____~~I}-------~
~ '--y-I Tone
GND Oscillator Output
Symbol description
ALU : Arithmetic logic unit CG : Clock generator
P, PL : Program counter S : Shift register
SCI, SC2 : Stack register of program counter X, SB : Temporary register
~--------'---SHARP -----.-.-..-..-.--
119
CMQS4-Bit 1-Chip Microcomputer SM-S40
• Pin Description
Pin name 1/0 Circuit type Function
K1-K 4 I Acc - K1 -K 4
,
R register output;
Ra I/O ' Pull down
a F IF is\nput when R registerRa' is reset
R re~ister output;
Rb I/O Pull down
f3 F IF is input when R register Rb is reset
al-al6
0 Display RAM contents output as LCD segment signals
bl -bi6
H1-H s 0 8·value output capability;used for LCD common output
SI-S4 0 S register output
RC 0 R register output
ALM 0 For sound generator
T I Pull up For test (Connected to GND normally)
Sync I External clock input
Rf 0 System clock output
When system clock is running,
Vc 0
output at the same voltage as Vnn
VDlSP LCD driver power supply
Vnn, GND Power supply for logic circuit

Vnn '-5,,5-+0,3 V 1
Pin voltage VDlSP -5.5-+0,3 V 1,2
VIN .' VM -0.3-+0.3 'V 1
Storage temperature Tst~ -'-55-+150 "C
Note 1: The maximum applicable voltage on any pin with respect to GND,
Note 2: VDlSP;;;;;VDD

Vnn -5,5-+4.0 V
Supply voltage
VDlSP -5,5-+-3.0 V
Oscillator frequency fose 120(TYP.) kHz
--'-'-"'-~-,--SHARP------'-'---""""'-
120
• Electrical Characteristics (V DD =-4.5V, Ta=25'C)

VIH 0.6 V
Input voltage 3
VIL VDD +0.6 V
IIH! VIN=OV 20 pA
4
IlL! VIN =-4.5V 1.5 pA-
Input current
IIH2 VIN=OV 3.0 pA
5
IIL2 VIN =-4.5V 1.5 pA
VOA No load condition VDISP = -4.5V -0.2 V
VOB No load condition VDlsp =-4.5V -1.38 -0.97 V
Voc No load condition VDlSP = -4.5V -3.53 -3.12 V
Output voltage 6
VOD No load condition VDISP- -4.5V -4.3 V
VOE No load condition VD1SP= -4.5V -2.35 -1.95 V
VOF No load condition VDISP= -4.5V -2.55 -2.15 V
10Hi VouT =-0.5V 40 pA
7
lOLl VOUT=VDD+0.5V 2 pA
10112 VOUT= -0.5V 100 pA
5
Output current IOL2 VOUT=VDD+0.5V 2 pA
IOH3 VouT=-0.5V 100 pA
8
IOL3 VOUT=VDD+0.5V 5 pA
IOH4 VOlIT =-0.5V 100 pA
9
IOL4 VOUT=VDD+0.5V 100 pA
During operation 230 pA
-rz-- - - --
IDA
IDs During system clock stop 1 ~A
Note 3: Applied to pins Kl- K" R" Rb e Hl-Hs Waveform eal-as,bl-bs Waveform
Note 4: Applied to pins Kl- K,
~
--------- - VOA Vo.'
Note 5: Applied to pins R" Rb
-------VOB
Note 6: Applied to pins HI-H8, al-aI6, bl-bl6 ----- - VOE
Note 7: Applied to pins SI--S, ------ -Voc ------- - V OF
Note 8: Applied to pin RC ------------- - VOIl - - - - - - - - - - - VIlIl
Note 9: Applied to pin ALM
Note 10: fose= 120kHz(TYP.) and VDlSP= -4.5V e Clock from external input pin SYNC
. 50kHz-144kHz
121
.CMOS 4-Bit 1-Chip Microcomputer SM-540
~"""""""'''''''''''''_ _' I11!11!1••_''''_ _~''''~''''''''''''.-..r ....
• Application
1. Game machine
.• System Configuration (for LCD game)
16 x 16 dot matrix
LCD
K2 t - - - {
Hs K3~--{
SM-540
K,iE---{
Vc S,I-----I
S21-------'
lOOkO
R,
ViliSI'
BOkO
Piezoelectric
buzzer
2SC45B
122
CMOS 4-Bit 1-Chip Microcomputer SM-550/SM-555
CMOS 4-Bit I-Chip

SM-550/SM-555 Microcomputer

The SM-550/SM-555 are 4-bit single chip E-
CMOS microcomputers with 1,024 bytes of ROM, ~~C-:~~~~~tO~~~
80 words of RAM, a15 stage divider and an event 0.. 0.. 0.. 0.. E-C-'o..o.. 0.. 0..0.. 0..
~ r
counter.
They has the advantages of high-speed instruc·
tion cycle of 1.6 ,us(SM-550)/3.3 ,us(SM-555), 5
different interrupts, subroutine stack in the RAM
area, and byte-by-byte data transfer capability.
They are well suited for low power application
systems with many control ports.
• Features
1. CMOS process
4. Instructions 94 Top View
5. Subroutine nesting using RAM area
External interrupts 2
Internal interrupts 3
10. External ROM/RAM expandable
11. Timer/event counter
12. Serial interface 8 bits
13. Standby mode (10,uA current consumption)
14. Single power supply (2.7-5.5V)
15. Instruction cycle (MIN.)
1.6 ,us(SM-550)
3.3 ,us(SM-555)
123
CMOS4-Bit 1""Chip Microcomputer
'. Block Diagram
P
L
ROM
"'"
(:I
D
Parallel
(1,024 X8l:: '1 ~) I/O
Port
GND 7
RESET 17 Parallel
Output
Port
Parallel
I/O
Port
Symbol description
A,B : Accumulators Pl', PI. : Program counters
ACL : Auto clear circuit PO - PB : Registers
ALU : Arithmetic logic unit PSW : Program status word regi'ster
CG : Clo~k generator RD, RE, RF : Mode registers
DIV : DivIder SB : Shift registers
H,L,D,E : General-purpose registers SP : Stack pointer
IE : Interrupt enable F /F TC : Count registers
IFT,IFA,IFS TM : Module registers
IFB,IFV : Interrupt requests
IME : Interrupt mask enable F /F
124
• Pin Description
P7 I Pull up 4·bit parallel
PO, PI
110 Input-pull up 110 selectable by instruction
P5,P8
P6 110 Input·pull up 110 selectable using RF register
P4 110 Input-pull up Serial interface input capability using RE register
P2,P3 0 4-bit parallel
INTA,INTB I Pull up Interrupt input
TEST I Pull down For test (Connected to GND normally)
RESET I Pull up Auto clear
~ 0 System clock output
CKj, CK z For system clock oscillation
OSC IN , OSCOUT For clock oscillation

Supply voltage Voo -0.3-+7.5 V 1
Input voltage VIN -0.3-V oo +0.3 V 1
Output voltage VOUT -0.3-V oo +0.3 V 1
Output current lOUT 40 rnA 2
Operating temperature Tope -20-+70 °C
Storage temperature T st " -55-+150 °C
Note 2: Sum of current output from (or flowing into) output pin.

Supply voltage Voo 2.7 5.5 V
Crystal oscillator frequency fose -. 32.768 kHz 3
VDD =5V 0.25 2.5
Basic clock SM-550 f MHz
VDD =3V 0.25 1
oscillator 4
V[)[)=5V 0.25 1.2
frequency SM-555 f MHz
V Do =3V 0.25 0.48
Note 3: Oscillation start time: within 10 seconds
Note 4: Degree of fluctuation frequency: ± 30%
(tolerance of voltage fluctuation: ± 10%)
.....-.-.-..-.-------SHARP----------
125
CMQS 4-Bitt-Chip Microcomputer SM-550/SM-555
• Electrical Characteristics (V DD =2.7-5.5V, Ta;=-20-+70"C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit ,Note

VIHI 0.7VDD VDD V
1
V ILI 0 0.3VDD V
Inptit voltage
V IH2 VDD -0.5 VDD V
2
VIL2 0 0.5 V
2 200
Input current lIN VIH=OV pA 1
IVoo =5.0V±10% 20 200
10Hl VOH =V DD -0.5V 50 pA
3
lOLl VoL =0.5V 250 pA
IOH2 VOH =V DD -0.5V 100 pA
4
Output current IOL2 VOL =0.5V 500 pA
VOH = 100
IOH3 pA
V DD -0.5V IVoo =5.0V±10% 400 5
VoL =0.5V 0.5
J IOL3 mA
IVoo =5.0V±10% 1.6
f=0.5 MHz, VDD =3.0V±10% 0.9
lop rnA 6
f=l MHz, V DD =5.0V±10% 1
Current consumption 5 7
I---
1ST Standby IVoo=3.0V±10% 12 pA
8
current IVoo=5.0V±10% 50
Note 1: Applied to pins POO-P03, Plo-PI" P40-P43, P50-P53, P6o-P63, P8o-P83 (during input mode)
P7o-P73, INTA, INTB, RESET.
Note 2: Applied to pins CK1, OSCIN, TEST.
Note 3: Applied to pin CK2
Note 4: Applied to pin '"
Note 5: Applied to pins POO-P03, Plo-P13, P40-P43, P50-P53, P6o-P63,
P8o- P83 (during output mode)
P2o- P23, P30- P33
Note 6: No·load, condition
Note 7: No-load condition when crystal oscillation circuit is not operating. Connect OSCIN pin to GND.
Note 8: No-load condition when crystal oscillation circuit is operating
• Oscillation circuit
_ CKI CK2
~ R
• Clock oscillation circuit

The clock oscillation circuit is composed by con-
External cIOCk-rl
-tJ
R rCKI
fl,
necting a resistance to the CKI and CK, pins. When
inputting an external' clock directly, input it
through CKI and leave CK2 open.
The system clock ( ~ ) used is the clock supplied
to CK, divided by 4.
1:J
CR oscillation
Open
External clock
126
• Applications
1. Controllers for various home appliances, au-
dio equipment, office equipment, etc.
2. Vending machines
• System Configuration (for mechanism controller)
+5V
~
u
Z
f- Z -
-::<: ~
Cl E-<O
::>
:>
U ;;;u U
Cl
>- UlZ
~0
Ul 0 E-<
0
INTA
Pulse input {
INTB
P40
I SM-550/SM-555
P43 P83
POo \ } Control signals
Control signals \
P8 0
P0 3 P6 3
Pl o I } Input signals
I P60
PI,
.----.----$HARP--------
127
CMOS 4""Blt 1-Chip Microcomputer SM-551/SM':556
CMOS 4-Bit I-Chip

SM . . 551/SM-556 Microcomputer

The SM-5511SM-556 is a 4-bit single chip
CMOS microcomputer with 2,048 bytes of ROM,
128 words of RAM, a 15-stage divider, an event
P~2
.c~unter and 48 110 ports. It has the advantages of P83 7
3 P50
P43
a high-speed instruction cycle of 1.6 I'- s, 5 differ- P9.
ent interrupts, subroutine stack in the RAM area, P9 1
P92 P40
and byte-by-byte transfer capability. It is well
suited for low power application systems with
many control ports.
I P20
• Features
1. CMOS process
4. Instructions 94
Internal interrupt 3
13. Standby mode (10 I'-A current consumption)
14. Single power supply (+2.7-+5.5V)
1.6I'-s(SM-551)
3.3I'-s(SM-556)
128
CMOS 4-Bit 1-Chip Microcomputer SM-551/SM~556
• Block Diagram
SP
H L
Q
.,.; D E
Parallel
ROM I/O
(2,048X8) ~
Port
en
..s
Test
PU PL
RESET
Parallel
Output
Port
Clock
Output
Parallel
110
Port
~----~v v~-----
Parallel Output Port Parallel 110 Port
Symbol description
A,B : Accumulators IME : Interrupt mask enable F/F
ACL : Auto clear PU, PL : Program counters
ALU : Arithmetic logic unit PO-PB : Registers
CG : Clock generator PSW : Program status word register
DIV : Divider RD, RE, RF : Mode registers
H,L,D,E : General-purpose registers SB : Shift register
IE : Interrupt enable F/F SP : Stack pointer
IFT,IFA, TC : Count register
IFS, IFB, IFV : Interrupt requests TM : Module register
-.-..-~.------ .......... -SHARP ------------

129
-CMOS 4-Bit 1-Chip Microcomputer . SM-551/SM-556
-~""""""----~--"""'--~~~*'-""-"-""""'"
• Pin Description
P7 I Pull up 4-bit pararell
PO,PI
110 Input-pull 'up I/O selectable by instruction
P5,P8
P6 I/O Input-pull up I/O selectable using RF register
P4 I/O Input-pull up Serial interface input capability using RE register
P9,PA,PB I/O Input-pull up I/O selectable by instruction
P2, P3 0 4-bit pararell
INTA,INTB I Pull up Interrupt input
CK b CK 2 For system clock oscillation
OSC IN , OSC OllT For clock oscillation
\roo,GND Power supply for logic curcuit

.Parameter Symbol '. Ratings Unit Note
Output voltage VOllT -0.3-V oo +0.3 V 1
Output current . IOllT 40 rnA 2
Storage temperature T sto -55'-+150 "C
Note 2: Sum of current output from (pr flowing into) output pin.

Paramet'er Symbol Conditions MIN. TYP. MAX. Unit Note
Crystal oscillator frequency fose 32.768 kHz 3
Voo=5.0V 0.25 2.5
Basic clock SM-55I f MHz
Voo=3.0V 0.25 1.0
oscillation 4
Voo=5.0V 0.25 1.2
frequency SM-556 f MHz
Vo~=3.0V 0.25 0.48
Note 3: Oscillation start time: within 10 seconds
Note 4: Degree of fluctuation frequency: ± 30%
(tolerance of voltage fluctuation: ± 10%)
'-'-~--'-'---SHARP ----.-..----~---
130
• Electrical Characteristics (VoD=2.7-5.5V, Ta= -20- +70"C)

VIllI 0.7VOD . VIll) V
5
V ILI 0 0.3VDD V
Input voltage
VIH2 Voo-0.5 V OD V
6
V IL2 0 0.5 V
2 200
Input current liN Vm=OV pA 5
IVOD=5.0V± 10% 20 200
1111 VOII =V DD -0.5V 50 pA
7
lOll VOL =0.5V 250 pA
10112 VOII =V DD -0.5V 100 pA
8
Output current IOL2 VoL =0.5V 500 pA
VOII = 100
1011:1 pA
VoD -0.5V I VoD =5.0V±10% 400 9
VoL =0.5V 0.5
10L3 rnA
I Voo =5.0V±10% 1.6
f=0.5 MHz, V DD =3.0V±1O% 0.9
lop rnA 10
f=1 MHz, V Do =5.0V±10% 1
Current consumption Standby current 5 11
r----
1ST IVoD =3.0V±10% 12 pA
12
I VoD =5.0V±10% 50
Note 5: Applied to pins POO-P03, Plo-P13, P4o-P43, P50-P53.
P6o-P63, P8o-P83, P90-P93 (during input mode)
P7o-P73, INTA, INTB. RESET.
Note 6: Applied to pins CKI, aSCIN, TEST.
Note 7: Applied to pin CK"
Note 8: Applied to pin ~
Note 9: Applied to pins POO-P03, Plo-Ph, P4o-P4", P50-P53,
P6o-P63, P8o-P83, P90-P93 (during output mode)
P2o-P23, P3o-P3", PAo-PA", PBo-PB"
Note 11: No·load condition when crystal oscillation circuit is n~t operating
Note 12: No·load condition when crystal oscillation circuit is operating
• Oscillation Circuit
C,,=lSpF, Cn =22pF
• Clock Oscillation Circuit

The clock oscillation circuit is composed by' con- External c l O C k - - r l
necting a resistance to the CKI and CK2 pins. When
inputting an external clock directly, input it
openi:J
The system clock ( 1» used is the clock supplied
to CKI divided by 4. CR oscillation External clock
------------SHARP------------
131
CMOS4-Bit1-Chip Microcomputer, SM-551/$M-556
• Applications _
1. Controllers for' various' home appliances, audio
equipment, office equipment, etc.
2. Vending machines
+5V
PA 3
INTA I
Pulse input { PAo
INTB
P9 3
P40 Control signals
I
\ SM-551/SM-556 P9 0
P43 P8 3
POo I
-
Control signals
\ P80
P0 3 P6 3
Pl o I } Input signals
\ P60
132
CMOS 4-Bit I-Chip

SM-552/SM-557 Microcomputer

The SM-552/SM-557 is a 4-bit single chip
CMOS microcomputer with 4,096 bytes of ROM,
256words of RAM, a 15 stage divider and an event
counter.
They has the advantages of high-speed instruc·
tion cycle of 1.6ps(SM-552)/3.3ps(SM-557), 5
different interrupts, subroutine stack in the RAM
area, and byte-by-byte data transfer capability.
They are well suited for low power application
systems with many control ports.
• Features
1 2 3 .I, 3 6 7 g 9 10 11 I I 14 13
1.
CMOS process
~ ~ ~ 8 ~ I~ I~ ~ ~ ~ ~ ~ £ ~ 0:Top View
2.
ROM capacity 4,096 X 8 bits g; 1il :::: :::: c.:>
o
3.
RAM capacity 256X4 bits
4.
Instructions 94
5.
Subroutine nesting using RAM area
6.
Input ports 4 bits
7.
8.
Input/Output ports 28 bits
9.
Interrupt function
Internal interrupts 3
1.6 ps(SM-552)
3.3 ps(SM-557)
------.-.----~--SHARP---~-~--
133
CMOS 4~Bit t-Chip Microcomputer SM-552/SM;.557
• Block Diagram
P
L
D
ROM Parallel
(4, 096X81:: ," ~ ) I/O
Port
RAM
(256X41:: '" r)
Parallel
Output
Port
OSC\\ 4
OSCo,"r 5
Parallel
I/O
Port
,
Parallel Parallel Parallel
Output Port I/O Port Input Port
Symbol description
A,B : Accumulators Pl', PL : Program counters
ACL : Auto clear circuit PO-PB : Registers
ALU : Arithmetic logic unit PS W : Program status word register
CG : Clock generator RD,RE,RF : Mode registers
DIV : Divider SB : Shift registers
H,L,D,E : General-purpose registers SP : S tack point er
IE : Interrupt enable F IF TC : Count registers
IFT,IFA, IFS TM : Module registers
IFB, IFV : Interrupt requests
IME : Interrupt mask enable F IF
, . - . - - - - - - - - - S H A R P -~.-....-------.-.--
134
'CMOS 4-Bit 1-Chip Microcomputer SM-552/SM-557
• Pin Description
P7 I Pull up 4 -bit parallel
PO,Pl
110 Input-pull up 110 selectable by instruction
P5, P8
I
P6 110 Input-pull up 110 selectable using RF register
P4 I/O Input-pull up Serial interface input capability using RE register
P9, PA, PB 110 Input-pull up 110 selectable by instruction
P2,P3 0 4-bit parallel
INTA,INTB I. Pull up Interrupt input
CK h CK 2 For system clock oscillation
OSC IN , OSC OUT For clock oscillation

Input voltage VIN -0.3-V nn +0.3 V 1
Output voltage VOUT -0.3-V no +0.3 V 1
Storage temperature TstK -55-+150 ·C
· Note 2: Sum of current output from (or flowing into) output pin.
• Recommended Operating Conditic:ms

Parameter Symbol MIN. TYP. MAX. Unit Note
Crystal oscillator frequency fose 32.768 kHz
0.25 2.5 3
Basic clock SM-552 f MHz r----
0.25 1 4.
oscillator
1.2
frequency SM-557 f
0.25
0.25 0.48
MHz r--L
4
Note 3: VDD=5.0V
Note 4: VDD=3.0V
135
CMOS 4;',Bit t-Chip M i c r o c , o m p u t e r S M - : 5 5 2 / S M - 5 5 7
'-1III!IIIIi~.II,I"...
, ......................~. . . . . . . . . . . . . . . . . . ..-...-.;~-"......_ , . " . . , . " , . "
• E,lectrical Characteristics (V DD =2.7-5.5V, Ta=-2,0-+70t)

VIlli 0. 7Vuo V DD V
5
V ILt 0 0.3VDD Vi
Input voltage
'v III2 V DD .c:.0.5 V DD V
6
VIL2 0 0.5 V
2 200
Input current lIN VIN=OV pA 5
IVoo =5.0V±10% 20 200
10m VoIl =V Do -0.5V 50 pA
7
lOLl VOL =0.5V 250 pA
10112 VoII =V oo -0.5V 100' pA
8
Output current IOL2 VOL =Q.5V 500 /LA
VOII~ 100
IOIl~1 pA
VDo -0.5V I V",,=5.0V±10% 400 9
0.5
IOL3 VOL =0.5V rnA
I VoD =5.0V±10% 1.6
f=0.5 MHzV Do =3.0V±10% 0.3
lop rnA 10
f=1 MHz V DD =5.0V±10% 1
Current consumption 50 11
pA
~
1ST Standby current
5
Note 5: Applied to pins POo-PO" P1o-P13, P4o-P,43, P50-P53, P6o-P63, P8o-P83,
P90-P9, (during input mode) P7o-P73, INTA, INTB; RESET.
Note 6: Applied to pins CKI, OSC IN , TEST.
Note 7: 'Applied to pin CK 2
Note 8: Applied to pin '"
Note 9: Applied to pins POO-P03, P1o-P13, P4o-P43, P50-P53, P6o-P6"
P8o- P8, , P90- P9:1 , (during output mode)
PZo-PZ" P30-P3,; PAo-PA3, PBo-PB3
Note. 10: No·load condition
Note. 11: No-load condition when crystal oscillation circuit is operating
Note. 12: No-load condition when crystal oscillation circuit is not operating
• Oscillation Circuit
CG=15pF, CD=22pF
• Clock Oscillation Circuit

The clock osciUation circuit is composed by con-
necting a resistance to the CKI and CK, pins. When
inputting an external clock directly, input it
External ciOCk-fi
The system clock ( ¢ ) used is the clock supplied openi:j
to CK, divided by 4.
C R oscillation External clock
.---.----.-~------.-~SHARP - - - - - . - - - - . . - - ........
136
• Applications
1. Controllers for various home appliances, audio
equipment, office equipment, etc.
2. Vending machines
+sv
PA3
INTA \
Pulse input { PA o
INTB
P93
P4 0
\ Control signals
\ SM -5521 SM -557 P9 0
P43 P83
POo \
Control signals \
P03 P80
P63
.. Plo \ } Input signals
- \
Ph
P6 0
.....-.~-.---- ........S H A . R P - - - - - - - - -
137
CMOS 4-Bit 1-Chip Microcomputer SM-5E3
S M- 5 E3 CMOS 4-Bit I-Chip ,Microcomputer

• Description • . Ph; Connections
The SM-5E3 is a 4-bit single chip CMOS micro-
RAM, a 15 stage divider and an event counter. It
has the advantages of a high-speed instruction cy-
cle of 1.6 ps, 5 different interrupts, subroutine P21 I
P22 2
stack in the RAM area, and byte-by-byte data
P2, '
transfer capability. It is well suited for low pow- P3. •
er application systems with many control ports. P3, 5
P32 6
P33 7
P40 8
P41 9
P42 ,.
P4,lI
PSo 12
P5,13
• Features PS2 14
P53 15
1.
CMOS process P60 "
2.
ROM capacity 4,096 X 8 bits P6,17
P62 18
3.
RAM capacity 256 X 4 bits P63 19
4.
Instructions 99 TEST 2.
5.
Subroutine nesting using RAM area P70 21
P71 22
6.
Input ports 4 bits P72 23
7.
Output ports. 16 bits P7" ,.
8.
Input/Output ports. 48 bits
9.
Interrupt function (External interrupts 2 and
internal interrupts 3)
10. External ROM/RAM expandable Top View

14. Single power supply (+2.7-+5.5V)
15. 1.6 ps instruction cycle (MIN.)
- . - - - - - - - - - S H A R P . - . . . . - . - - . - - - - - - -.........
138

compter with 4,096 bytes of ROM, 160 X 4 bits of
RAM, timer/event-counter and mUltiplex interrupt.
It is best suited to controllers of application sys-
tems to drive multi LCD segments.
• Features
1. CMOS process
(including 32 X 4 bits for display)
4. Instructions 93
8. Timer/event-counter
9. Interrupt functions 5
External interrupt
Serial 110 interrupt Top View
Timer/event-counter interrupt
f. signal interrupt
Divider overflow interrupt
11. Standby mode
12. Direct LCD driver circuits (1/4 duty, 113 bias
and 128 segments (MAX.))
13. Insturuction cycle 6.67 ps (MIN.)
--'---'---SHARP'--'---'--~--
139
• Block Diagram
SP Parallel
H I/O
D Port
ROM
(4,096XS)
RAM
Test (12SX4 )
PU PL
RESET
R4
R5
R6
Clock Output 2 R7
RD Segment
RE Output
RF
,
Common Segment Output
Output
Symbol description
A,B : Accumulators IME. : Interrupt mask enable F F
ACL : Auto clear PI-P3 : Registers
ALU : Arithmetic logic unit PL,PU Program counters
BR,DS : Common signal control F/F PSW : Program status word register
CG : Clock generator R4- R7 : General- purpose registers
DIV : Divider RD,RE,RF: Mode registers
D,E,H,L : General-purpose registers SB : Shift register
HC : Common signal circuit SP : Stack pointer
IE : Interrupt enable F /F TC : Count register
IFA,IFB TM : Module register
IFS,IFT,IFV: Interrupt requests
-------~---SHARP-~-~-~---
140
• Pin Description
PO O-P0 3 I Pull up Acc +- PO O-P0 3
P1 0 -P1 3 I/O Pull up I/O selectable by instruction
I/O selectable individually
P2 0 -P2 3 I/O Pull up
Sound output only when P2 3 pin is used for output
P3 0 -P3 3 I/O Pull up Serial interface input capability using RE register
SO-S31 0 Display RAM contents output as LCD segment signals
H1-H 4 0 4·value output capability; used for LCD common output
0 System clock output
'"
CK[, CK 2 For system clock oscillation
OSC'N. OSC OUT For clock oscillation
Vos P• VOA• VOB LCD driver power supply
Voo• GND Power supply for logic circuit
• 'Absolute Maximum Ratings

Voo -0.3-+7 V
Supply voltage 1
VosP -0.3-+7 V
Output voltage VOUT -0.3-V oo +0.3 V 1
Storage temperature T sto -55-+150 "C
Note 2: Sum of current output from (or flowing into) output pin.
• Recommended Operating Conditions (V nn =2.7-5.5V)

Voo 2.7 5.5 V
Supply voltage
VosP 2.7 Voo V
Basic clock oscillator 250 600
f kHz 3
frequency VnD=4.5~5.5V 250 2000
6.6 16
Instruction cycle t /-,s
VDD =4.5-5.5V 2 16
Crystal oscillator frequency fosc 32.768 kHz
Note 3: Degree of fluctuation frequency: ±30%
• Oscillation circuit
CKI CK2
~ R
CG=15pF. CD=22pF
....--.-~---------SHARP -------------------
141
CMOS 4-Bit 1.-Chip Microcomputer SM-:563
• Electrical Characteristics (Voo=2.7-5.5V, Ta=-20-+70t),

VIHI 0.7Voo Voo V
1
V ILl 0 0.3Vpo V
Input voltage
VIHZ Voo-0.5 Voo V
2
VILZ 0 0.5 V
20 200
Input cu'rrent 'IIH V1N=OV p.A 1
I VDD =4.5-5.5V 2 200
IOHl VOH =V DD -0.5V 50 p.A
3
, lOLl VOL =0.5V 250 p.A
10HZ VoH =V oo -0.5V 5 250 p.A
4
Output current IOLZ VOL ;:0.5V 500 p.A
VOH = 400
IOH3 p.A
Voo-0.5V I VDD =4.5-5.5V 100
5
VOL =0.5V 1.6
IOL3 rnA
I VDD =4.5-5.5V 0.5
Rc 5 20 kn 6
Output impedance
Rs 10 40 kn 7
VI 2.7 3 V
Vz Vosp=3.0V 1.7 2 2.3 V
Output voltage 8
V3 No·load 0.7 1 1.3 V
V4 0 0.3 V
i
lop f=600kHz, Voo=3.0V 0.4 1.5 rnA 9
Current consumption Vosp=3.0V 15 40 10
1ST Standby mode I
Voo=3.0V 8 20
p.A ~
11
Note 1: Applied to pins POO-POI, RESET
Plo- Ph, P2o- P23, P30-P32 (during input mode)
Note 2: Applied to pins CKl, Test, OSCIN
Note 3: Applied to pin CK2
Note 4: Applied to pins Plo- Ph (during output mode)
Note 5: Applied to pins P2o- P23, P3o- P32 (during output mode)
;
Note 6: Applied to pins HI-HI
Note 7: Applied to pins SO-S31
Note 8: Applied to pins H2-Hl, So-S;"
COA=lpF, COB=lpF

Note 10: No·load condition when bleader resistance is ON
Note 11: No·load condition when bleader resistance is OFF
142
• Applications • Applications Example

The instruction cycle of the SM563. is fast and Portable devices, auto dialers, sphygmomano·
the unit operates on little power, and therefore it is meters, thermometers, pulsemeters, radio control-
ideal for use as a controller with a liquid crystal lers, cameras, home appliances, various timers,
display in a wide range of hand-held equipment VTR timers, home security system, pocket games
and home appliances.
Key matrix
-.-------SHARP--------
143
CMOS4-Bit 1-Chlp Microcomputer .SM.;572
5 M- 57 2 CMOS 4-Bit I..Chip MicrOC()mputer·

• Description I • Pin Connections·
The SM-572 is a 4-bitsingle chip CMOS micro-
of RAM, 8 bits A/D converter and timer/counter.
It is best suited for applications requiring A/D
circuits.
• Features
1. CMOS process
3. RAM capacity 128 X 4 bits·
4. Instructions 93
7. Output port . 1 bit
9. Timer/counter
8-bit counters 2
Timer interrupt 2
11. A/D converter 8 bits
Conversion time 32 ps(MIN.)
13. Instruction cycle 2 ps (MIN.)
....------,---SHARP"-~--------
144
• Block Diagram
.
Input/Output Port
V,w
Val.
ROM
I 2,032 x9 ) Input
Port
MPX .
•
Input Output Port
Symbol description
ALU : Arithmetic logic unit Ace : Accumulator
X : X register SR Stack register
B : RAM address, register RO,Rl,R2,R3: Latch
C : Carry F/F DIV Divider
PC : Program counter
SP : Stack pointer
CG : System clock generator
MPX.: Multiplexer
A/D : A D convertor and Comparator unit
~'-'-'-----SHARP~'-''------'--'--
145
CMos 4-Bit 1-Chip Microcomputer SM-572
• Pin Description
KC o -KC 3 I Acc +- KC o - KC:l or AID conversion analog input
Acc +- KI, KH, KT, KL
KI, KH
I KI ~ (IF flag set), KH +- (HF flag set),
KT,KL
KT +- (External timer signal input)
Z registor contents output;Can be tested individually
ZO-ZI5 110
Reset ZF IF ",hen used as input pins
PO-P 3 1/0 3 states Acc - . PO-P:l
QO-Q:l +- Acc
QO-Q:l 110
Reset QF IF when used as input pins
110 RO, Rl, R2 +- Acc
RO,Rl,R2
Reset RF IF when used as input pins
F 0 Sound output or 1 bit output
T I Pull down For test (Connected to GND normally)
.fOUT 0 System clock output
CLl> CL 2 For system clock oscillation
OSC IN , OSC OliT For clock oscillation
VRH , VRL AID conversion standard power supply
Voo , GND Power supply for logic curcuit

Supply vo'tage Vo~ -0.3-+7.5 V
Input voltage VIN -0.3-V nn +0.3 V
Output voltage VOUT -0.3-V nn +0.3 V
Output current * lOUT 30 rnA
Operating temperature T~pr -10+70 'C
Storage temperature T". -55+150 'C
·Source current from output pin or sum of sync current.

Supply voltage Vno 2.7-5.5 V
4-0.2 (Voo=5V)
System oscillator frequency fCL KfHz
2-0.2 (Voo=3V)
500-50 (VDD=5V)
System clock frequency fs kHz
250-50 (V DD =3V)
Timer clock frequency fosc 32.768 (TYP.) kHz
146
• Electrical Characteristics (V oo =2.7-5.5V,.Ta=-20-+70"C)

VUII 0.7Voo Voo
V 1
V 1LI 0 0.3Voo
Input voltage
V IJI2 Von -0.5 Voo
V 2
V1L2 0 0.5
VDD =5.0V±10% 80 300 800
lUll V1N=Von p.A 3
Input current VDIl =3.0V±lO% 20 90 300
VDIl =5.0V±1O% 8 25 100
11112 V1N=Vnn p.A 4
VDIl =3.0V±lO% 2 8 35
VDIl =5.0V±lO% 1
10111 VOII =V IlD -O.5V rnA 5,6
VDIl =3.0V±lO% 0.4
VDI)=5.0V±lO% 25
lOll Vou=0.5V p.A 5
Output current 10
VDIl =5.0V±lO% 1
IOL2 VolI =0.5V rnA 6
0.4
1011 VOII =V IlIl -0.5V 200
p.A 7
10112 VolI =0.5V 200
Vllo =5.0V±lO% 1
ACL input pulse width t ACL ps 13
VDIl =3.0V±10%
V Illl rise time for VDIl =5.0V±lO% 50
tV1l1l ms 14
the internal ACL operation VDD =3.0V±10%
VDIl =5.0V±lO% 1.5
fs=500kHz
IA VDD =73.0V±10% 1 rnA 8
VDD =5.0V±lO% 0.5
fs=100kHz
VDD =3.0V±lO% 0.3
VDD =5.0V±10% 5
Current consumption
OFF mode VDD =3.0V±lO% 3
flA 9
VDD =5.0V±10% 50
p.A 10
1ST VDIl =3.0V±10% 30
VDD =5.0V±10% 400
p.A 11
Hold mode VDD =3.0V±10% 100 ,
VDD =5.0V±'10% 600
p.A 12
VDD =3.0V±lO% 200
Note 1: Applied to pins KH;KL, KI, Pa-Po, Q3-QO, R03-ROo, R13-Rlo, R23-R20, R33-R32, KC:,-KCo
Note 2: Applied to pins Z[5-Z0, CL[, OSCIN/KT, ACL .
Note 3: Applied to pins Q3-QO, R03-ROo, R1:J-Rlo, *R23-R20, *R3a-R30, *ZI5-Z0
Note 4: Applied to pin ACL
Note 5: Applied to pins Q3-QO, R03-ROo, Rl:l-Rlo, R23-R20, R33-R3o, Z15-Z0
(*Jf CMOS buffer is specified for mask option, Note 6 applies to these pins.)
Note 6: Applied to pins P3- Po, F, fOliT
Note 7: Applied to pin CL 2
Note 9: When the OSC1N/KT pin is connected to GND and in no· load condition.
Note 10: When the timer clock crystal oscillation circuit and timer 1 are operating and in no·load condition.
Note 11: When the OSClN/KT pin is connected to GND and in no·load condition, f,= 100kHz
Note 12: When the OSClN/KT pin is connected to GND and in no·load condition, f,=500kHz
Note 13: tACL is the ACL input pulse width required to cause ACL to operate when Von has completely risen.
VDD _______~~~,----------VDD
W
tVDD
GND
ACL __________~VDD - O.5V
tACL
Note 14: tVDD is the power supply rise time necessary for the built·in ACL to operate (ACL input pin is connected to GND).
147
....................,.-...;
CMOS 4.,.Bit 1-Chip Microcomputer
~ ..............................-................ 'SM";'S72
• Oscillation Circuit (values for referen'ce)

(a) System clock frequency generating circuit (example 1)
(1) 400kHzoscillation (2) 2 MHz oscillation
Oscillator. KBR-400B : Made' by Kyocera C~LI

CL2 Oscillator KBR-2.0MS : Made by Kyocera
Rr=IMO Corp. Rr Rr=lMO Corp.
Rd=5600 Rd Rd=8200
CI=330pF [] Cl =33pF
C'2=330pF C2 I I C2 C2 =33pF
'- (b) System clock frequency generating circuit (example 2)
VDD-fcL Characteristics R-fcLCharacteristics
N
N ::t:
i1 2
" 2
\\
Rr=lOkO ~ootv
»
"~
.."».
g.
~ 0.5
§ 0.4
]
~
.,
o
0.3 -- Rr=82kO
.&
J:: 0.5
c
.~
1;;
=
.<l 0.2
0
.,
\Joo=3
~\
V
2 4 6 10 100
Supply voltage Voo (V) Externally attached resistance R (kO)
(c) Clock generating circuH for timer (example)
When fosc=32.768kHz
Cl = 22pF. C2 = ~2pF
Crystal: 32.768 kHz
(d) External clock input circuit
CLI CL2 OSCOUT

t t
Open Open
Pulse generator Pulse generator
148
Ceramic buzzer
}
.
o
'"Ii
<fl
Control output
--.v
'-----<----f I--~...... DD
149

of RAM, 8-bit A/D converter, timer/counter and Qo I
8-bit serial 1/0_

lt is best suited for applications requiring A/D
circuits_
• Features
1. CMOS process OSC(wr 14
OSCI,/KT 15
2_ ROM capacity 4,069 X 9 bits KL 16
3_ RAM capacity 192X4 bits
4. Instructions 93
~~~ N N N ~ N NN N NN Top View
7. Output ports 1 bit
9. Timer/counter: 8-bit counters 2
External interrupts 21Timer interrupts 2
13. Instruction cycle 2 ps (MIN.)
64-pin dual-in-line package
Top View
150
5 M- 5 79 CMOS 4-Bit I-Chip Microcomputer

The SM-579is a 4-bit single chip CMOS micro-
of RAM, 8-bit A/D converter, timer/counter and Qo I
Villi 2
8-bit Serial I/O. ACL 3
lt is best suited for applications requiring A/D CLi •
circuits. CL2 5
• Features
1. CMOS process
4. Instructions 93
Top View
7. Output ports 1 bit
9. Timer/counter: 8-bit counters 2
Timer interrupts 2
14. Instruction cycle 2 p.s (MIN.)
64-pin dual-in-line package
Top View
----~.-.------SHARP-----.-.-~
151
.....,,~- .. .....
CMOS4-Bit 1-Chip Microcomputer
~ ~......,~~ ......-..-,;.-.... .... .....
; ~" ~ ~.-. ......
,SM-590
SM~'5 90 CMOS4-Bit I-Chip MicrocomputeJ"

• Description • PinConnections
computer with 50S bytes of ROM. 32 X 4 bits of ROo I
RAM.
It is best'suited for use in a compact controller. a R02 ,
sy~tem subcontroller and other various application R03 4
systems. R33/CL2 5
CLI6
I.
ACl,
Features
1.CMOS process ROo I
2.ROM capacity 50SX S bits

" 3.RAM capacity 32 X 4 bits
4.Instructions 41 R02 ,
5.Subroutine nesti~g 4 levels R03 5
R3,,/CL2 6
6.Input/Output' ports 15 bits(MAX.)
Available for use as lOrnA output port
10 bits (MAX.) by mask option
GND 9
(RO o-R0 3• RIo-RIa, R3 h R3 2)
7. Standby mode
S. Single power supply (2.5-5.5V)
9. Instruction cycle 1 fLs
10.
Package 110 ports
16DIP 11 bits
lSDIP 13bits
20DIP 15bits
Top View
152
CMOS 4-Bit .1-Chip Microcomputer SM-590
• Block Diagram
Parallel I/O Parallel Out/Osillator

Oscillator
VIlIl
RAM
(32X4) GND
ROM ACL
1508X8J
. Symbol description
A.... : Accumulators PC : Program counter
ALU : Arithmetic logic unit RO-R3 : Register
B : RAM address register SP : Stack pointer
C : Carry F F SR : Stack register
CG : Clock generator X : Temporary register
• Pin Description
RO o -R0 3 110 Pull down *1 Acc - RO o-R0 3 , RO o-R0 3 <-- RAM
Rl o -R1 3 110 Pull down* 1 Ace - Rl o-R1 3 , Rl o-R1 3 <-- RAM
R2 o -R2 3 110 Pull down/open drain * 2 Acc - R2 o-R2 3 , R2 o -R2 3 <-- RAM
R3 0 -R3 3 110 Pull down*1 Acc - R3 0 -R3 3 , R3 0 -R3 3 <-- RAM
V DD , GND Power supply for logic circuit
*1 Mask option; Open drain 110 or CMOS output selectable
* 2 Mask option
-----~.--.---....----SHARP -----.----~-
(
153
CMOS 4-Bit 1-Chip Microcomp~ter SM-590

Supply voltage Voo -0.3-+7.5 V
Input voltage ' VI -0.3-V oo +0.3 V
Output voltage Vo -0.3-V oo +0;3 V
Source output current sum :ZIoH 120 mA
Sync output current sum :ZIoL ' 20 mA
Operating temperature T@f -10-+70 'C
Storage temperature T stg -55-+150 'C

Parameter Symbol Conditions MIN. TYP. MAX. Unit
3V±0.5V 4 50
Command execution time tSYS /Ls
5V±0.5V 1 50
• Clock Input Signal AC Characteristics

Clock rise time tr Voo =2.5-5.5V 50
ns
Clock fall time tf Voo =2.5-5.5V 50
tL Voo=5V±0.5V 0.08 6.3
Clock pulse width /LS'
tH Voo=3V±0.5V 0:45 6.3
Note: When external clock is input
• Electrical Characteristics (Voo=2.7V-5.5V. Ta=-10'C-+70'C)

Vun 0.7Voo Voo V
1
V1LI 0 ,0.3V oo V
Vm2 Voo-0.5 Voo V
2
Input voltage V1L2 0 0.5 V
V1L3 Voo =5V±10% 0.7 1.4 2.1 V
3
e:.V 1 Voo=5V±lQ% 1.1 2 3<.1 V
Voo =3V±10% 15 70 200
Imi VIN=VOO /LA 1
Input current V oo =5V±10% 70 250 750
Voo=3V±1O% 7 20
1m2 V1N=VOD
20 60
/LA 4:
Voo=5V±1O%
IAI tsys=2 f1S VDo =5V±10% 1 3 mA
Voo =3V±10% 100 200
Current consumption IA2 tSys= 10 f1s /LA 5
Voo =5V±10% 200 500
1ST Standby mode 1 ;, 2 /LA
154
Output current (Ta= -lO·C - +70·C)

10 (MIN.) IOH (rnA) IOL (rnA) IOL (pA) Note'
~n
Pin
Voo =5V±10% Voo=3V±10% VoL=Oo4V
VoH =V oo -2V VOH =V OD -0.5V Voo =5V±10% lIE
VOL =Oo4V
Voo =5V±10% lIE
ROo 10 1 1.6 0.8 15 8
R0 1 10 1 1.6 0.8 15 8
R0 2 10 1 1.6 0.8 15 8
R0 3 10 1 1.6 0.8 15 8
RIo 10 1 1.6 0.8 15 8
Rl1 10 1 1.6 0.8 15 8
R12 10 1 1.6 0.8 15 8
R13 10 1 1.6 0.8 15 8
R20 4 0.5 15 8
R21 4 0.5 15 8
R22 4 0.5 15 8
R23 4 0.5 15 8
R3 0 4 0.5 1.6 0.8 15 8
R3 1 10 1 1.6 0.8 15 8
10 1 6
R3 2 1.6 0.8 15 8
3 004 7
CL 2/R3 3 1 0.15 0.6 0.3
Mask option
2 1
switch number
Note 1: Applied to pin ROo, ROI, RO" R03, RIo, Rh, Rh, Rh, R20, R2l, R2" R23, R30, R3l, R3,
. Note· 2: Applied to pins ACL, CL I
Note 3: Applied to pin R2, (when standby cancel signal is input)
t:. VI=VIH3-VIL3 (See the SM590 programming manual for details)
Note 5: No-load condition
Note 6: When the contents of the R latch is output to the R3, pin_
Nate 7: When the clock input to the CLI pin is output from the R3, pin_
lIE: VDD=3V±1O%
155

computer with 1,016 bytes of ROM, 56X4 bits of
RAM.
It is best suited for use in a compact controller, a
system subcontroller and other various application
systems.
• Features
1. CMOS process
4. Instructions 41
6. Input/Output ports 15 bits (MAX.)
Available for use as lOrnA output port 10 bits
(MAX.) by mask option
(RO o-R0 3, R1 o-R1 3 , R3j, R3 2)
7. Standby mode
8. Single power supply (2.5 - 5.5V)
9. Instruction cycle 1 f.1S ROo 1
10'~P~a-c-ka-g-e-'~I~/O~p-(o-rt-s-
16DIP 11 bits
18DIP 13bits RO" ,
20DIP 15bits R3,,/CL2 6
Top View
-'-'---'-'--SHARP~-------~-----
156
• Block Diagram
Parallel I/O
, . -_ _ _ _ _ _ _ _ _ _.-J.4 _ _ _ _ _ _ _ _ _ _...,
Parallel Out/Oscillator Oscillator
Voo
RAM
(56X4) GND
ROM ACL
(1016X8 )
Symbol description
A('(' : Accumulators PC : Program .counter
ALU : Arithmetic logic unit RO-R3 Register
B : RAM address register SP : Stack pointer
C : .Carry F/F SR : Stack register
CG : Clock generator X : Temporary register
• Pin Description
RO o-R0 3 I/O Pull down*l Ace - ROo-RO:l , ROo-RO a +- RAM
Rio-Ria I/O Pull down*l Acc -Ri o-Ri 3 , Ri o-Ri 3 +- RAM
R2 o-R2 3 I/O Pull down/open drain * 2 Acc - R2 o-R2 3 , R2 o-R2 3 +- RAM
R3 o-R3 3 I/O Pull down* 1 Ace - R3 0 -R3 3 , R3 0 -R3 3 +- RAM
V DD, GND Power supply for logic circuit
* 1 Mask option; Open drain 110 or CMOS output selectable
*2 Mask option
-.-----------SHARP.-..-.--------
157
CMOS 4-Bit 1-Chip Microcomputer SM:.591

Supply voltage Voo -0.3-+7.5 V
Input voltage V, -0.3-V oo +0.3 V
Output voltage Vo -0.3-V oo +0.3 V
Source output current sum -IIoH- 120 rnA
_ Sync output current sum IIoL 20 rnA
Operating temperature Toor -10-+70 t

3V±0.5V 4 50
Command execution time Tsys ps
5V±0.5V 1 50
• Clock Input Signal AC Characteristics

Clock rise time tr Voo =2.5-5.5V 50
ns
Clock fall time t( Voo =2.5-5.j'iV 50
tL Voo=5V±0.5V 0.08 6.3
Clock pulse width ps
tH Voo=3V±0.5V 0.45 6.3
Note: When external clock is input
• Electrical Characteristics (Voo=2.7V-5.5V, Ta=-10t-+70t)

Vnll 0.7Voo - Voo V
1
V'LI 0 0.3Voo V
Input voltage VIII 2 Voo-0.5 Voo V
2
V'L2 0 0.5 V
V'L3 Voo =5V±10% 0.7 1.4 2.1 V
3
6V, Voo =5V±10% 1.1 2 3.1 V
Voo =3V±10% 15 70 200
Inll ' V'N=V OO pA 1
Input current Voo =5V±10% 70 250 750
Voo =3V±10% 7 20
IIII2 V'N=V OO pA 4
Voo =5V±10% 20 60
IAI tsys=2 ps Voo =5V±10% 1 3 rnA
Voo =3V±10% 100 200
Current consumption IA2 ' tSys= 10 pA pA 5
Voo =5V±10% 200 500
1ST Standby mode 1 2 pA
158
Output current (Ta= -IO·C - +70·C)

10 (MIN.) IOH (rnA) IOL (rnA) IOL (p. A) Note
~
Voo =5V±10% Voo =3V±10% VOL =O.4V VOL =O.4V
Pin VoH =V oo -2V VoH =V oo -O.5V Voo =5V±10% liE Voo =5V±10% liE
ROo 10 1 1.6 0.8 15 8
R0 1 10 1 1.6 0.8 15 8
R0 2 10 1 1.6 0.8 15 8
R0 3 10 1 1.6 0.8 15 8
RIo 10 1 1.6 0.8 15 8
Rl1 10 1 1.6 0.8 15 8
R12 10 1 1.6 0.8 15 8
R13 10 1 1.6 0.8 15 8
R20 4 0.5 15 8
R21 4 0.5 15 8
R22 4 0.5 15 8
R23 4 0.5 15 8
R3 0 4 0.5 1.6 0.8 15 8
R3 1 10 1 1.6 0.8 15 8
10 1 0.8 6
R3 2 1.6 15 8
3 0.4 0.8 7
CL 2 /R3 3 1 0.15 0.6 0.3
Mask option
2 1
switch number
Note 1: Applied to pins ROo, ROl, RO" R03, RIo, Rh, Rh, Rh, R2o, R21, R22, R23, R3o, R31, R32
Note 2: Applied to pins ACL, CL I
Note 3: Applied to pins R22 (when standby cancel signal is input)
!!. Vr=VIH3-VrL3 (see the SH59I programming manual for details)
Note 5: No-load condition
Note 6: When the contents of the R latch is output to the R3 2 pin.
Note 7: When the clock input to the CLI pin is output from the R3, pin.
lIE: VDD =3V±10%
----....-......-.--------SHARP - - - - - - - - - - - - -
159
DevetQpment Guide for 4-Bit 1-Chip Microcomputers (SM Series)
I . . . . . .. .
DeveJ6pmentguidefor.4-Bif 1-Chip
Microcomputers (SM Series)
(1) Description
functions required of the microcomputer are clear.
To facilita,te efficient product development us- Specifications should be prepared by the user, but
ing Sharp's SM series 4-bit, I-chip microcompu-
consultation on SM series microcomputers will be
ters, we have established a general development
provided on request. In addition, a programming
procedure covering determination of specifications manual is available for each microcomputer. .
to actual delivery of the microcomputer as shown
below.
® Determining the microcomputer to be used
Select a microcomputer mos.t suitable for the pro-
duct. After determining the model of microcompu-
(2) Development Procedure
ter, we will work out a rough development sche-
CD Determination of specifications dule in consultation with the user.
Specifications for a product you intend to de- ® System design
velop must be determined in such a way that the Detailed specifications for the operation of the
End user side work SHARP.side.w~rk
r1 h
Technical meeting/Determining
specifications
Creating check- System' design

out device I
I J
Checker, checklist, circuit diagram of checker -~
Write programme/
assemble /debug
t Program demonstration
Final check of I!t
program PLA designation
I J
Program approval t
ROM design drawing
-l
TS evaluation/approval: I TS manufacture/
I forwarding
l X------
TS approval ~ I
ES evaluation/approval I. J
I
ES manufacture/
forwarding
I
(Can be eliminated)
I
I
ES approval
+
1-------
I
I
CS man.ufacture/ (Can be eliminated)
C S evaluation / approval :
I forwarding
L t.I ______
CS approval ~.
Mass production
Delivery of goods l J
I
160
Development Guide for 4-Bit 1-Chip Microcompliters (SM Series)
--.-..---.-.-..-..-..-.-.-.-..-..-..-.-
microcOl~puter and its peripheral circuitry are de- after consultating with the user.
termined of this stage. We recommend that the user ® PLA (Programmable Logic Array) assignments
confer with Sharp's staff even if the user himself If the program is developed by the user, the user
under takes program development. prepares the PLA assignments diagram which
If Sharp is to carry out program development, should be submitted to Sharp about two weeks be-
the user must prepare the specifications first. Af- fore the date on which the ROM is scheduled to be
ter consultation with Sharp, the user determines submitted. The procedure for PLA assignment is
the final specifications. The subsequent schedule covered in the programming manual. Pre-printed
will then be settled after consultation with the
user.
@ Writing the program
PLA assignment forms will be provided to the user
on request.
When the program is developed by Sharp, we
will make the PLA assignments.
@
2
==~
A flow chart is worked out and based on it,
machine code is written. The mnemonic codes ®, ROM submission
used for coding are covered in the programming If the program is developed by the user, the
manual or cross-assembler manual. After coding, ROM must be submitted in the form of either an
a source file is prepared using a computer editor. EPROM or diskettes. Along with the ROM , the
Sharp's microcomputer development tools, the ROM map should also be submitted to make sure
SM-D-8000II or SM-D-80 system can be used for that the correct data can be ,read from the ROM.
this purpose. A microcomputer development sys- Whoever develops the program, it is impossible
tem running under the CP/M (Digital Research Inc.) to change the program after the ROM is submitted.
operating system can also be used. For the prepa- The final confirmation of program operation must
ration of source file, refer to the respective de- be extremely thorough.
velopment systems' manuals (SM-D-8000II User's ®> TS (Technical Sample)
Manual, for example). The TS is submitted to the user in a ceramic
® Assembler package for performance evaluation as a trial mod-
The object file is created from the source file us- el. If no problems are found, the user shall issue a
ing the cross-assembler prepared for the develop- statement of performance approval. Note that' the
ment system. TS package is a ceramic type and differs from that
There are a number of cross-assemblers avail- which will be mass produced.
able to meet the requirements of respective SM @ ES (Engineering Sample)
series products. Please, contact us for details. . After approval ofthe TS, the ES is prepared and
® Debugging and program revision submitted to the user. The ES is normally con-
After the object file has been created, the prog- tained in a plastic package the same shape as that
ram must be debugged by operating the EVA board which will be mass produced.
or CPU unit while using the checker to monitor After evaluating the performance of the ES, the
program operatfon. If the program is not running user shall issue performance approval, assuming
properly, it must be revised and re-qssembled until no problems are encountered. The ES may be skip-
a satisfactory object file is prepared. A number of ped if desired.
development tools are available to perform this @ CS (Commercial Sample)
task efficiently. After approval of the ES, the CS is prepared and
(j) Final confirmation of program operation submitted to the User. The CS is the mass-pro-
The final confirmation of the program is in- duction trial model so it is made in the same shape
cluded in the debugging work described in (2) ® if and quality as that which will be mass prodl:lced.
program development was made by the user. After evaluating the performance of the CS, the
If Sharp undertook program development, three user shall issue performance approval, assuming
copies of programming specifications are usually no problems are encountered. The CS may be skip-
presented to the user for final confirmation of ped if desired.
program operation one week before the ROM is @ Mass production
submitted. If no problem is found in the program- After approval of the CS, mass production is in-
ming specifications, a copy of programming speci- itiated. If the ES and/or CS is omitted, the user
fications shall be sent back to us bearing a signa- shall advise us when to start mass production.
ture of approval.
In the event that probelms are discovered in the (3) Development Tools
program at this time, the program will be revised To faciJ.itate program development for SM
161
Development
.'
.~~~~~~~~~
Guide
I
......
for 4-BIt 1-Chip Microcomputers ,(SM Series)
~~ .......-....:--,.-..-
r-SM~W--~--~----------------~~
r---~-------------'
SM-D -8000 II I CPU :
I
I
I
Floppy disk I
I
I
I
I
ROM OK) I
II
RAM (64K) I I
I ___________________________ JI
I
I
SIO
I
I PTP/PTR
IL __________________ JI
Terminal printer
(Sharp writer, etc.)
SM-series
series microcomputers, two kinds of development evaluation board
tools are available: one which uses the SM-D-
8000II and one which uses the sharp MZ-80B
computer.
Development tools equipped with an RS232C in-
terface running under the CP1M OS can also be
used.
CD SM-D-8000II system
This emulator consists of the keyboard, display
LED, PROM writer, and interfaces. Although it is
possible for the SME-20 to debug the prograin by
connecting the CPU unit or EVA board, more effi- Debugger unit
cient debugging can be achieved by transferring
the object file through the SM-D-8000II and
RS232C interface.
For details, see the SM software package manual
and instruction manuals of the SM series,SM-
D-800011 and SME-20. SM .evaluation
The SME-20 can be connected not only to the board
SM-D-80001l, but to any development device
equipment with an RS232C interface.
@ SM-D-80 system
. The SM series development system can be confi-
gured by connecting the debugger unit and SM ev-
alution board to the basic FDOS system (MZ-80B,
floppydisk, printer) of the commercial personal
computer MZ-80B. Various utility 'programs such
as a cross-assembler, debugger and editor which
operate under the control of the FDOS are pro-
vided as standard equipment to facilitate efficient
program debugging.
162
....,....,....,~....,....,~....,~~....,....,~~ ..........
Development Guide for 4-Bit 1-Chip Microcomputers (SM Series)
~....,
Connector for PROM writer ----,

I
Power.
I
I
r------------------l I
I
I
I
I
I
ROM (2K) I
I
I
I
I
RAM (64K) I
I
I
I
Expansion I/O
MZ-80B system I
(FDOS)
L ___________ _ _____J
I
I I
I I
I I
I I
IL ____ Main body of debugger unit I
..---___.i..J---:-_ _-:--. _ _ _ _ ...lI
Floppy disk
SM -series
Printer evaluation board
....--------SHARP--------
163
a-Bit 1-Chip Microcomputers
Z8-01 Microcomputer Unit LH0801
LHOSO 1 Z8-0! Microcomputer Unit

Compared to earlier single-chip microcomputers,
the Z8 offers faster execution; more efficient use of
memory, more sophisticated interrupt, input/out-
put and bit-manipulation capabilities ; and easier
system expansion.
Under program control, the Z8 can be tailored to
the needs of its user. It can be configured as a
stand-alone microcomputer with 2K bytes of inter-
nal ROM, a traditional microprocessor that man-
ages up to124K bytes of external memorY,or a par-
allel-processing element in a system with other
processors and peripheral controllers linked by the
Z-BUS. In all configurations, a large number of
pins remain available for 110.
• Features
1. Complete single-chip microcomputer with in-
ternal ROM, RAM and 110
• RAM 124 bytes
• ROM 2K bytes
• 110 32 lines
2. On-chip two programmable 8-bit counter/tim-
ers, each with a 6-bit programmbre prescaler Top View
3. Full-duplex UART
4. 144-byte register file
5; Register pointer so that short, fast instructions
can access any working register groups
6. Vectored, priority interrupts for 110, counter /
timers, and UART
7. Up to 62K bytes addressable external space
each for program and data memory
8. On':'chip oscillator
9. High speed instruction execution
• Working register operating time: 1.5 ps
• Average instruction execution time: 2.2 fJ.S
,; Maximum instruction execution time: 5.0 fJ.S
10. Low-power standby option which retains con-
tents of general-purpose registers
11. Single + 5V power supply
12. All pins are TTL compatible
---.--.-----SHARP-----,~--...-.-,
166
• Block Diagram
Serial and Parallel System _

I/O and Control Clock :ll
Vte( +5V) GND(OV) f"---., ~
}-------{ll}-------{
Port 3 Machine Timing

&
Instruction Control
ALU
Flags
UART
Program Memory
(2,048X8)
Register Pointer
Counter/Timer
Register File Program Counter

(I24x8 )
Interrupt Control
Port 2 Port 0 Port 1
~-------vr-------- '---------vr ---------

I/O or As-Als I/O or AD o -AD 7
--~--~--SHARP'-~-''''''''-'--~
167
Z8-01 Microcomputer Unit LH0801.
• Pin Description
Pin Meaning I/O Function
PO O-P0 7 Port 0 I/O 8-bit I/O port, programmable for I/O.
Pl o -P1 7 Port 1 I/O Programmable for I/O in btyes.
P2 o-P2 7 Port 2 I/O Programmable for I/O in bits.
P3 0 -P3 7 Port 3 I/O P3 0 -P3 3 for input, P3 r P3 7 for output.
- 0 Active "Low", activated for external address memory
AS Address Strobe
. transfer.
- Active "Low", activated for external data memory
DS Data Strobe 0
transfer.
R/W Read/Write 0 Read at "High", Write at "Low".
RESET Reset I Active "Low". Initializes.
XTALl Clock 1 I Clock terminal pin.
XTAL2 Clock 2 0 Clock terminal pin.

Input voltage VIN -0.3-+7 V
Output voltage VOllT -0.3-+7 V
Operating temperature Tops 0-+70 'C
Storage temperature T stg -65"':'+150 'C
• DC Characteristics (Vee=5V±5%, Ta=0-+70'C)

Driven by external clock
Clock input high voltage VeH 3.8 Vee V
oscillator
Clock input low voltage VCL -0.3 0.8 V
oscillator
Input high voltage VIR 2.0 Vee V
Input low voltage VIL -0.3 0.8 V
Reset input high voltage VRH 3.8 Vee V
Reset input low volta,ge VRL -0.3 0.8 V
Output high voltage VOH IOII =-250pA 2.4 V 1
Output l~w voltage VOL IOL=+2.0mA 0.4 V 1
Input leakage current IlL OV:;;;:V IN :;;;:+5.25V -10 10 pA
Output leakage current IOL OV~VIN~+5.25V -10 10 pA
Reset input current IIR Vee=5.25V, VRL=OV -50 pA
Supply current Icc 180 rnA
Supply current IMM 10 rnA
Note 1: [OH= -100,u A and [OL= l.OmA as to Ao-All, MDS, SYNC, SCLK and [ACK in LH0802.
Vee
2.lkO 1.5kO
From output From output l8kO
under test ruDder test
;>CJ>-------...... ;'O>--+--CrystaI2
o---~-~~~~
74LS04 ~CL-=15pF MAX.
' - - - -.....--'Crystall
lCL=15:PFMAX.
Test load 1 Test load 2 TTL external clock interface circuit
- - . . - . . - . . - - - - - - - - - S H A R P -~-.-.-.------
lEl8
• External I/O or Memory Read/Write (Vcc=5V±5%, Ta=0-+70"C)
Symbol Parameter Conditions MIN. MAX. Unit Note

TdA (AS) Address valid to AS t delay Test load 1 50 ns 2
TdAS (A) AS t to address float delay Test load 1 70 ns 2
AS t to input data required
TdAS (DI) Test load 1 360 ns 4
valid delay
TwAS AS t low width Test load 1 80 ns 2
TdA (DS) Address float to DS ! delay Test load 1 0 ns
- I Read Test load 1 250 ns 3
TwDS DS low width
I Write Test load 1 160 3
TdDS (DI) DS! to input data required valid Test load 1 200 ns 4
ThDS (DI) Input data hold time 0 ns
TdDS (A) DS t to address active delay Test load 1 80 ns 2
TdDS (AS) DS t to AS! delay Test load 1 70 ns 2
TdR (AS) Read valid to AS t delay Test load 1 50 ns 2
TdDS (R) DS t to read not valid Test load 1 60 ns 2
TdDO (DS) Output data valid to DS! delay Test load 1 50 ns 2
TdDS (DO) DS t to output data not valid delay Test load 1 80 ns 2
TdW (AS) Write valid to AS t delay Test load 1 50 ns 2
TdDS (W) DS to write not valid delay Test load 1 60 ns 2
Note 1: All timing references use 2.0 V for a logic "I" and 0.8 V for a logic "0".
Note 2: Delay times are for an input clock frequency of 8 MHz. If below this frequency, add the incremental clock period to the standard
delay time.
Note 3: DS lower width is for an input clock frequency of 8 MHz. If below this frequency, add 3 increments of clock period to the
standard. The width varies with execution command.
Note 4: These delay times show system memory access time with an 8·MHz QC unit. If below this frequency, add 4 increments of clock
period for TdAS (OIl or 3 increments of clock period for TdDS (OIl.
CLOCK
PORT 0,
DM
PORT 1
AS
TdDS(R)
DS dTdRIAS'
_TdWIAS) *" TdDS(W)~
RiW
'-'-'--'-'-'--SHARP'--'-'-'-'---
169
• Additional Timing Table (Vcc=5V±5%, Ta=O-+70'C)I:

TpC Input clock period 125 1,000 ns
Driven by, external
TrC, TfC Clock input rise and fall times 25 ns
clock oscillator >
Driven by external
TwC Input clock width 37 ns
clock oscillator
TdSC (AS) System clock input to AS delay ns 5
TdSY (DS) Command sync output to DS delay 200 ns 5,6
TwSY Command sync output pulse width 160 ns 5,6
Note : All timing references use 2.0 V for a logic "1" and 0.8 V for a logic "0". __ ,
Note 5: Test load 1 is used when' SCLK and SYNC are outputt via port 3, aad test load 2 when SCLK and SYNC are direct-output with
64-pin version.
Note 6: With an 8 MHz QC unit. If below this frequency, add 2 increments of clock period.
CLOCK
SCLK
AS Data input 1--------1

sample
DS Read cycle-=-1\-----\;-Write cycle r

t:TdSY (DS 1---+1
SYNC ~_,T_w_S_Y_____jt
• Handshake Timing (V cc =5V±5%, Ta=0-+70'C)

,
TsOI (DA) Data in setup time 0 ns
ThDA (OI) Data in hold time 230 ns
Input handshake
TwDA Data available width 175 ns
Test load 1
Input handshake
20 175 ns
Test load 1
TdDAL (RY) DAV! to RDY! delay
Output handshake
0 ns
Test load 1
Input handshake
150 ns
Test load 1
TdDAH (RY) DAVt to RDY t delay
Output handshake
0 ns
Test load 1
TdDO (DA) Data out to DA V ! delay Test load 1 50 ns
TdRY (DA) RDY to DAV t delay Test load 1 0 205 ns
170
DAV
(input)
TdDAL(RY)
RDY
(output)
Port read
Input handshake
DATA OUT ~ Data out valid

----~DO(DA)
DAV
(output)
RDY--------------~------~~~~--~
(input) ~---......---~
Output handshake
171
.z~-01 Microcomputer Unit LH0801
• Architecture
(1) Address Spaces
(i) Program Memory The 16-bit program Z8 instructions can access registers directly or
counter addresses 64K bytes of program memory indirectly with an 8-bit address field. The Z8 also
space. Program memory can be located in two areas 'allows short' 4-bit register addressing using the
: one internal and the other external (Fig. 1). The , Register Pointer (one of the control registers). In
first 2048 bytes consist of on-chip mask-prog- the 4-bit mode, the register file is divided into nine
rammed ROM. At addresses 2048 and greater, the working-register groups, each occupying 16 con-
Z8 executes external program memory fetches. tiguous locations. The Register Pointer addresses
The first 12 bytes of program memory are re- the starting location of the active working-register
served for the interrupt vectors. These locations' group'.
contain six 16-bit vectors that correspond to the (iv) Stacks Either the, internal register file
six available interrupts. or the external data memory can be used for the
(ii) Data Memory The Z8 can address 62K stack. A 16-bit Stack Pointer (R254 and R255) is
bytes of external data memory beginning at loca- used for the external stack, which can reside any-
tion 2048 (Fig. 2). External data memory may be where in data memory between locations 2048 and
include with or separated from the external prog- 65535. An 8-bit Stack Pointer (R255) is used for
ram memory space. OM, an optical I/O function the internal stack that resides within the 124
that can be programmed to appear on pin P3 4 , is general-purpose registers (R4-R127).
used to distinguish between data and program
memory space.
(iii) ,Register File The 144-byte register
file includes four I/O port registers (RO-R3), 124 65,535
general-purpose registers (R4-R127) and 16 con-
trol and status registers (R240-R255). These reg-
isters are assigned the address locations shown in
Fig. 3.
External data me,mory

65, 535
External ROM or RAM

2, 048
Location of firs t
byte ,of instructJon On-chip ROM
executed after '-....
reset 12
f"'------ --- --- -------- 2,048 t-'---------1
11 IRQ5
10 IRQ5 Not addressable
9 IRQ4
O~ ______________ ~
8 IRQ4
7 IRQ3
Interrupt vector
6 IRQ3
(Lower byte)
5'" IRQ2
Fig. 2 Data memory map
,4 J! IRQ2
Interrupt vecto r 3 IRQ1
(Upper byte ) 2 IRQ1
1 IRQO
0 IRQO
Fig: 1 Program memory map
172
Za-01 Microcomputer Unit LH0801
LOCATION IDENTIFIERS
255 STACK POINTER(BITS 7-0) Sl'L
254 STACK POINTER(BITS 15-8) SPH
r--;--;:::==t--------., 255
-..J: ~253
253 REGISTER POINTEIt RP
252 PROGRAM CONTROL FLAGS FLAGS r7r6irsr4 I 000 0
251 INTERRUPT MASK REGISTER IMR l~
I_--::-:~:--.-_~I 240
The upper nibble of the reg ister file address
250 INTERRUPT REQUEST REGISTER
249 INTERRUPT PRIORITY REGISTER
IRQ
IPR
>----+ provided by the register pointer specifies the
,active working-register group_
248 PORTS 0-1 MODE POIM r--------,127
247
246
PORT 3 MODE
PORT 2 MODE
P3M
P2M
--1l
245 TO PRES CALER
TIMER/COUNTER 0
PREO
TO
-.J
244
243 T1 PRES CALER PREI
, l
242 TIMER /COUNTER I Tl
TMR
r-Jl
241 TIMER MODE
240 SERIAL I/O
NOT
SIO
1-- -f
l 1-_ _ _ _ _ _ _ _-1 of the register
The lower nibble
IMPLEMENTED
r--.--ir file address
SPECIFIED WORKING~ provided by the
127 l REGISTER GROUP instruction
GENERAL- PURPOSE
r
t- - ,..
points to the
specified
REGISTERS
__ll-________
f -I register'
4
3 PORT 3 P3 It--------t 15
2 PORT 2 P2 r
1 PORT I PI --l r---iIOP;rts---- ~
,0 PORT 0 PO Register file
Fig. 3 The register file Fig. 4 The register pointer
(2) I/O ports vide address bits AsAll (lower nibble) or As-A15
The Z8 has 32 lines dedicated to input and out- (lower and upper nibble) depending on the required
put. These lines are grouped into four ports of address space.
eight lines each and are configurable as input, out- (iii) Port 2 bits can be programmed independent-
put or address/data. Under software control, the ly as input or output. The port is always available
ports can be programmed to provide address out- for I/O operations. In addition, Port 2 can be confi-
puts, timing, status signals, serial I/O, and parallel gured to provide open-drain outputs.
I/O with or without handshake. All ports have ac- (iv) Port 3 lines can be configured as I/O or
tive. pull-ups and pull-downs compatible with TTL control lines. In either case, the direction of the
loads. eight lines is fixed as four input (P3 0 -P3 3 ) and four
( i ) Port 1 can be programmed as a byt.e I/O output (P3 4 -P3 7 ). For serial I/O, lines P3 0 and P3 7
port or an address/data port for interfacing exter- are programmed as serial in and serial out respec-
nal memory. tively.
Memory locations greater than 2048 are refer- • handshake for Ports 0, 1 and 2 (DA V and
enced through Port 1. To interface external mem- ROY)
ory, Port 1 must be programmed for the multi- • four external interrupt request signals
plexed Adress/Data mode. If more than 256 exter- (IRQo-IRQ3)
nal locations are required, Port 0 must output the • timer input and output signals (TIN and TOUT)
additional lines. • Data Memory Select (OM).
(ii) Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing external (3) Serial Input/Output
memory. Port 3 lines P3 0 and P3 7 can be programmed as
For external memory references, Port 0 can pro- serial I/O lines for full-duplex serial asynchronous
----.-~-"----SHARP-.-~--:-----
173
'Z8,...,01 Microcomputer Unit LH0801
receiver/transmitter operation. The bit rate is con·

Transmitted Oata (No Parity) trolled by Counter/Timer' 0, with a maximum rate
of 62.5K b~ts/second.
ISPjspl0710610sl04103102101100lSTI The Z8 ~utomatically 'adds a start bit and two
T I
Transmitted Oata (With Parity)
LSTART BIT
EIGHT OATA BITS
TWO STOP BITS
stop bits to transmitted data (Fig. 5). Odd parity ,is
also available as an option.
'(4) Counter/Timer
The Z8 contains two 8-bit programmable coun-
ISplSpl P 106105104103102101lDoiSTI ter/timers (To and T I ), each driven by its own 6-bit
TI
programmable prescaler. The T I' prescaler can be
I LSTART BIT
SEVEN DATA BITS
driven by internal or external clock sources;
OOD PARITY however, the To prescaler is driven by the internal
I TWO STOP BITS clock bnly.
The counters can be start{!d, stopped, restarted
Received Oata (No Parity) to continue, or restarted from the initial value. The
IspI0710610sI0,10,,10210110oISTI counters can also be programmed to stop upon
reaching zero (single-pass mode) or to automaticaily
I ,
L.START BIT
EIGHT OATA BITS
reload the initial value and continue counting (mod-
I ONE STOP BIT ulo-n continuos mode). The counters, but not the
prescalers, can be read any time without disturbing
Received Oata (With Parity)
their value or count mode.
ISpl pI0610sI0,10,,102101100ISTI
(5) Interrupts
I L.START BIT
SEVEN OAT A BITS The Z8 allows six different interrupts from eight
II PARITY ERROR FLAG
ONE STOP BIT sources: the four Port 3 lines P3 0 -P3 3, Serial In,
Serial Out, and the two counter/timers. These in-
Fig. 5 Serial data formats terrupts are both maskable and prioritized.
All Z8 interrupts are vectored. Polled interrupt
systems ,are also supported.
~-------'---SHARP~~-------.-Ir~
174
Z8-01 Microcomputer Unit LH080t
• Instruction Set Notation FLAGS Flag register (control register 252)

RP Register pointer (control register 253)
(1) Addressing modes IMR Interrupt mask register (control register
The following notation is used to describe the 251)
addressing modes and instruction operations as Assignment of a value is indicated by the symbol
"+-". For example.
shown in the instr~ction summary.
dst +- dst + src
IRR Indirect register pair or indirect indicates that the source data is added to the des-
working-register pair address tination data and the result is stored in the destina-
Irr Indirect working-register pair only tion location. The notation "addr (n)" is used to re-
X Indexed address fer to bit "n° of a given location. For example,
DA Direct address dst (7) refers to bit 7 of the destination operand.
RA Relative address (3) Flags.
1M Immediate Control Register R252 contains the following six
R Register or working-register address flalSs :
r Working-register address only C Carry flag
IR Indirect-register or indirect working-re- Z Zero flag
gister address ·S Sign flag
Ir Indirect working-register address only V Overflow flag
RR Register pair or working register pair D Decimal-adjust flag
address H Half-carry flag
(2) Symbols Affected flags are indicated by :
The following symbols are used in describing the o Cleared to zero
instruction set. 1 Set to one
dst
src
Destination location or contents
Source location or contents
* Set or cleared according to operation
Unaffected
cc Condition code (see list) X Undefined
@ Indirect address prefix (4) Condition codes
SP Stack pointer (control registers 254-255) See Table 1.
PC Program counter
Table 1 Condition codes

Value Mnemonic Meaning Flags set
1000 Always true ......
0111 C Carry C=l
1111 NC No carry C=O
0110 Z Zero Z=l
1110 NZ Not Zero Z=O
1101 PL Plus S=O
0101 MI Minus S=l
0100 OV Overflow V=l
1100 NOV No overflow V=O
0110 EQ Equal Z=l
1110 NE Not equal Z=O
1001 GE Greater than or equal (S XOR V) =0
0001 LT Less than (S XOR V) =1
1010 GT Greater than (Z OR (S XOR V)) =0
0010 LE Less than or equal (Z OR (S XOR V)) =1
1111 UGE Unsigned greater than or equal C=O
0111 ULT Unsigned less than C=l
1011 UGT Unsigned greater than (C=O AND Z=O) = 1
0011 ULE Unsigned less than or equal (C OR Z) =1
0000 Never true ......
-------------------SHARP - - - - - - - - - - - - - - - - -
175
Z8-01 ~icrocomputer Unit LH0801
(5) Opcodemap
Lower Nibble (Hex)

o 2 3 4 5 6 7 8 9 A B C o E F
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.5 6.5 12/10.5 12110.0 6.5 12/10.0 6.5
o DEC DEC ADD ADD ADD ADD ADD ADO LD LD DJNZ JR LD JP INC
R, JR, rio rz rio Ir2 Hz. RI 1H z• RI HI.IM lR),IM rJ. Hz rz. RI rt. RA ce, RA rJ, 1M ce, DA r,
~
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5
RLC RLC ADC ADC ADC ADC ADC ADC
R, JR, rl. rz r]. Ir:! Hz, RI ~ IR z• RI RhlM rRJ.IM
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5
r------
2 INC INC SUB SUB SUB SUB SUB SUB
R, JR, rl. r2 rio Irz H2. HI IR 2 • RI R],IM IR],IM
B.O 6.1 6.5 6.5 10.5 10.5 10.5 10.5 r------
3 JP SRP SBC SBC SBC SBC SBC SBC
lRRI JM ri. rz rl. Ir 2 R:h HI IR2.RJ R],IM IRlolM
~
B.5 B.5 6.5 6.5 10.5 10.5 10.5 10.5
4 DA DA OR OR OR OR OR OR
R, JR, rl. rz rJ, Irz Hz, H, 1H z, HI R 1 ,IM IRIoIM
~
10.5 10.5 6.5 6.5 10.5 10.5 10.5 10.5
5 POP POP AND AND AND AND AND AND
R, JR, rl. rz rl.Irz Hz. RI IRz• RI R!,IM IRIoIM
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 r------
6 COM COM TCM TCM TCM TCM TCM TCM
)( R, JR, r., rz rl.Irz Hz. RI IRhR\ HI.IM IR!.IM
CI) ~
e. CI)
7
10/12.1 12/14.1
PUSH PUSH TM
6.5 6.5
TM
10.5
TM
10.5
TM
10.5
TM
10.5
TM
H,' JR, rl. rz r], Irz Hz. RI IH20 Rl H],IM IR1.IM
:0
.0 10.5 10.5 12.0 18.0 r--;;:,-
Z 8 DEC""' DEC""' LDE LDEI 01
Oi HH, JR, rt.Irrz Irl.IrfL
0.
0. 6.5 6.5 12.0 18.0 r----;u-
::J RL RL LDE LDEI
9 EI
R, JR, fz,Irf, Ir2.lrr]
10,5 10.5 6.5 6.5 10.5 10.5 10.5 lO~5 ~
A INCW INCW CP CP CP CP CP CP RET
RR, JR, r l . f2 flo Ir2 R z• R t lRz• RI R"IM lRhIM
6.5 6.5 6.5 6.5 10.5 10.5 10.5 ]0.5 r----w:o
B CLR CLR XOR XOR XOR XOR XOR XOR IRET
R, JR, 1'10 1'2 rlt Ir2 R2• R\ IR 2 • RI R"IM IR"IM
6.5 6.5
RRC RRC LDC LOCI
12.0 18.0 10.5 r---s:s-
C LD RCF
R, JR, 1'1, Irrz Ir I. Irr2 rio x. R~
6.5 6.5
SRA SRA LDC LOCI
12.0 18.0 20.0 20.0
CALL
10.5
LD
r---s:s-
D CALL' SCF
R, IRI r~. 11'1'1 Ir2.lrr, IRRI DA rlo x, RJ
6.5 6.5 6.5 10.5 10.5 10.5 10.5 ~
E RR RR LD LD LD LD LD CCF
R, JR, 1'1.11'2 R 2 • Rl IR z, RJ RItIM lRloIM
8.5 8.5 6.5 10.5 ~
F SWAP SWAP LD LD NOP
R, JR, 11'\, r2 Rz.IR I
-=--------------------''---------~-------,--~~------------~-------------------~
Bytes per Instruction 3 2 3
Lower Opcode
Nibble Legend:
R =8~Bit Address
Execution
Cycles
t Pipeline Cycles
r = 4 ~ Bit Address
R 1 or rJ = Dst Address
R2 or n = Src Address
Sequence:
Upper Opcode Opcode, First Operand, Second Operand
Nibble - A ~--- Mnemonic
Note: The blank areas are not defined.
First Operand Second Operand
176
(6) Instruction Summary Instruction I Addr Mode Opcode Byte Flags Affected
Instruction I Addr Mode 'Opcode Byte Flags Affected and OperationJ dst src (Hex) CZSVDH
and Operation I dst src (Hex) CZSVDH LDEI dst,src Ir Irr 83 ------
ADC dst,src (Note 1) 10 ****0* dst<-src Irr It 93
dst<-dst + src + C r<-r + 1; rr<-rr + 1
ADD dst,src (Note 1) 00 ****0* Nap FF ------
dst <-dst + src
ANDdst,src (Note 1) 50 -**0-- OR dst,src (Note 1) 40 -**0--
dst<-dst AND src dst<-dst OR src
CALL dst DA D6 ------ POP dst R 50 ------
SP<-SP-2 IRR D4 dst<-@SP IR 51
@SP<-PC;PC<-dst SP<-SP+ 1
CCF EF * - - - - - PUSH src R - - - - - -
C<-NOTC 70
SP<-SP - 1; @SP<-src IR 71
CLR dst R BO - - - - - -
dst<- 0 IR Bl RCF CF o- - - - -
o- - C<-O
COM dst R 60 -**
. dst<-NOT dst IR 61 RET AF - - - - -
CP dst,src (Note 1) AD ****-- PC @SP;SP<-SP+ 2
dst<-src RLdst ~ R 90 ****--
DA dst R 40 ***X- - C 7 0 IR 91
dst<-DA dst IR 41
RLCdst~R 10 ****
DEC dst R 00 -***- - C 7 0 IR 11
dst<-dst-l IR 01
DECW dst RR 80 -***-- RR dst 4il L[ii)J IRR
C 7 0
EO
E1
****
dst<-dst-l IR 81
DI 8F - - - - - - RRC dst I@:[ii}J
C 7 0
R
IR
CO ****
IMR(7)<-0 Cl
DJNZ r,dst RA rA - - - - - - SBC dst,src (Note 1) 3D ****1*
r<-r-l r=O-F dst<-dst - src - C
if r o PC<-PC + dst
Range: +127,-128 SCF DF 1-----
EI ------ C<-l
9F
IMR(7) <-1 SRA dst R DO ***0--
INC dst r rE -***-- 4£lCil?f--l IR D1
dst<-dst+l r=O-F SRP src 1M 31 ------
R 20 RP<-src
IR 21
INCW dst RR AO -***-- SUB dst,src (Note 1) 20 ****1*
dst<-dst+ 1 IR Al dst <-dst - src
IRET BF ****** SWAPdst ~
7 4 3 0
R FO X**X--
FLAGS<-@SP; SP<-SP + 1 IR Fl
PC<-@SP;SP<-SP+2;IMR(7)<-1
TCM dst,src (Note 1) 60 -**0--
JP cc,dst DA cD ------
(NOT dst) AND src
if cc is true c=O-F
PC<-dst IRR 30 TM dst,src (Note 1) 70 -**0--
JR cC,dst RA cB ------ dst AND src
if cc is true, c=O-F XOR dst,src (Note 1) BO -**0--
PC <-PC + dst dst<-dst XOR src
Range: +127,-128
LD dst,src r 1M rC ------ Note 1 These instructions have an identical set of addressing
dst<-src r R r8 modes, which are encoded for brevity. The first opcode nibble is
R r r9 found in the instruction set table above. The second nibble is ex·
r=O-F pressed symbolically by a 0 in this table, and its value is found
r X C7
X r D7 in the following table to the left of the applicable addressing mode
r Ir E3 pair.
Ir r F3 For example, to determine the opcode of an ADe instruction use
R R E4 the addressing modes r (destination) and Ir (source). The result is
R IR E5 13
R 1M E6
IR 1M E7
IR R F5
LDC dst,src r Irr C2 ------ Addr Mode
dst<-src Irr r D2 Lower
src Opcode Nibble
LDCI dst,src Ir Irr C3 ------ dst
dst<-src Irr Ir D3
i
r<-r + l;rr<-rr + 1 r
------
r Ir
LDE dst,src r Irr 82 R R
dst<-src Irr r 92 R IR
R 1M
IR 1M
-----------SHARP--------..-,
177
Z8~01 Microcomputer Unit LH0801
• Register
R240 (510) R244 (TO)

Serial I/O R:egister Counter/Timer 0 Register
(FOH: Read/Write) (F4H: Read/Write)
-,
I~I~I~I~I~I~I~I~I ID71 Dsl Dsl D.I D31 D2 rDll Do I

[SERIAL DATA (Do=LSB) LTD INITIAL VALUE
(WHEN WRITTEN)
(RANGE: 1-256 DECIMAL
01-00 HEX)
To CURRENT VALUE
(WHEN READ)
R241 (TMR) R245 (PREO)

Timer Mode Register Prescaler 0 Register
(F5H: Write Only)
II
(FlH : Read/Write)
ID71 D61 Dsl D,I D31D21 DII Do' ID71 D61 Dsl D" D31 D21 DII Do'
TOUT M~g:~~oo
To OUT=OI
LO=NO FUNCTION
I=LOAD To
LLCOUNT MODE
O=To SINGLE-PASS
Tl OUT = 10 O=DIS. ABLE To COUNT 1 = To MODULO-N
INTERNAL CLOCK OUT =11, I=ENABLE To COUNT RESERVED
T IN MODES O=NO FUNCTION '
EXTERNAL =00 I=LOAD Tl
CLOCK INPUT PRES CALER MODULO
GA TE INPUT = 01 O=DISABLE Tl COUNT (RANGE: 1-64 DECIMAL
TRIGGER INPUT = 10 I=ENABLE Tl COUNT , 01-00 HEX)
(NON-RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
R246 (P2M)
Port 2 Mode Register
R242 (T1)
Counter Timer 1 Register (F6H: Write Only)
(F2H: Read/Write)
I~I~I~!~!~I~I~I~I
I D11 D6! Dsl D.I D31 D21 Dl ! Do I
LTI INiTIAL VALUE Lp 20- P 27 I/O DEFINITION
(WHEN WRITTEN) o DEFINES BIT AS OUTPUT
(RANGE 1-256 DECIMAL 01-00 HEX) 1 DEFINES BIT AS INPUT
TI CURRENT VALUE
(WHEN READ)
R247 (P3M)
R243 (PRE1) Port 3 Mode Register
Prescaler 1 Register (F7H: Write Only)
1LL dDo]
(F3H: Write Only)
ID11D61 DsID.ID31 D21 D
ID1 ! D61 Dsl D.I D31 D21 Dd Do' L 0 PORT 2 PULL-UPS OPEN DRAIN
1 PORT 2 PULL-UPS ACTIVE
I RESERVED
o P32=INPUT P3s=OUTPUT
COUNT MODE
O=TI SINGLE-PASS 1 P32=DAV1i/RDYO P3s=,RDYO/DAVO
I=Tl MODULO-N 00 P 33 = INPUT P 3. = OUTPUT
CLOCK SOURCE ~np33=INPUT P3.=DM
1 = Tl INTERNAL 11 P33=DAVl/RDYl P3.=RDYI/DAVI
O=Tl EXTERNAL TIMING INPUT o P31 = INPUT (TIN) P3s=OUTPUT (TouT)
(TIN) MODE I P31 =DAV2/RDY2 P3s=RDY2/D AV2
o P 30 = INPUT P 31 = OUTPUT .
PRESCALER MODULO 1 P30=SERIAL IN P37 = SERIAL OUT
(RANGE: 1-64 DECIMAL o PARITY OFF
01-00 HEX) 1 PARITY ON
178
...........................................................................................................
, '
R248 (P01M) R252 (FLAGS)

Port 0 and 1 Mode Register Flag Register
J
(F8u: Write Only) (Feu: Read/Write)
I D7! Ds! Ds! D.! Da! D2! DI! Do! I~I~I~I~I~!~I~!~I

~
PO.-P07 MODE
OUTPUT =00
INPUT = 01 .
A12- Als = IX
EXTERNAL MEMORY
C'POO-P03
LOO=OUTPUT
01=INPUT
MODE
IX = Aa- All
STACK SELECTION
0 = EXTERNAL
Llll &SER FLAG Fl
USER FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
TIMING 1 =INTERNAL OVERFLOW FLAG
NORMAL=O Plo-Ph MODE
EXTENDED = 1 00 = BYTE OUTPUT SIGN FLAG
01 = BYTE INPUT ZERO FLAG
10=ADo-AD7
11 = HIGH· IMPEDANCE ADo- AD7, CARRY FLAG
AS,DS, R/W,Aa-All,AwAls
IF SELECTED
R249 (lPRl R253 (RP)

Interrupt Priority Register Register Pointer
(F9u: Write Only) (FDu: Read/Write)
I D71 Dsl Dsl D.I D31 D21 DI I Dol
RESERVE~ !
A)
INTERRUPT GROUP
PRIORITY
r7~1~
rs~
I ~LLDON'T CARE
IRQ3,IRQ5 PRIORITY ( GROUP RESERVED =000 DON'T CARE
0= IRQ 5> IRQ 3 '---+--+-- rs DON'T CARE
1=IRQ3>IRQ5 C > A > B=OOI
IRQO, IRQ2 PRIORITY (GROUP B) A > B > C =010 r4 DON'T CARE
0=IRQ2>IRQO A > C > B=Ol1 REGISTER POINTER
1 =IRQO>IRQ2 B > C > A = 100
IRQl,IRQ4 PRIORITY (GROUP C) C > B > A=10l
O=IRQl>IRQ4 B > A > C=110
I=IRQ4>IRQl RESERVED=lll
R250 (IRQ) R254 (SPH)

Interrupt Request Register Stack Pointer
(F Au: Read/Write) (FEu: Read/Write)
1
. I~!~I~I~I~I~I~I~I
IRQO=P32 INPUT
IRQ 1 = P 33 INPUT
IRQ 2 = P 31 INPUT [STACK POINTER UPPER
IRQ3=P3o INPUT, SERIAL INPUT BYTE (SPa-SPIs)
IRQ4=To, SERIAL OUTPUT
IRQ5=TI
RESERVED
R251 (lMR) R255 (SPL)

Interrupt Mask Register Stack Pointer
(FBu: Read/Write) (FFH : Read/Write)
l[
.ID7IDsIDs!D.IDaID21 DIIDol
RESERVED
[1 ENABLES IRQO-IRQ5
(Do=IRQO)
1 ENABLES INTERRUPTS
I D71 Dsl Dsl D.I D3\ D21 DII Do I
[STACK POINTER LOWER
BYTE (SPO-SP7)
- - - - - - - - ' - - - - - - - S H A R P ----~.-.-.-..-.-.--
179
Z8-02 Development Device 'LH0802
LH0802 ,Z8-02 Development Devic;:e, ' _

• Description' • Pin Connections
Th~ 64:-pin Z&,..02 is the development version of
the Z8-01 with internal mask-programmed ROM.
This device allows the user to build the prototype
systems in hardware with an actual device and to
deveiop the code that is eventually mask-prog-
P30 P2,
rammed into the on-chip ROM of the Z8-0l. RESET 6
TheZ8-02 is identical to the Z8-01 with the IVW P2,
following exceptions : P2,
• The internal ROM has been removed. P21
• The ROM address lines and data lines are buff- P20
ered and brought out to external pins. P3,
P3,
• Control lines for the new memory have been
added.
Pis
PI,
PI,
PO, PI,
PQ. Pit
PO,
lACK 21 In
SYNC Do
In
·Ao
Al
Ao
A,
An A.
AlO A,
A,
Top View
- . . . . - . - - - - - . - . - - S H A R P ~...-...-.~-- .......... - - - - - - - - -
'180
Z8-02 Development Device LH0802
• Block Diagram
., ."
., .,Q
!~
. . iii
.~
....
System .... ~ rJl .,
In
Serial and Parallel
1/0 and Control Clock ~ .. ~
. In
A
Vee( +5V) GND(OV) ~~~A « """"
17 2 3 6 7 8 9
Port 3
Instruction Control
....
ALU
..."""
UART Flags
0
.,.'"
In
:g
«
....
[!
Register Pointer .,"E
::e
Counter/Timer
Register Fil e
(I24X8)
Program 'Counter
....."
E
Po.
...
Interrupt
Acknowledge 21 Interrupt Control
!
Output -:;;"
A
..".."
E
Po.
Port 0 Port 1
'-----yr---~ ' - - - - vr -----

I/O or As-A,s I/O or AD o -AD 7
* 1 Program Memory Data Strobe Output
* 2 System Clock Output
* 3 Instruction Sync Output
• Pin Description
The Z8-20 has 64 pins, 40 of which are the
same as those on the Z8-01. The remaining 24
pins are as follows.
Pin Meaning 110 Function
Ao-A l l Address Bus 0 Address signal for internal ROM.
Do-D 7 Data Bus I Data signal for internal ROM.
MDS Data Strobe 0 Active "Low". Internal ROM addresses are valid.
lACK Interrupt Acknowledge 0 Active "High". Detects an interrupt.
-- Active "Low". For synchronizing the command
SYNC Command Synchronization 0
fetch cycle.
SCLK System Clock 0 Internlll system clock. 1/2 of the external clock.
181
?8-03 Protopack Emulator LH0803
LH0803 Z8-03 Protopack Emulator

The 28-03 (LH0803) is a ROMless version of
the standard 28-01, housed in a pin compatible
P36
40-pin package.
XTAL2 2 P31
The 28-03 carries a 24-pin socket for a direct
XTALl 3 P27
interface to program memory. 2716 type EPROM
can be used for program memory. P26
The 28-03 allows the user to build the pro- P25
totype and pilot production units. When the final RESET 6 P24
program is established, the user can then switch R!W 7 P23
over to the 28-01. P22
P21
P35 P20
P33
P34
Ph
Pl6
PIs
Pl4
Pb
Pl2
PIt
Plo
Top View
.-..-.------SHARP---.-------
182
Z8-03 Protopack Emulator LH0803
• Block Diagram
S erial and Parallel System t

I/O and ~ontrol Clock :l
GND(OV) ~p:;
r------{ll}----{
Port 3
ALU
Instruction Control
...e-"
~
0 "
UART Flags ....
Ul
Ul
""
«""
...>.
Registe~ Pointer .'"
E
::?l
Counter ITimer
Register File
(124XS)
E
......
...'"
Program Counter 0..
;;
Interrupt .=i""
Acknowledge
Output
Interrupt Control
Q
!.
....
.....'"
E
0..
I/O or ADo - AD?

*1 Program Memory Data Strobe Output
*2 System Clock Output
* 3 Instruction Sync Out put
o : This is equipped with ROM
• Pin Description
The pins of the 28-03 are compatible with those
of the 28-01. For the pin description, refer back'
to the 28-01 explanation.
183
Z8::J 1 MicrOComputer Unit LH0811·
LH0811 Z8-11 Microcomputer Unit

Compared to earlier single-chip microcomputers,
the Z8 offers faster execution; more efficient use of
P36
memory; more sophisticated interrupt, input/out-
put and bit-manipulation c~pabilities ; and easier XTAL2 2 o P3l
system expansion. XTALl 3 P27
Under program control, the Z8can be tailored to P26
the needs of user. It can be configured as a stand- P2s
alone microcomp·uter with 4K bytes of internal RESET 6 P2.
ROM, a traditional microprocessor that manages up R/W 7 P23
to 120K bytes of external memory, or a parallel-
P22
processing element in a system with other proces-
P2l
sors and peripheral controllers linked by the
Z-BUS. In all configurations, a large number of P3s P20
pins remain available for I/O. GND 11 P33
P32 P3.
POo Ph
POI P16
P02 PIs
• Features PI,
P03
1. Complete single-chip microcomputer with in- PO. Pis
ternal ROM, RAM and 110 POs Ph
• RAM 124 bytes P0 6 Pll
• ROM 4K bytes
P07 Plo
• 110 32 lines Top View
2. On-chip two programmable 8-bit counter/tim-
ers, each with a 6-bit programmable prescaler
3. Full-duplex UART
4. 144-byte register file
5. Register pointer so that short, fast instructions
can access any working register groups
6. Vectored, priority interrupts for 110, counter/
timers, and UART
7. Up to 60K bytes addressable external space
each for program and data memory
8. On-chip oscillator
9. High speed instruction execution
• Working register operating time: 1.5 ps
• Average instruction execution time: 2.2 ps
• Maximum instruction execution time: 5.0 ps
10. Low-power standby option which retains con-
tents of general-purpose registers
12. All pins are TTL compatible
~-""""'-------SHARP---'----'-'
184
• Block Diagram
"0 ~
"0 cil....
!
0;::
~
!::
i:: ''""
System ~ -,
(fJ
Serial and Parallel
"'oS" ! "'"...."
, ~-~ " Q" ..:
I 0 and Control ."
Vee( +5V) GND(OV) ~
11

&
Instruction Control
ALU
Flags
UART
Program Memory
(4,096X 8)
Register Pointer
Counter Ti mer

(124XS)
Interrupt Control
T T
I/O or As-A15 I/O or ADo- AD7
• Pin Description
The pins of the 28-11 are compatible with those
of the 28-01. For the pin description, refer back
to the 28-01 explanation.
----~-.--~......---SHARP.-.----.-.---
185
Z8...,1,2 Development Device LH0812
LH08·12 Z8-12 Development Device

The 64-pin 28-12 is the development version of
the 28-11 with internal mask-programl\led ROM.
This device allows the user to build the prototype
systems in hardware with an actual device and to
develop the code that is eventually mask-program-
med into the on-chip ROM of the 28-11.
The 28-12 is identical to the 28-11 with the
following exceptions :
• The internal ROM has been removed.
• The ROM address lines and data lines are buff-
ered and brought out to external pins_
added.
Top View
~~'--~'---SHARP---'-~-'-~"""'"
186
Z8-12 Development Device LH0812
• Block Diagram
"0
~
...
!: "0 Ul
~
"'; ...
System
~ Ul ''""
Serial and Parallel
Clock
~ "--
"'" -0os !os "...
-0
I/O an1 Control -0
Vcc(+5V) GND(OV) ~ 0::: " 0:::" 0 ...::
Port 3
Instruction Control
~
ALU "
2-
~
0"
'"
UART Flags
"...'"
-0
-0
«:
»
...
0
S
Register Pointer
"
;;;:
S
Counter Timer
Register File
'"...
bJl
1124X81 ...0
p..
Program Counter
0;
Q.
Interrupt ..:;
Acknowledge 11 Interrupt Control !
O~tput
0'"
S
...'"
OJ)
...0
p..
Port 2 Port a Port 1
I/O or ADo-AD,
--------SHARP--------
187
..........-..
,
Z8~12 Development Device
-----..,.~ ....
. - . - . -........-~--:.--.: ...... -....
LH08t2
• Pin Description
The 28-12 has 64 pins, 40 of which are the
same as those on the 28-11. The remaining 24
Ao-A l l Address Bus· 0 Address signal for internal ROM
Do -D 7 Data,Bus I Data signal for inter.nal ROM.
MDS Data Strobe 0 Active "Low". Internal ROM addresses are valid.
lACK Interrupt Acknowledge 0 Active "High". Detects an interrupt.
-- Active "Low". For synchronizing the command
SYNC Command Synchronization 0
fetch cycle.
SCLK System Clock 0 Internal system clock. 112 of the external clock.
188
Z8-13 Protopack Emulator LH0813
LH0813 Za-I3 Protopack Emulator

The 28-13 (LH0813) is a ROMless version of
the standard 28-11, housed in a pin compatible P36
40-pin package. o P31
The 28-13 carries a 24-pin socket for a direct
P2,
. interface to program memory. 2732 type EPROM
can be used for program memory. P26
The 28 -13 allows the user to build the pro- P25
totype and pilot production units. When the final RESET 6 P2.
program is established, the user can then switch
over to the 28-11.
P23
P22
P21
a
P3s
P32 P3.
POo Ph
POI P16
POz P1s
POs Pl.
P13
P12
Ph
P07
Top View
"
189
ZS",'13 Protopack Emulator LH0813
• Block Diagram
Serial and Parallel System t

I/O and Control Clock :l
" Vee( +5V) GND(OV) ~c::
,}-----~ }-------~111}_----~
Port 3
Instruction Control
1
:;
o
<Il
<Il
UART Flags ...
:g'"
..:
Register Pointer
Counter Timer
Register File
(124X8 )
Program Counter
Interrupt
1
..:;
Acknowledge
O~tput
Interrupt Contro}
Q
..
!
......e
o
...
Il-.
I/O or ADo - AD7

• Pin Description
The pins ofthe Z8-13 are compatible with those
of the Z8-11 and Z8-01 as well. For the p~n de-
scription, refer back to the Z8-01 explanation.
--....--.-~....----SHARP -----------....-,
190
LH0881 Z8-81 Microcomputer Unit

• Description
LH0881 is the ROMless version of the LH08011
• Pin Connections
LH0811(Z8) single-chip microcomputer and offer P36

the outstanding feature of the Z8 Family archi- 0 P3l
tecture. Port 1 is configured to function as multi·
P2,
plexed Address/Data bus (ADo - AD 7 ), while Port 0
is software configurable to output address bus (As P26
- A15). Therefore, this device is capable of P25
addressing up to 128K bytes of the external memo RESET 6 P24
~
ory space. Using the external memory instead of P2,
the internal memory, it is possible to design more DS P2 2
powerful microcomputer system incorporating a
AS P2l
minimum number of support devices.
P35 P2 0
GND P3,
P32 P34
• Features POo Ph
POI 1'16
1. Complete microcomputer, 24 lIO lines, and up
to 64K bytes addressable external space each PO, PIs
for program and data memory. PO, 1'14
2. 143 bytes register file, including 124 general· P04 1'13
purpose registers, three lIO port registers, and POs 1'12
16 status and control registers.
P06 Ph
3. Register pointer so that short, fast instructions
P07 1'10
can access anyone of the nine working-register
groups. Top View
4. Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit pro·
grammable prescaler.
5. Vectored priority interrupts for lIO, counter/
timers, and UART.
191
• Block Diagram
"''""
.i.:
! '"
-.: "'t" en
0
:;;: (/J '"'"

Serial and Parallel System ~ .......
I/O and Control Clock ~ oj ~oj"'" '...."
"0
A
Vee GND ~~ '"
0:: Q. "'"
«:
11 3 6

&
Instruction Control
ALU
Flags
UART
Register Pointer
Counter/Timer

(124XS)
Interrupt Control
y
I/O or As - A15 ADo'::'AD7
• Pin Description
The pins of the 28-81 have the same functions
as those of the Z8-01 and 28-11, except pins P1 0
to P1 7 •
Address/Data bus 110 Multiplexed address/data bus.
---':-'-~-------SHARP,------~-'--""
192
• Address space port registers (RO, R2, R3), 124 general-purpose

registers (R4-RI27) and 16 control and status reg-
(1) Program Memory isters (R240-R255).
The Z8-81, having a 16-bit program counter, These registers are assigned the address loca-
addresses 64K-bytes of external program memory. tions shown in Fig. 2.
All the command codes are fetched from these ex- Z8-81 instructions can access registers directly
ternal program memories. or indirectly with an 8-bit address field. This also
For the Z8-81, the first 12 bytes of program allows short 4-bit register addressing using the
memory are reserved for the interrupt vectors. Register Pointer (one of the control registers). In
These locations contain six 16-bit vectors that cor- the 4-bit mode, the regiter file is divided into nine
respond to the six available interrupts. Program working register groups, each occupying 16 con-
execution begins at location OOOeH after a reset. tiguous locations. The Register Pointer addresses
the starting location of the active working-register
(2) Data Memory * group.
The Z8-81 can address 64K bytes of external
data memory. External data memory may be in- (4) Stacks
cluded with or separated from the external prog- Either the internal register file or the external
ram memory space. DM, an optional I/O function data memory can be used for the stack. A 16-bit
that can be programmed to appear on pin P3" is Stack Pointer (R254 and R255) is used for the ex-
used to distinguish between data and program ternal stack, which can reside anywhere in data
memory space. memory. An 8-bit Stack Pointer (R255) is used for
the interanl stack that resides within the 124
(3) Register File general-purpose registers (R4-RI27).
The 143-byte register file includes three I/O
LOCATION r-""""'~=-________""-----' IDENTIFIERS

255 SPL
254 SPH
253 RP
252 FLAGS
~1 IMR
~O IRO
249 IPR
248 PO,M
65535 247 P3M
246 P2M
245 PREO
244 TO
243 PRE1
LOCATION OF 242 T1
FIRST BYTEOF 241 TMR
INSTRUCT!ON~ 240 SIO
EXECUTED
AFTER RES ET 12 ~---------------- NOT
11 IRQ5 IMPLEMENTED
EXTERNAL 1271-----------1
10 IRQ5 MEMORY
9 IRQ4
8 IRQ4
7 IRQ3 GENERAL-PURPOSE
INTERRU PT 6 IRQ3 REGISTERS
VECTOR
5~ IRQ 2
(LOWERBYTE)
41»' IRQ2
3 IRQ1 41-____~~~------~
INTERRUPT 3 P3
VECTOR 2 IRQ1 2 P2
(UPPER BYTE) 1 IRQO
0 IRQO o1r-~~~~~~~~ PO
Fig. 1 Program memory map Fig. 2 The register file
193
\28-81 Mic!ocomputer Unit 'LH0881
• port Functions • Registers

The 28-81 has a dedicated memory interface The 28-81 control registers are the same as on
port (Port 1) and in,put/output ports (Port 0, 2, 3). the 28-01128-11, except two bits D3 and D. in the
These ports are' given eight lines each. The func- Port 0, 1 Mode Register (R24.8). ',
tions of Port 0, 2 and 3 are the same as t~ose of the
Z8-01111. • Serial Input/Output
Port 1 is a dedicated Z- bus compatible memory The 28-81 serial input/output functions are the
interface_ The operations of Port 1 are supported same as those of the 28-01/28-11. (Refer back to
by the Address Strobe (AS) and Data Strobe (DS) the 28-01 o.escription.)
lines, and by the'Reac!/Write (R/W) and Data Mem-
ory (DM) control lines_
• Counter/Timers
The low-order program and data memory add-
ress (Ao-A7) are output through Port 1 and are The 28-81 counter/timer functions are the same
multiplexed with data in/out (Do-D7). Instruction' as those of the 28-01128-11. (Refer back to the
fetch and data memory read/write operations are 28-01 description.)
done through this port.
Port 1 cannot be used as a register nor can a • Interrupts
handshake mode be used with this port. The 28-81 interrupt functions are the same as
If more than eight address lines are required with those of the 28-01128-11. (Refer back to the
the 28-81, additional lines can be obtained by 28-01 description.)
programming Port 0 bits as address bits. The least-
-significant four bits of Port 0 can be configured to • Instructions and AC/OC Characteristics
supply address bits A.-All for 4K byte addressing
These data of the 28-81 are the same as for the
or both nibbles of Port 0 can be configured to
28-01/28-11. (Refer back to the 28-01 descrip-
supply address. bits A.-AI5 for 64K byte addres-
tion.)
sing.
R248 (P01 M) Port 0, 1 Mode Register (F8H Write only)
I ])7 I DBI D51 D.I D31 D2 I DI I Do I

PO.-P07 MOD,E I ~OO-P03 MODE
OUTPUT=OO-.J L!.IOO=OUTPUT
INPUT = 01 01 = INPUT
lX=A5-All
EXTERNAL MEMORY TIMING STACK SELECTION

NORMAL =0-------' L----O=EXTERNAL
~ EXTENDED = 1
I=INTERNAL
L------RESERVED (MUST BE 0)
194
CMOS 8-Bit 1-Chip -Microcomputer -SM-803
5 M- 803 CMOS 8-Bit I-Chip Microcomputer

The SM-8D3 is the CMOS version of LHD811
(Z8). This device is configured as a stand-alone
microcomputer with 4K bytes of internal ROM,
128 bytes of RAM, up to 6DK bytes addressable XTAL2 2
external space each for program and data memory, XTALI 3
two programmable 8-bit counter/timers, and UART.
RESET 6
R/W 7
• Features
1. CMOS silicon-gate process technology
2. Complete microcomputer, 4K bytes of ROM,
128 bytes of RAM, 32 110 lines, and up to
6DK bytes addressable external space each for
program and data memory
3. 144-byte register file, including 124 general-
purpose registers, four 110 port registers, and
16 status and control registers
4. Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit pro-
grammable prescaler
5. Vectored priority interrupts for 110, counter /
timers, and UART
6. Average instruction execution time of 2.2 ps Top View
7. On-chip oscillator which accepts crystal or ex-
ternal clock drive
8. Power saving function (HALT/STOP instruc-
tion mode)
9. Low power consumption 12mA (TYP.)
ID~ Single +5V power supply
11. 4D-pin dual-in-line package (or 44-pin quad-
flat package)
....--------SHARP---------
195
CMOS8-Bit 1-Chip Microcomputer SM-803
• Block Diagram
Serial and Parallel

I/O and Control
Vee( f5V) GND(OV)
Machjne Timing
&
Instruction Control
ALU
Flags
UART
Program Memory
( 2,048X8)
Register Pointer
Counter ITimer
Register File
Program Counter
(l24X8)
• Interrupt Control
Port 0 Port 1
~-------v~--------
I/O I/O or As-Als I/O or ADo-AD7
• Pin Description !
Pin Meaning lIO Function

PO O -P0 7 Port 0 lIO 8-bit lIO port, programmable for lIO.
Pl o-P1 7 Port I lIO Programmable for lIO in bytes.
P2 o-P2 7 Port 2 lIO Programmable' for lIO in bits.
P3 0 -P3 7 Port 3 lIO P3 0 -P3 3 for input, P3 4 -P3 7 for output.
- Active "Low", activated for external address memory
AS Address strobe 0
transfer.
-' Active "Low"" activated for external data memory
DS Data strobe 0
transfer.
R/W Read/Write 0 Read at "High", write at "Low".
RESET Reset I Active "Low". initializes.
XTALl Clock I I Clock pin.
XTAL2 Clock 2 0 Clock pin.
196
CMOS 8-Bit 1-Ch~p Microcomputer SM-803

, Parameter Symbol Ratings Unit
. Output voltage VOUT -0.3-+7 V
Operating temperature Toor 0-+70 "C
Storage temperature T sto -65-+150 "C
• DC Characteristics (Vee=5V±10%, Ta=0-+70"C)

oscillator
Clock input low voltage VeL -0.3 0.8 V
oscillator
Input high voltage VIH 2.0 Vee V
Reset input low voltage VRL -0.3 0.8 V
Output high voltage VOH IoH = -250,u A 2.4 V
Output low voltage VOL IOL=+2.0mA 0.4 V
Input leakage cuurrent I IlL I OV";:V IN ";:+5.25V 10 ,uA
Output leakage current 11m I OV";:V IN ";:+5.25V 10 ,uA
Reset input current IIR Vee=5.25V, VRL=OV -50 ,uA
Vee Vee
Vee
2.1k!l
Output pin 1.5k!l
under test
: > O - -.....-L;;>O-~---Crystal 2
74LS04 ;;;CI.=15 p FMAX.
'----~-- Crystal 1
ICI.=15 PF MAX.
Test load 1 TTL, external clock interface circuit
• AC Characteri~tics So there is no power consumption now. This mode

The SM-803 is compatible with the 28-01 as to is cleared by a reset input, port 3 input, or timer
the AC characteristics. Refer back to the 28-01 interrupt at a mask option (designated at the time
of ROM input).
description.
(2) STOP mode·
• New Functions The STOP mode is brought by decoding a STOP
The SM-802 has two standby modes; HALT instruction (FF6FH).
and STOP.
(1 ) HALT mode
The HALT mode is introduced by decoding a
HALT instruction (FF7F H). In this mode, the
oscillation circuit is kept in operation, but no sys-
tem clock is internally supplied any more.
197
.~.-...., .........
CMo.S 8-Bit 1-Chip Microcomputer
~...,.-....,~, ........-:...,...,...,...,-.-
SM-812
SM-812 ,
CMOS 8-Bit I-Chip Microcomputer
.
The SM-812 is an 8-bit single chip CMOS micro·
€omputer with 2,048·byte of ROM, 128·byte of
RAM, timer/counter ,and multiplex interrupt capa·
bility.
It is best suited to high-function controllers due WAIT I
to its single power supply and high-speed proces· Ml 2
sing capability. P3./SI 3

P31/SCK '
P32!SO s
P33/MRQ '
P3./CN 7
P3s/T 8
P36/RD •
P37/WR IO
• Features NC 11
NC 12
1. CMOS process PO./AD. 13
2. ROM capacity 2,048 X 8 bits POJ/ADI U
3. RAM capacity 128 X 8 bits P02!AD2 15
4. 64-byte (MAX.) of address space P031 AD, I'

PO,I AD, 17
5. InstrudioJ?s 81 POsl ADs 18
6. Subroutine nesting using RAM area PO,I AD, 19

9. Timer/counter
8 bit counter 2'
8 bit prescaler 1 Top View
Serial 110 interrupt 1
Timer interrupts 2
Non-maskable interrupt 1
12. Standby mode (HALT mode, STOP mode)
14. Instruction cycle 1 ps(MIN.)
198
• Block Diagram
Output Ports and I/O Ports and

External Address Bus External Data Bus
-" ~
WAIT
Signal Input
Sync.
Clock Output
S ync... Reset
PC
j
9
IIlO Ports
'
Clock Output SP
RAM ROM
A F 192XB
B C 4096xB
D E
H L
11
49
IIO Ports
t--;;~~-+e--j Prescaler
P5
9
IOutput
Ports
Interrupt Input Interrupt Input Oscillator

(non - maskable)
Symbol description
ADR : Address latch TM : Ti'mer modular register
ALU : Arithmetic logic unit TAC, TCB: Timer counter
PC : Program counter IE : Interrupt enable F /F
SP : Stack pointer IME : Interrupt master enable F /F
F· : Flag register IFO-IF3 : Interrupt request register
A,B,C,D,E,H,L : General-purpose registers OSC : System clock oscillator
INC/DEC : Incrementer / decrementer PO-P5 : Port register
199
OMOS8-Bit 1-0hip Microcomputer SM-812
• Pin Description
Pin 110 Circtit Function
P4o~P47 110 Pull-up Programmable for 110 in bits
P2 o/DB o External memory data bus
Bidirectional Pull-up at input lIO in bytes
~P27/DB7 signal
POol ADo BXternal memory address
0 Output in bytes
~P17/AD15 signal
P3 0/S1 Oil Pull-up at input Serial data input
P3 1/SCK O/Bidirectional Pull-up at input Serial clock input/output
P3 2 /S0 0 Serial data output
P3 3 /MRQ 0 Memory request output
Output in bytes
P3 4 /CN Oil Pull -up at input Timer counter input
P3 5/T 0 Counter signal output
P3 6 /RD 0 Read signal output
P3 7 /WR 0 Write signal output
P50~P57 0 Pull-up Settablel resettable in bits
-- Used to prolong an access time for external memory
WAIT I Pull-up
or to clear the standby mode.
INT I Pull·-l!P Maskable interrupt request
NMI I Pull-up. Non·maskable interrupt request
RESET I Pull-up Auto clear
TEST I For testing (usually connected to GND)
'" OUT. Ml 0 Synchronization clock output
CK lo CK 2 For clock oscillator
VDD • GND Logic circ·uit power supply
----------SHARP...--.----------
200
. CMOS 8-Bit 1-Chip Microcomputer SM-813
5 M- 813 CMOS a-Bit I-Chip Microcomputer

The SM-813 is an 8-bit single chip CMOS micro-
computer with 4,096-byte of ROM, 192-byte of
RAM, timer/counter and multiplex interrupt capa-
bility.
It is best suited to high-function controllers WAIT 1
Ml '
due to its single power supply and high-speed pro- P30/SI 3
cessing capability. P3'/SCK ,
P3';SO s
P3,/MRQ •
P3,/CN '
P3s/T 8
P3. 9 43 Viln
P3,1O " P40
RD 11
• Features WR 12
" NC
40 P2,fDB,
1.
CMOS process POD/ADD 13 39 P2./DB.
PO,/AD, 14 38 P2s/DBs
2.
ROM capacity 4,096 X 8 bits PO,fAD, 15 37 P2,/DB,
3.
RAM capacity 192 X 8 bits P03/ AD, 16 36 P2,/DB,
PO,,/AD,17 35 P2,fDB,
4.
64K-byte (MAX.) of address space POs/ADs 18 34 P2,/DB,
5.
Instructions 81 PO./AD. 19 33 P20/DBo
6.
Subroutine nesting using RAM area
7.
9.
Timer/counters
8-bit counters 2
8-bit prescaler 1 Top View
Serial I/O interrupt 1
Timer interrupt 2
Non-maskable interrupt 1
14. Instruction cycle l!'-s (MIN.)
201
.CMOS8-Bit1-Chip Microcomputer SM ..813
___ ~_ .......... . . , . - :_ _ ~_~. _______r.-_.._ _ ~'-' •
• BlOck Diagram
Output Ports and I/O Ports and

External Address Bus External Data Bus
J. _ _ _ _ _ _""'
,------A------,
940
WAIT
Signal Input
Sync.
Clock Output
S ync. Reset 6
Clock Output
RAM ROM
192XB 4096xB
l
P5 ~ Output
I Ports
9 J

(non - maskable)
Symbol description
ADR : Address latch TM :. Timer modular register
ALU : Arithmetic logic unit TAC, TCB : Timer cou~ten
F : Flag register IF 0 - IF 3 : Interrupt request register
A,B,C,D,E,H,L : General-purpose regi sters OSC : Sy!!tem clock oscillator
INC/DEC : Incrementer/decrementer PO - P 5 : Port register
202
• Pin Description
Pin I/O Circtit Function
P4 o-P4 7 I/O Pull-up Programmable for I/O in bits
P2o/DBo- External memory data bus
I/O Pull-up at input I/O in bytes
P27/DB7 signal
POo/ADo External memory address
0 Output in bytes
-P1 7/AD 15 signal
P3 0 /SI 0/1 Pull-up at input Serial data input
P3 1 /SCK O/Bidirectional Pull-up at input Serial clock input/output
P3 2 /SO 0 Serial data output
P3 3 /MRQ 0 Memory output
Output in bytes
P3 4 /CN 0/1 Pull-up at input Timer counter input
P3 5 /T 0 Counter signal output
P3 s 0
P3 7 0
P5 0 -P5 7 0 Pull-up Settablelresettable in bits
.~
RD 0 Read signal for external memory
WR 0 Write signal for external memory
WAIT I Pull-up
INT I Pull-up Maskable interrupt request
NMI I Pull-up Non-maskable interrupt request
RESET I Pull-up Auto clear
"'OUT. Ml 0 Synchronization clock output
CK h CK 2 For clock oscillation
VDD• GND Logic circuit power supply
-..-..-.----------SHARP.....-..---------
203
OMOS 8-Bit 1-Chip Microcomputer .. LU8l0Vl
LU81 0 V1 CMOS a-Bit I-Chip Microcomputer

• Description • Pin Con.nections
LU810Vl, eliminating the internal ROM from
SM-812, is the ROM less version of SM-812 and it
uses Port 0 and Port 1 exclusively as the address
bus and Port 2 as the data bus. Other functions
are compatible with those of SM-812.
WAIT I
Ml 2
• Features
1. CMOS process
2. ROM capacity 128X 8 bits
3. 64K-byte (MAX.) of address space
4. Instructions 81
5. Subroutine nesting using ~AM area
7. Input/Output ports 8 bits " OBI
8. Timer 1counter 3:, DB.
8-bit counters 2
8- bit prescaler 1
Top View
Serial 1/0 interrupt 1
Timer interrupts 2
Non-maskable interrupt l '
13. Instruction cycle 1 ps(MIN.)
204.
CMOS 8-Bit 1-Chip Microcomputer LU810V1
• Block Diagram
Address Bus Data Bus

A ,--------A----,
WAIT
!
Signal Input
Sync.
Clock Output
Reset
P3 fIIO p,,,,
, Sync.
~
Clock Output U
~ RAM
l
Q
" 192x8
u'
2S
fIIO p""
49
GND
Test
Prescaler
P5
9
IO"'~'
Ports

(non -maskable)
Symbol description
ADR : Address latch TM : Timer modular register
ALU : Arithmetic logic unit TAC, TCB: Timer counter
F : Flag register IF 0 - IF 3 : Interrupt request' register
A, B, C, D, E, H, L : General-pupose registers OSC : System clock oscillator
INC/DEC : Incrementer / decrementer PO-' P5 : Port register
--.-..-..-..-r'-'-~SHARP ----------------
,205
---.-.-.-:---.....---
cMos 8-Bit 1-Chip Mjcrocomputer
.........
• Pin Description
..............,............ .---.. ~---~---
LU810V1
Pin 110 Circtit Functioq

P4 o-P4 7 110 Pull up Programmable for 1/0 in bits
External memory data bus
DB o-DB 7 1/0 Pull up at input I/O in bytes
signal
External,memoryaddress
AD o-AD 1s 0 Output in bytes
signal
, P3 0 /SI Oil "
Pull up at input Serial data input
P3 1 /SCK Oil Pull up at input Serial clock input! output
P3 z /S0 0 Serial data output
P3 3 /MRQ 0 / Memory request output
Output in bytes
P3 4 /CN Oil Pull up at input Timer counter input
-,
P3 s /T 0 Counter signal output
P3 6 /RD 0 Read signal output
P3 7 /WR 0 Write signal output
P5 0 -P5 7 0 Pull up Settablel resettable in bits
WAIT I Pull up
INT I Pull up Maskable interrupt request
NMI I Pull up Non-maskable interrupt request
1> OUT. Ml 0 Synchronization clock output
CK h CK z For -clock oscillation
VDD• GND Logic circuit power supply
- .
.....-.~~------SHARP~-~-------------
206
28 Series Ordering Information
.-..-..-...-,.-..-...-,.-...-,..-,..-,.-...-,---..-,.-.
Z8 Series Ordering Information

Below is discussed how to order the Z8 series list of ROM to see if the read-out data are correct.
products. With the ROM data media, we computer-aid·
Customers are requested to submit an EPROM or ed-design a ROM masking magnetic tape and make
paper tape as the ROM data media. The following up EPROM or paper tapes, and their list, in order
information should be attached in any form and to make sure the designed ROM data are correct.
any means. These materials are then checked up by the cus-
(1) ROM data media tomer for approval. If it is okay, we start masking
(2) Specific data (chip select, marking, and and make some technical evaluation samples (TS),
other information) which are delivered to the customer. When the
(3) Your company's name, your own name, and samples are accepted, the customer will send us a
stamp "TS Confirmation". By a mass-production order at
(4) Ordering date the moment or later, we will start producing the
When submitting the ROM drawings, two sets of product in large quantities.
ROM data media are also required together with a
Client SHARP
t----+---~Business dept .t--'--------,l>j Project dept.

' - - - - - -......
t----+---~fiB3.u~s~in~e;ss;dde~PrttJ.-----------,
Business dept.
L-...;..:.-----+---~Business dept..I------------jE---.J
Business dept.
Business dept.
....--------SHARP-------.-.
207
a-Bit Microprocessor
and Peripheral LSls
Z80/Z80A/Z80B Central Processing Unit LH0080/LH0080A/LH0080B
LH0080/LH0080A/LH0080B
ZSOIZSOAlZSOB Central Processing Unit
The Z80 product line is a complete set of micro-
computer components, development system~ and
support software. The Z80 microcomputer com-
ponent set includes all of the circuits necessary tp o
bUild high-performance microcomputer systems
with virtually no other logic and a minimum num·
ber of low cost standard memory elements.
The LH0080 Z80 CPU (Z80 CPU for short be-
low) i~ the third generation microprocessor im-
plemented using an N-channel silicon-gate process.
The Z80 CPU is designed for using the standard
memory components, higher system throughput and
more efficient memory utilization. In addition, the
output signals of the Z80 CPU is decoded to con-
trol peripherals. The Z80 CPU requires only
single + 5V DC power supply and single phase
clock, theref~re it is easy for the Z80 CPU to Im-
plement into a system.
The LH0080A Z80A and LH0080B Z80B CPU
are the high speed version which can operate at the
4MHz and 6MHz system clock, respectively.
Top View
• , Features
1. 8-bit parallel processing single-chip micro-
processor
2. N-'channel silicon-gate process
3. 158 instructions (The instruction of the 8080A
are included as a subset; 8080A software com-
patibility is maintained)
4. 22 registers
5. The capability of 3 modes maskable interrupt
and non-maskable interrupt
6. On-chip dynamic memory refresh counter
7. Instruction fetch cycle: 1.6ps(Z80), 1.0lPS
(Z80A), 0.67 ps(Z80B)
8. Single + 5V power supply and single phase
clock
9. All inputs and outputs fully TTL compatible
10. 40-pin dlial-in-line package
'--~~-----------SHARP -~---!.........-.---
210 "
Z80/Z80AlZ80B Central Processing Unit LH0080/LH0080A/LH0080B
• Block Diagram
System Data
,
Bus
Halt State
Memory Request
Input/Output Request Data Bus Interface
Read
Write
Bus Acknowledge
Machine Cyclel Instructionrr-_ _ _---'
Instruction
Refresh ALU
Decoder Register 1-,...------,
Interrupt Request
Non- Maskable Interrupt
Wait
Bus Request
Reset
Address Bus Interface
V~~ GND System

C+5V) COy) Clock System Address Bus
211
Z80/Z80A/Z80B Central Processing Unit LH0080/LHOO80A/LH0080B
• Pin Description
Pin Meaning liD Function
Ao-A 15 Address bus 3-state 0 System address bus
{3idirectional
. Do-D 7 Data bus System data bus
3-state
- ! Active "Low". Indicates that the current machine cycle
Ml Machin(t cycle one 0
is the OP .code fetch cycle of an instruction execution.
Active "Low''',- Indicates that the address bus holds a
MREQ Memory request 3-state 0 valid address for a memory read or memory wri~e op-
eration.
Active "Low". Indicates that the lower 8 bits of the
addres& bus holds a valid liD address' for an liD read
--
10RQ liD request 3-state 0 or write operation. Also generated concurrently with
-
Ml during an interrupt acknowledge cycle to indicate an
interrupt response.
- Active "Low". Indicates that the CPU wants to read data
RD Memory read 3-state 0
from memory or an liD device.
Active "L(')w". Indicates that the CPU data bus holds
-
WR Memory write 3-state 0- valid data to be stored at the addressed memory or liD
location.
Active "Low". Indicates that the lower 7 bits of the_sys-
-- tern address bus can be used as a refresh address to the
RFSH Refresh 0
system's dynamic memories. Tog~ther with MREQ at
"Low".
Active "Low". Indicates that a Halt instruction is being
-- executed. While halted, the CPU exe~utes NOPs to main-
HALT Halt state 0
tain memory refresh. The Halt state is cleared with RE-
- - -- --
SET, NMI, or INT (when allowed).
Active "Low". Indicates to the CPU that the addressed
-- memory or liD devices are not ready for a data transfer.
WAIT Wait I
The CPU continues to enter a wait state as long as this
signal is acti ve.
Active "Low". Generated by liD devices. The CPU hon-
-- Maskable interrupt
INT I ors a request at the end of the current instruction if the
request
interrupt enable flip-flop is enabled.
Active "Low". Has a higher priority than INT. Always
recognized at the end of the current instruction, inde-
-- Non-maskable
NMI I pendent of the status of the interrupt enable flip-flop.
interrupt request
Automatically forces the Z80 CPU to restart at location
0066H.
Active "Low". Resets the int~rrupt enable flip-flop, the
--- program counter interrupt vector register and the mem-
RESET Reset I
ory refresh register, and sets the interrupt status to
Mode 0, in order to initialize the CPU.
Active "Low". Has a higher priority than NMI. Always
--- recognized at the end of the current machine cycle. Acti-
BUSRQ Bus request I
vated to allow a bus 11)aster other than the CPU to con-
tro the system bus.
--- Active "Low". Indicates to the requesting device that the
BUSAK Bus acknowledge O.
external circuitry can control the system bus.
CLOCK System clock I Inputs+5V single-phase clock.
--.----~--SHARP'---.--..--~.-..-.--
\. I ' " •
212 -

Input voltage VIN -0.3-+7.0 V
Output voltage VOllT -0.3-+7.0 V
Operating temperature Topr ' 0-+70 "C
Storage temperature T,tg -65-+150 "C
Standard Test Conditions

The characteristics below apply for the follow-
ing standard test conditions, unless otherwise
noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.
All ac parameters assume a load capacitance of
100 pF. Add IOns delay for each 50. pF increase
in load up to a maximum of 200 pF for the data
bus and 100 pF for address and control lines.
• DC Characteristics (Vcc=5V±5%, Ta=0-+70"C)

Clock input low voltage VILC -0.3 0.45 V
Clock input high voltage V IHC Vcc- 0 .6 Vcc+ 0.3 V
Input low voltage V1L -0.3 0.8 V
Input high voltage VIH 2.0 Vcc V
Output low voltage VOL IOL =1.8mA 0.4 V
Output high voltage VOH IoH =-250,uA 2.4 V
.- Z80 CPU 150 rnA
Curre~t consumption Icc ,Z80A CPU 200 rnA
Z80B CPU 200 rnA
Input leakage current I ILl I O::£VIN::£VCC 10 ,uA
3-state output leakage
current in float
I ILEAK I VOllT =O.4V -Vcc 10 ,uA
• Capacitance (f=lMHz, Ta=25"C)

Clock capacitance CCLOCK 35 pF
Unmeasured pins returned
Input capacitance CIN I 5 pF
to ground
Output capacitance COllT 10 pF
--~--'----SHARP'-''---'----
213
• AC Characteristics (Vcc=5V±5%, Ta=0-+70°C)
280 CPU 280A CPU 280B CPU*

No. Parameter Symbol Unit
MIN. MAX. MIN. MAX. MIN. MAX.
1 Clock cycle time TcC 400* 250* 165* ns
2 Clock pulse width (High) TwCh 180* 1l0* 65 * us
3 Clock pulse width (Low) TwCl 180 2000 110 2000 65 2000 ns
4 Clock fall time TfC 30 30 20 ns
5 Clock rise time TrC 30 30 20 ns
6 Clock t to address valiC\ delay TdCr (A) 145 110 90 ns
7 Address valid to MREQ ~ delay TdA (MREQf) 125 * 65* 35 * ns
8 Clock ~ to MREQ ~ delay TdCf (MREQf) 100 85 70 ns
9 Clock t to MREQ t delay TdCr (MREQr) 1QO 85 70 ns
10 MREQ pulse width (High) TwMREQh 170* 110* 65* us
11 MREQ pulse width (Low) TwMREQ1 360* 220* 135* ns
12 Clock ~ to MREQ t delay TdCf (MREQr) 100 85 70 us
13 Clock ~ to RD ~ delay TdCf (RDf) 130 95 80 ns
14 Clock t to RD t delay TdCr (RDr) 100 85 70 ns
15 Data setup time to clock t TsD (Cr) 50 35 30 ns
16 Data hold time from RD t ThD (RDr) 0 0 0 ns
17 WAIT setup time to clock ~ TsWAIT (Cf) 70 70 60 ns
18 WAIT hold time after clock ~ ThWAIT (Cf) 0 0 0 ns
19 Clock t to M1 ~ delay TdCr (Mlf) 130 100 80 ns
20 Clock t to M1 t delay TdCr (Mlr) 130 100 80 us
21 Clock t to RFSH ~ delay TdCr (RFSHf) 180 130 110 ns
22 Clock t to RFSH t delay TdCr (RFSHr) 150 .120 100 ns
23 Clock ~ to RD t delay TdCf (RDr) 110 85 70 ns
24 Clock t to RD ~ delay TdCr (RDf) 100 85 70 ns
Data Setup to clock t during
25 TsD (Cf) 60 50 40 us
M2 , M3 , M4 or M5 cycles
26 Address stable prior to IORQ ~ TdA (IORQf) 320* 180* 110* ns
27 Clock t to IORQ ~ delay TdCr (IORQf) 90 75 65 ns
28 Clock ~ to IORQ t delay TdCf (I0RQr) 110 85 70 ns
29 Data stable prior to WR ~ TdDm (WRf) 190* 80* 25 * ns
30 Clock ~ to WR ~ delay TdCf (WRf) 90 80 70 ns
31 WR pulse width TwWR 360* 220* 135* us
32 Clock ~ to WR t delay TdCf (WRr) 100 80 70 ns
33 Data stable prior to WR ~ TdDi (WRf) 20* -10* -55* us
34 Clock t to WR ~ delay TdCr (WRf) 80 65 60 us
35 Data stable from WR t TdWRr (D) 120* 60* 30* us
36 Clock ~ to HALT t or ~ TdCf (HALT) 300 300 260 ns
37 NMI pulse width TwNMI 80 80 70 ~
us
38 BUSREQ setup time to clock t TsBUSRQ (Cr) 80 50 50 ns
39 BUSREQ hold time after clock t ThBUSRQ (Cr) 0 0 0 ns
40 Clock t to BUSACK ~ delay TdCr (BUSAKf) 120 100 90 us
41 Clock ~ to BUSACK t delay Tdef (BUSAKr) 110 100 90 us
42 Clock t to data float delay TdCr (Dz) 90 90 80 ns
43 Clock t to control output float delay
----- - TdCr (CTz) 110 80 70 us
(MREQ, IORQ, RD, and WR)
44 Clock t to address float delay TdCr (Az) 110 90 80 ns
MREQ t ,IORQ t, RD and WR t
45 TdCTr (A) 160* 80* 35 * ns
to address hold time
t Rising edge, ~ Falling edge
.....-.----------SHARP - - - - - - - - - - - - - - - -
214
No. Z80 CPU Z80A CPU Z80B CPU*

Parameter Symbol Unit
46 RESET ! to clock t setup time TsRESET (Cr) 90 60 60 ns
47 RESET from clock t hold time ThRESET (Cr) 0 0 0 ns
48 INT to clock t setup time TsINTf (Cr) 80 80 70 ns
49 INT from clock t hold time ThINTr (Cr) 0 0 0 ns
50 M1 ! to IORQ ~ delay TdMlf (I0RQf 920* 565* 365* ns
51 Clock ~ to IORQ ~ delay TdCf (IORQf) 110 85 70 ns
52 Clock t to IORQ t delay TdCf (IORQr) 100 85 70 ns
53 Clock ~ to data valid delay TdCf (0) 230 150 130 ns
All ac parameters assume a load capacitance of 100 pF. Add 10
p s delay for each 50 pF increase in load up to a maximum of 200
pF for the data bus and 100 pF for address and control lines. +5V
• For clock periods other than the minimums shown in the table, 2.lkO
calculate parameters using the following expressions.
* All timings are preliminary and subject to change.
• Footnotes to AC Characteristics
No. Symbol Z80 Z80A Z80B
1 TeC TwCh+TwCl+TrC+TfC TwCh + TwCI + TrC + TfC TwCh + TwCl + TrC + TfC
2 TwCh MAX.200ps MAX.200ps MAX.200ps
7 TdA (MREQf) TwCh+TfC-75 TwCh+TfC-65 TwCh+TfC-50
10 TwMREQh TwCh+TfC-30 TwCh+TfC-20 TwCh+TfC-20
11 TwMREQl TcC-40 TeC-30 TeC 30
26 TdA (IORQf) TcC-80 TcC-70 TeC-55
29 TdO (WRf) TeC-210 TcC-170 TeC 140
31 TwWR TeC-40 TcC-30 TcC 30
33 TdO (WRf) TwCI+TrC-180 TwCl +TrC-140 TwCl+TrC:-140
35 TdWRr (0) TwCI + TrC - 80 TwCl+TrC-70 TwCl+TrC 55
45 TdCTr (A) TwCl+TrC-40 TwCI+TrC-50 TwCl+TrC-50
50 TdMIf (IORQf) 2TcC+TwCh+TfC-80 2TeC+TwCh+TfC-65 2TeC+TwCh+TfC 50
AC Test Conditions:
VlH=2.0V VIHC=Vcc-O.6V VOH=2.0V FLOAT= ±O.5
VIL=O.8V VILC=0.45V VOL=O.8V
- - - - - - - - - - - - - - - - - - - - - S H A R P ........ _ - - - . - . . - . _ -
215
.4.~O/Z80AlZ80B Central Processing Unit ,L~OO80/LH0080A/LH.0080B
• CPU Timing (1.) Instruction Opcod~ Fetch

The Z80 CPU executes instructions by proceed-, The CPU places the contents of the Program
ing through a specific sequence of operations: Counter (PC) on the addre~s bus at the start of the
• Memory read or write . cycle (Fig. 1). Approximately one;-half clock cycle
.' 110 device read or write lat~r, MREQ goes active.,WheQ active, RD indicate$
.: Jnterrupt acknowledge that the memory d~ta ca~ be enabled onto the CPU
The basic clock per;iod is referred to as a T time data bus.
or cycle, ahti three or more T cycles make up a The CPU samples the WAIT input with the fall-
machine cycle (MI, M2 or M3 for instance). ing edge of clock state T,. During clock states T3
Machine cycles can be extended either by the CPU and Ti of an Ml cycle dynamic RAM refresh can
automatically inserting one or more Wait states or , occur while the CPU starts decoding and execu'ting
by the insertion of Dne or more Wait states by the the instruction. When the Refresh Contro\signal
user. becomes active, refreshing of dynamic memory can
. take place. '
CLOCK
Note: Tw-~ait cycle added when necessary for slow ancilliary devices.
Fig. 1 Instruction opcode fetch
(2) Memory Read or Write Cycles ,(3) Input or Output Cycles "
Fig. 2 shows the timing of memo!:L,fead or write Fig. 3 shows the timing for an 110 read or 110
cycles other than~ opcode fetch (M 1) cycle. write operation.
The MREQ and RD signals functibn exactly as in During 110 operations, the CPU automatically in-
the fetch cycle. 1n a memory write cycle, MREQ serts a single wait state (T w). This extra wait state
also becomes active when the address bus is stable. allows sufficient time for an 110 port to decode the
The WR line is aj::tive when the data bus is stable, address from the port address lines.
so 'that it can be used directly as an R/W pulse to
most semiconductor memories.
• J
--~~----SI-tARP---------~-
2H5
l LH0080/LH0080AlLH0080B
Z80/Z80AlZ80B Central Processing Unit
CLOCK
Ao-A15
MREQ
WAIT
RO
{
Read operation
~-r--cr--!--J ,/--'---~)"f--"" 1,-+--"\1 r----
00-07
1
Write operation
WR
00-07
Fig. 2 Memory read or write cycles
'-"---'--~'---SHARP-'-'----------
217
ZSO/Z80AlZ80BCentral Processing Unit . LH0080/LH0080A/LH0080B ( .
" . '", ¥' , '"
T2 Tw· Tw T3
CLOCK
. {RD
I/O read operation
Do-D7
I/O write operation{ WR
Do-D7 --------~============:;~D[a~t~a~o~utL:======}
Note: Tw =One wait cycle automatically inserted by CPU.
Fig. 3 Input or output
(4) Interrupt requesVacknowledge,cycle

cle, IORQ becomes active (instead of MREQ) to indi-
The CPU samples the interrupt signal with the cate that the interrupting device can place an 8-bit
rising edge of the last clock at the end of any in- vector on the data bus. The CPU automatically
struction (Fig. 4). When an interrupt is accepted, a adds two wait states to this cycle.
special Ml cycle is generated. During this Ml cy-
CLOCK
Notel: TL=Last state of previous instruction.

Note 2: Two wait cycles automatically inserted by CPU (*).
Fig. 4 Interrupt request/acknowledge cycle
218
(5) Non-maskable interrupt request cycle mal instruction fetch except that data put on the
bus by the memory is ignored. The CPU instead ex-
NMI is sampled at the same time as the maskable ecutes a restart (RST) operation and jumps to the
interrupt INT but has higher priority and cannot be NMI service routine located at address 0066H
disabled under software control. (Fig. 5).
The subsequent timing is similar to that of a nor-
- Last Mcycle ------~~--------------------Ml------------------~

Last T time Tl Ts
CLOCK
NMI
Ml
MREQ
RD
RFSH
'Although NMI is an asynchronous input, to guarantee its being

recognized on the following machine cycle, NMI's falling edge
must occur no later than rising edge of the clock cycle preceding
T LAST-
Fig. 15 Non-maskable interrupt request operation
(6) Bus requesVacknowledge cycle (7) Reset cycle
The CPU samples BUSREQ with the rising edge RESET must be active for at least three clock cy-
of the last clock period of any machine cycle (Fig. cles for the CPU to properly accept it. As long as
6). If BUSREQ is active, t~CPU sets its address, RESET remains active, the address and data buses
data, and MREQ, IORQ; RD, and WR lines to a float, and the co~trol outputs are inactive. Once
high-impedance state with the rising edge of the RESET goes inactive, three internal T cycles are
next clock pulse. At that time, any external device consumed before the CPU resumes normal proces-
can take control of these Iines,usually to transfer sing operation. RESET clears the PC register, so
data between memory and I/O devices. the first opcode fetch will be location 0000 (Fig. 8).
219
,~ ..........,..................,....
Z80/Z80A/Z80B C,entral Processing Unit
, '
......,......,......,- ............
LHQ080ltH0080AlLH0080B
.....,
CLOCK
BUSRQ
Ml
Unchanged
Note: TL=Last state of any M cycle.

Tx=An arbitrary clock c~c1e used by requesting device.
Fig. 6 Z-bus request/acknowledge cycle
Ml ",/E MI "'1:'- MI
CLOCK
HALT
HAL T instruction received r-t®
NMI ~------------------------
Note: INT will also force a Halt exit.
Fig. 7 Halt acknowledge cycle
220
CLOCK
RESET
Ml
============~~~~~~~7r-~f~--------------~
Il/IllI
MREQ, ------______~~~~r-----~£rc--------------------~--------
RD, WR, \___
IORQ,RFSH,
BUSAK,
HALT
Fig. 8 Reset cycle
+5V
+5V
B
74123
A Q 1-------,1
MI----I )---- RESET
7408
151588 151588
Reset switch
RESET
~~------------------
Fig. 9 Reset circuit and timing diagram when M1 cycle has no wait state
221
Z80/Z80A/Z80B Central Processing Unit LH0080/LH0080AlLH0080B
(Reference circuit> RESET signal.

The RAM contents may be adversely affected by (2) A walt state in the Ml cycle
resetting the CPU while it is in operation. Input a RESET signal to start sampling this sig-
To prevent this, a RESET signal should be input nal at the clock rising in the Ml cycle's T3 state.
in the following timings. ~hen a 1 walt state occurs, this type of RE-
(1) No walt state in the M1 cycle SET signal can be generated by the circuit di-
Input a RESET signal to start sampling this sig- agrammed in Fig. 10. In the circuit shown in Fig. 2,
nal at the clock rising in the Ml cycle's T, state. no RESET signal is given during an interrupt ac-
Fig. 9 shows a typical circuit generating such a knowledge cycle. •
WAIT signal circle WAIT

r--- -,---- -- - - ------------, +5V
I
I +5V I +5V·
I I
7432 :+5V
I
MI I
I
MREQ I
B
I 74123
I A Q'-------'"-.....
CLOCK RESET
7408
+5V.
IS1588
CLOCK
MI ~'-_ _ _ _ _ _ _ _ --J/
MREQ
\.....______-.J/
\1...-.,-_--1,
RESET
\~-----
Fig. 10 Reset circuit and timing diagram when
M1 cycle has a wait state
--.--.----...-.--SHARP ----~.-.-.-
222
• CPU Registers
A Accumulator F Flag Register A' Accumulator F' Flag Register

B General Purpose C General Purpose B' General Purpose C' General Purpose
D General Purpose E General Purpose D' General Purpose E' General Purpose
H General Purpose L General Purpose H' General Purpose L' General Purpose
, 8 bits .
I Interrupt Vector I R Memory Refresh
IX Index Register
IY Index Register
SP Stack pointer
PC Program Counter
, 16 bits .
• Architecture
(1) CPU Registers
(i) Program Counter (PC) The program
(.) Ref'esh Registe, IR) Tb, built-in ce-
fresh register provides user-transparent dynamic
14 ~
counter holds the 16 bits memory address of a cur~ memory refresh. Its lower 7 bits are automatically
rent instruction. The CPU fetches the contents incremented during each instruction fetch cycle.
from memory address specified by the PC. While the CPU records a fetched instruction and
The PC feeds the data to the address line, auto- executes the instruction, the refresh register data
matically setting the PC value to + 1. When a prog- are placed on the address bus by a REFRESH con-
ram jump takes place, a new value is directly set to trol signal.
the PC. (vi) Accumulator and Flag Register (A & F)
(ii) Stack Pointer (SP) The stack pointer The CPU has also two independent 8-bit accu-
holds the top 16-bit address of the stack with an mulators in combination with two 8-bit flag regis-
external RAM. An external file is based on LIFO ters.
(Last- In, First-Out). The accumulators store an operand or the re-
The data are transferred between a CPU-speci- sults of an 8-bit operation. The flag registers, on
fied register and the stack by a PUSH or POP in- the other hand, deal with the results of an 8-bit or
struction. The last-pushed data are first popped 16-bit operation; for example, seeing if the result
from the stack. is equal to 0 or not.
(iii) Index Register (IX & IV) For index (Vii) General-Purpose Registers There are
mode addressing, there are independent index reg- several pairs of general-purpose registers. In each
isters IX and IY, each of which holds 16-bit refer- pair, they can be used separately or as a 16-bit
ence address. paired register. The paired registers are BC, DE,
In the index mode, the index registers are used to HL, as well as Be' DE' HL'. Either of these sets can
designate the memory area for data input/output. work by an "Exchange" instruction at any time on
With an INDEX ADDRESSING instruction, an a program.
effective address comes by adding a one-byte dis- (2) Arithmetic/Logical Unit (ALU)
placement to the register content. This displace-
An 8-bit arithmetic/logical operation instruction
ment is an integral signed two's complement num-
is executed by the ALU inside the CPU. The ALU
ber
connects to each register through the internal bus
(iv) Interrupt Register (I) The 280 CPU has
for data transfer between them.
indirect subroutine call mode for any memory area
according to an interrupt. For this purpose, this
(3) Instruction Register, CPU Control
register stores the upper 8 bits of memory address
for vectored interrupt processing and the lower 8 Each instruction is read out of the memory, held
bits for the interrupting device. in the instruction register, and decoded. The con-
'-~'---'---SHARP'-''-------
223
\
Z80/Z80A/Z80BCentral 'Processing Unit LH0080/LH0080A/LH0080B
.......~.....,_ _................,............ . -...............-..r......._ _...............
/
trol unit controls this action and gives control sig- vice places an instruction on the data bus. This isa
nals necessary to read and write data from and to Restart instruction or a Call instruction.
the registers. (ii) Mode 1 Interrupt Operation. Mode 1
The,control unit also makes ALU control signal operation is very similar to that for the NML The
and other external control signals. prir-cipal difference is that the Mode 1 interrupt
(Interrupts: General Operation> The Z~W,CPU has a restart location of 0038H only.
accepts two interrupt input signals: NMI and INT_ ,(iii) Mode 2 Interrupt Operation. This in-
The NMI is a non-maskable interrupt and has the terrupt 'mode has been designed to utilize most
highest priority. INT is a lower priority interrupt effectively the capabilities of the Z80 microp-
and it requires th,at interrupts be enabled in soft- rocessor and its associated peripheral family. The
ware in order to operate. interrupting peripheral device selects the starting
address (16 bits) of the interrupt service routine. It
(1) Non-Maskable Interrupt (NMi) does this by placing an 8-bit vector on the data
The non-maskable interrupt will be accepted at bus during the interrupt acknowledge cycle. The
all times by the CPU. CPU forms a pointer using this byte as the lower
After recognition of the NMI signal, the CPU 8-bits and the contents of the I register as the up-
jumps to restart location 0066H. per 8-bits. This points to an entry in a table of
addresses for interrupt service routines. The CPU
(2) Maskable Interrupt (INT) then jumps to the routine at that address.
The maskable interrupt, INT, has three prog-- All the Z80 peripheral devices have the inter-
ram mabie response modes available. rupt priority circuit with a daisy-chain configura-
(i) Mode 0, Interrupt Operation. This tion. puring an interrupt acknowledge cycle, vec-
mode'is similar to the 8080Amicroprocessor in- tors are automatically fed. For more details, refer
terrupt service procedures. The interrupting de- to the Z80 PIO description. _
Table
~op::: :~::
t
_1;---ypOinte: b,'_S____,7_bi_ts 101
_ t'-___ From application device
I register contents
To the beg inning of service rotine
Fig. 1 Mode 2 interrupt diagram
- . . . . - . - - - - - - - S H A R p . - . . . . - . . - - - - - - .......... - -
224
• Instruction Set
Table 1 8-bit load group
Symbolic OP code HEX code Flags No. of No. of No. of

Mnemonic Comments
operation 76 543 210 (Basic) C Z P/V S N H Bytes MCycles T States
, , ,
LD r, r r+-r 01 r r 40+ • • • • •• 1 1 4
LD r, n r+-n 00 r 110
+- n -+
06+
• • • • • • 2 2 7
r,r Reg.
LD r,(HL) r+- (HL) 01 r 110 46+ • • • • •• 1 2 7 000 B
LD r, (IX+d) r+- (IX+d) 11 011 101
01 r 110
DD
46+
• • • • • • 3 5 19 001
010
C
D
+- d -+ 011 E
LD r, (IY+d) r+- (IY+d) 11 111 101
01 r 110
FD
46
• ••• • • 3 5 19 100
101
H
L
+- d -+ 111 A
LD (HL), r (HL)+-r 01 110 r 70+ • ••• • • 1 2 7
LD (IX+d), r (IX + d)+-r 11 011 101
01 110 r
DD
70+
• • • • • • 3 5 19
+- d -+
LD (IY+d), r (IY+d)+-r 11 111 101
01 110 r
FD
70+
• ••• • • 3 5 19
+- d -+
LD (HL), n (HL)+-n 00 110 110
+- 0 -+
36 • •• • • • 2 3 10
LD (IX+d), 0 (IX + d)+-n 11 011 101

00 110 110
DD
36
• • • • • • 4 5 19
+- d -+
+- 0 -+
LD (IY+d), 0 (IY + d)+-o 11

00
111 101
110 110
FD
36
• • • • • • 4 5 19
+- d -+
+- 0 -+
LD A, (BC) A+- (BC) 00 001 010 OA • • • • • • 1 2 7

LD A, (DE) A +- (DE) 00 011 010 1A
•••• •• 1 2 7
LD A, (00) A+- (00) 00
+-
III 010
0 -+
3A • • • • • • 3 4 13
+- 0 -+
LD (BC), A (BC) +- A 00 000 010 02

• • •• • • 1 2 7
LD (DE), A (DE) +- A 00 010 010 12
• • • • • • 1 2 7
LD (00), A (00) +- A 00
+-
110 010
0 -+
32
• • • • • • 3 4 13
+- 0 -+
LD A,I A +- I 11
01
101
010
101
111
ED
57
• t IFF t 0 0 2 2 9
LDA,R A+-R 11
01
101
011
101
111
ED
5F
• t IFF t 0 0 2 2 9
LDI,A I +- A 11
01
101
000
101
III
ED
47
• • • •• • • 2 2 9
LDR,A R+-A 11
01
101
001
101
111
ED
4F
• • • • • • 2 2 9
Notes: r, r' means any of the registers A, B, C, D, E, H, L, IFF the content of the interrupt enable flip-flop, (IFF) is copied into the P/V flag_
Flags: C (carry), Z (zero), S (sign), P/V (parity/overflow), H (half carry), N (add/substract)_
: • =unchanged, O=reset, 1 =set, X=undefined.
: t set or reset according to the result of the operation.
-----~---SHARP-.----.-..---
225
\ .
Table 2 16-bit load group
Mnemonic
LD dd, nn
Symbolic
operation
dd ~nn
OP code
-- -
00 ddO 001
0 -+
0
HEX code
76 543 210 (Basic) C
01+ • •
Z
.,.
Flags
pd S
••
N H
No. of
3 3
No. of
10
No. of
Bytes M CyCles T States
Comments
dd Reg.
LD IX, nn IX - 00 11 011 101 DO
• • • • •• 4 4 14 00 BC
-- --
00 100 001 21 01 DE
0
0 10 HL
LD IY, 00 IY -00 11 111 101 FD
• • • • • • 4 4 14 11 SP
-- --
00 100 001 21
0
n
10 HL, (00)
10 dd, (00)
H +- (00+1)
L-(no)
ddH +- (00+1)
-- --
00 101 016
n
n
11 101 101
2A
ED
• • • • ••
• • • • ••
3
4
5
6
16
20
no : 2·byte oumber.
Lower byte just
after opcode.
Upper byte comes
ddL - (no) 01 dd1 011
+-
- n
0 --
4B+ next.
10 IX, (no) IXH +- (nn+ 1) 11 011 101 DD • • • • • • 4 6 20
-- --.
IXL - (nn) 00 101 010 2A
n
n
LD IY, (nn) IYH +- (on+1) 11 111 101 FD
• • • • • • 4 6 20
IYL - (rin)
-
00 101 010
.fl
2A
-
-- --
10 (nn), HL (nn+1) 4 - H 00 100
(nn) - L n
010 22
• • • • • • 3 5 16
n
10 (nn), dd (on+1) +- ddH 11 101 101 ED • • • • •• 4 6 20
-- --
(nn) - ddL 01 ddO 011 43+
n
n
10 (nn), IX (on+ l)+-IX~ 11 011 101 DD • • • • •• 4 6 20
-- --
(nn) +- IXL 00 100 010 22
n
n
10 (nn), IY (nn+ l)+-IYH 11 111 101 FD
• • • • • • 4 6 20
(nn) - IYL
--
00 100
n
n --
010 22
10 SP, HL SP -HL 11 111 001 F9

• • • • •• 1 1 6
10 SP, IX SP - IX 11 011
11 111
101
001
DD
F9 • • • • • • 2 2 10
10 SP, IY SP - IY 11 111
11 111
101
001
FD
F9 • • • • •• 2 2 10
PUSH qq (SP-2)+-qqL 11 qqO 101 C5+

• • •• •• 1 3 11
PUSH IX
(SP-1)+-qqH
(SP-2)+-IXL 11 011
(SP-1)+-IXH 11 100
101
101
DD
E5 • • .. • • • 2 4 15
qq
00
01
Reg.
BC
DE
PUSH IY (SP-2)+-IYL 11 111
(SP-l)+-IYH 11 100
101
101
FD
E5 • • •• •• 2 4 15 10
11
HL
POP qq qqH +- (SP+ 1) 11 qqO

qqL - (SP)
001 Cl+ • • • • • • 1 3· 10
AF
POP IX IXH+-(SP+ 1) 11 011

IXL +- (SP) 11 100
101
001
DD
E1 . • • • • • • 2 4 14
POPIY IYH'" (SP+1) 11 111

IYL - (SP) , 11 100
101
001
FD
E1 • • • • • • 2 4· 14
Notes: dd is any of the register pairs BC, DE, HL, SP.

qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively, e.g., BCL=C, AFH=A.
Flags: *
• =unchanged, O=reset, 1 =set, X=undefined, =set or reset according to the result of the operation
226
Table 3 Exchange, block transfer, block search groups

Mnemonic Comments
EX DE, HL DE-HL 11 101 011 EB
•••••• 1 1 4
EX AF,AF' AF-AF' 00 001 000 08
•••••• 1 1 4
• • • • • •
~~I'fj
EXX 11 011 001 D9 1 1 4 Register bank and
IDE-DE' auxiliary register
\lIL HL' bank exchange
EX (SP), HL H ..... (SP+1)
L-(SP)
11 100 011 E3
• • •••• 1 5 19
EX (SP), IX IXH ..... (SP+1)

IXL - (SP)
11
11
011 101
100 011
DD
E3
•••••• 2 6 23
EX (SP), IY IYH ..... (SP+1)

IYL - (SP)
11
11
111 101
100011
FD
E3
•••••• 2 6, 23
LDI (DE) - (HL)

DE - DE+1
11
10
101 101
100 000
ED
AO
•• t
<D
• 0 0 2 4 16 Load (HL) into (DE),
increment the poin·
HL - HL+1 ters and decrement
BC - BC-1 tl1e byte counter (OC)
LDIR (DE) - (HL)
DE - DE+1
11 101 101
10 110 000
ED
BO
• • 0 • 0 0 2 5 21 If BC+O
HL - HL+1
BC - BC-1
If BC=O end 2 4 16 If BC=O
LDD (DE) - (HL)
DE - DE-1
11 101 101
10 101 000
ED
A8
• • t
<D
• 0 0 2 4 16
HL - HL-1
BC - BC-1
LDDR (DE) - (HL)
DE -DE-1
11 101 101
10 111 000
ED
B8
• • 0 • 0 0 2 5 21 If BC+O
HL - HL-l
BC - BC-1
If BC=O end 2 4 16 If BC=O
CPI A- (HL)
HL ~ HL+1
11 101 101
10 100 001
ED
Al
• t t t
® <D
1 t 2 4 16
BC - BC-1
CPIR A- (HL)
HL - HL+1
11 101 101
10 110 001
ED
B1
• t t t
® <D
1 t 2 5 21 If BC+O and
A+(HL)
BC - BC-1
If A= (HL) or 2 4 16 If BC=O or
BC=O end A= (HL)
CPD A- (HL)
HL - HL-1
11 101 101
10 101 001
ED
A9
• t t t
® <D
1 t 2 4 16
BC - BC-1
CPDR A- (HL)
HL - HL-1
11 101 101
10 III 001
ED
B9
• t t t
® <D
1 t 2 5 21 If BC+ 0 and
A+(HL)
BC - BC-1
If A= (HL) or 2 4 16 If BC=O or
BC=O end A= lHL)
Note: <DP IV flag is 0 if the result of Be =0, otherwise PIV = 1
®Z flag is 1 if A= (HL), otherwise Z=O
Flags: • = unchanged
o = set, 1 = reset
J = set or reset according to the result of the operation
227
Z~O/Z80AlZ8QB Centr.al Processing Unit LH0080/LH0080A/LH0080B
. ~ .
Table 4 8-bit arithmetic and logical grQup
Symbolic OP code HEX code, Flags No. of No. of No. of

Mnemonic' Comments
operation 76 543 210 (Basic) C Z PIV S N H Bytes MCycles T States
ADD A, r A-A+r 10 k r 80+ ct t V t 0 t 1 1 4
r Reg.
t
ADD A, n A-A+n
ADD A, (HL) A +- At (HL)

-
11 k 110 C6+
n -+
10 k 110 86+
f
t t
V
V
t
t
0
0
t
t 1
2 2
2
7
7
000
001
010
B
C
0
ADD A, (IX +d) A +- At Vxtd) 11011 101 DO t t V t 0 t 3 5 19
011 E
ADD A, (Iytd)
-
10 k 110 86+
A+- A+ (Iytd) 11 111 101

d -+
FD t t V t 0 t 3 5 19
100
101
111
H
L
A
-
10 k 110 86+
d -+ Mnemonic k
ADC A, s A+- A+s+C
4 types
t t V t 0 t ADD 000
SUB s A-A-s
available
t t V t 1 t ADC 001
SBC A, s A .... A-s-C
based on
t t V t 1 t UIB 1:10 4>10 SUB 010
AND s A - Al\s 0 t P t 0 1 2 2 7 SBC 011
the above ADD
OR s A-AVs
instruction
0 t P t 0 0 1 2 7 AND 100
XOR s A - AEBs
(see Comments)
0 t P t 0 0 3 5 19 OR 110
CP s 'A-s t t V t 1 t XOR 101
INC r r - r+1 00 r t 00+ • tt V t 0 t 1 1 4 CP 111
INC (HL) (HL) +- (HL) + 1 00 110 e 30+ • V t 0 t 1 3 11 S=r, n, (HL),
INC (IX+d) (IX+d) - 11 011 101 DO • t V t 0 t 3 6 23
,
(IX + d), (IY +d)
INC (IY+d) (lY+d) -

-
(lX+d)+l 00 110 i
d -+
11 111 101
30+
FD • t V t 0 t 3 6 23 Mnemonic t
DEC m m-m-1
-
(IY+d)+l 60 110 e 30+
4 types
d -+
available
• t V t 1 t 1*2 1*2 4*2
INC
DEC
m=r, (HL),
100
101
1 3 11
based 'on (IX+d), (lY+d)
3 6 23
J the above INC
3 6 23
instruction
Note: V and P mean overflow and parity, respectively. ,.1: depends on s.
Flags: • = unchanged ,.2: depends on m.
O=reset
l=set
X=undefined
J = set or reset according to the 'result of the operation
. r
- - - . - -........... ----SHARP---~~--------~
228
Table 5 General purpose arithmetic and CPU control groups

Mnemonic Comments
operation 76 543 210 (Basic) C Z P/V S N H Bytes M Cycles T States
DAA Decimal
adjustment
00 100 III 27 t t P t
• t 1 1 4 Decimal adjust
accumulator.
(add/subtract)
CPL A-A 00 101 111 2F
•••• 1 1 1 1 4 Complement
accumulator
(one's complement).
NEG A-O-A 11 101 101 ED t t V t 1 t 2 2 8 Negate acc.
01 000 100 44 (two's complement).
CCF C-C 00 111 111 3F t • • • 0 X 1 1 4 Complement carry flag.
SCF C-1 00 110 111 37 1
•• • 0 0 1 1 4 Set carry flag.
NOP No operation 00 000 000 00 • •• • • • 1 1 4
HALT CPU halted 01 110 110 76
• • • • •• 1 1 4
DI IFF-O 11 110011 F3
• •• • •• 1 1 4 Interrupt not enable
EI IFF - 1 11 111 011 FB
• • • • •• 1 1 4 Interrupt enable
1M 0 Set interrupt
mode 0
11
01
101 101
000 110
ED
46
• • • • • • 2 2 8 Set interrupt mode.
1M 1 Set interrupt
mode 1
11
01
101 101
010 110
ED
56
• • • • •• 2 2 8
1M 2 Set interrupt
mode 2
11
01
101 101
011 110
ED
5E
• • • • • • 2 2 8
Note : IFF indicates the interrupt enable flip· flop, CY indicates the carry f1ip·f1op.
Flags: • = unchanged, O=reset, 1 =set, X=undefined, , =set or reset according to the result of the operation
Table 6 16-bit arithmetic group

Mnemonic Comments
operation 76 543 210 (Basic) C Z P/V S N H Bytes M Cycles T States
ADD HL, ss HL-HL
+ss
00 ssl 001 09+ t • • • 0 X 1 3 11
ss Reg.
ADC HL, ss HL-HL 11 101 101 ED t t V t 0 X 2 4 15 00 BC
+ss+C 01 ssl 010 4A+ 01 DE
SBC HL, ss HL-HL 11 101 101 ED t t V t 1 X 2 4 15 10 HL
-ss-C 01 ssO 010 42+ 11 SP
ADD IX, pp IX-IX+pp 11
00
011
pp1
101
001
DD
09+
t • • • 0 X 2 4 15
pp Reg.
ADD IY, rr IY - IY+rr 11
00
111
rr1
101
001
FD
09+
t • •• 0 X 2 4, 15
\
00 BC
01 DE
INC ss ss - ss+l 00 ssO 011 03+
• • •••• 1 1 6 10 IX
INC IX IX - IX+l 11
00
011
100
101
011
DD
23
• • • • • • 2 2 10 11 SP
INC IY IY - IY+1 11
00
111
100
101
011
FD
23
• • • • • • 2 2 10
rr Reg.
DEC ss ss - ss-l 00 ssl 011 OB+
• • • • • • 1 1 6 00 BC
DEC IX IX - IX-l 11
00
011
101
101
011
DD
2B
• • •••• 2 2 10 01
10
DE
IY
DECIY IY - IY-l 11
00
III
101
101
011
FD
2B
• • • • • • 2 2 10 11 SP
Note: ss is any of the register pairs BC, DE, HL, SP.

pp is any of the register pairs BC, DE, IX, SP.
rr is any of the register pairs BC, DE, IY, SP.
Flags: • =unchanged, O=reset, 1 =set, X=undefinede, , =set or reset according to the result of the operation
229
zao/zaOA/zaOB Central Processing Unit LHooao/LHooaOA/LHooaoB
Table 7 Rotate arid shift groups

Mnemonic Comments
operation 76 543 210 (Basic) C Z PlY S N H ' Bytes MCycles T States
RLCA ~ 00 000 111 07 + • • • 0 0 1 1 4 Rotate left circular

A accumulator.
RLA ~A
00 010 111 17 + • •• 0 0 1 1 4 Rotate left
accumulator.
RRCA ~
A
00 001 111 OF + • •• p 0 1 1 4 Rotate right circulart
accumulator.
RRA Lii3=@lJ 00 On 111 IF + ••• 0 0 1 1 4 Rotate right

A accumulator.
R,LCr 11 001 011 CB + t p t 0 0 2 2 ,8 Rotate left circular
00 k r 00+ register r.
RLC (HL) 11 001 011 CB t t p t 0 0 2 4 15
r Reg.
00 k 110 06+ ,
000 B
RLC (IX+d) 11 011 101 DD t t p t 0 0 4 6 23
~ 11 001 011 CB
001 C
r. (HL). 010 D
(IX+d).
<- d .....
011 E
(IY+d) 00 k 110 06+
100 H
RLC (IY+d) 11 111 101 FD t t p t 0 0 4 6 23
101 L
11 001 011 CB
<- d ..... 111 A
00 k 110 06+
RLm ~m t + p + 0 0
Mnemonic k
RLC 000
RRC m ~
m
t + p
+ 0 0 RRC 001
RL 010
RR
RRm LiBi=@J + + P + 0 0
'2* 2* 8,* !
SLA
011
100
m 2 4 15
4 6 23 SRA 101
SLAm ~m t + p t 0 0 4 6 23 SRL 111
SRAm ~ t t ,P t 0 0 m=r. (HL).

(IX+d). (IY+d).
SRL m ~
m t t p t 0 0 * depends on m.
Rotate digit left and
A~
11 101 101 ED right between the
RLD
(HL) 01 101 111 6F • t p + 0 0 2 5 18 accumulator and
location (HL).
-
The content of the
RRD A~ 11 101 101
01 100 111
ED
67 • t p t 0 0 2 5 18
upper half of the
accumulator is un·
(HL)
affected.
Flags: • =unchanged
O=reset
l=set
X = undefined
t = set or reset according to the result of the operation
230
Z80/Z80AlZ80B Central Processing Unit LH0080/LH0080AlLH0080B
Table 8 Bit set, reset and test group

Mnemonic Comments
operation 76 543 210 (Basic) C Z PlY S N H Bytes M Cycles T States
BIT b, r Z +- rb 11 001 011
01 b r
CB
40+
• t X X 0 1 2 2 8
r Reg.
000 B
BIT b, (HL) Z +- (HL)b 11 001 011
01 b 110
CB
46+
• t X X 0 1 2 3 12
001 C
010 D
BIT b, (IUd) Z +- (IX+d)b 11 011 101
11 001 011
DD
CB
• t X X 0 1 4 5 20
011 E
100 H
+- d .....
101 L
01 b 110 46+
111 A
BIT b, (IY+d) Z +- (IY+d)b 11 111 101
11 001 011
FD
CB
• t X X 0 1 4 5 20
+- d ..... b Bit Tested

000 0
01 b 110 46+
001
SET b, r n+-1 11 001 011
a b r
CB
• • •• •• 2 2 8
010 2
1
011
SET b, (HL) (HL)b +- 1 11 001 011
a b 110
CB
06+
• • • • •• 2 4 15
100
3
4
101 5
SET b, (IX+d) (IX+d)b +- 1 11 011 101
11 001 011
DD
CB
• • •• • • 4 6 23
110 6
+- d ..... 111 7
a b 110 06+
SET b, (IY+d) (IY+d)b +- 1 11 111 101
11 001 011
FD
CB
• • •• • • 4 6 23 Mnemonic
SET
a
11
+- d ..... RES 10
a b 110 06+
2* 2* 8*
2 4 15 m=r, (HL),
RES b, m fib +- 0
4 6 23 (IX+d), (IY+d)
4 6 23 * depends on m
Note: The notation mb indicates bit b (0 to 7) or location ffi.
o= reset
l=set
X=undefined
; = set or reset according to the result of the operation
-.....-.-------SHARP-------------
231
Z80/Z80Al~80B C~ntral processing Unit' LH0080/LH0080AlLH0080B
Table 9 Jump group

Mnemonic Comments
operation 76 543 210 (Basic) C Z PIV S N H Bytes M Cycles T States
• • ••••
--
JP nn pc,- nn 11 000 011 C3 3 3 10
cc Condition
n -+
000 NZ
n -+
•••••• 001 Z
JP cc, nn
--
If condition cc
is true PC ... nn,
otherwise con-
11 cc 010
n -+
n -+
C2+ 3
3
3
3
10
10
010
011
100
NC
C
PO
tinue
JR e PC - PC+e 00 011 000
.... e-2 -+
18
••• •• • 2 3 12
101
110
PE
P
III
JR C, e If C=1
PC - PC+e ....
00 111 000
...
e-2
38
•••••• 2 3 12
NZ : non-zero
M
If C=O 2 2 7 Z : zero
continue C: carry
JR NC, e If C=O
PC - PC+e ....
00 110 000
e-2 -+
30
• • • • • • 2 3 12 PO : parity odd
PE : parity even
If C=1 2 2 7 P: sign positive
continue M : sign negative
JR Z, e If Z=1
PC - PC+e ....
00 101 000
e-2 \ -+
28 • •• • • • 2 3 12
IfZ=O 2 2 7
continue
JR NZ, e If Z=O
PC - PC+e ....
00 100 000
e-2 -+
20
•••••• 2 3 12
IfZ=1 2 2 7
continue
JP (HL) PC-HL 11 101 001 E9
• • • • • • 1 1 4
JP (IX) PC -IX 11 011 101
11 101 001
DD
E9
• • • • • • 2 2 8
JP (IY) PC -IY 11 III 101

11 101 001
FD
E9
• • • • • • 2 2 8
DJNZ, e If B - B-1 00 010 000

Bio .... e-2 -+
10 • • • • • • 2 -3 13
PC - PC+l
! If B=O 2 2 8
) continue
-Note: e represents the extension in the relative addressing mode.
<
e is a signed two's,complement number in the range -126.129>
e -2 in the opcode provides an effective address of pc+e as PC i,s incremented by 2 prior to the addition of e.
e itself is obtained from opcode position_
O=reset
1=set
X=undefined
t =set or reset according to the result of the operation
~-------~--SHARP-"---'------
232
Table 10 Call and return group

Mnemonic Comments
operation 76 543 210 (Basic) C Z PlY S N H Bytes M Cycles T States·
,
•••• ••
--
CALL nn (SP-1) .... PCH 11 001 101 CD 3 5 17 cc Condition
(SP-2) .... PCL n -+ 000 NZ
PC -nn n -+ 001 Z
••••••
CALL cc, nn If condition cc is
false continue,
otherwise same
as CALL nn
--
11 cc 100 C4+
n -+
n -+
3
3
5
3
17
10
010
011
100
NC
C
PO
101 PE
RET PCL - (SP)
PCH .... (SP+ 1)
11 001 001 C9 •••••• 1 3 10 110
111
P
M
RET cc If condition cc is
false continue,
11 cc 000 CO+ •••••• 1 '3 11
otherwise same 1 1 5 r p
as RET 000 OOH
RET! Return from
interrupt
11
01
101
001
101
101
ED
4D
• • • • •• 2 4 14 001
010
08H
10H
RETN Return from
non· mask able
11
01
101
000
101
101
ED
45
• • • • •• 2 4 14 011
100
18H
20H
interrupt 101 28H
RST p (SP-l) +- PCH
(SP - 2) +- PCL
11 t 111 C7+ • • • • •• 1 3 11 110
111
30H
38.
PCH - 0
PCL - P
O=reset
l=set
X = undefined
• = set or reset according to the result of the operation
'--''-~-----SHARP'-''---~----
233
zao/zaOA/zaOB Central Processing Unit lHooaO/lHOOaOAllHOOaOB
Table 11 Input and output group

Mnemonic Comments
IN A, (n) A+- (n) 11011 011
+- n .....
DB • • • • • • 2 3 11 n ..... Ao-A7
Aex ..... As-A15
IN r, (C) r +- (C) 11 101 101 ED
01 r 000 .40+
• t P t 0 t 2 3 12
INI (HL) +- (C) 11 101 101 ED X t X X 1 X 2 4 16 C"'" Ao-A7

B +- B-1 10 100 010 A2 CD B ..... As-A15
HL +- HL+1
INIR (HL) +- (C) 11 101 101 ED X 1 X X 1 X 2 5 21 Reg.
r.
B +- B-1 10 110 010 B2 @ (If Bi'O)
000 B
HL +- HL+l 2 4 16 001 C
Repeat until (If B=O)
010 0
B=O 011 E
INO (HL) +- (C) 11 101 101 ED X t X X 1 X 2 4 16 100 H
B +- B-1 10 101 010 AA CD 101 L
HL +- HL-1
111 A
IN OR (HL) +- (C) 11 101 101 ED X 1 X X 1 X 2 5 21
B +- B-1 10 111 010 BA (If Bf 0)
HL +- HL-1 @ . 2 4 16
B=O
OUT (n),A (n) +- A 11
+-
010 011
n .....
D3 • • • • • • 2 3 11 n ..... (A·BUS)O-7
Aex ..... (A·BUS)S-15
OUT (C), r (C) +- r 11
01
101 101
r 001
ED
41+
• • • • •• 2 3 12
OUTI (C) +- (HL) 11 101 101 ED X t X X 1 X 2 4 16 C ..... Ao-A7

B +- B-1 10 100 011 A3 CD
HL +- HL+l
OTIR (C) +- (HL) 11 101 101 ED X 1 X X 1 X 2 5 21 B ..... As-A15
B +- B-1 10 110 011 B3 (If BfO)
HL +- HL+l @ 2 4 16
B=O
OUTD (C) +- (HL) 11 101 101 ED X t X X 1 X 2 4 16
B +- B-1 10 101 011 AB CD
HL +- HL-l
OTDR (C) +- (HL) 11 101 101 ED X 1 X X 1 X 2 5 21
B +-B-1 10 111 011 BB (If Bfa)
HL +- HL-l @ 2 4 16
B=O
Note: CDlf the result of B-1 is zero the Z flag is set, otherwise it is reset.
®Z flag is set upon instruction completion only.
Flags: • =unchanged
O=reset
l=set
X=undefined
l = set or reset according to the result of the operation
------~-.-.--SHARP -.-....,-----~.-.--
234
Z80/Z80A/Z80B Parallel -Input/Output Controller LH0081.1LH0081A1LH0081 B
LH0081/LH0081A/LH0081B
Z801Z80AlZ80B Parallel Input/Output Controller
The 280 product line is a complete set of micro-
computer components, development systems and
support software. The 280 microcomputer com-
ponent set includes all of the circuits necessary to
build high-performance microcomputer systems D6
with virtually no other logic and a minimum num-
The LH0081 280 PIO (280 PIO for short below) BfA SEL 6
is a programmable two port device which provides
TTL compatible interfacing between peripheral de-
vices and the 280 CPU. The 280 CPU configures
280 PIO to interface with standard peripheral de-
vices such as tape punchers, print~rs, keyboards,
etc.
The LH0081A 280A and LH0081B 280B PIO
are the high speed version which can opeate at the
• Features
1. Two independent 8-bit bidirectional peripheral
interface ports with "handshake" data transfer
control Top View
2. N-channel silicon -gate process
3. Anyone of the following four modes of opera-
tion may be selected.
• Byte output mode
• Byte input mode
• Byte bidirectional bus (available on Port A
only)
• Bit mode
4. Programmable interrupt
5. Vectored daisy chain priority interrupt logic
included
6. The port B outputs can drive Darlington tran-
sistors
8. Single +5V power supply and single phase
clock
235
Z80/Z80A/Z80B ParallellnputlOutput Controller LH0081 ILH0081 AlLH0081B
• Block Diagram
Internal
Control Logic ;:;
fr Port A
0 " Data Bus
::.
..:;"
c.
u ...:
System Data Bus
's.
0
....:I
.
~
0
Il.
-=fr
0"
::.
..:;"
c.
Port AlB Select '"

"
o:l
:::>
Il.
u -=fr Port B
Machine Cycle 1
0 " Data Bus
I/O ::.
..:;"
c.
o:l
Interrupt
~
..0
Il.
Control Logic
BReady
B Strobe
-'" ~
..:;
> > ''""or" '" 0-=
u
0
'"+ 2Q U
u z e '" :c :c'"
0:: oj
oj
u
" ~"
> " '"
~
'»"
~
.. ..
:::s ~
c.
~
.E'" ..:;!.. !..

Ul :::s c.
:::s
..:;
'-'-~-----SHARP-------'-
236
Z80/Z80AlZ80B Parallel Input/Output Controller LH0081/LH0081A/LH0081B
• Pin Description
Bidirectional
Do-D 7 Data bus System data bus.
3-state
- Defines which port is accessed. A high selects port B,
B/A SEL Port B or A select I
and a low port A.
- Defines the type of data transfer on the data bus. A high
C/D SEL Control or data select I
selects control, and a low data.
- Active "Low". A low enables the CPU to transmit and
CE Chip enable I
receive control words and data.
Standard Z80 system clock used for internal synchro·
CLOCK System clock I
nization signals.
- Machine cycle one Active "Low". Indicates that the CPU is acknowledging
M1 I - --
an interrupt, when both M1 and IORQ are active.
Active "Low". Read operation when RD is active, and
-- Input/ output write operation when it is not active. Indicates that the
IORQ I
request CPU is acknowledging an interrupt, when both IORQ
-
and M1 are active.
RD Read cycle status I Active "Low". Read operation when active.
lEI Interrupt enable in I Active "High". Forms a priority-interrupt daisy-chain.
lEO Interrupt enable out 0 Active "High". Forms a priority-interrupt daisy-chain.
INT Interrupt request Open drain, 0 Active- "Low". Active when requesting an interrupt.
Bidirectional Transfers information between port A and a peripheral
Ao-A 7 Port A bus
3-state device.
Active "Low". Used as a handshake line for data trans-
---
A STB Port A strobe I fer synchronization on port A. Not used in the bit con-
trol mode.
Active "High". Used as a handshake line for data trans-
A RDY Port A ready 0 fer synchronization on port A. Not used in the bit con-
trol mode.
Bidirectional Transfers information between port B and a peripheral
Bo-B 7 Port B bus
3-state device.
Active "Low". Used as a handshake line for data trans-
--
B STB Port B strobe I fer synchronization on port B. Not used in the bit con-
trol mode.
Active "High". Used as a handshake line for data trans-
B RDY Port Bready 0 fer synchronization on port B. Not used in the bit con-
trol mode. -

Input voltage V IN -0.3-+7 V
Output voltage V OUT - -0.3-+7 V
Operating temperature T oDr 0-+70 ·C
Storage temperature T sto -65-+150 ·C
237
Z80/ZS0A/Z80B Parallel Input/Output Controller LH008t1LH0081AILH0081 B
• DC Characteristiqs (Vcc =5V±5%,'Ta=0-+70t)

Parameter Symbol Conditions MLN. TYP. MAX. Unit
Clocl~ input low voltage VILe -0.3 0.45 V
Clock input high voltage V IHe Vee- 0.6 Vee+ 0.3 V
Input high voltage VII'! 2.0 5.5 V
Output low voltage VOL IOL =2mA 0.4 V
Output high voltage VOH IoH = -250pA 2.4 V
Supply current Icc VoH =1.5V 100 rnA
Input leakage current I ILl I O:;;;VIN~Vee 10 pA
3 state output! data
bus input leakage current
I Iz I 0:;;;V1N:;;;V ee 10 pA
Darlington drive current IOHD REXT =390n -1.5 rnA
• CapaCitance (f=lMHz, Ta=25t)

Unmeasured pins returne<1
Input capacitance C1N 7 pF
to ground
Output capacitance COUT 10 pF
• AC Characteristics (Vcc=5V±5%, Ta=0-+70t)
Z80 PIO Z80A PIO Z80B PIO (Note 9)

No. . Parameter Symbol Unit Note
1 Clock cycle time TcC 400 (Note 1) 250 (Note 1) 165 (Note 1) ns
2 Clock width (high) TwCh 170 2000 105 2000· 65 2000 ns
3 Clock width (low) TwCl 170 2000 105 2000 65 2000 ns
CE, B/ A, C/O to RD, IORO ~
6 TsCS (RI) 50 50 50 ns 6
setup time
Any hold times for specified.
7 Th 0 0 0 ns
setup time
8 RD, IORQ to clock t setup time TsRI (C) 115 115 70 ns
9 RD, IORQ ~ to data out delay TdRI (DO) 430 380 300 ns 2
RD, IORQ t to data out
10 TdRI (DOs) 160 110 70 ns
float delay
11 Data in to clock t setup time TsDI (C) 50 50 40 ns CL-50pF
IORQ ~ to vector out delay
12 TdIO (001) 340 160 120 ns 3
(INT ACK cycle)
13 M1 ~ to clock t setup time TsMl (Cr) 210 90 70 ns
M1 t to clock ~ setup time
14 TsMl (Cf) 0 0 0 ns 8
(M1 cycle)
Ml ! to lEO ~ delay (interrupt
15 -
immediately preceding M1 ~ )
TdMI (lEO) . 300 190 100 ns 5,7
tEl to IORQ ~ setup time

16
(INT ACK cycle)
TsIEI (10) 140 140 100 ns 7
5
17 IEI ~ to lEO ~ delay TdlEI (IEOf) 190 130 120 ns
C~=50pF
IEI t to lEO t delay
18 TdlEI (IEOr) 210 160 160 ns 5
(After ED decode)
238
Z80 PIO Z80A PIO Z80B PIO (Note 9)

No. Parameter Symbol Unit Note
IORQ t to clock ! setup time
19 (to activate READY on next TelO(C) 220 200 170 ns
clock cycle)
5
20 Clock ! to READY t delay TdC (RDYr) 200 190 170 ns
CL=50pF
21 Clock ! to READY ! delay TdC (RDYf) 150 140 120 ns 5
22 STROBE pulse width TwSTB 150 150 120 ns 4
STROBE t to clock ! setup
23 time (to activate READY on TsSTB (C) 220 220 150 ns 5
next clock cycle)
IORQ t to PORT DATA stable
24 TdIO (PO) 200 180 160 ns 5
delay (Mode 0)
PORT OATA to STROBE t
25 TsPD (STB) 260 230 190 ns
setup time (mode 1)
STROBE ! to PORT OAT A 230
26 TdSTB (PO 210 180 ns 5
stable (mode 2)
STROBE t to PORT OAT A
27 TdSTB (PDr) 200 180 160 ns CL=50pF
float delay (mode 2)
PORT OAT A match to INT !
28 TdPD (INT) 540 490 430 ns
delay (mode 3)
29 STROBE t to INT ! delay TdSTB (INT) 490 440 350 ns
Note 1: TcC=TwCh+TwCI+TrC+TfC.
Note 2: Increase TdRI (DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Note 3: Increase TdIO (DOl) by IOns for each 50 pF, increase in load up to 200 pF max.
Note 4: For Mode 2 : TwSTB>TsPD (STB).
Note 5: Increase these values by 2 ns for each 10 pF increase in load up to 100 pF max.
Note 6: TsCS (RI) may be reduced. However, the time subtracted from TsCS (RI) will be added to TdRI (DO).
Note 7: 2.5 TcC>(N-2) TdIEI (IEOf)+TdMI (IEO)+TsIEI (IO)+TTL buffer delay, if any.
Note 8: Ml must be active for a minimum of two clock cycles to reset the PIa.
Note 9: Z80B PIa numbers are preliminary and subject to change.
-------------SHARP-----.-........;...--
239
.............. -.. -.,.-.-....
Z801Z80A/Z80B ParallellnputlOutput Controller'
.• AC Timing Chart
- .- .--
..........,...... ...-.~....,~ ....
LH0081/LH0081A/LH0081 B
CLOCK
CE
B/A,C/O
RD,IORQ
OUT
{
Do-D, .
IN
IORQ
Ml
lEI
lEO
READY
(ARDY or BRDY)
STROBE
(ASTB or B8TB)
Mode 0
Ao-A, Mode 1
Mode 2
Mode 3
---"---~----SHARP---'-""""'~""""'------
240
Z80/Z80AlZ80B. Parallel Input/Output Controller LH0081/LH0081A/LH0081B
• Programming (3) Interrupt control

(1) Interrupt vector read The interrupt control words are as follows.
An interrupting device needs giving an 8-bit in-
terrupt vector to the CPU_ Using this vector, the
CPU forms an interrupt service routine address_
y y
Effective in bit Indicates that the information
control mode is interrupt control words
Bit7 = 1: Interrupt enable flag is set to en-

able an interrupt.
Bit7=O: Interrupt enable flag is reset to dis-
(2) Operation mode select
able an interrupt.
An operation mode is selected by writing data to Bit6-4: Defines interrupt conditions in the
the 2-bit mode control register in the following bit mode. Ignored in other modes.
manner- Bit3-0: Indicates interrupt control words.
If bit4 = I, the following control words are sup-
I~: I::(:ID~ IDrl :'1 ~I posed to be written in the mask register.
'-y------' '-----v------"
Mode Words Indicates
Mode Words
X means they are not used
Mode Ml MO Only the port data line with MB=O is monitored.

Byte output mode 0 0 When the interrupt conditions are satisfied, an in-
Byte input mode 0 1 terrupt takes place.
Bidirectional byte bus mode 1 0
Bit control mode 1 1
Interrupt
In selecting the bit control mode, an input/output enable X X X 0 0 1 1
flag
direction should be set later.
'---...r----"
Not affected by Interrupt control words
these -bits
Iio=l :Input ; I10=O:Output
• Timing
(1) Output mode (Mode 0) Ready stays active until the positive edge of the
An output cycle is always started by the execu- strobe line is received, indication that data was
tion of an output instruction by the CPU_ The WR * taken by the peripheral. T~positive edge of the
strobe pulse generates an INT if the interrupt en-
pulse from the CPU latches the data from the CPU
data bus into the selected port's output register. able flipflop has been set and if this device has the
The WR * pulse sets the Ready flag after a Low- highest priority.
going edge of CLK, indicating data is available.
241
. Z80/Z80A/Z80B Parallel Input/Output Controller . LHOb81/LH0081 AlLH0081 B
CLOCK
WR*
Port output
RDY
8TB
(2) Input mode (Mode 1) and cannot accept any mote data until the CPU
When STROBE goes Low, data is loaded into the completes a rea~When a read is complete, the
selected port iriput register. The next rising edge of positive edge of RD sets Ready at the next Low-
strobe activates INT, if Interrupt Enable is set and going transition of CLK. At this time new data can
this is the highest-priority requesting device. The be loaded into the PIO.
following falling edge of CLK resets Ready to an in·
active state, indicating that the input register is full
CLOCK
Port input
RDY
RD"
(3) Bidirectional mode (Mode 2)

Port A's vector will be used during port output and
This is a combination of Modes 0 and 1 using all Port B's will be used during port Input. Data is
four handshake lines and the eight Port A I/O allowed out onto the Port A bus only when- ASTB
lines. Port B must be set to the bit mode and its ·is Low: The rising edge of this strobe can be used
inputs must be masked. The Port A handshake to latch the data into the peripheral.
lines are used for output control and the Port B
lines are used for input control. If interrupts occur,
242
CLOCK
WR"
A RDY __________________-J
Port A data bus ------------C~~}t-~:1!~Q-+---
INT
B RDY
ter data from those port data lines assigned as in-

(4) Bit mode (Mode 3)
puts. The input register contains data that was pre-
The bit mode. does not utilize the handshake sig- sent immediately prior to the falling edge of RD. An
nals, and a normal port write or port read can be interrupt is generated if interrupts from the port
executed at any time. When writing , the data is are enabled and the data on the port data lines
latched into the output registers with the same tim- satisfy the logical equation defined by the 8-bit
ing as the output mode. mask and 2-bit mask control registers. However, if
When reading the PIO, the data returned to the Port A is programmed in bidirectional mode, Port B
CPU is composed of output register data from those does not issue an interrupt in bit mode and must
port data lines assigned as outputs and input regis- therefore be polled.
CLOCK
Port data bus
RD
L Data word 1 placed on bus
243
.-.-.--.........---..
Z80/Z80A/Z80B Parallel .Input/Output Controller
(5) Interrupt acknowledge timing.

i
....,-----------~- ......,-....-
LH0081/LH0081 A/LH0081B
programmed 8-bit interrupt vector on the data bus

During Ml time, peripheral Cflntroliers are inhi- at this time. lEO. is held Low until a Return From
bited from changing their interrupt enable status, Interrupt (RETI) instruction is executed by the·
permitting the Interrupt Enable signal to ripp.le CPU while lEI is High. The 2-byte RETI instruc-
through the daisy chain. The peripheral with lEI tion is decoded internally by the PIO for this pur-
High and lEO Low during INT ACK places a pre- pose.
Last T state Tw' Tw' T3

CLOCK
MI
lEO
lEI
(6) Return from interrupt cycle goes Low again. If the second byte of the opcode
was a "40", then the opcode was an RET! instruc-
If a Z-:80 peripheral has no interrupt Pending tion.
·and is not under service, then its IEO=1E1. If it has After an "ED" opcode is decoded, only the
an interrupt under service (i.e., it has already inter- peripheral device which has interrupted and is cur-
rupted and received an interrupt acknowledge) rently under service has its lEI High and its lEO
then its lEO is always Low, inhibiting lower prior- Low. This device is the highest-priority device in the
ity devices from interrupting. If it has an interrupt daisy chain that has received an interrupt acknow-
pending which has not yet been acknowledged, lEO ledge. All other· peripherals have lEI = lEO. If the
is Low unless an "ED" is decoded as the first byte next opcode byte decoded is "40". this peripheral de-
of a 2-byte opcode. In this case, lEO goes High un- vice resets its "interrupt under service" condition.
til the next opcode byte is decoded, whereupon it
CLOCK
lEI
lEO
244
Z80/Z80A/Z,80B Counter Timer Circuit LH0082/LH0082A1LH0082B
LH0082/LH0082A/LH0082B
Z801Z80AlZ80B Counter Timer Circuit "
support software. The 280 microcomputer com- o
build high- performance microcomputer systems
The LH0082 280 eTe (Z80 eTe for short be-
low) is a programmable, four channel device that ZC/TOo 7
provides counting and timing functions for the Z80
epu. The Z80 epu configures the 280 eTC's four
independent channels to operate under various
modes and conditions as required.
The LH0082A 280A and LH0082B Z80B eTe
are the high speed version which can operate at the
Top View
• Features
1. Four independent programmable 8-bit coun-
terl16-bit timer channels
2. N-channel silicon gate process
3. Each channel may be selected to operate in
either a counter mode or timer mode
4. Programmable interrupts on counter or timer
states
5. When the down-counter reaches the zero count
the eTe reloads its time constant automatically
and continues it's channel operation
6. Readable down counter
7. Selectable 16 or 256 clock prescaler for each
timer channels
'8. Selectable positive or negative trigger may in-
itiate timer or counter operation
9. Three channels have Ze/TO outputs capable of
driving Darlington transistors
10. Vectored daisy chain priority interrupt logic
included
clock
1,3. 28-pin dual-in-line package
·----.-..--~---SHARP .......... - - - . - - - - -
245
.._..._._----------_.....-....
Z80/Z80AlZ80B Counter Timer Circuit
• Bl.ock ,Diagra~
_-_.........
LH0082/LH0082A1LH0082B
Zero Count/
Timeout Output
Clock/Trigger
Input
Internal
System Control Logic
Zero Count/
Data Ti meout Output
Bus Clock/Trigger
Input
Zero Count/
Timeout Output
Clock/Trigger
Input
Clock/Trigger
Input
tIII
., > ><:>
...
C,)
0
-.,.,"
III .=i
., 0
<;;
. .,.
U)
t:>:: + ;:; G <1' ;jS

uu z a t:>:: c ;jS
> " !III

'"
~
.,......"
~
~
~
C
~
.,"...... ..."...
<fl
]
] !
.=i
• Pin Description
Bidirectional
3-state
CS o, CS 1 Channel select I $elects one of the four independent channels.
- Active "Low". A Low enables the CPU to transmit and
CE Chip enable I
receiv~ control words and dat'a.
Standard Z80 system clock used. for internal synchro-
nization signals.
,
- Active "Low". Indicates that the CPU is acknowledging
Ml Machine cycle one I - --
an interrupt, when both Ml and IORQ are active.
write operation when it is not active. Indicates the CPU
IORQ I/O request I
is acknowledging an interrupt, when both IORQ and Ml
are active.
RD Read cycle status I Active "Low". Read operation when active.
246
Z80/Z80AlZ80B Counter Timer Circuit LH0082/LH0082A/LH0082B
,

lEI Interrupt enable in I Active "High". Forms a priority-interrupt daisy-chain.
lEO Interrupt enable out 0 Active "High". Forms a priority-interrupt daisy-chain.
INT Interrupt request Open drain, 0 Active "Low". Active when requesting an interrupt.
RESET Reset I Active "Low". Resets the interrupt bits.
CLK/TRG o- External clock/timer
I Counter / timer input for four independent channels.
CLK/TRG a trigger input
ZC/TOo - External clock/timer Active "High". 0/112 output for four independent chan-
0
ZC/T0 2 trigger out nels. No output terminal at channel 3.

Output voltage VOUT -0.3-+7 V
Storage temperature T sto -65-+150 t
• DC Characteristics (Vcc=5V±5%, Ta=0-+70t)

Clock input low voltage VILC -0.3 0045 V
Clock input high voltage VIHC Vcc-0.6 Vcc+0.3 V
Output low voltage VOL IOL=2mA 004 V
Output high voltage VOH IOH= - 25O I'A 204 V
Supply current Icc t c =400ns 120 rnA
Input leakage current ILl O~VIN~VCC 10 I'A
3-state output leakage current I ILOH I 2AV~VouT';;:Vcc 10 I'A
3-state output leakage current I ILOL I VouT=OAV 10 I'A
Darlington drive current IOHD VoH =1.5V, REXT =390n -1.5 rnA
(f=lMHz, Ta=25t)
• CapaCitance
Input capacitance CIN 5 pF
to ground
---~----SHARP-'----------
247
Z8Q/Z80AlZ80BCounter Timer Circuit LH0082/LH0082A/LH0082B
Z80 CTC Z80A CTC Z80BCTC

No. Symbol Parameter Unit Note *.
1 TeC Clock cycle time 400 (Note 1) 250 (Note 1) 165 (Note 1) ns
2 TwCh Clock width (high) 170 2000 105 2000 65 2000 ns
3 TwCI Clock width (low) 170 2000 105 2000 65 2000 ns
4 TfC Clock fall time 30 30 20 ns
5 TrC Clock rise time 30 30 20 ns
6 Th AU hold times 0 0 0 ns
7 ' TsCS (C) CS to clock t setup time 250 160 100 ns
8 TsCE (C) CE to clock t setup time 200 150 100 ns
9 TsIO (C) 10RQ t to clock t setup time 250 115 70 ns
10 TsRD (C) RD ! to clock t setup time 240 115 70 ns
11 TdC (DO) Clock t to data out delay 240 200 130 ns 2
12 TdC (DOz) Clock ! to data out float delay 230 110 90 ns
13 TsDI (C) Data in to clock t setup time 60 50 40 ns
14 TsMl (C) M1 to clock t setup time 210 90 70 ns.
M1 ! to lEO ! delay (interrupt
15 TdMl (lEO) - 300 190 130 ns 3
immediately preceding MI)
IORQ ! to data out delay
16 TdIO (001) 340 160 110 ns 2
(INT A cycle)
17 TdlEI (IEOf) lEI ! to lEO ! delay 190 130 100 ns 3
lEI t to lEO t delay
18 TdIEI (lEOr) 220 160 110 ns 3
(after ED decode)
19 TdC (INT) Clock t to INT ! delay TeCt200 TeCt 140 TeC+ 120 ns 4
CLK/TRG t to INT ! delay
TeCt230 TeCt 160 TeC+ 130 ns 5
20 TdCLK (lNT) tsCTR (C) satisfied
CLK/TRG t to INT ! delay
ZTeCt530 ZTcCt 370 ZTcCtZ80 ns 5
tsCTR (C) not satisfied
21 TcCTR CLK/TRG cycle time 2TcC 2TcC 2TcC ns 5
22 TrCTR CLK/TRG rise time 50 50 40 ns
23 TfCTR CLK/TRG fall time 50 50 40 ns
24 TwCTRI CLK/TRG width (low) 200 200 120 ns
25 TwCTRh CLK/TRG width (high) 200 200 120 ns
CLKITRG t to clock t setup
26 TsCTR (Cs) 300 210 150 ns 5
time for immediate count
CLK/TRG t to clock t setup
27 TsCTR (Ct) time for enabling of prescaler on 210 210 150 ns 4
following clock t
28 TdC (ZC/TOr) Clock t to ZC/TO t delay 260 190 140 ns
29 TdC (ZCITO!) Clock ! to ZC/TO ! delay 190 190 140 ns
t Rising edge, I falling edge
[A] 2.5 TcC> (n·2) TdlEI (lEaf) + TdMI (lEO) + TsIEI (10) + TTL buffer delay, if any.
[B] RESET must be active for a minimum of 3 clock cycles.
Notel: TcC=TwCh+TwCl+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pF maximum for data lines, and 100 pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode.
*: All timings are preliminary and subject to change.
--~--'-'--SHARP''''''---------
248
Z80/Z80A/Z80B Counter Timer Circuit LH0082/LH0082A/LH0082B
• AC Timing Chart
r
I'---CD---..
~ "~n~_r~
® ~ ®
CLOCK
... ;:q)
r
CSo, CSI )l ](
-CE 1--(1)- ~ -®
'\. J
IE-@~
- - ~ r-®
Read
IORQ \. L
®~ ®-~
-RO
'\. ¥
®--iE--- ®- ~
00-07
fE--@~ i-@ f-J
CSo, CS, X X
-CE k-ev-- ~ -®
"\L. ¥
write - - ~- .....-4 ®
IORQ 'll /
®--k--oo .....-..f- ®
Do-Oj )l }(
I-@--"'~
MI
-{
Inter
acknowl edge
--
IORQ
00-07
~@ h
I
I f..:--@
,
@f
~
-@+/
-
lEI
I-©
lEO
INT --®l~
~@ :i
/ \L
,..".1. @ ®l =:-I
CLK/TRGo-3 = I
(Counter mode) --1 re-@~ @~@---I
lb.$"
i-----@ ---J
CLK/TRGo-3 ----'
(Timer mode) k-~
ZCITOo-2
~@-r ~
@\.
. ~49
t:801Z80AIZ80B Counter Timer Circuit 'LH0082/LH0082A/LHOO82B
• Programming The operation starts at the second clock rising

if the trigger input meets the set-up time, and
(1) Operation mocie select
at the third clock rising if It does not. If an ex-
To select a channel operating mode, write a chan- ternal trigger input is given before writing a
nel control word having bit 0 changed to 1 in the time c,onstant the' condition of bit 3 = 0 is
channel control register. caused.
D7 Ds Ds D. D3 D2 Dl Do • Bit 2 = 0: Indicates that there is no time con-
Inter- Pre- eLK/ Trigger Time stant written after the channel control word.
rupt scaler TRO mode constant This bit cannot be 0 for the channel control
Mode value Reset 1
enable edge mode
selection word to be immediately given when the chan-
nel is reset.
D3 and Ds are used i~ timer mode only. • Bit 2 = 1: Indicates that there is a time constant
written after the channel control word. When
• Bit 7 = 0: Disables a channel interrupt. a time constant is written during a down-
• Bit 7 = 1: Enables a channel interrupt each counter operation, the new constant is set into
time the down-counter counts down to zero. the time constant register. But the counter
No interrupt is produced even with bit 7 as 1, keeps on counting. Once the counter counts
after the counter has counted down to zero zero, the new constant is available to use.
with bit 7 as O. • Bit 1 = 0: The channel acts as a down-counter.
• Bit 6 = 0: Selects the timer mode, having the • Bit 1 = 1: Stops the operation as a down-coun-
prescaler output as the down-counter clock. ter. With bit 2 = 1, the operation restarts after
The timer's period comes in te. P. TC. Where a time contant is written.
te represents system clock period, P has 16 With bit 2 = 0, the channel does not act until a
or 256 (divisional scale by the prescaler), and hew control word is given.
TC means an 8-bit programmable time con-
stant (max. 256). (2) Time constant programming
• Bit 6 = 1: Selects the counter mode, having the
An 8-bit time constant is written into the time
external clock (CLK input) signal as the down-
constant register, following the channel control
counter clock. The prescaler is not used.
word with bit 2 = 1. "00" (hexadecimal) indicates
• Bit 5 = 0: ,Used for the timer mode only. The
the time constant 256.
'prescaler divides the system clock into 16 sec-
07 Os Os 0, Do
tions.
.Bit 5 = 1: Used for the timer mode only. The
TC7 I TCs I TCs lTC, TCa TC2 TCI TCo
prescaler divides the system clock into 256
(3) Interrupt vector programming
sections.
• Bit 4 = 0: Starts the timer operation at the trig- If the Z-80 CTC has one or more interrupts en-
ger input falling edge in the timer mode. In the abled, it can supply interrupt vectors to the Z-80
counter mode, the down-counter comes on at CPU. To do so, the Z-80 CTC must be pre-prog-
the clock input rising edge. rammed with the most-significant five bits of the
• Bit 4 = 1: Starts the timer operation at the trig- interrupt vector. Programming consists of writing
ger input rising edge in the timer mode. In the a vector word to the 110 port corresponding to the
counter mode, the down-counter comes on at Z-80 CTC Channel O. Note that Do of the v~ctor
the clock input rising edge. word'is always zero, to distinguish the vector from
• Bit 3 = 0: Effective in the timer mode only. a channel control word. Dl arid D2 are not used in
With bit 1=1, the timer starts at the rising programming the vector word. These bits are sup- ,
edge of the machine cycle T2 which is next to plied by the interrupt logic to identify the channel
the write cycle of a time constant. With bit requesting interrupt service with a unique inter-
1 =0, the timer starts at the rising edge of the rupt vector. Channel 0 has the highest priority.
machine cycle Tl which is next to the write cy-
cle of this control information .
• Bit 3 = 1: Effective in the timer mode only. The
timer starts by an external trigger input that
is given after the rising of the machine cycle
T2 next to the write cycle of a time constant.
250
Z80/Z80AlZ80B Counter Timer Circuit LH0082/LH0082A1LH0082B
D6 Ds D, D3 Dz D, Do and CSo selects the channel to be read. Ml must be

V6 Vs V3 v, Vo High to distinguish this cycle from an interrupt
acknowledge. No additional wait states are allowed.
(3) Interrupt acknowledge timing
Dz D, Channel
Fig. 3 shows interrupt acknowledge timing. Af-
0 0 0
ter an interrupt request~e Z-80 CPU sends an
0 1 1
interrupt acknowledge (Ml and IORQ). All chan-
1 0 2
nels are inhibited from changing their interrupt re-
1 1 3
quest status when Ml is ~tive-about two clock
cycles earlier than IORQ. RD is High to distinguish
• Timing this cycle from an instruction fetch.
The CTC interrupt logic determines the highest
(1) Write cycle timing priority channel requesting an interrupt. If the
Fig. 1 shows write cycle timing for loading con- CTC interrupt enable input. (lEI) is High, the high·
trol, time constant or vector words. est proiority interrupting channel within the CTC
The CTC does not have a write signal input, so it places its interrupt vector on the data bus when
generates one internally when the read (RD) input IORQ goes Low. Two wait states (TWA) are auto-
is High during T,. During T, IORQ and CE inputs matically inserted at this time to allow the daisy
are Low. Ml must be High to distinguish a write chain to stabilize. Additional wait states may be
cycle from an interrupt acknowledge. A 2-bit bin- added.
ary code at inputs CSt and CSo selects the channel (4) Return from interrupt cycle
to be addressed, and the word being written is If a Z-80 peripheral has no interrupt pending
placed on the Z-80 data bus. The data word is and is not under service, then its lEO = lEI. If it has
latched into the appropriate register with the ris- an interrupt under service (i.e.,it has already inter-
ing edge of clock cycle T3. rupted and received an interrupt acknowledge)
(2) Read cycle timing then its lEO is always Low, inhibiting lower prior-
Fig. 2 shows read cycle timing. This cycle reads ity devices from interrupting. If it has an interrupt
the contents of a down-counter without disturbing pending which has not yet been acknowledged, lEO
the count. is Low unless an "ED" is decoded as the first byte
During clock cycle T2, the Z-80 CPU initiates a of a 2-byte opcode. In this case, lEO goes High un-
read cycle by driving the following inputs Low: RD, til the next opcode byte is decoded, whereupon it
IORQ, and CEo A 2-bit binary code at inputs CSt goes Low again. If the second byte of the opcode
Tl
ru ~ ~rurL
T2 T3
CLOCK
~
X Channel address
X
IORQ
\ I
RD
Ml
Input
I I I
Fig. 1 Write cycle timing
---~"'-'-----SHARP--'-----'-
251
Z801Z80A/Z80B Counter Timer Cifc:uit LHOO82/LH0082A/LH0082B,
was a "4D," then the opcode was an RETI instruc~ in the daisy chain that has received an interrupt
tion. acknowledge. All other perjpherals have IEI' '" lEO. '
After an' "ED" opcode is decoded, only the If the next opcode byte decoded is "4D", this
peripheral device which 'has interrupted and is peripheral device resets its "interrupt under ser-
currently under service has its IEI High and its vice" condition.
, lEO Low. This device is the highest-priority device
CLOCK
Channel address
Ml
0 0 -0 7 Output
Fig_ 2 Read cycle timing
Last T
state Tl T2 Tw· Tw· Tg T.
n-l\....J ~ rL ~ ~ ~ ru
,....-
CLOCK ---01
Ml It II
IORQ \ 11
lEI
--- --- J
L ---- --
- ---- ----
--~
lEO
- ""\ -,
-h --- --- ~-U

r----
00- 0 7 I Vector
I
Fig. 3 Interrupt acknowledge timing
. - - . - - - - - - - - - - - $ H A R P . - - - - - . - . . - . .......... ~---
\
25,2
Z80/Z80AlZ80B Counter Timer Circuit LH0082/LH0082A/LH0082B
Tl T2 T3 T. Tl T2 T3 T. Tl
CLOCK
Ml
RD
Do-D7
lEI
lEO
Fig. 4 Return from interrupt cycle
CD Daisy chain prior to interrupt
During service
® When Channel 2 requests interrupt and receives ackno~ledge.
During service
,® When Channell requests interrupt and receives acknow ledge.

In this case, Channel 2 service is discontinued temporarily.
® When Channell service is completed and RETI instruction is executed.

In this case, Channel 2 service is restarted.
® When Channel 2 service is ~ompleted and RETI instruction is executed.

Fig. 5 Daisy-chain interrupt service
253
Z80/Z80A/Z80B Counter Timer Circuit LH0082/LH0082A/LH0082B
(5) Daisy-chain interrupt service (6) Counter operation/timer operation

Fig. 5 shows a typical nested interrupt order In the counter mode, the CLK/TRG pulse input
with the CTC. Channel 2 first requests an inter· decrements the down-counter. The trigger is asyn-
rupt to be serviced. If the higher-priority Channel chronous, but the count is synchronized with CLK.
1 requests an interrupt while Channel 2 is in ser- For the decrement to occur on the next rising edge
vice, the Channel 2 service is interrupted and of CLK, the trigger edge must precede CLK bya
Channell is serviced instead. Now the Channell minimum lead time. In the timer mode, a CLK/TRG
service routine has been completely executed, an pulse input starts the timer on the second succeed-
RETI instruction can be given to indicate that ing rising edge of CLK. The trigger pulse is asyn-
Channel 1 has been serviced. At this moment, chronous, and it must have a minimun width. A
Channel 2 will be in service again. minimun lead time (210 ns) is required between the
active edge of the CLK/TRG and the next rising
edge of CLK to enable the prescaler on the follow-
ing clock edge.
CLOCK
CLK
~ \ / L
Counter mode
Down counter I Zero count

\
ZC/TO
/ \
CLOCK
TRG
I \ Timer mode
Prescaler / Start operatig
Fig. 6 Counter operation/timer operation
254
Z80/Z80A Direct Memory Access LH0083/LH0083A
ZSOIZSOA
LH0083/LH0083A Direct Memory Access l

support software. The Z80 microcomputer com-
ponent set includes all o'{ the circuits necessary to
build high-performance microcomputer systems
The LH0083 Z80 DMA (Z80 DMA for short be-
low) is a powerful and versatile device for controll-
ing and processing of data transfers. Its basic
function of managing CPU-independent transfers
between two ports is augmented by an array of fea-
tures that optimize transfer speed and control with
little or no external logic in systems using an 8-or
16-bit data bus and a 16"'bit address bus.
Transfers can be done between any two ports BAO 13
(source and destination), including memory-to-I10,
BAI 14
memory-to-memory, and I10-to-I10. Dual port
BUSRQ 15
addresses are automatically generated for each
transaction and may be either fixed or incrementing/ CE/WAIT
decrementing. In addition, bitmaskable byte searches
can be performed either concurrently with transfers
or as an operation in itself.
The LH0083A Z80A DMA is a high speed ver-
sion which can operate at the 4MHz system clock.
Top View
• Features registers and an entire previous seQuence can

1. Transfers, searches and search/transfers in be repeated, automatically
byte-at-a-time, burst or continuous modes 5. Extensive programmability of functions CPU
2. Cycle length and edge timing can be programmed can read complete channel status
3. Dual port addresses generated for memory- 6. Vectored daisy chain priority interrupt logic
to-JlO, memory-to-memory, or I10-to-I10 op- 7. Single + 5V power supply and single phase
erations Adderess may be fixed or automat- clock
ically incremented/decremented 8. TTL-compatible inputs and outputs
4. Next-operation loading without disturbing cur- 9. 40-pin dual-in-line package
rent operations via buffered starting-address 10. N-channel silicon-gate process
.-.-----,---SHARP----------
255
..........,.....................................................................-
Z-80/Z80A Direct Memory Access
,
LH0083/LH0083A
,
• Block Diagram
•...:0:.::;
;; ;; u"
l/')
0
0
+
u
u
:>
-'"
>.
Ul
E
'"
7
Bus Acknowlege In
Bus Acknowlege Out Interrupt
Interrupt 'Request 'and Bus -Plllse Byte
Port A
Interrupt Enable In Priority , Logic COllnter
Logic Address
Interrupt Enable Out
System
Syste'm Data Bus Address
Bus
Machine ,Cycle 1 Bus Control Byte Port B

I/O ReqQest Control and Match Address
Memory Request Status
Logic Registers Logic
Read
256
• Pin Description
Ao-A'5 Address bus 3-state 0 System address bus.
Bidirectional
Do -D 7 Data bus System data bus.
3-state
-- Active "low". Used to form a bus priority- interrupt
BAI Bus acknowledge in I
daisy-chain.
-- Active "low". U sed to form a bus priority- interrupt
BAO Bus acknowledge out 0
daisy-chain.
BUSRQ Bus request Open drain, 0 Active "low". Active when controlling the bus.
--- Active "low". Acts as CE when the CPU accesses the
CE/WAIT Chip enable I
DAM, and as WAIT when the DAM is the bus master.
Standard 280 system clock used for internal synchro·
nization signals.
- Active "low". Indicates that CPU is acknowledging an in·
terrupt, when both Ml and IORQ are active.
Active "low". Transmits and receives data from the CPU
-- Bidirectional as an input line. Acts as 10RQ for another device as an
IORQ Input/output request
3-state output line. Indicates that the CPU is acknowledging an
-- -
interrupt, when both IORQ and Ml are active.

-- Active "low". Requests a transfer from or to memory
MREQ Memory request 3-state 0
with the DMA as a bus master.
Active "high". Used to form a priority-interrupt
lEI Interrupt enable in I ,
daisy-chain.
Active "low". Used to form a priority-interrupt
lEO Interrupt enable out 0
daisy-chain.
---- Active "low". Active when requesting an interrupt. Can
INT/PULSE Interrupt request/pulse Open drain, 0
also generate pulses.
- Bidirectional Active "low". Reads data from the CPU as an input line.
RD Read -
3-state Acts as RD for another device as an output line.
- Bidirectional Active "low". Writes data from the CPU as an input line.
WR Write -
3-state Acts as WR for another device as an output line.
With the DMA as a bus master, starts DMA operation
RDY Ready I
when active, and stops it when not active.
-
----------SHARP-.--..-.-----
257
Z80/Z80A ,Direct Memory Access LH 0083/LH0083A

Operating temperature T oDe 0-+70 ·C
Storage temperature Tstg -65-+150 ·C
• DC Characteristics (Vce=5V±5%, Ta=0-+70·C)

Clock input low voltage VILe -0.3 0.45 V
Clock input high voltage VIlle Vee- 0 .6 5.5 V
Input high voltage VIII 2.0 5.5 V
IOL =3.2mA for BUSREQ
Output low voltage VOL 0.4 V
IOL =2.0 mA-for all others
Output high voltage Vall IoH =-250pA 2.4 V
Current I Z80 DMA t,=400ns 150 mA
Icc
consumption I Z80A DMA tc= 250ns 200 mA
Input leakage current I ILl I O~VIN~Vee 10 pA
3 -state output leakage current I lLOII I VouT=2.4V - -
10 pA
3-state output leakage current I lLOL I VOllT =O.4V 10 pA
Data bus leakage current in
input mode
I ILD I OV~VIN~VCC 10 pA
• Capacitance (f=IMHz, Ta=25·C)

;Unmeasured pins returned
! to ground
-~------SHARP-------'-
258
• AC Characteristics
(1) Acting as CPU peripheral (inactive state)

280 DMA 280A DMA
MIN. MAX. MIN. MAX.
1 Clock cycle time TcC 400 4000 250 4000 ns
2 Clock width (high) TwCh 170 2000 110 2000 ns
3 Clock width (low) TwCl 170 2000 110 2000 ns
4 Clock rise time TrC 30 30 ns
5 Clock fall time TfC 30 30 ns
6 Hold time for any specified setup time Th 0 0 ns
7 IORQ, WR, CE ! to clock t setup time TsC(Cr) 280 145 ns
8 RD ! to data output delay TdDO(RDf) 500 380 ns
9 Data in to clock t setup (WR or Ml) TsWM(Cr) 50 50 ns
10 IORQ ! to data out delay (INT A cycle) TdCf(DO) 340 160 ns
II RD t to data float delay (output buffer disable) TdRD(D2) 160 110 ns
12 lEI! to IORQ ! setup (INT A cycle) TsIEI(IORQ) 140 140 ns
13 lEI t to lEO t delay TdIEOr(lElr) 210 160 ns
14 lEI! to lEO ! delay T dIEOf(IElf) 190 130 ns
Ml ! to lEO ! delay
15 TdMl(IEO) 300 190 ns
(interrupt just prior to Ml ! )
16 Ml ! to clock t setup TsMlf(Cr) 210 90 ns
17 MIt to clock ! setup TsMlr(Cf) 20 -10 ns
18 RD ! to clock t setup (Ml cycle) TsRD(Cr) 240 115 ns
Interrupt cause to INT ! delay
19 - Tdl(INT) 500 500 ns
(INT generated only when DMA is inactive)
20 BAI t to BAO t delay TdBAlr(BAOr) 200 150 ns
21 BAI ~ to BAO ~ delay TdBAIf(BAOf) 200 150 ns
22 RDY active to clock t setup time TsRDY(Cr) 150 100 ns
Note : t Rising edge, ! Falling edge.
Note 1: Negative minimum setup values mean that the first-mentioned event can come after the second-mentioned event.
--~'--""-'--SHARP'--------
259
---.--. .......- ....... ............,..............-.. ........
Z80/Z80A~ Direct Memory Access
..-.-.. ~ ~ ......
,... LH0083/LH0083A"
CLK
CE. IORQ. WR.
RD
MI
lEI
lEO
INT I
Interrupt state
_________F@).JI
-----+I----~ .
:: ~1~---(-@~)----;d~----
RDY ~-@
~ _
Inactive
Acting as CPU peripheral (Inactive state)
260 .
Z80/Z80A Direct Memory Access. LH0083/LH0083A
(2) Acting as bus controller (active state) (Vco=5V±5%, Ta=0-+70"C)
Z80 DMA Z80A DMA

MIN. MAX. MIN. MAX.
1 Clock cycle time TcC 400 250 ns
2 Clock width (high) . TwCh 180 2000 110 2000 ns
3 Clock width (low) TwCl 180 2000 110 2000 ns
4 Clock rise time TrC 30 30 ns
5 Clock fall time TfC 30 30 ns
6 Address output delay TdA 145 110 ns
7 Clock t to address float delay TdC(AZ) 110 90 ns
8 Address to MREQ ~ setup (memory cycle) TsA(MREQ) (21+(5)-75 (2)+(5)-75 ns
Address stable to IORQ, RD, WR ~ setup
9 TsA(IRW) (1)-80 (1)-70 ns
(110 cycle)
*10 RD, WR t to addr. stable delay TdRW(A) (3)+(4)-40 (3)+(41-50 ns
*11 RD, WR t to addr. float delay TdRW(AZ) (3)+(4)-60 (3)+(4)-45 ns
12 Clock ~ to data out delay TdCf(DO) 230 150 ns
*13 Clock t to data float delay (write cycle) TdCr(Dz) 90 90 ns
Data in to clock t setup
TsDI(Cf)
14
15
.(read cycle when rising edge ·ends read)
Data in to clock ~ setup
TsDO(WfM)
50
60
35
50
ns
ns
4 ==
;;
*16
(read cycle when falling edge ends read)
Data out to WR ! setup (memory clcle) TsDO(WPI) (1)-210 (1)-170 ns
=
17 Data out to WR ~ setup (110 cycle) TsDO(WPI) 100 100 us
*18 WR t to data out hold time TdWr(DO) (31+(4)-80 (3)+(4)-70 us
19 Hold time for any specified setup time Th 0 0 fis
20 Clock! to MREQ ! delay TdCf(Mf) 100 85 ns
21 Clock t to MREQ t delay TdCf(Mr) 100 85 us
22 Clock ~ to MREQ t delay TdCf(Mr) 100 85 ns
23 MREQ low pulse width TwMI (1)-40 (1)-30 ns
*24 MREQ high pulse width TwMh (2)+(51-30 (21+(3)-20 ns
25 Clock t to IORQ ! delay TdCr(If) 90 75 us
26 Clock t to IORQ t delay TdCr(lr) 100 85 ns
*27 Clock! to IORQ t delay TdCr(Ir) 110 85 us
28 Clock t to RD ~ delay TdCr(Rf) 100 85 ns
29 Clock! to RD ~ delay TdCr(Rf) 130 95 ns
30 Clock t to RD t delay TdCr(Rr) 100 '85 ns
31 Clock ~ to RD t delay TdCr(Rr) 110 85 us
32 Clock t to WR ~ delay TdCr(Wf) 80 65 ns
33 Clock ~ to WR ~ delay TdCf(Wf) 90 80 ns
34 Clock t to WR t delay TdCr(Wr) 100 80 us
35 Clock ~ to WR t delay TdCf(Wr) 100 80 us
36 WR Low pulse width TwWl (1)-40 (1)-30 ns
37 WAIT to clock ~ setup TsWA(Cf) 70 70 us
38 Clock t to BUSREQ delay TdCr(B) 150 100 us
39 Clock t to IORQ, MREQ, RD, WR float delay TdCr(lz) 100 80 ns
Note : t Rising edge. ~ Falling edge
Note 1: Numbers in parentheses are other parameter numbers in this table; their values should be substituted in equations.
, Note 2: All equations imply DMA default (standard) timing.
Note 3: Data must be enabled onto data bus when RD is active.
Note 4: Asterisk (*) before parameter number means the parameter is not illustrated in the AC Timing Diagrams.
26f
Z8Q/Z80A Direct Memory Access Lti0083/ LH0083A
..~---;.,.~""",,,--,,,,,,,,,,,,,,-,-,-,,,,,, ..-,,-,,-,,,,,,,,,,,
'CLK;
DO-D7{ Input
Output
--~~--#-~---4+-----+---~
RD
WR
BUSR
Acting as bus controller (active state)
• Prpgramming • Read Register 0
The Z-80 DMA has two programmable fun-

damental states_
• an enabled state, in which it can gain control
of the system buses and direct the transfer
I Xlix
.
T~O
D7 D6 D5 D. D3 D2 Dl Do
O~I
t L: =D.MAS;;~:: ::~RED
I XI I
L O = READY ACTIVE
O=INTERRUPT PENDING
- O=MATCH FOUND .
of data between ports, and O=END OF BLOCK
• a disabled state, in which it can initiate neither ~--------------INTERRUPT PENDING
bus requests nor data'transfers. When the • Read Register 1

DMA is powered up or reset by any means, ~I~I~I~~I~I~I~~I~~' BYTE COUNTER
it is automatically placed into the disabled (LOW BYTE)
state.
(1) Reading • Read Register 2

r--"TI__I'--"-I-TI'--I'--"-I--'--'1 'BYTE CO UNT E R
The Read Registers (RRO-RR6) are read by the (HIGH BYTE)
CPU by addressing the DMA as an 110 port using
an Input instruction. The readable bytes contain
DMA status, byte-counter values, and port addres- • Read Register 3
ses since the last DMA reset. The registers are al- ,....-...--r--r-,---rr-r-...,.." PORT A AD DRES S
L-..,I--'-.....l..~~~J..-~-' COUNTER (LOW BYTE)
ways read in a fixed sequence beginning with RRO
and. ending with RR6.
• Read Register 4
1 I 1 1 PORT A ADDRESS
I-.l-...I....-'---'---I__"--...L.......I COUNTER (HIG H B YT E)
.-,------------.--..-SHARP-----.-.,.-.-.-.-.--
262
• Read Register 5 • Wr.ite Register 2

r-r--r---r-~"-""T'"""--' PO RT B AD D RE S S D, D6 Ds D. D3 D2 D, Do'
COUNTER (LOW BYTE) I 0 I I I I I 0 I 0 I 0 [ BASE REGISTER
1
I
• Read Register 6
I PORT B ADDRESS
I
BYTE
O=PORT B IS MEMORY
l=PORT B IS I/O
L..-...L.........L-~......L--J_J..-............. COUNTER (HIGH BY1IE) o =PORT B ADDRESS DECREMENTS
1 =PORT B ADDRESS INCREMENTS
o =PORT B ADDRESS VARIABLE
1 =PORT B ADDRESS FIXED
(2) Writing
~-r-'-r--r--r--'-'---.-.., PORT B VARIABLE
Control or command bytes are written into one L..-,-..J..,.....L---'---L..,..-J-.-.L..,-..J..,...J TIMING BYTE
or more of the Write Register groups (WRO-WR6)
by first writing to the base register byte in that
J=CYCLE LENGTH=4
l=CYCLE LENGTH =3
bo
group. All groups have base registers and most 1 O=CYCLE LENGTH=2
1 1 =DO NOT USE
groups have additional associated registers. The O=IORQ ENDS 112 CYCLE EARLY
associated registers in a group are sequentially 0= MREQ ENDS 1/2 CYCLE EARLY
accessed by first writing a byte to the base register 0= RD ENDS 112 CYCLE EARLY
containing register-group identification and poin- 0= WR ENDS 1/2 CYCLE EARLY
ter bits (I, s) to one or more of that base register's
associated registers. • Write Register 3
• Write Register 0
D, D6 Dj D. D3 D2 D, Do BASE
D, D6 Ds D. D3 D2 D, Do
I 1 I I I I I I 0 I 0 [ REGISTER
[ 0 I I I I [ BASE REGISTER BYTE
Jl 1 BYTE
b0 61= TRANSFER
DO NOT USE DMA ENABLE =1
INTERRUPT ENABLE=l
l=STOP
MATCH
ON
1 0= SEARCH
1 1= SEARCH/TRANSFER
O=PORT B --->PORT A [ I I I I I I I I MASK BYTE
l=PORT A--->PORT B (0= COMPARE)
I I I I [ PORT A STARTING ADDRESS [ I I I I I I I [MATCH

(LOW BYTE) BYTE
I I 1 J PORT A STARTING ADDRESS
I I I I I I I I
(HIGH BYTE)
J BLOCK LENGTH
D, D6 Ds D. D3 D2 D, Do
(LOW BYTE)
ll1 J 1 1 0 1 I BASE
I I I [ BLOCK LENGTH REGISTER
(HIGH BYTE) BY TE= b b BYTE
CONTINU OUS= 0 1
BU RST= 1 0
D, D6 Ds D. D3 D2 D, Do DO NOT PROG RAM= 1 1
I0 I I I I 1 I 0 I 0 I BASE REGISTER BYTE L [ [ I I I I I I PORT B STARTING
ADDRESS (LOW BYTE)'
~
I b=PORT
l=PORT
A IS MEMORY
A IS I/O I PORT B STARTING
ADDRESS (fiG" BYTE)
o =PORT A ADDRESS DECREMENTS
1 =PORT A ADDRESS INCREMENTS INTERRUPT CONTROL BYTE
o = PORT A ADDRESS VARIABLE 0
1 =PORT A ADDRESS FIXED
INTERRU PT j 1=INTERRUPT ON
MATCH
j
I I I I [ J ~?~1t i'f-lJABLE ON R DY=l
STATUS AF FECTS
l=INT ERRUPT AT
EN D OF BLOCK
VE CTOR=l l=PULSE GENERATED
b J=CYCLE LENGTH=4
[ I I I I I I r [ PULSE CONTROL
o l=CLCLE LENGTH =3
BYTE
1
1
O=CYCLE LENGTH =2
l=DO NOT USE
!
INTERRUPT
[ I I [
VECTOR'
O=IORQ ENDS 112 CYCLE EARLY I I
O=MREQ ENDS 112 CYCI;E EARLY VECTOR IS AUTOMATICALLY { 0 o = INTERRUPT ON RDY
O=RD ENDS 112 CYCLE EARLY
MODIFIED AS SHOWN 9 1o == INTERRUPT ON MATCH
INTERRUPT ON END
ONLY IF" STATUS 1 OF BLOCK
O=WR ENDS 112 CYCLE EARLY
AFFECTS VECTOR" BIT IS SET i 1 = INTERRUPT ON MATCH
AND END OF BLOCK
263
.---....--AIIIIIIiII'-............
. Z80/Z80A Direc.t. Memory Ac.cess
• Write -Register 5
-~-~- . . ....-
LH0083/L:H0083A
~
....:...&..---I.-r-....,..~...,L...;.......~~
BASE REGIS TER
BYTE
O=REApy ACTIVE LOW /
'. 1 == READY ACTIVE HIGH
O'=CE ONLY
l=CE!WAIT MULTIPLEXED
STOP RESTART ON END
O=STOP ON END OF BLOCK
l=AUTO REPEAT ON END ,QF BLOCK
D7 D6 Ds D. D3 D2 DJ Do
I1I I I I I I1I1 I BASE REGISTER BYTE
I I I I I
C3 1 0 0 0 0 INTERRUPT LINE RESET, INTERRUPT REQUEST AND BUS REQUEST DISABLE,
INTERNAL READY STATE CLEAR, CE MULTIPLEX DISABLE, AUTOMATIC REPEAT
STOP
C7 1 0 0 0 1 PORT A TIMING TOZ80 STANDARD TIMING
CB 10010 PORT B TIMING TO ZIlO STANDARD TIMING
CF 1 0 0 1 1 BOTH PORTS START ADDRESS LOAD, BYTE CaNTER CLEAR
D3 1 0 1 0 0 ADDRESS CONTINU):': FROM CURRENT VALUE, BYTE COUNTER CLEAR
AB o 1 0 1 0 INTERRUPT ENABLE
AF o 1 011 INTERRUPT DISABLE
A3 o 1 0 0 0 INTERRUPT CIRCUIT RESET AND DISABLE (SAME AS RETI) , INTERNAL READY
STATE CLEAR
87 o 0 0 0 1 DMA ENABLE} EFFECTIVE FOR ALL SECTIONS BUT INTERRUPT.
83 o 0 0 0 0 DMA DISABLE NOT ALL FUNCTIONS RESETTABLE, HOWEVER
A7 o 1 0 0 1 READ SEQUENCE START FOR 1ST REGISTER DESIGNATED BY READ MASTER
REGISTER .
BF o 1·1 1 1 STATUS REGISTER READ SETUP. FROM STATUS REGISTER FOR NEXT READ
B3 o 1 1 0 0 INTERNAL READY STATE TO BE FORCEDLY CLEAR OF "RDY" PIN (USED. FOR
DMA BETWEEN MEMORIES NEEDING NO RDY SIGNAL. NOT OPERATIVE IN "BYTE
.MODE")
88 o 0 0 1 0 REINITIALIZE. END-OF-BLOCK BIT CLEAR
B7 o 1 101 ENABLE AFTER RETI. BUS REQUEST ONLY AFTER RETI EXECUTION
BB o 1 1 1 0 READ MASK FOLLOWS
I 0 I I I I II I
! I READ MASK (I=ENABLE)
1 1'-------BYTE
STATUS BYTE
fL'_ _ _
- BYTE COUNTER (LOW 'BYTE)
COUNTER (HIGH BYTE)
L _L_-_-_-_-_-=--=--=--=--=--=PORT A ADDRESS 1LOW BYTE)
L_ _ _ _ _ _ _ _ PORT A ADDRESS HIGH BYTE)
PORT B ADDRESS LOW BYTE)
'-----------PORT B ADDRESS HIGH BYTE)
264
Z80/Z80A Direct Memory Access . LH0083/LH0083A
• Timing wait cycle between T2 and T3. If the CE/WAIT line

is programmed to act as aWAIT line during the
(1) Inactive state timing (DMA as CPU DMA's active state, it is sampled on the falling edge
. Peripheral)
of Tz for memory tr~nsactions a~d the falling edge
In its disabled or inactive state, the DMA is of Tw for I/O transactions. If CE/W AIT is Low
addressed by the CPU as an I/O peripheral for during this time another T -cycle is added, during
write and read (control and status) operations. which the CE/W AIT line will again be sampled.
Write timing is illustrated in Fig. 1. The duration of transactions can thus be indefinite-
Reading of the DMA's status byte, byte counter ly extended.
or port address counters is illustrated in Fig. 2.
(2) Active state timing (DMA as BUS CLOCK~

Controller)
(i) Default read and write cycles
W:Q -hLd::::::
-+-++---+-.. .cb
By default, and after reset, the DMA's timing of
read and write operations is exactly the same as Do-D7
the Z-80 CPU's timing of read and write cycles for
men:lOry and 110 peripherals, with one exception: Fig. 1 CPU-DMA write cycle timing
during a read cycle, data is latched on the falling
edge of T3 and held on the data bus across the
boundary between read and write cycles, through
th'e end of the following write cycle.
Fig. 3 illustrates the timing for memory to-I/O
port transfers and Fig. 4 illustrates IIO-to-memory
transfers. Memory-to-memory and I/O-to-I/O
transfer timings are simply permutations of these
diagrams.
The default timing uses three T -cycles for mem- Fig. 2 CPU-DMA Iread cycle timing
ory. transactions and four T -cycles for 110 transac-
tions, which include one automatically inserted
.---'---.---SHARP....--.--.--.-.~--
265
Z60!Z80A Dire.ct Memory Access LH00J33!LH0083A
.....................,.....__....,_ _ _....,.-r.__... -.:~....,.- __ ~_.
I+-- Memory Read I/O Write
n-~
TJ
. . . ~ ~r-Lr-~ L
T2 T3 Tl Tz ' Tw T3
,....
.' CLOCK
--
'--
X X L
MREQ \ I
Read {
RD
\ J
: Write
{
IORQ
_
1\ r~
WR \ rr--
Do-D7 \ l)-
-- ---- ·7 r- ---- ---- --- 7 ..,- ---- r--
-- ---- ... ----
oJ
\
1---- -' ""1---- ---
\
Fig. 3 Transfer from memory to 1/0 device
I/O Read Memory Write --;0
Tl T2 Tw T3 Tl Tz T3
- rLlLr- ~n- ~r--~~

~
CLOCK
- X X I'X
-
_ {IORQ \ I
,Read .-
RD ' \ I
l}-
MREQ
\
\ I
Write { _
WR
I\..W
-- ---- ---- ---- ---- ---- ---
CE/WAIT
-- --- ---_. J \ T \: ---
Fig. 4 Transfer from 1/0 device to memory
(ii) Variable cycle and edge timing The from action on the RDY line. The DMA always
Z-80 DMA's default operation-cycle length for the completes its current byte operation in an orderly
source (read) port and destination (write) port can fashion before releasing the bus.
be independently programmed. This variable-cycle By contrast, BUSREQ is not released in Con-
feature allows read or write cycles consisting of tinuous mode when RDY goes inactive.
two, three or four T-cycles (more if Wait cycles Instead, the DMA idles after completing the current
are inserted), thereby increasing or decreasing the byte operation, awaiting an active RDY ~ain.
speed of all signals generated by the DMA. ~ddi (vii) Bus release on match If the DMA is
tion, the trailing edges of the IORQ, MREQ, RD and programmed to stop on match in Burst or Con-
WR signals can be independently terminated tinuous modes, a match causes BUSREQ to go inac-
one-half cycle early. Fig. 5 illustrates this. tive on the next DMA operation, i.e., at the end of
In the variable-cycle mode. unlike default timing, the next read in a search or at the end of the fol-
IORQ comes active one-half cycle before MREQ, lowing write in a transfer (Fig. 10). Due to the
RD and WR. CE/W AIT can be used to extend only pipelining scheme, matches are determined while
the 3 or 4 T-cycle variable memory cycles and the next DMA read or write is being performed.
only the 4-cycle variable 110 cycle. The CE/W AIT The RDY line can go inactive after the matching
line is sampled at the falling edge of T2 for 3-or. operation begins without affecting this bus-release
4-cycle memory cycles, and at the falling edge of timing.
T3 for 4-cycle 110 cycles. (Viii) Interrupts Timings for interrupt ack-
During transfers, data is latched~ the clock nowledge and return from interrupt are the same
edge causing the rising edge of RD and held as timings for these in other Z-80 peripherals. (Re-
through the end of the write cycle. fer to the Z80 PIO.)
(iii) Bus requests Fig. 6 illustrates the bus Interrupt on RDY (interrupt before requesting
request and acceptance timing. The RDY line, bus) does not directly affect the BUSREQ line. In-
which may be programmed active High or Low, is stead, the interrupt service routine must handle
sampled on every rising edge of CLK. this by issuing the following commands.
If it is found to be active, and if the bus is not in a. Enable after return from interrupt (RETI)
use by any other device, the following rising edge (Command code 87H)
of CLK drives BUSREQ low. After receiving BUS- b. Enable DMA (Command code 87H)
REQ the CPU acknowledges on the BAI input c. An RETI instruction
either directly or through a multiple-DMA daisy
chain. When a Low is detected on BAI for two con-
secutive rising edges of CLK, the DMA will begin
transferring data on the next rising edge of CLK.
(iv) Bus release byte-at-a-time In Byte at
a Time mode. BUSREQ is brought High on the ris-
ing edge of CLK prior to the end of each read cycle
(search-only) or write cycle (transfer and transferl
search) as illustrated in Fig. 7. This is done regard-
less of the state of RDY.
The next bus request fo!:.l!!e next byte will come
after both BUSREQ and BAI have returned High.
(v) Bus release at end of block In Burst
and Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Fig. 8). The last byte in
the block is transferred even if RDY goes inactive
before completion of the last byte transfer.
(vi) Bus release on not ready In Burst
mode, when RDY goes inactive it causes BUSREQ
to go High on the next rising edge of CLK after the
completion of its current byte operation (Fig. 9).
The action on BUSREQ is thus somewhat delayed
-.-.-----.-.--SHARP..-......-------
267
Z80/Z80A Direct Memory Access LH0083lLH0083A
-...r.-_......_ ..- I r - . - . - . - . - . -_ _..._-.:,..-.-.-
CLOCK
"""\r---
Ao-AIS .J1'- __ _
-...J,----I-'
MREQ ~r T-,--r-T ,, - - -
- - I , ,
I I
RD, WR .L_..I_ L._.L_ I '
• 2 CYClE 3 ~YCLE ~ CYCLE '

EARLY END EARLY END EARLY END
Fig. 5 Variable cycle and edge timing
CLOCK
-INACTIVE
-B-U-SR-Q- ==~::_j-rt-----1'"'". --t I---+_+-_-+__+-__
I
BAl __ J I
DMA DMA
INACTIVE ACTIVE
Fig. 6 Bus request and acknowledgement
CLOCK ~~. _ _ _ _ _ _ _ _ _ _ __
BUSRQ-HI
I
I
BAI I I
i I"'D'M.A
DMA
ACTIVE --+- INACTIVE
Fig. 7 Bus clear (byte mode)
268
Z80lZ80A Direct Memory Access LH0083lLH0083A
CLOCK ---ILnY
ACTIVE
RDY INACTIVE
LAST BYTE
L OPERATION--i.......-DMA INACTIVE
r - IN BLOCK
Fig. 8 End of block bus clear (burst, continuous mode)
ACTIVE
RDY INACTIVE ~.~_ _ _-I-_ _ _ _ _ __
BUSRQ
'- CURRENT BYTE
iOPERATION DMA INACTIVE
Fig. 9 No READY bus clear (burst mode)
RDY INACTIVE
BUSRQ --~I-.----i~'~-~I~B~Y~T~E~n~+~l~R~E~A~D~~
BYTE n - + I N MATCH FOUN DMA INACTIVE
READ IN ON BYTE n
Fig. 10 Mating bus clear (burst, continuous mode)
------~-----SHARP .. . . . - . - . - . - - - - - -
269
................ -........... -........-..... - . - . . -.........................
l80/l80A/l80B Serial Input/Output Controller LH0084/84A!84B/85/85A/85B/86/86A/86B
LH0084/LH0084A/LH0084B .
LH0085/ LH0085A/LH0085B Z80/Z80A<Z80B Serial
LH0086/LH0086A/LH0086BInputiOutput Controller
The 280 product line is a complete set of micro- LH0084/LH0084A/LH0084B
support software_ The 280 microcomputer com- o
build high-performance microcomputer systems
The LH0084/85/86, 280 SIO (280 SIOfor
short below) is a dual-channel multi-function
peripheral component designed to satisfy a wide
lEO 7
·i.
LH0085/LH0085A/
LH0085B
RxDB
:: RxCB
SYNCB
...•. TxCB
variety of serial data communications requirements
,. TxDB
in microcomputer systems. Its basic function is a W/RDYA 10 31 GND
serial-to-parallel, parallel-to-serial converter / SYNCA 11 30 W/RDYB
controller, but-within that role-it is configurable
~.. SYNCBLH0086/LH0086A
by systems software so its "personality" can be
::~=c~Hio08~XDB
RxCA
optimized for a given serial data communications
TxCA
application.
TxDA TxDB .. RxCB
The 280 SIO is capable of handling asynchro·
~:~:
nous and synchronous byte-oriented protocols DTRA
RTSA RTSB •••..:.
such as IBM Bisync, and synchronous bit-oriented
protocols such as HOLe and IBM SOLe. This ver- CTSA CTSB ~ .. DTRB
satile device· can also be used to support virtually DCDA 19
any other serial protocol for applications other CLOCK
than data communications (cassette or floppy disk Top View
interfaces, for example).
The 280 SIO can generate and check eRe codes 2. Single + 5V power supply and single phase
in any synchronous mode and can be programmed clock
to check data integrity in various modes. The de- 3. Two independent full duplex channels
vice also has facilities for modem controls in both 4. Data rates: 0 to 500K bits/second (at 2.5 MHz
channels. In applications where these controls are system clock)
not needed, the modem controls can be used for : 0 to 800K bits/second (at 4MHz system clock)
general-purpose I/O_ : 0 to l200K bits/second (at 6MHz system clock)
The 280. SIO has six types as below according 5. Asynchronous operation
irs system clock and bonding option_ The 280A • 5, 6, 7 or 8 bits/character
SIO and the 280B SIO are a high speed version • 1, lY2 or 2 stop bits/character
which can operate at the 4MHz and 6MHz system • Even, odd or no parity
clock, respectively. • Xl, X16, X32 and X64 clock modes
• LH0084 280 SIO/O • LH0084B Z80B SIO/O • Break generation and detection
• LH0085 280 SIOIl • LH0085B Z80B SIO/l • Parity, Overrun and Framing error detec-
• LH0086 Z80 SIOI2 • LH0086B Z80B SIO/2 tion
• LH0084A Z80A SIOIO 6. Binary synchronous operation
• LH0085A Z80A SIOIl • Internal or external character synchroniza-
• LH0086A Z80A SIO/2 tion
• One or two Sync characters in separate reg-
isters
• Automatic Sync character insertion
• Features • eRe generation and checking
1. N-channel silicon-gate process 7. HOLe or IBM SOLe operation
.-..-------SHARP.---..-.i--.----~
270
Z80/Z80A/Z80B Serial Input/Output Contorller LH0084/84A184B/85/85A185B/86/86A186B
• Abort sequence generation and detection • CRCgeneration and checking

• Automatic zero insertion and detection 8. Vectored daisy chain priority interrupt logic
• Automatic flag insertion 9. CRC-16 or CRC-CCITT block check
• Address field recognition 10. Separate modem control inputs and outputs for
• I-field residue handling both channels
• Valid receive messages protected from over- 11. Modem status can be monitored
run 12. 40-pin dual-in-line package
• Block Diagram
12 Receive Data A
13 Receive Clock A
15 Transmit Data A
A 14 Transmit Clock A
~
-10 Wait/Ready A
Channel A
Internal 11 !Extarnal Charactor
Control and
Control Synchronization A
Status
Logic Request To
Registers 1 Send A
System Data Bus 18 Clear To Send A
~
16 Data Terminal
e" Ready A
0" 19 Data Carrier
Detect A
----=
Q.
~ '24 Request To
<Il
Send B
Chip Enable '23'Clear To Send B
"
.0
Data Terminal
~ Ready B ~
Machine Cycle 1 8 0..
U Channel B 22 Data Carrier
Interrupt Detect B
I/O Request Control Control and
Read Logic Status Receive Data B
Command/Data Registers Receive Clock B
Select
Channel Select Transmit Data B
B Transmit Clock B
30 Wait/Ready B
External Charactor
Synchronization B
Bonding option is as below
SYNCB SYNCB ... RxDB

RxDB RxDB RxCB
RxTxCB RxCB TxCB
TxDB TxCB TxDB
DTRB TxDB DTRB
SIO/O SIO/l SIO/2
271
Z80YZ80AlZ80B Serial Input/Output Controller LHOO84/84A184B/85/85A185B/86/86A186B
.. Pin Description
Bidirectional
Do-D 7 · Data bus System data bus
3-state
- Defines which channel is accessed. Channel B at "High",
B/A Channel A or B select I
channel A at "Low".
-
"' Defines the ty·pe of information transfer on the data bus.
C/D Control or data select I
Control word at "High", data at "Low".
- , Active "Low". A Low enables the CPU to transmit and
CE Chip enable I
receive control words and data.
Standard 280 system clock used for internal synchro-
CLOCK System clock , I
nization signals.
- I
Active "Low". Indicates that the CPU is acknowledging
an interrupt, when both Ml and IORQ are active.
-- write operation when it is not active. Indicates that the
IORQ Input/output request I
CPU is acknowledging an interrupt, when bbth IORQ
-
and Ml are active.
RD Read cycle status I Active "Low". Read operation when active,
RESET Reset I Active "Low". Resets the interrupt bits.
Active "High". Used to form a priority-interrupt daisy
lEI Interrupt enable in I
chain.
Active "High:' Used to form a. priority-interrupt daisy
chain.
INT Interrupt request Open drain, 0 Active "Low". Active when requesting an interrupt.
W/RDYA Active "Low". READY when ~he DMA is a bus master,
--- Wait/ready Open drain, 0 --
W/RDYB WAIT when the CPU is a bus master.
---- Active "Low". Enables the respective transmitters. Also
CTSA,CTSB Clear to send I
applicable as general-purpose input pins.
---- Active "Low". Enables the respective receivers. Also ap-
DCDA, DCDB Data carrier detect I
plicable as general-purpose input pins.
RxDA, RxDB Receive data I Active "Low". Data line for receiving
TxDA, TxDB Transmit data 0 Active "Low". Data line for transmitting.
RxCA, RxCB Receiver clock I Active "Low". Receiving synchronization clock.
TxCA, TxCB Transmitter clock I Active "Low". Transmitting synchronization clock.
Active '.'Low". Indicates that the transmitter is empty
----
RTSA,RTSB Req uest to send 0 during transfer. Also applicable as general-purpose out-
put pins.
---- Active "Low". Also applicable as general-purpose out-
DTRA,DTRB Data terminal ready 0
put pins.
--- Active "Low". Acts the same way as CTS and DCD in
SYNCA, External character
I the asynchronous mode. Driven "Low" in the synchro-
SYNCB synchronization
nous. mode when a synchronizing pattern is achieved.
---:--.---~---,.~--SHARP - - - - - - - - - - - -
272· ,
.........-..-......-..............-......................-.
Z80lZ80AlZ80B SeriallnputlOutput Controller
.-..-.
LH0084184A184BI85/85A185B/86/86A186B
. ' Absolute Maximum Ratings

• DC Characteristics (Vee=5V±5%. Ta=0-+70"C)

Clock input high voltage V lEe Vcc-0.6 5.5 V
Input high voltage VIII 2.0 5.5 V
Output low voltage VOL IOL=2.0mA 0.4 V
Output high voltage VOIl IoH =-250 pA 2.4 V
Input leakage current I ILl I O<VIN<Vee 10 ~A
3 -state output! data
bus input leakage curreut
I Iz I 0<V1N<Vee 10 pA
SYNC pin leakage current I LSY 0<V1N<Vee -40 10 pA
Current consumption Icc 100 rnA
• Capacita!,,!ce (f=lMHz. Ta=25"C)

Input capacitance C1N 5 pF
to ground
(1 ) AC characteristics ( I )
Z80 SIO Z80A SIO Z808 SIO
1 Clock cycle time TcC 400 4000 250 4000 165 4000 ns
2 Clock width (high) TwCh 170 2000 105 2000 70 2000 ns
5 Clock width (low) TwCl 170 2000 105 2000 70 2000 ns
6 CEo C/D. 8/ A to clock t setup time TsAD(C) 160 145 60 ns
7 IORQ. RD to clock t setup time TsCS(C) 240 115 60 ns
8 Clock t to data out delay TdC(DO) 240 220 150 ns
Data in to clock t setup
9 TsDI(C) 50 50 30 ns
(Write or M1 cycle)
10 RD t to data out float delay TdRD(DOz) 230 110 90 ns
IORQ ! to data out delay
11 TdIO(DOI) 340 160 100 nS'1
(I NT ACK cycle)
~~-------SHARP.-.----.----
273
Z80/Z80AlZ80B Serial InpuVOutput Controller LH0084/84A184BI85/85A185B/86/86A1868
Z80 SIO Z80A SIO Z80B SIO

12 Ml to clock t setup time TsMl(C) 210 90 75 ns
lEI to IORQ ~ setup time
13 TsIEl(IO) 200 140 120 ns
(INT ACK cycle) /
Ml ~ to lEO ~ delay
14 - TdM 1 (lEO) 300 190 16"0 ns
(interrupt before MlJ
15 IEl t to lEO t delay (after ED decode) TdlEl(IEOr) 150 100 70 ns
16 lEI ~ to INT ~ delay TdlEl(IEOf) 150 100 70 ns
17 Clock t to INT ~ delay TdC(INT) 200 200 150 ns
IORQ ~ or CE ~ toW IRDY ! delay
18 TdIO(W IRWf) 300 210 175 ns
(wait mode)
Clock t to W IRDY ! delay
19 TdC(W/PR) 120 120 100 ns
(ready mode)
Clock ~ to W IRDY float delay
20 TdC(W/RWz) 150 130 110 ns
(wait mode)
Any unspecified hold
21 Th 0 0 0 ns
when setup is specified
t Rising edge, ! Falling edge.
(2) AC timing chart ( I )
CLK
CE,C/D,B/A
IORQ,RD
RD
IORQ
Ml
lEI
lEO
~NT
-~.~~----......-r--SHARP ...-.-------~~~..--.
274
Z80/Z80A/Z80B Serial Input/Output Controller LH0084/84A184B/85/85A185B/86/86A186B
(3) AC characteristics (I)

Z80 SIO Z80A SIO Z80B SIO
1 Pulse width (high) TwPh 200 200 200 ns
2 Pulse width (low) TwPI 200 200 200 ns
3 TxC clock time TcTxC 400 00 400 00 330 00 ns
4 TxC width (low) TwTxCI 180 00 180 00 100 00 ns
5 TxCwidth (high) TwTxCh 180 00 180 00 100 00 ns
6 TxC +to TxD delay (xl mode) TdTxC(TxD) 400 300 220 ns
Clock
7 TxC +to W IRDY +delay (ready mode) TdTxC(W IRRf) 5 9 5 9 5 9 period
Clock
8 TxC +to INT +delay TdTxC(INT) 5 9 5 9 5 9 period
9 RxC cycle time TdRxC 400 00 400 00 330 00 ns
10 RxC width (low) TwRxCI 180 00 180 00 100 00 ns
11 RxC width (high) TwRxCh 180 00 180 00 100 00 ns
12 RxD to RxC t setup time (xl mode) TsRxD(RxC) 0 0 0 ns
13 RxC t to RxD hold time (xl mode) ThRxD(RxC) 140 140 100 ns
Ciock
14 RxC t to W IRDY +delay (ready mode) TdRxC(W IRRf) 10 13 10 13 10 13 period
Clock
15 RxC t to INT +delay TdRxC(INT) 10 13 10 13 10 13 period
Clock
16 RxC
-_ ...
t to SYNC +delay (output modes) TdRxC(SYNC) 4 7 4 7 4 7 period
SYNC +to RxC +setup
17 TsSYNC(RxC) -100 -100 100 ns
(external sync modes)
t Rising edge, l Falling edge
Note: In all mode, the System Clock rate must be at least five times the maximum data rate.
(4) AC timing chart (I)
TxD
iE-----(7'J----i
W/RDY
--------~I-~~---~~~-~®~-------~\l~:/
RxD
W/RDY
.--..-------SHARP---------
275
.....~--- ...........
Z80/Z80AlZ8Q8 Serial·lnputiOutput Controller
•. Transmit and Receive Data Path

~.--. ...... ......
I;H0084/84A/848/8pI85A1858/86/86A/868
~....,~~ .-...;~---...., ....
CPU 1/0
To. Channel B. ._ _ _ _ _ _ _~_ _ _ _-'-_ _-""'''--_ _ _ _~_ _ _ _ _ _ _ _ _-,

External Status Lo.gic
Co.ntro.l Logic etc. ----------::""'""----"7'<:::-------,
Data
Fig. 1 Transmit and receive data path .
• Programming
The system program first issues a series of com-
mands that initialize the basic mode of operation
• Read Register 1 (RR 1)
The RRI contains the status bits for specific
receiving coditions as well as the one-field fraction
codes for the SDLC receive mode.
and then other commands that qualify conditions
within the selected mode.
Both channels contain registers that must be
programmed via the system program prior to op-
eration_
(1) Read Registers
The SIO contains three read registers for Chan- • Read Register 2 (RR 2)
nel B and three read registers for Channel A
(RRO-RR2) that can be read to obtain the status in- D7 Da Ds D. D3 Dz DI Do
formation. The status information includes error V7 I Va Vs V, V3 V2 VI Vo
conditions, interrupt vector and standard communi- y
Valiable if .. status affects
cations-interface signals vecto.r" is pro.grammed
• Read Register 0 (RR 0)
Da Ds Dz Do
Break Tx. CTS Sync DCD Tx INT Rx char· (2) Write Registers
/abort under· Ihunt buffer pending acter The SIO contains eight write registers fo·r Chan- .
run empty (ch.A) avail·
IEOM o.nly able nel B and eight write registers for Channel A
(WRO-W,R7) that are programmed separately to
configure the functional personality of the chan-.
nels.
---~-----~SHARP-------""-~-~-
276
Z80/Z80AlZ80B Serial Input/Output Controller LH0084/84A184B/85/85A185B/86/86A186B
• Write Register 0 (WR 0) • Write Register 4 (WR 4)

The WR4 has the bits control both receivers and
D6 Ds D2 DJ Do
transmitters.
CRC CRC Command Command Command Pointer Pointer Pointer
reset reset bit bit bit bit bit bit In initializing for transmitting and receiving,
code code 2 1 0 2 1 0 these bits must be set up before the WR1, WR3,
1 0
, V
II.
V
WR5, W:R6, and WR7.
Control words Register pointers
.Write Register 1 (WR 1)
D6 Ds Do
Wait/ Wait/ Wait/ Receive Receive Status Tx Ext
ready ready ready inter: inter· affects INT INT
enable function onR/T rupt rupt vector enable enable • Write Register 5 (WR 5)
mode I mode 0
The WR5 contains the bits (except for D,) to
control the transmitters.
• Write Register 2 (WR 2)

D6 Ds D, DJ Do
The WR2 contains the interrupt vector for both DTR Txbits Txbits Send Tx CRC16 RTS Tx
channels and is only in the Channel B. When the /char- /char- break enable /SDLC CRC
status affected vector (WR1, D,) is 1, the vector acter acter enable
1 0
from the SIO during the interrupt acknowledge cy-
cle varies (V 3 - V,) depending on the interrupt con-
ditions_ The WR2 contents do not vary then. • Write Register 6 (WR 6)
D7 D6 Ds D, D3 Do
v, I Vo I Vs I v. I V3 VJ Vo
• Write Register 3 (WR 3)

The WR 3 contains the bits and parameters to • Write Register 7 (WR 7)
control the receivers_
D6 D5 D, DJ Do
Rx bits Rx bits Auto Enter Rx Address Sync Rx
char- char- enable hunt CRC search charae" enable
aeter aeter phase enable mode ter load
1 0 inhibit
277
... _---.-.....- -................_------
Z80/Z80AlZ80B Serial Input/Output Controller
• Timing
. LHOOa4l84A184B/85/85A185B/86/86A186B
ated by a 2-80 CPU output instruction to write a

data or control byte into the SIO.
(1) Read cycle
{3) Interrupt cycle
The timing signals generated by a 2-80 CPU in- The interrupt-acknowled~ing and return-fr-
put instruction to r.ead a data or status byte from om-interrupt cycles are of the same timing as for
the SIO are illustrated in Fig_ 2. other 280 peripherals. (Refer to the 280 PIO.)
(2) Write cycle
Fig. 3 illustrates the timing and data signals gener-
Tw T3
CLOCK
Channel address
RD
Ml
DATA ---------------« Output )>--:---

Fig. 2 Read cycle timing
T\ T2 Tw T3 T\
CLOCK
CE Channel address
IORQ
RD
Ml
DAtA
X Input
X
Fig. 3 Write cycle timing
278
Floppy Disk Controller LH011 O/LH011 OA
LH0 11 0/ LH0 110A Floppy Disk Controller

The LHOllO is a micro-program controlled
Floppy Disk Controller (FDC) designed as one of
the Z80 peripherals.
The LHOllO is fabricated with N-channel sili· 06
con-gate process technology, and packaged in a 07
40-pin dual-in-line package.
INT
The LHOllO provides a TTL compatible inter·
MUXS
face and requires a single + 5V power supply.
ROY
lOX
WP/TRo
VFO
• Features LCT/DIR 11 lEO
RS2 ORQ
1. Can be connected directly to the Z80 CPU bus
FRISTP
• Daisy chain interrupt signal
• Interrupt vector output RSo PSL
• Recognition of the Z80 CPU RETI instruc· CLOCK 15
tion WOA
2. DMA or program controlled data transfers WG
3. Separate clocks for system control and FDD RRO
control. IORQ WOW
4. Can be connected to other microprocessors FCLK 21 GNO
5. IBM format compatible Top View
• Single-sided, Dual-sided (FM)
Dual-sided double-density (MFM)
• FM: 128,256,512 bytes/sector 16. Interrupt enable and disable are programmable
MFM: 256, 512,1024 bytes/sector 17. Window inversion is programmable
• 8, 15, 26 sectors/track 18. Input/Output is TTL compatible (except for
6. Can control minifloppies (change the 2MHz clocks)
FCLK to a 1MHz clock)
7. Can control 2 dual-sided double-density floppy
disk drives (4 single-sided drives)
8. A wealth of commands including VERIFY
command
*Can be specified as head load or head unload
9. A wealth of error status indicators available
during command processing
10. CRC generation and checking (X16+X12+X5+ 1)
11. Deleted data address mark (DDAM) processing
capabilities
12. Multi -sector processing capabilities
13. Signals generated for adjusting write data
under MFM recording
14. Inner track processing capabilities
15. Stepping speed, head load time and head unload
time after command processing' are program·
mabie
--'--'~--'--"-SHARP . - . - - - - - - - - - - -
279
,
N
00
.0
1 • I'l
to
I .1 ~
0"
()
7'
I I9
C"l"l C"lUl C
0"0
~C"l
-""~
o CIl
""'-'" S"
I;
9
co
....
I
I\)
3
I Write
::;;: :0
:0 :0
0 0
::0
'"rn
1!9.
.....,
I '"
I
::;;: :0
:0 :0 Ul Machine Cycle I-
Unit Select ..... ..... ..... ~
I Head Load 00
H~ad Select <D
"l
0
0
::;;: :0
..,::0 ..,:0
Read
Chip Enable
I/O Request
I
VFO Control .... C"l
Low Current/Direction .... 0 ::;;: :0
~ :0 :0
"i
I
en Write Gate ~ w w
I Write Data t'"' ::;;: :0

»
N
Preshift Early
Preshift Late
0
'!9.
"
.,. .,.:0
:0
System Data Bus

Faul t Reset/Step '" ~ :0
'C Multiplexed FDD Input to> :0 :0
CJ1 CJ1
Signal ~elect ::
I
/1 Wmdow'"
Read Raw Data l:l
::;;:
:0
:0 :0
0'> en
L :os::
::;;:
...,:0
I
I
0-' Interrupt Enable In
s::;;0 Data Request
I ..
'I::l
"i
0
"i
9
I~terrupt Enable Out
Interrupt Request
..,....
I
h
....
<>
<:
"" "0z
I +
C11
<:
<:>
<:
I I~
I' I~
• Pin Description
Bidirectional
Do-D 7 Data bus System data bus
3-state
Used to select FDC internal register (RRO-RR6, WRO-
RSo-RS2 Register select I
WR7).
- Active low. Produced by ANDing Ml and RESET' of
Ml Machine cycle 1 I
CPU. Active Ml with IORQ causes interrupt.
RD Read cycle I Active low. Read operations proceed when active.
- Active low. Command or data transactions with CPU
CE Chip enable I
possible when active. ,
Active low. Active RD designates read operation; inac-

-
-- tive RD designates write operation.
IORQ 110 request I -- -
Interrupt occurs when IORQ and Ml are simultaneously
active.
Standard Z80 system clock is used as internal sync
signal.
2-MHz clock is used for synchronizing FDD control sig-
FCLK FDC clock I
nal(l-MHz clock for mini-floppy control).
Active high. Used to form interrupt priority arbitration
lEI Interrupt enable input I
loop circuit (daisy chain).
IEO Interrupt enable output. 0 Active high. Used with IEI to form daisy chain.
INT Interrupt request Open-drain 0 Active low. Active when placing interrupt request.
Active high. Data request signal for transactions be-
DRQ Data request to DMA 0
tween FDC and DMA.
MUXS Multiplex 0 Multiplexer select signal.
Active high. WP signal at high MUXS, indicating that
WP/TRo Write protect/track zero I mounted diskette is write-protected. TRo signal at low
MUXS, indicating that the head is positioned at track O.
Active high. FL T signal at high MUXS, indicating fault
FLT/TS Fault/2-side disk I status of FDD. TS signal at low MUXS, indicating that
2-side disk is mounted.
Active high. FR signal at high MUXS, resetting fault sta-
FR/STP Fault reset/step 0
tus of FDD. STP signal at low MUXS, indicating seek.
Active high. Connected to FDD low current input and
direction input. Denotes LCT signal except when seek
command is in effect, becoming high when head selects a
LCT/DIR Low current/direction 0
cylinder above track 44. DIR signal during seek com-
mand, becoming high when seek direction is toward disk
center (from perimeter).
RDY Ready I Active high. FDD ready signal
Active high. Indicates the physical starting point on the
IDX Index I
disk track.
With double-sided FDD, low HDS selects head 0 ; high
HDS Head select 0 HDS selects head 1. With single-sided FDD, HDS can be
used as FDD select signal.
HDL Head load 0 Active high. Puts the FDD head in load state.
US Unit select 0 Active high. Selects FDD unit.
WG Writing gate 0 Active high. Write command to FDD.
WDA Write data 0 Active high. Serial data transferred to FDD.
RRD Read data I Active high. Serial data from FDD.
Released by VFO circuit, used in separating RRD data
WDW Window I
and clock.
------------------SHARP - - - - - - - - - - - -
281
Pin' Meaning 110 Function

VFO VFO control, 0, Active high. Advises lock timing'to VFO'circuit.
,
Active high. Write correction signal in MFM mode, in-
PSL Pre·shift 0 structing external write-correction circuit to delay
WDA. Maintains active status in FM mode.
Active high. Write-cortectionsigTIal in MEM mode, in·
P~E Pre·shift early 0 structing external write· correction circuit to accelerate
WDA. Maintains active status in FM mode.
*Resetting FOC FOC has no reset terminal, but by maintaining Ml at low for more than 2-c1ock lengths when both IORQ and RD,are high,
the FOC's intern~1 reset flag is set and FDC reset is in effect. Reset status can be released by making access to an FOC register.

Parameter Syoibol Ratings Unit
'Output voltage VOUT -0.3-+7 V
• DC Characteristics (V cc =5V±5%, Ta=0-+70t)

Clock input low voltage VCL -0.3' 0.45 V
Clock input high voltage VCH Vee-0.6 Vee + 0.3 V
Output high voltage VOH IOH =-250pA 2.4 V
Input leakage current I ILl I OsVINsV CC 10 pA
Data bus 110 leakage current I Iz I O~VIN~VCC 10 pA
Supply current Icc

I LHOllO 170
rnA
I LHOllOA 180
• Capacitance (f=IMHz, Ta=25t)

Parameter Symbol Conditions MIN. MAX. Unit
Clock input capacitance CCLOCK 10 pF
Input capacitance CIN All pins except the one to be 7 pF
Output capacitance COUT tested should be grounded. 10 pF
Input/Output capacitance CliO 12 pF
'-~~--------"""SHARP -.-..-.----.-.-~
I
282
(1) CPU interface (V cc =5V±5%, Ta"",0-+70t)
LH0110 LH0110A
MIN. MAX. MIN. MAX.
1 Clock period TcC 400 111 250 111 ns
2 Clock pulse width, high TwCh 170 2000 105 2000 ns
3 Clock pulse width, low TwCl 170 2000 105 2000 ns
4 Clock rise time TfC 0 30 0 30 ns
5 Clock fall time TrC 0 30 0 30 ns
6 Hold time Th 0 0 ns
7 Setup time to clock t under read/write cycle. TsCE(C) 240 145 ns
Delay time from RD J, to data output under
8 TdRI(DO) 500 380 ns
read cycle.
Data setup time to clock t under write/M1
9 TsDI(C) 50 50 ns
cycle.
Delay time from 10RQ J, to data output
10 TdIO(DIO) 340 160 ns
(interrupt cycle).
11 Delay time to bus floating. TdRI(DOs) 160 110 ns
12 lEI setup time to IORQ J, (interrupt cycle). TslEl(IO) 200 140 ns
13 Delay time from lEI t to lEO t. TdIEI(JEOr) 210 160 ns
14 Delay time from lEI J, to lEO J, TdlEl(IEOf) 190 130 ns
Delay time from M1 J, to lEO J,
15 TdMl(IEO) 300 190 ns
(at interrupt before M1 J,)
M1 J, setup time to clock t under INTA/M1
16 TsMl(Cr) 210 90 ns
cycle.
RD J, setup time to clock t under read/M1
17 TsRI(C) 240 115 ns
cycle.
18 Delay time from FCLK J, to INT output TdC(INT) 300 300 ns
10RQ J, setup time to clock t under 110
19 Ts(IO) 240 115 ns
cycle.
(1) TcC=TwCh+TwCI +TfC+TrC.
t indicates rising edge, l l~dicates failing edge.
. . - . - . . - ., -.. - - . - . - - S H A R P. ----------
283
Floppy Disk Coi:Jtroller LH011 OlLH011 OA
(2) FDD interface ,

LHOllO/LHOllOA
MIN. TYP. MAX.
FDC clock period, standard floppy disk 500 ns
20 TcFC
FDC clock period, mini-floppy disk 1000 ns
21 FDC clock pulse width, high TwFCh 220 ns
22 FDC clock pulse width, low TwFCI 220 ns
23 FDC clock rise time TfFC 30 ns
24 FDC clock fall time TrFC 30 ns
25 Delay time from FDC clock t TdPS(FC}l 280 ns
.•.
Delay time from FDC clock t
26 TdWDA(FC) 170 ns
(FDC clock !, in the case of MFM)
Write data pulse width, MFM 250 ns
27 .TwWDA
Write data pulse width, FM 500 ns
28 Step pulse width TwSTP 12 f1.S
29 Step period TcSTP 1 ms
30 Fault reset pulse width TwFR. 12 f1S
Delay time from clock t to fulfill IORQ
31 TdDRQ(FC) 230 ns
setup time ;
Data request period, MFM 16 f1.S

32 TcDRQ
Data request period, FM 32 f1.S
33 Index pulse width TwIDX 50 f1.S
34 Read data pulse width TwRRD 100 ns
35 WDW setup time to read data TsWDW(RRD) 100 ns
36 WDW hold time from read data ThWDW(RRD) 100 ns
Window cycle time, MFM 1 . f1.S
37 TcWDW
Window cycle time, FM .•.
2 f1.S
38 Delay time from FDC clock ! to VFO TdVFO(FC) 150 ns
t indicates rising edge, ! indicates falling edge.
~--.-......-----SHARP -----.--:--------~.-
284
• AC Timing Diagram
"High" "Low"
Timing test level : CLOCK Vcc-O.6V 0.45V
OUTPUT 2.0V O.8V
, INPUT 2.0V O.8V
FLOAT ..:IV O.5V
CLOCK
CE
RSo-RS2
IORQ
RD
--+--1t I
----------------'h
®~
i
J F !
~---
~--@-
lEI
iEO----+@'---
lEO
-.---------SHARP----------
285
t, Floppy Disk Controller LH011 O/LH011 OA
'_ _ _. . . .a._a._ _ ....................-....,._ _....._
~
:
.
-
FCLK
PSL,PSE
WDA
VFO
DRQ
CLOCK
~--®'--.;..j
WDW
RRD
286
• Internal Structure • FDC Registers

The FDC consists of a CPU bus interface,· in- (1) FDC readout registers
ternal control circuit (microprogram controlled), in-
Among the seven FDC readout registers RRO-
terrupt control circuit and floppy disk drive (FDD) RR6, RR3 and RR4 are cleared at the beginning of
control circuit. The interrupt control circuit arbi- each command. The registers have the functions
trates device priority and produces interrupt vec-
listed in Table 1.
tors.
The FDC has the registers: Table 1 FDC readout register functions
• Two 8-bit data registers (RRO, WRO) Register Function
• Six 8-bit status registers (RRl, RR6) RRO Data buffer
• Seven 8-bit control registers (WRI-WR7) PRI Control status
RR2 DMA control status; FDD control status
PR3 Error status, A
RR4 Error status, B
PR5 Physical track address
PR6 Sector address
• Read Register 0 (RRO)
I~I~I~I~I~I~I~I~I
~I- - - - - - B u f f e r register for latching data readout from FDD

• Read Register 1 (RR1)
I D7 I Ds I Ds I D. I Ds I Dz I Dl I Do I
~ Head selection }
Unit selection Correspond to D7-Ds of WR3
Status selection
Deleted data address mark (DDAM) detection
(cleared at beginning of each command)
Seek (remains "l"during command execution)
Error B (ORed bits of RR4)
Error A (ORed bits of RR3)
Command end (set by reading RRl)
I D7 I Ds I Ds I D. I Ds I D2 I Dl I Do I
~ DRQ
HDL
MUXS
FLT/TS
(indicate the status of FDD coutrol signals)
WP/TRo
IDX
RDY
FDC ready (remains "0" during command execution)
-~-------SHARP--'-'-""-'-------
287
Floppy Disk. Controller . LH011 O/LH011 OA
I D7 I D6 I D5 I D4 I D3 I Dz I D1 I Do I
L Mis~ing data transfer (no data transfer between DRQs)
Mis~ing DAM receptio~ (no DAM reception after ID and sync field dete~tion)
Missing sync field reception (no sync field reception
within stated bytes after ID detection)
Seek error/i1iconsistency error (TRo=O.after stated number of step pulses sent
by SEEK ZERO command; inconsistency of data dete~ted by VERIFY command)
Write error (FLT=l after writing i\lto FDD)
Fault error (FriD fault status when initiating WRITE.

WRITE WITH DDAM or WRITE ID command)
Write protect error (write-protected status when initiating WRITE.
WRITE WITH DDAM or WRITE ID command)
Not-Ready error (FDD not ready at c~mmand initiation.)
I D7 I D6 I Ds I D4 I D3 I Dz I D1 I Do I
~ CRC error (data field)

CRC error (ID field)
DDAM error (DDAM detected by READ command)
Undefined record length'(ID field data size is not defined.)
Side error (inconsistent side data in ID field)
Address error (track data in ID field inconsistent with WR4)
Defective track (track data in 10 field is FFH)
Missing ID detection (target 10 remains undetected after 5 lOX receptions)
' - - - - - - - Current physical track address .

' - - - - - - - . , - - - - - - - U n u s e d (0)
I~I~I~I~I~I~I~I~I
IL-____ Sector address following access
' - - - - - - - - - - - - U n u s e d CO)
Table 2 FDC write register functions
Register Function
(2) FDC writing registers WRO Data buffer
WRI Command designation
Among the eight registers WRO-WR7 written in
WR2 Time setting
by CPU, WRl, WR3, WR5 and WR6 do not accept ·WR3 Number·of·sectors designation and pin control
writing when FDC is busy. Tte registers have the
WR4 Logical track address
functions listed in Table 2.
WR5 Physical track address
WR6 Sector address
WR7 Interrupt vector
288
Write Register 0 (WRO) Write Register S (WRS)
I D7 I D6 1 Ds 1 D.I I~I~I~I~I~I~I~I~I
L
D3 1 D2 1 D, 1 Do 1
LSector address to be
[ Buffer register for data sent to FFD
accessed (same as RR6)
Urjused
Write Register 1 (WR1)
Write Register 7 (WR7)
I~I~I~I~I~I~I~I~I
L FDC command
Window inversion (inversion prevented by "0")
[ Interrupt vector (read out at INT A)
Index count (index pulse'count after command
completion until head unloading : 0 for 2 pulses
; 1 for 5 pulses)
MFM/FM
-EIIDI interrupt enable flag • Commands
Write Register 2 (WR2) (1) Brief description
CD SEEK ZERO (0000/1)
L
I D7 1 D6 1 Ds 1 D4 1 D31 D2 1 D, 1 Do 1
Draw the head up to track 00. With command
[Step rate time having LSB=O, task is excuted while retaining the
(N ms for value N; 20 ms head unload status; with LSB= 1, it is excuted
for value N=O) while retaining the head load status.
Head load time (4M ms for value M; 64 ms for ® SEEK (0010/1)
value M=O) Move the head to specified track. With LSB=O,
(time length is doubled for mini -floppy disk) task is execused while retaining the head unload
status; with LSB= 1, it is executed while retaining
Write Register 3 (WR3) head load status.
® READ (0100)
Read data from specified sector and transfer
[Number of sectors for each byte in data section to main system. When
continuous access
data address mark is DDAM, operation is termin-
HDS } ,
L-------US (FDD signal control) ated as DDAM error.
~----------MUXS e!) READ DDAM (0101)
Same as READ command, except that address
DAM causes DDAM error, while DDAM does not
Write Register 4 (WR4) cause error.
(§) READ BOTH (0110)
Same as READ command, except that address
mark DDAM does not cause error.
[Track address (seek track address ® READ CRC (0111)
under SEEK command; track address Same as READ BOTH, except that data is not
in ID field in other commands)
transferred to main system.
(J) VERIFY (1000)
Unused
Compare each byte in data section read out from
a specified sector with the corresponding byte of
Write Register S (WRS) data received from main system.
® READ ID (1001)
Read out data in ID section of specified track and
transfer each byte to main system.
(same as RR5)
® WRITE (1010)
Unused
Write each byte of data received from main sys-
tem into specified sector.
-----......-------SHARP--.-.....I.----------
289
Floppy Disk Controller' LH011 O/LH011 OA
@ WRITE WITH DDAM (1011). WRITE 1D1 26 sectors/track (FM: 12.8 bytes/
Same as WRITE command, except that DDAM sector; MFM: 256 bytes/se(!tor)
and not DAM is written as address mark. WRITE 1D2 15 sectors/track (FM: 256 bytes/
@ WRITE 1D1 (1100) \ sector; MFM: 512 bytes/sector)
@ WRITE 1D2 (1101) WRITE 1D3 8 sectors/track (FM: 512 bytes/sec-
@ WRITE 1D3 (1110) tor; MFM: 1024 bytes/sector)
Write initialization (ID section) and gaps of spe- ~ RESET STATUS (1111)
cified track. In this command, data section is filled Initialize floppy disk drives.
with gaps.
(2) Commands and error status register A
::s::
Error status
DB7
Not-rea-
dy-error
SEEK
ZERO
X
SEEK
0
READ
0
READ READ
DDAM BOTH
0' 0
READ
eRe
0
VERIFY
0
READ
ID
0 0
WRITE WRITE
WRITE WITH ID
DDAM 1,2,3
0
RESET
STATUS
0 X
Write pro-
DB6
tect error
X X X X X X X X 0 0 0 X
DB5 Fault error X ·X X X X X X X 0 0 0 X

DB4 Write error X X X X X X X X 0 0 0 X
DB3
Seek error 0 X X X X X X X X X X X
Inconsisten- X X X X X X 0 X X X X X
cyerror
Missing
DB2 sync field X X 0 0 0 0 0 X X X X X
reception
Missing
DBI DAM X X 0 0 .. 0 0 0 X X X X X
reception
Missing
DBD data X X 0 0 0 X 0 0 0 0 0 X
transfer
(~) Commands and error status register B
~
WRITE WRITE
SEEK READ READ READ READ RESET
SEEK READ VERIFY WRITE WITH ID
ZERO DDAM BOTH eRe ID STATUS
Error status DDAM 1,2,3
Missing ID
DB7
detection .
X X 0 0 0 0 0 0 0 0 X X
DB6 Defect track X X 0 0 0 0 0 X 0 0 X X

Address
DB5
error
X X 0 0 0 0 0 X 0 0 X X
DB4 Side error X X 0 0 0 0 0 X 0 0 X X

Undefined
DB3 record X X -0 0 0 0 0 X 0 0 X X
length
,DDAM
DB2
error
X X 0 0 X X X X X X X X
eRe error
DBI X X 0 0 0 0 0 Or 0 0 X X
(ID field)
eRe error
DBD
(data field)
X X 0 0 0 0 0 X X X X X
--------SHARP--------
290
Floppy Dis~ Controller LH011 O/LH011 OA
• CPU Interface Timing

(1) FDC write cycle (3) Interrupt acknowledge cycle
MI -,L_ _ _ _ _ _r----
RSo
RS2 I I
CE
MI,RD--------------~----------- lEI ====-===_1
Do-D7 ______~I~_______________ r::
Do-D7--------------~c::J~------
Vector
(2) FDC read cycle (4) Interrupt return cycle
CLOCK
CLOCK
MI ~~~ __ r--~ __ ~----
~ ____________c= RD
----~CJ~------~~~-----
==:::':.::.-_-:.J"r--------------
MI ED 4D
lEI
,'-_____-Jr--- lEO
----------------------~,---
Do -D 7 - - - - - - - - - - - - - - - -__<::::)----
Data
---------~------SHARP ---~-.--------
291
! Flbppy Disk Controller
.-.-.-~-.-~-~
• FDD Interface Timing

..... ..... ~ ~.-: .--.....
LH011 O/LH011 OA
. (1) READ, READ DDAM, READ BOTH, READ CYC, VERIFY, READ 10 command timing
-------1H)~J__-
,~ .j)J--'-
=::::~------~~ Command termination-:----r--
..lo......-------!H -!~---
~---------~Jj l~j---
--'---..A.---------it}
(' 11
:) 1 - - - - !
. . f 5~Falls if next command

. .
No head load walt time needed if preceedmg command was is not issued within a
a read/write command. certain time span.
--L1,:::;SL:yn:,:;;c.J.,.1~ID;U...I_--r.;ls;;,:YD;;;;;c.J.,.1---\rl~:_--l._-..JI.;;s~YD:::..cIL.o:1;:;:D. J,I_ _
Gap Data section . Gap
(2) PSL and PSE timing
FCLK
WDA -1l n n ~
D C D C D C D C D
PSL
PSE
MFM mode
FCLK
WDA
J CI n
D
n C D
11.:..-
C
PSL
PSE High FM mode
- - - - - - . . . . . - - . - - . . . - . - - S H A R P -.-.--~-,-.--
292
Floppy Disk Controller LH011 O/LH01.1 OA
(3) WRITE 101, WRITE 102, WRITE 103 command timing
~--------~n~------~i~~(---
'------.....-.l!l {~'r--~-
Jl Com~~i~
T---------------~\~\------------~5~rj- - - - -
----J''----------ll! (
\~j
(I-----(~~ •
Falls if next command
• d ·th·
- - - -__r......c::;NLo head load wait time needed if preceeding command was . 'C IS not I.SSU~ WI ID
a read/write command. r a certam hme span.
f 5~~f-I
_ _ _ _ _--11 Jl i~fj...___
X Valid ~~ ~t::::to---=
X Valid
U 1t::::tD==
ID
Gap Sync
II gap
lJ ISync I I
ID
Gal! )1
(4) WRITE, WRITE WITH OOAM command timing
US =:::x r{ II
HDS ::::::x'--------l(\}-.---------\11(-----
MUXS _____ 1.J If-f--C-o-m-m-a-nd-te-r-m-in-a-ti-on-:::C~--------
RDY ::J~~--------{ljf---------j~!-----
LCT _ _ _J\...X --------i}~ ~(..

! If---\~alls If next command
HDL No head load wait time needed if preceeding command was ~is not issued within
(head/write command. a certain time span.
VFO
------I. . ~l-l- - - - -
WG
--------------~~~~------il(~-----
------------~~========~r\~~·====
WDA
PSE
PSL -----~~~----~I~~--
---....L..--L...-~.I-~.I-..LI--tH I Gap
Sync ID , \ Data section Sync ID
. Gap Sync
.--.-.-----SHARP-.--------
293
Floppy Disk Controlle,r LH0110lLH0110A
(5) RESET STATUS command timing
MUXS :.:.J L..:'

TYP.
-J 12ps l+-
FR. rlL._'_---:._
FLT
DIR'
HDL
(6) SEEK ZERO command timing
MUXS:-1~ ____________~~______~r::
STP
TY .
12ps
15}ls for 20ms seek rate time
HDL __-LI____________________~~~------------
DIR ::t~ ____________________ ~ij~----------
TRO
------------------------~l~
(7) SEEK command timing
MUXS~~_ _ _ _ _ _ _ _~!~---Lr-:
STP , c:::::J '

!----ITY~
12ps 15}ls for 20ms seek rate time
HDL __-LI____________________~:----~------
DIR J ~)
RDY .;,.j
294
Low current
LCT/DIR
Dire ction
MUXS
!
- Fault reset
FR/STP
----- - Step
- Write protect
WP/TR o
Multi-
plexer -- Track zero
Fault
FLT/TS
....- 2-side disk
LHOIIO US Unit select

FOC HDS Head select
HDL Head load
WG Writing gate
IDX Index
RDY Ready
RRD Read data
WDW
VFO circuit
~
VFO MFM
PSL
6
PSE
~
Delay
WDA circuit Write data
FCLK CJ2MHz
(lMHz fo r mini -floppy disk)
Oscillator
.-.----~~-SHARP~-.----------.-,
295
--............
Z80 CMOS Central Processing Unit
~ ..... .- -~- -
... .. ......- . -...-,..-.............. -
LH5080/LH5080LlLH5080LM
LH5080/LH5080L/LH5080LM
zao CMOS Central Processing Unit
The LH50BO is 2BO CPU fabricated with CMOS LH5080/LH5080L
silicon-gate process technology and is fully com-
patible with the conventional NMOS 2BO CPU
(LHOOBO). o
The LH50BO is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation. '
The LH5080LlLH5080LM provides power save
mode controlled by software. '
• Features
1. 2BO CMOS CPU
2. Fully compatible with the NMOS 2BO CPU
(LHOOBO)
3. 15B instructions
4. 22 registers
5. 3 modes of maskable interrupt and a nonmask-
able interrupt
6. Instruction fetch cycle 1.6 flS
7. Single + 5V power supply and single phase
clock
B. All inputs and outputs except clock input fully
TTL compatible
9. Fully static operation (DC-2.5MHz)
10. Low power consumption
11. Power save mode (LH50BOLlLH50BOLM)
(LH50BO/LH5080L)
13. 44-pin quad-flat package (LH50BOLM)
Note: The l80 CMOS CPU (LH5080/LH5080LlLH5080LM) is

compatible with the l80 NMOS CPU (LH0080). So there is
no descrip.tion here about the pins, CPU registers,
architecture, interrupts, basic timings, and instruction, sets.
Refer back to the l80 NMOS CPU described earlier.' ,
29p
Z80 CMOS Central Processing Unit LH5080/LH5080L/LH5080LM
• Block Diagram
System Data Bus

A
Halt State
Memory Request
Data Bus Interface
Input /Output Request
Read
Write
Bus Acknowledge Instruction Inst.
CPU Decoder ALU
Machine Cycle 1 Timing Reg.
Refresh Control
Interrupt Request Register Array

Non Maskable Interrupt
Wait
Bus Request
Reset
Address Logic a~d Buffer
System Address Bus
297
Z80 CMOS Central Processing Unit LH5080/LM50BOLlLH5080LM
, ,.-..-.-.-.:__,._.. ~ ....__,._.......-....................i.r.....r.--
Output voltage VOUT, -0.3-+7 V
Operating'temperature Topr 0-+70 t
Storage temperature T s ," -65-+150 t
• DC Characteristics (Vee=5V±10%, Ta=0-+70t)

Clock input high voltage V IHC Vee- 0.6 Vcc+ 0.3 V
Input low voltage VIL -0.3 O.B V
Output low voltage VOL IOL=1.BmA 0.4 V
Output high voltage VOH IOH=-250 pA 2.4 V
Current conswnption Icc (Note) 10 mA
Input leakage current I ILl I VIN=OV, Vee 10 pA 1
3·state output leakage current IILOH I VouT=Vee 10 pA 2
3·state output leakage current I ILOL I VOUT=OV 10 pA 2
Data bus leakage current I ILD I O~VIN~Vee 10 pA
Current conswnption in PS VIH=;,OV, Vee
leeps 50 150 pA
mode (LH50BOL/LH50BOLM) Output pin open
Note: TcC=400ns, Vn.=O.~ VIH=Vcc-OAV, output pin open.
Notel: The INT , WAIT, NMI and (BUSRQ) pins are arranged as shown below. Note 2: The Ao-A3 pins are arranged as shown below.
Note 1 and 2: The Do- D7 pins are arranged as shown ,below.~
(f=1MHz, Ta=25t)
• Capacitance
Symbol Parameter MAX. Unit
CeLocK Clock capacitance 5 pF
CIN Input capacitance 6 pF
to ground
COUT Output capacitance 10 pF
298
Z80 CMOS Central Processing Unit LH5080/LH5080LlLH5080LM
• AC Characteristics (Vcc=5V±10%, Ta=0-+70·C)
No. Parameter Symbol MIN. MAX. Unit

1 Clock cycle time TcC 400* ns
2 Clock pulse width (high) TwCh 180* ns
3 Clock pulse width (low) TwCl 180 ns
4 Clock fall time TfC 30 ns
5 Clock rise time TrC 30 ns
6 Clock t to address valid delay TdCr (A) 145 ns
7 Address valid to MREQ ~ delay TdA (MREQf) 125* ns
8 Clock ~ to MREQ ~ delay TdCf (MREQf) 100 ns
9 Clock t to MREQ t delay TdCr (MREQr) 100 ns
10 MREQ pulse width (high) TwMREQh 170* ns
11 MREQ pulse width (low) TwMREQ1 360* ns
12 Clock ~ to MREQ t delay TdCf (MREQr) 100 ns
13 Clock ~ to RD ~ delay TdCf (RDf) 130 ns
14 Clock t to RD t delay TdCr (RDr) 100 ns
15 Data setup time to clock t TsD (Cr) 50 ns
16 Data hold time after RD t ThD (RDr) 15 ns
17 WAIT setup time to clock ~ TsWAIT (Cf) 70 ns
18 WAIT hold time after clock ~ ThWAIT (Cf) 15 ns
19 Clock t to M1 ~ delay TdCr (Mlf) 130 ns
20 Clock t to M1 t delay TdCr (M1r) 130 np
21 Clock t to RFSH ~ delay TdCr (RFSHf) 180 ns
22 Clock t to RFSH t delay TdCr (RFSHr) 150 ns
23 Clock ~ to RD t delay TdCf (RDr) 110 ns
24 Clock t to RD ~ delay TdCr (RDf) 100 ns
Data setup to clock t during
25 TsD (Cf) 60 ns
M2, M3, M4 or Ms cycles
26 Address stable prior to IORQ ~ TdA (IORQf) 320* ns
27 Clock t to IORQ ~ delay TdCr (IORQf) 90 ns
28 Clock ~ to IORQ t delay TdCf (IORQr) 110 ns
29 Data stable prior to WR ~ (memory cycle) TdDm (WRf) 190* ns
30 Clock ~ to WR ~ delay TdCf (WRf) 90 ns
31 WR pulse width TwWR 360* ns
32 Clock ~ to WR t delay TdCf (WRr) 100 ns
33 Data stable prior to WR ~ (110 cycle) TdDi (WRf) 20* ns
34 Clock t to WR ~ delay TdCr (WRf) 80 ns
35 Data stable from WR t TdWRr (D) 120* ns
36 Clock ~ to HALT t TdCf (HALT) 300 ns
37 NM1 pulse width TwNMI 80 ns
38 BUSREQ setup time to clock t TsBUSRQ (Cr) 80 ns
39 BUSREQ hold time after clock t ThBUSRQ (Cr) 15 ns
40 Clock t to BUSACK ! delay TdCr (BUSAKf) 120 ns
41 Clock ! to BUSACK t delay TdCf (BUSAKr) 110_ ns
42 Clock t data float delay TdCr (Dz) 90 ns
Clock t to control output float
43 ----- - TdCr (CTz) 110 ns
delay (MREQ, IORQ, RD, and WR)
t Rising edge, ~ Falling edge .
.....--.-.-.--.---SH~RP-------.-.
299
Z80'CMOS Central Processing Unit LH5080/LH5080L/LH5080LM
No. Parameter Symbol MIN. MAX. Unit

44 Clock t to address float delay TdCr (Az) 110 ns
MREQ t ,IORQ t, RD t, and
45 TdCTr (A) 160* ns'
WR t to address hold timE:
46 RESET to clock t setup time TsRESET (Cr) 90 os
47 Clock t to RESET hold time ThRESET (Cr) 15 ns
4S INT to clock t setup time TsINTf (Cr) SO ' ns
49 Clock t to INT hold time ThINTr (Cr) 15 ns
50 M1 ! to IORQ ! delay TdMIf (IORQf) 920* ns
51 Clock ! to IOR~ ! delay TdCf (IORQf) 110 ns
52 Clock t to IORQ t delay TdCf (IORQr) 100 ns
53 Clock ! to data valid delay TdCf (D) 230 ns
t Rising edge, ! Falling edge
• For clock periods other than the minimums shown in the table, calculate parameters using the expressions in, the table on
the following page. '
.. All timings are preliminary and subject to change.
Footnotes to AC Characteristics
No. Symbol Formula
1 TcC TwCh+TwCl+TrC+TfC
2 TwCh MAX. 2001's
7 TdA (MREQf) TwCh+TfC-75
10 TwMREQh TwCh+TfC-30
11 TwMREQl TcC-40
26 TdA (IORQf) TcC-SO
29 TdD (WRf) TcC-210
31 TwWR TcC-40
33 TdD (WRf) TwCI+TrC-1S0
35 TdWRr (D) TwCl+TrC-SO
45 TdCTr (A) TwCI+TrC-40
50 TdMlf (IO~Qf) 2TcC+TwCh+TfC-SO
AC Test Conditions
e Input voltage amplitude: 004 V to 2.8V e Input judge level: 0.8V and 2.0V
e Input signal rise and fall time : IOns eOutput judge level: 0.8V and 2.0V
eClock input voltage amplitude: OAV to eOutput load: ITTL+ 100 pF
Vcc-0.6V
Output Pins Measuring Circuit
Output pin o-.......~t-----1Ie-~ CRI-CR<: IN914 or eguivalent

CR, CI: 50pF for all pins
CR 3
CR.
---.------,~--SH~RP.--,.-----~-- .........
300
Z80 CMOS Central Processing Unit LH5080/LH5080L/LH5080LM
• Power Save Function is then cleared and the reset just as before is
carried out.
The LH5080L/LH5080LM features the power
(ii) Clearing with NMI: Input the NMI signal
save (PS) function. After a HALT instruction has
(edge trigger) to clear the PS mode and to car-
been executed, the internal clock signal is automati-
ry out the instruction next to the HALT. Now
cally cut off to bring the CPU into the halt mode.
the non-maskable interrupt processing routine
(1) PS mode setting will be introduced.
With a HALT instruction executed, the PS mode (iii) Clearing with INT: Input the INT signal
will be automatically established. In this mode, the (level trigger) regardless of which state the in-
internal clock signal is cut off to save the power terrupt enable flag is in. The PS mode is now
consumed for the clock signal operation. Cutting an cleared and the HALT instruction executed. If
external clock signal does not give any problem in- the interrupt enable flag is set up and the INT
side, therefore, in this mode. To cut off the external signal is "Low' at the clock pulse rise timing
clock, it is possible to utilize the rise timing of a in the last clock cycle of the HALT instruction,
HALT signal output. It should be noted, however, the mask able interrupt processing routine will
that this timing cannot be used to restart the exter- be introduced as the next machine cycle.
nal clock.
In the PS mode, the bus request (BUSRQ) is not
accepted and the memory refresh is not done, CLOCK
either.
HALT~
PS·,
~~--Ml---------------------
RESET . ...:===~~~~~~~~-r---
CLOCK
Ml
* PS is internal signal, and not output externally.
PS· _+--+~+--+...J
Halt clear by NMI INT
* PSis internal signal, and not output externally.
PS mode setting CLOCK
HALT
(2) PS mode clear
PS·
The PS mode is cleared by any of the following;
reset (RESET), non-maskable interrupt (NMI) and NMI
INT
maskable interrupt (INT).
When the external clock is shut down in the PS * PS is internal signal, and not output externally.
mode, a stable clock signal must be input before
PS mode clear by MI signal
clearing the PS mode.
(i) Clearing with RESET: Input the RESET sig-
nal for more than 3 clock cycles. The PS mode
------------SHARP .-.-..----------
301
zao. CMOS Parallel 1/0 Controller LH5081 fLH5081 L/LH5081 LM
,;.tI!IIIIIII'.-..-..... ......-..-..-..-,..-..- ..- -...... - . - . -
.....,~
LH5081/LH5081L/LH5081LM
zao CMOS Parallel 110 Controller
The LH5081 is Z80 PIOfabricated with.CMOS LH5081/LH5081L
silicon gate prQ(;ess techrlOlogy and is fully com-
patible with the conventional NMOS Z80 PIO
(LH0081).
The LH5081 is designed with CMOS fully static
circuits and so provides low power consumption CE 4
and wide range power supply voltage operation. C/D SEL 5
The LH5081L1LH5081LM provides power save
BIA SEL 6
mode controlled by softwave. -
• Features
1. Z80 CMOS PIO
2. Fully compatible with NMOS Z80 PIO
(LH0081)
3. Tow independent 8-bit bidirectional peripheral
interface ports with handshake data transfer
control
4. 4 programmable operating modes
• Byte input mode
• Byte output mode
• Byte bidirectional bus mode (Port A only) Top View
• Byte control mode
5. Programmable interrupt on peripheral status
conditions
LH5081LM
6. Vectored daisy chain priority interrupt
7. Darlington transistor drive capability (port B
output)
8. All inputs and outputs except clock input fully
TTL compatible
clock
10. Fully static operation (DC-Z.5MHz)
12. Power save mode (LH5081L1LH5081LM)
13. Status read mode (LH5081L1LH5081LM)
(LH5081/LH5081L)
15. 44-pin quad-flat package (LH5081LM)
1 2 3
Note: The Z80 CMOS CPU (LH5081/LH5081L) is compatible
I~I~ ~
• with the Z80 NMOS PIO (LH0081). So there is no descrip·
tion here about the pins, programming, and basic timings Top View
waveforms. Refer back to the Z8.0 NMOS PIO described
earlier.
302
Z80 CMOS Parallel 1/0 Controller LH5081/LH5081 L/LH5081 LM
• Block Diagram
Internal
Control Logic
Port A
Port A Data Bus
Input!
Output
System
Data
Bus
CPU
Bus
Input!
Output
Port A!B Select Logic
Command/Data
Select
Chip Enable Port B
~
Macbine Cycle 1 Port B Data Bus
I!O Request Input!
Read Output
Interrupt
Control Logic
:; > ....u0 ..'". .s. ..'"

It)
+ = u
Q .'" ::c... ::c..
<:I'
0
u
.,;;
z
(.!) .e p::
Q. ..
r.z:I
...
'Vi
..'" . Q.
r.z:I
.s !. ...'"
CIl Q.
! '"
.... !
.s
----~-.-----SHARP ----.----------~
303
Z80 CMOS Pataltel 1/0 Unit' LH5081 ILH5081 LlLH5081 LM

Supply voltage Vcc -0.3-7.0 V
Input voltage VIN -0.3-Vcc +0.3 V
Output voltage VOUT -0.3-Vcc +0.3 V
Operating temperature Topr 0-+70 t
Storage temperature Ts". -65-+150 t
Parameter Symbol Conditions MIN. TYP. MAX. Unit -Note

Clock input high voltage VIHC Vcc- O.G Vcc+ 0.3 V
Input high voltage V IH 2.2 Vcc+ 0. 3 V
Output low voltage VOL 10L =2inA 0.4 V
IOH=-1.6mA 2.4 V
Output high voltage VOH
10H= -250 1'A Vee -D.4V V
Current consumption Icc (Note) 2 6 rnA
Input leakage current I ILl I VIN=OV, Vcc 10 pA 1
3-state output leakage current I lLOH I VOUT=VCC 10 I'A 2
3-state output leakage current I lLOL I VOUT=OV 10' I'A 2
Data bus leakage current input I ILD I oS::VIN S::VCC 10 I'A
Darlington drive current 10HD, V OH = 1.5V, Port only -1.5 rnA
Current consumption in PS
Iccps Output pin open, VIN=OV, VCC 1 100 pA
mode (LH5081L/LH5081LM) -
Note TcC=400ns, VIL=OAV, VIH=VCC-O.4V, output pin open.

Note 1: The A STB and B STG pins are arranged as shown below. • The INT pin is arraged as shown below.
,.,,,,,,,,,, ,,1m•• ""ID-'

Note 2: The Ao-A7 and Bo-B7 pins are arranged as shown below.
Interruput requestL
• Capacitance (f=lMHz, Ta=25t)
Parameter Symbol Conditions MAX. Unit

to ground
304
Z80 CMOS Parallel I/O Controller LH5081 ILH5081 L/LH5081 LM
• AC Characteristics (V cc =5V±10%, Ta=0-+70t)
No. Parameter Symbol MIN. MAX. Unit Note

1 Clock cycle time TcC 400 (Note l) ns
2 Clock width (high) TwCh 170 ns
3 Clock width (low) TwCI 170 ns
4 Clock fall time TfC 30 ns
6 CE, BfA, CfD to RD, 10RQ ~ setup time TsCS (RI) 50 ns 6
7 Any hold times for specified setup time Th 15 ns
8 RD, 10RQ to clock t setup time TsRI (C) 115 ns
9 RD, 10RQ ~ to data output delay TdRI (DO) 430 ns 2
10 RD, 10RQ t to data output float delay TdRI (DOs) 160 ns
11 Data in to clock t setup time TsDI (C) 50 ns CL =50pF
12 10RQ ~ to data o_ut delay (INT ACK cycle) TdlO (DOl) 340 ns 3
13 M1 ~ to clock t setup time TsMI (Cr) 210 ns
14 Ml t to clock ~ setup time (Ml cycle) TsMI (Cf) 0 ns 8
Ml ~ to lEO ~ delay
15 TdMI (lEO) 300 ns 5,7
(interrupt immediately preceding MI l)
16 lEI to 10RQ ~ setup time (INT ACK cycle) TsIEI (10) 140 ns 7
5
17 lEI l to lEO ~ delay TdlEI (IEOf) 190 ns
CL =50pF
18 lEI t to lEO t delay (after ED decode) TdlEI (lEOr) 210 ns 5
10RQ t to clock ~ setup time
19 TcIO(C) 220 ns
(to activate READY on next clock cycle)
5
20 Clock ~ to READY t delay TdC (RDYr) 200 ns
CL =50pF
21 Clock ~ to READY l delay TdC (RDYf) 150 ns 5
22 STROBE pulse width TwSTB 150 ns 4
STROBE t to clock ~ setup time
23 TsSTB (C) 220 ns 5
(to activate READY on next clock cycle)
24 10RQ t to PORT DATA stable delay (mode 0) TdlO (PD) 200 ns 5
PORT DATA to STROBE t setup time
25 TsPD (STB) 260 ns
(mode 1)
26 STROBE ~ to PORT DATA stable (mode 2) TdSTB (PD) 230 ns 5
STROBE t to PORT DATA float delay
27 TdSTB (PDr) 200 ns CL =50pF
(mode 2)
28 PORT DATA match to INT l delay (mode 3) TdPD (INT) 540 ns
29 STROBE t to INT ~ delay TdSTB (INT) 490 ns
Note 1: TcC=TwCh+TwCl+TrC+TtC.
Note 2 : Increase TdRI (DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Note 3 : Increase TdIO (001) by 10 ns for each 50 pF, increase in loading up to 200 pF max.
Note 4 : For Mode 2 : TwSTB>TsPD (STB).
Note 5 : Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max.
Note 6 : TsCS (RI) may be reduced. However, the time substracted from TsCS (RI) will be added to TdRI (DO).
Note 7 : 2.5 TcC > (N·2) TdIEI (IEOf)+TdM1 (IEO)+TsIEI (10) + TTL Buffer Delay, if any.
Note 8 : M1 must be active for a minimum of two clock cycles to reset the PIO.
AC Test Conditions:
• Input voltage amplitude: OAV to 2.8V
• Clock input voltage amplitude: OAV to Vcc-O.6V
• Input signal rise and fall time : IOns
• Input judge level: O.8V and 2.0V
• Output judge level: O.8V and 2.0V
• Output load: ITTL+ lOOpF (unless otherwise specified)
------~.--.----SHARP . - . - - . - . - . . - - ......... -
305
Z80 CMOS Parallel I/O Controller LH5081 ILH5081 LlLH5081 LM
• Power Save and Status Information (ii) PS mode clear The. PS mode is cleared
Read Function by detecting the fall of the Ml signal. When the ex-
ternal clock is off in the PS mode, however, a stable
Un1ike the LH00811LH5081, the LH5081Ll clock signal must be input before clearing the PS
LH5081LM has the power save (l:'S) and status in- mode.
formation read functions. When the CPU (LH50~OLlLH5080LM) is
(1 ) Power save function cleared from the PS mode and comes into the next
(i) PS mode setting When the CPU fetch cycle, therefore, the LH5081LlLH5081LM is
(LH5080LlLH5080LM) has executed an HALT in- also cleared from itsPS mode at ~he fall of the first
struction in the PS mode, the LH5081LlLH5081LM Ml signal in this cycle.
reads this HALT instruction to automatically go The PS mode clearing can be done by issuing an
into the-PS mode. Now the internal clock signal is interrupt request.
cut off. Therefore, cutting an external clock input Set up the interrupt generate conditions in Mode
gives no problem inside in this mode. 3 of the LH5081LlLH50S1LM. By this, an inter-
rupt request (INT) is issued even in the PS mode,
the CPU (LH5080LlLH5080LM) is cleared from
the PS mode, and thus LH5081LlLH5081LM is
also cleared.
(2) Status information read
Under the following conditions, the mode setup
Data--------~r---~~---+--------- bits and handshake signals of Port A and Port B
are read from the data bus during the read cycle.
PS'
----------------~ See the chart below.
PS mode set timing Conditions: CE = "Low"~RD = "Low", IORQ
"Low", C/D = "High", BI A = X (undefined)
Bits 7 6 5 4 3 2 1 0
Ml
IAMIIAMOjARD\jASTIlI BMII BMO~RDYjilSTBI .
Return to original state
ps'
* PSis internal signal and not output externally.

I
Uppermost two bits of tbe
~most two bits of ~he
B port mode co~t~ol reglstor
PS mode clear timing Aport mode control registor (Set mode bIts)
(Set mode bits)
LH5081/LH5081 LM status information words
306
Z80 CMOS Counter Timer Circuit LH5082/LH5082L1LH5082LM
LH5082/LH5082L/LH5082LM
zao CMOS Counter Timer Circuit
The LH5082 is 280 CTC fabricated with CMOS LH5082/LH5082L
silicon-gate process technology and is fully com-
patible with the conventional NMOS 280 CTC o
(LH0082).
The LH5082 is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation.
The LH5082L1LH5082LM provides power save
mode controlled by software.
• Features
1. 280 CMOS CTC
2. Fully compatible with the NMOS 280 CTC
(LH0082) Top View
3. 4 independent programmable 8-bit counter/
16-bit timer channels
4. Selectable counter/timer mode for each channel
5. Programmable interrupt triggered by counter/
timer
6. Downcounters !;eloaded automatically at zero
count
7. Readable downcounters
8. Selectablp. 16 or 256 prescaler (timer mode)
9. Selectable positive or negative triggers for timer
and selectable positive or negative clock edge
for counter
10. 2C/TO outputs of three channels capable of
driving Darlington transistors
11. Vectored and daisy chain piority interrupt
12. Single + 5V power supply and. single phase
clock
13. All inputs and outputs except clock input fully o U
TTL compatible " Z
14. Fully static operation (DC-2.5MHz)
15. Low power consumption Top View
16. Power save mode (LH5082L1LH5082LM)
(LH50821LH5082L) .
18. 44-pin quad-flat package (LH5082LM)
Note: The Z80 CMOS CTC (LH50821LH5082L/LH5082LM) is

compatible with the Z80 NMOS CTC (LH0082)_ So there is
no description here about the pins, programming, and basic
timing waveform. Refer back to the Z80 NMOS CTC descri-
bed earlier.
-~--------SHARP--'-''--'-'------
307
Z80 CMOS Counter Timer Circuit· LH5082~LH5082L/LH5082LM
• Block Diagram
Zero Count/
Timeout 0
Clock/Trigger 0
System' Internal
Data Control
Bus Logic Zero Count/
Timeout 1
Clock/Trigger
CPU Bus
Input/
Output
Logic Zero Count/
Channel { Timeout 2
Select
Machine Cycle 1 Clock/Trigger 2
Interrupt
I/O Request Logic
Clock/Trigger 3
_ _ c= -
~
'"
III > >
LI)
S
c:> "' ....
~ t; §": ~O _::1
'"
... Q) ....
~ + ~~.l t & t~ t:i
u zu)u !~]~!~
~ t!l ,.!;~
.-.-.----.....,.-.--SHARP-.-.-------
308
Z80 CMOS Counter Timer Circuit LH5082/LH5082L/LH5082LM

Supply voltage Vee -0.3-+7.0 V
Input voltage VIN -0.3-Vee +0.3 V
Output voltage VOUT -0.3-Vee +0:3 V
Operating temperature ToDr 0-+70 t
Storage temperature TstQ -65-+150 t
• DC Characteristics (Vee =5V±10%, Ta=0-+70t)

Clock input high voltage V IHe Vee- 0.6 Vee+ 0.3 V
Input low voltage V IL -0.3 0.8 V
Input high voltage . V LH 2.2 Vee V
Output low voltage VOl. IOL =2mA 0.4 V
IoH =-1.6mA 2.4 V
IoH = -250pA Vcc--:OAV V
Current consumption I Icc I (Note) 2.5 8 rnA
Input leakage current I ILl I VIN=OV, Vee 10 pA 1
3-state output leakage current I ILOH I VouT=Vee 10 pA
3 -state output leakage current I IIOL I VOUT=OV 10 pA
V()H=1.5V
Darlington drive current IOHD -1.5 rnA
AppIicated to ZC/TOo-ZCIT0 2
Current consumption in PS
Iccps Output pin open, VIN=OV, Vee 1 100 pA
mode (LH5082L1LH5082LM)
Note: TcC=400ns, TcCTR=l p.s, VIL=O.4V, VIH=Vee-O.4V, output pin open.
Notel: The CLK/TRGo-CLK/TGa pins arranged as shown below.
• Capacitance (f=lMHz, Ta=25t)

Parameter Symbol Conditions MAX. Unit
Clock capacitance CeLOeK 5 pF
to ground
309
280 GMOS Counter Timer Circuit LH5082/LH5082L1LH5082LM
• AC Characteristics (V cc =5V±10%, Ta;;=0-+70"C)
No. Para!lleter Symbol MIN. MAX. Unit Note

1 Clock cycle time TcC 400 (Note 1) ns
2 Clock width (high) TwCh 170 ns
3 Clock width (low) TwCl 170 ns
4 Clock Jail time TfC 30 ns
6 All hold times Th 15 ns
7 CS to clock t setup time TsCS (C) 250 ns
8 CE to clock _t setup time TsCE (C) 200 ns
9 IORQ ~ to clock t setup time_ TsIO (C) 250 ns
10 RD ~ clock t setup time TsRD (C) 240 ns
11 Clock t to data out delay TdC (DO) 240 ns 2
12 Clock ~ to data out float delay TdC (DOz) 230 ns
13 Data In to clock t setup time TsDI (C) 60 ns
14 Ml to clock t setup time TsMI (C) 210 ns
Ml ~ to lEO ~ delay
15 - TdMI (lEO) 300 ns 3
(interrupt immediately preceding Ml)
16 IORQ ~ to data out delay (INT A cycle) TdIO (001) 340 ns 2
17 lEI ~ to lEO ~ delay TdIEI (IEOf) 190 ns 3
18 lEI t to lEO t delay (after ED decode) TdlEI (IEOr) 220 ns 3
19 Clock t to INT ~ delay TdC(INT) TcCt200 ns 4
- CLK/TRG t to INT ~ delay
TdCLK (INT) TcCt230 ns 5
(tsCTR (C) satisfied)
20
CLK/TRG t to INT ~- delay
TdCLK (INT) 2TcCt530 ns 5
(tsCTR (C) not satisfied)
21 CLK/TR9 cycle time TcCTR 2TcC ns 5
22 CLK/TRG rise time TrCTR 50 ns
23 CLK/TRG fall time TfCTR 50 ns
24 CLK/TRG width (low) TwCTRI 200 ns
25 CLK/TRG width (high) TwCTRh 200 ns
CLK/TRG t to clocl~ t setup time for
26 TsCTR (Cs) 300 ns 5
immediate count
CLK/TRG t to clock t setup time for
27 TsCTR (Ct) 210 ns 4
enabling of prescaler on following clock t
28 Clock t to ZC/TO t delay TdC (ZC/TOr) 260 ns
29 Clock t to ZC/TO ~ delay TdC(ZCITOf) 190 ns
30 lEI setup time to 10RQ ~ (INT A cycle) TsIEI (10) 140 ns
t Rising edge, ! Falling edge
IAI 2.5 TcC>(n-2) TdIEI (IEOf)+TdMI (lEO) +TsIEI (IO)+TTL buffer delay, if any:
IBI RESET must be active for minimum of 3 clock cycles
Note1: TcC=TwCh+TwCI+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pI" maximum for data lines, and 100 pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode.
* All timing are preliminary and subject to change.
-~~-'--'---SHARP'-''-----'-~-
310
Z80 CMOS Counter Timer Circuit LH5082/LH5082L/LH5082LM
AC Test Conditions reads this HALT instruction to autmatically go into

the PS mode. In this mode, the internal clock
• Input voltage amplitude: 0.4 V to 2.S V
signal is cut off. The external clock may be off duro
• Clock input voltage amplitude: 0.4 V to
ing the PS mode.
Vcc-0.6V
• Input signal rise and fall time: IOns About the external clock stop, the same is true as
the power-saving CPU (LH50S0LlLH5080LM).
• Input judge level: O.S V and 2.0 V
• Output judge level: O.S V and 2.0 V (2) PS mode clear
.Output load: ITTL + 100 pF (unless other- The PS mode is cleared by the fall of M1 signal
wise specified) or the RESET signal.
When the external clock is off the PS mode,
• Power Save Function however, a stable clock signal must be input before
The LH50S2L1LH50S2LM has the power save clearing the PS mode.
(PS) function. Once cleared from the PS mode, the power-sav-
ing CPU (LH5080LlLH50S0LM) comes into the
(1) PS mode setting
next fetch cycle. At the time when the first M1 sig-
When the CPU (LH50S0LlLH50S0LM) has ex- nal during this cycle falls, the LH5082L1LH5082LM
ecuted a HALT instruction, the LH5082L/LH5082 LM is also cleared from the PS mode.
CLOCK CLOCK
Ml RESET~ . I
PS' Reset state same as LH5082
RD
Date * PS is an internal signal and not output externally.

_ _ _ _ _ _ _ _ _..:r Power save PS mode clear by RESET signal
state
* PS is an internal signal and not output externally. CLOCK

PS mode set timing
~
Ml
PS' ~'----- Return to original state
* PS is an internal signal and not output externally.

PS mode clear by MI signal
-----------SHARP-...-...-~-.---.-
311
16-Bit Microprocessor
and Peripheral LSls
ZS001 IZS001 AlZS002/ZS002A Central Processing Unit LHS001 IS001 A/S002/S002A
LH8001/LH8001A/LH8002/LH8002A
zaoo IIZSOO IAlZSOO2lZS002A. Central Processing Unit
• . Description • Pin Connections
LH800i, Z8001 CPU and LH8002, Z8002 CPU r------:----;::=====::----:L--:H=-SO--:Ol::-:;-=-LH=S=OO=-lA:i
are advanced 16-bit microprocessor that spans a
wide variety of applications ranging from simple
stand..,alone computers to complexparallel-proces-
.sing unit. Essentially Z8000 CPU is a monolithic
minicomputer central processing unit.
The LH8001A Z8001A and LH8002A Z8002A
CPU are the high speed version which can operate
at 6MHz system clock.
• Features
1. Regular, easy-to-use architecture
2. Instruction set more powerful than many mini-
computers
3. Directly addresses 8M bytes
4. Eight user-selectable addressing modes
5. Seven data types that ra~ge from bits to 32-bit
l<;mg words and word strings
6. System and Normal operating modes
7. Separate code, data and stack spaces Top View
8. Sophisticated interrupt structure
9. Resource-sharing capabilities 'for multiprocessing LH8002lS002A
systems
10. Multi-programming support
11. Compiler support
12. Memory management and protection provided
by Z8010 Memory Management Unit
13. 32-bit operations, including signed mUltiply
and divide
14. Z-BUS compatible
Top View
.-......-.--------SHARP .-..-....----------
314
I •
I
m
0"
0
'"0 II
I
I
ii"
CQ
;
3
Ii
I
I
I
Flags
Address
IData III i
,
I
»
Address St robe
Date Strobe
Memory Request
Bus Request Ii
I~
N Bus Acknowledge
'0
I Multi- Micro In
Multi- Micro Out I~
I Non- Maskable Interrupt
Segment Trap Segment I
h
Number
I Non- Vector Interrupt

Vector Interrupt
I System Clock
Control
Register
I
I 11 36
Vee GND II
w
....
01,
I
I ----.
U1
II
11111111
ZSQ(H IZ8001 A/Z8002/Za002A Central, Processing Unit LH8001 lLH8001 A/LH8002/LH8002A
• Pin Description
/
Addressl data' bus Bidirectional

ADo -AD I5 3-state MUltiplexed system address and data bus.
AS Address strobe 3-state 0 Active ~Low". Addresses,are valid.
DS Data strobe 3-state 0 Active "Low". Data are valid.
R/W Read/write 3-state 0 Read at "High". Write at "Low".
B/W Byte/word 3-state 0 Byte at "High". Word at "Low".
MREQ Memory request 3-state 0 Active "Low". For memory access.
ST o-ST 3 Status 3-state 0 Specifies CPU status.
N/S Normal/system mode 3-state 0 Normal mode at "High", System mode at "Low".
Designates segments to be accessed (for 28001 CPU
SNo-SNs Segment number 3-state 0
only).
- -
SEGT Segment trap I
Active "Low". Detects a segmentation trap from the
28010 MMU.
BUSRQ ' Bus request I Active "Low". Requests the bus line.
--- Active "Low". Indicates the relinquished control of the
BUSAK Bus acknowledge 0
bus.
RESET Reset I Active "Low", Resets the Z8000 CPU.
-- Active "Low". High-to-low transition not interrupted
NMI Non-maskable interrupt I
non-maskable.
VI Vectored interrupt I Active "Low". Requests a vectored interrupt.
-- Non-vectored
NVI I Active "Low". Requests a non-vectored interrupt.
Interrupt
STOP Stop I Active "Low". For single-step instruction execution.
-- Active "Low". For synchronizing with a peripheral
WAIT Wait I
device.
Ml Multi-micro I I Active "Low". Forms a resource-request dai&y chain.
Mo Multi-micro 0 0 Active "Low". Forms a resource-request daisy chain.
CLOCK System clock I Single-phase clock.

Input voltage V IN -0.3-+7.0 V
Output voltage V OUT -0.3-+7.0 V
Operating temperature T01>t 0-+70 t
Storage temperature - T st • -65-+150 t
"~ .
316
Z8001 IZ8001 A/Z8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
.-.-.-~.-.-~.-~~~.-~~~.-~.-

Clock input high voltage VCH Vcc-004 Vcc+ 0.3 V
oscillator
Clock input low voltage VCL -0.3 0045 V
oscillator
Input high voltage VIH 2.0, Vcc+ 0.3 V
Output high voltage VOH IOH = -250 fLA 204 V
Output low voltage VOL IOL=+2.0mA 004 V
Input leakage current I IlL I Oo4:S::V IN :S::204V 10 fLA
Output leakage current I IOL I Oo4~VouT~204V 10 fLA
LH800JlLH8002(4MHz) LH800IA/LH8002A(6MHz)
Number Symbol Parameter Unit
MIN. MAX. MIN. MAX.
1 TcC Clock cycle time 250 2000 165 2000 ns
2 TwCh Clock width (high) 105 2000 70 2000 ns
3 TwCI Clock width (low) 105 2000 70 2000 ns'
4 TfC Clock fall time 20 10 ns
5 TrC Clock rise time 20 15 ns
Clock t to segment number valid
6 TdC (SNv) 130 110 ns
(50 pF load)
7 TdC (SNn) Clock t to segment number not valid 20 10 ns
8 TdC (Bz) Clock t to bus float 65 55 ns
9 TdC (A) Clock t to address valid 100 75 ns
10 TdC (Az) Clock t to address float 65 55 ns
11 TdA (DR) Address valid to read data required valid 475* 305 ns
12 TsDI (C) Read data to clock ! setup time 30 20 ns
13 TdDS (A) DS t to address active 80* 45* ns
14 TdC(DW) Clock t to write data valid 100 75 ns
15 ThDR (DS) Read data to DS t hold time 0 0 ns
16 TdDW (DS) Write data valid to DS t delay 295* 195* ns
17 TdA (MR) Address valid to MREQ ! delay 55* 35* ns
18 TdC (MR) Clock ! to MREQ ! delay 80 70 ns
19 TwMRh MREQ width (high) 210* 135* ns
20 TdMR (A) MREQ ! to address not active 70* 35* ns
21 TdDW (DSW) Write data valid to DS ! (write) delay 55* 35* ns
22 TdMR (DR) MREQ ! to read data required valid 375* 230* ns
23 TdC (MR) Clock ! MREQ t delay 80 60 ns
24 TdC (ASf) Clock t to AS ! delay 80 60 ns
25 TdA (AS) Address valid to AS t delay 55* 35* ns
26 TdC (ASr) Clock ! to AS t delay 90 80 ns
27 TdAS (DR) AS t to read data required valid 360* 220* ns
28 TdDS (AS) DS t to AS ! delay 70* 35* ns
29 TwAS AS width (low) 85* 55* ns
,30 TdAS (A) AS t to address not active delay 70* , 45'* ns
31 TdAz (DSR) Address float to DS (read) ! delay 0 0 ns
32 TdAS (DSR) AS t to DS (read) ! delay 80* 55* ns
33 TdDSR (DR) DS (read) ! to read data required valid 205* 130* ns
34 TdC (DSr) Clock ! to DS t delay 70 65 ns
35 TdDS (DW) DS t to write data not valid 75* 45 ns
'-'--~----SHARP ----.----..----
317
------------------
Z8001 IZ8001 A/Z8002/Z80Q2A Central Processing, Unit LH8001lLH8001 A/LH8002/LH8002A
LH800IlLH8002(4MHz) LH800IA/LH8002A(6MHz)
Number Symb01 Parameter Unit
MIN: MAX. MIN. MAX.
36 TdA (DSR) Address valid to DS (read) l delay 180* 110* ns
37 TdC (DSR) Clock t to DS (read) l delay 12,0 85 ns
38 TwDSR DS (read) width (low) 275* ' 185* ns
39 TdC (DSW) Clock l to DS (write) l delay 95 80 ns
40 TwDSW DS (write) width (low) 185* 110* ns
41 TdDSI (OI) DS (liD) r to read data required valid 330* 210* ns
42 TdC(DSf) Clock l to DS (II 0) l delay 120 90 ns
43 TwDS DS (II 0) width (low) 410* 255* ns
44 TdAS (DSA) AS t to DS (acknowledge) l delay 1065* 690* ns
45 TdC (DSA) Clock t to DS (acknowledge) l delay 120 85 ns
DS (acknowledge) l to read data
46 TdDSA (DR) 455* 295* ns
required delay
47 TdC (S) Clock t to status valid delay 110 85 ns
48 TdS (AS) Status valid to AS t delay 50* 30* ns
49 TsR (C) RESET to clock t setup time 180 70 ns
50 ThR (C) RESET to clock t hold time 0 0 ns
51 TwNMI NMI width (low) 100 70 ns
52 TsNMI (C) NMI to clock t setup time 140 70 ns
53 TsVI (C) VI, NVI to clock t setup time 110 50 ns
54 ThVI (C) VI, NVI to clock t hold time 20 20 ns
55 TsSGT (C) SEGT to clock t setup time 70 55 ns
56 ThSGT (C) SEGT to clock t hold time 0 0' ns
57 TsMI (C) MI to clock t setup time 180 140 ns
58 ThMI (C) MI to clock t hold time 0 0 ns
59 TdC (MO) Clock t to MO delay 120 85 ns
60 TsSTP (C) STOP to clock l setup time 140 100 ns
61 ThSTP (C) STOP to clock l. hold time 0 0 ns
62 TsW (C) WAIT to clock l setup time 50 30 ns
63 ThW (C) WAIT to clock l hold time 10 10 ns
64 TsBRQ (C) BUSREQ to clock t setup time 90 80 ns
65 ThBRQ (C) BUSREQ to clock t hold time 10 10 ns
66 TdC (BAKr) Clock t to BUSACK t delay 100 75 'ns
67 TdC (BAKi) Clock t to BUSACK l delay 100 75 ns
68 TwA Address valid width 150* 95* ns
69 TdDS (S) DS t to STATUS not valid 80* 55* ns
Note: t Rising, ! Falling, ( I) 2TcC + TwCh - 130ns
* Clock-cycle-time-dependent characteristics.
------~~----SHARP -.--...-.---------
318
Z8001 IZ8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 A/LH8002/LH8002A
.-..-.----.-..-.~.-.------.-.~--.-..-.--.-.
• Composite AC Timing Diagram
RESET --~X~~~~~')50~
______________,. ~4~ r-'~
NMI
VI,NVI
SEGT
~
-
:>i
K53)a 1i54 = This composite timing diagram
does not show actual timing sequences.
Refer to this diagram only for the detailed
timing relationships of individual edges.
Use the preceding illustrations as an
explanation of the various timing sequences.
BUSRQ ~. ~
~.
BUSAK __________~JI--~
CLOCK )
WkiJr---\"'------'. r----. I I' L II.rg\.
.J~. ~ ,- V7\ ~ f'-----J I'V-
SNo-SN6 ~~~~ :i~--
____~rGr,9~~--~~~~ ~~
ADDRESS ----+-.r;><1:=t====1=~~ ~ ~f~
J '='
A",-AD"
{
DATA IN . "'f--®- 'l :> I@ f ~~_)
DATA OUT IE-I :""~f--~ ~ .J--t------t---+--+,j--+"'""'K...lr"--
MREQ
I_~ ,- ~ lfijO)\ -=. 'C/ ~@1'r-tk--+-+.(J
~ I",,......,H-+-tl'==t---+----t-........ lt"l T ---
~ t@;r-;-.o--t+-t--t{I~.zm-_ _-i j
--~--+-l~ ~v~ ~-o ~IE-t-L""-f{I~33}---I' ~ ~

AS
MEMORY ./ IQI N., I=' 1-

READ -- I~~,~~~+=+=~;+==::l
'\I!!! ~
MEMORY ~
WRITE -' ~ ',v
DS ;g ~f@-l
INPUT /
OUTPUT -'
"""J<-+_--~+_+_--+-_, ~
~ .~m
~/"I .... - - -...
~
.J--_
f-~I ~ -@- .JI' .. ~
INTERRUP~ f-@-'4 -.IM'!I...." ~Y' . J . r-_ r.---
ACKNOWLEDGE -"!!:J.'- -1(!:;lI-1 .. ...---}
STo-STg
)<
READ/WRIfE---....
NORMAL/SYSTEM ~------------------------------~I
BYTE/WORD
-~'-'--'-'--SHARP---'-'--~-"--"'"
319
Z8001 IZ8001 AlZ80021Z8002A Central' Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
• Register Organization
The 28000 CPU is a register-oriented machine
that offers sixteen 16-bit general-purpose regis- Rol7 RHO 01 7 RLO
01 }
ters and a set of special system registers.
(1) General-purpose register
RROf
RR2,
=~I
RHl
RH2 II
RLl
RL2
I RQO
All general-purpose registers can be used as R31 RH3 "" RL3

accumulators and all but" one as index registers or
}R~
memory pointers.
../
RR4{
R41 RH4 i RIA
Register flexibility is created by grouping and R51 RH5 I RL5

overlapping multiple registers (Fig. 1 and 2). For
byte operations, the first eight 16-bit registers RR6{
R61 RH6 I RL6
(RO ... R7) are treated a~ sixteen 8-bit registers

R71 RH7 ! RL7
}R~
{ RsI15 0
(RLO, RHO, ..., RL7, RH7). The sixteen 16-bit reg~
RR8 R91
isters are grouped in pairs (RRO ... RR14) to form
32-bit long-word registers. Similarly, the register { RIOI
set is grouped in quadruples (RQO ... RQ12) to RRIO Rlli
form 64-bit registers.
(2) Specific -purpose register RR12{ RI21
The 28000 CUP has the following specific-pur- . Rl3
pose registers. RQl2
• Refresh counter { R141
RR14 Rl5 SYSTEM STACK POINTER
• Program status register
• Program status area pointer R15 NORMAL STACK POINTER
The refresh counter can be used to automatically
Fig. 2 Z8002 general-purpose register
refresh dynamic memory. The refresh counter reg-
ister consists of a 9-bit row counter, a 6-bit rate
RRO{
Ro~17====R=H=0===0*!=7==R=L=0==~0 RATE 9 S ROW o
I RHI i RLl
I I I I I I
R2~1==~R=H=2==~!===R=L=2==~
I I
R3~L====R=H=3==~i==~R~L~3==~
RR2{
Fig. 3 Refresh counter
R4~1====R=H=4===*i===§RL~4~==9
RR4{
R5~1==~R=H=5==ii==RL=5==~ counter and an enable bit (Fig. 3).
R6~1====R=H~6===\~I==~R§L~6==~
This group of status registers contains the prog-
RR6{ ram counter, flags and control words. When an in-
R7~1====R=H=7==~===R=L=7==~ terrupt or trap occurs, the entire" group is saved
RRS{ =:~I==================~ "and a new program status group is loaded.
Fig. 4 illustrates how the program status groups
.of the 28001 and 28002 differ.
RRIO{RIO :=1= = = = = = = = = = = 9
Rll~l.=======~
RR12{ ::: ==============:
:=1
R14' SYSTEM STACK POINTER (SEG.NO.)

RQI2
R14 NORMAL STACK POINTER (SEG.NO.)
RRl4 {
" R15' SYSTEM STACK POINTER (OFFSET)
Rl5 NORMAL STACK POINTER (OFFSET)
Fig. 1 Z8001 general-purpose register

Z8001 IZ8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
trap, which is generated by the 28010.

The remaining traps occur when instructions li-
mited to the system mode are used in the normal
mode, or as a result of the System Call instruction,
or for an EPA instruction. The descending order of
priority for traps and interrupts is : internal traps,
non-maskable interrupt, segmentation trap, vec-
tored interrupt and non-vectored interrupt.
Z8001 Program Status R-egisters When an interrupt or trap occurs, the current
~ 0 program status is automatically pushed on the sys-
I0 ISfGIj'Ef<jT ~UIj'B~R I0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 I tem stack. The program status consists of the pro-
cessor status (PC and FCW) plus a 16-bit identi-
l,urPfRPFls~T, 10,0,0,0,0,0,0,01 fier. The indentifier contains the reason or source
Z8002 Program Status Area Pointer of the trap or interrupt. For internal traps, the
identifier i.s the first word of the trapped instruc·
~ 0 FLAG AND tion. For external traps or interrupts; the identifier
I0 ~/3EP.4JVIE!NVIf 0, 0 , 0 Ic Iz Is HDAI H I0 , 0 1 WORD
CONTROL
is the vector on the data bus read by the CPU dur-
I , , , , " ADDRESS
, , , , , , J I PROGRAM
COUNTER
ing the interrupt-acknowlege or trap-acknowlege
cycle.
Z8002 Program Status Registers
After saving the current program status, the new
~ 0 program status is automatically loaded from the
I ,UfP~RrIfITfRI 10,01 0 ,0,0,0,0,01
program status area in system memory. This area
is designated by the program status area pointer
Z8001 Program Status Pointer
(PSAP).
Fig. 4 zaooo CPU status group
• Data Type
28000 instructions can operate on bits, BCD
digits (4bits), bytes (8 bits), words (16 bits), long
• Interrupt and Trap Structure
words (32 bits) and byte strings and word strings
The 28000 provides a very flexible and power- (up to 64 kilobytes long). Bits can be set, reset and
ful interrupt and trap structure. Interrupts are ex- tested ; digits are used in BCD arithmetic opera-
ternal asynchronous events requiring CPU atten- tions ; bytes are used for charircters or small inte-
tion, and are generally triggered by peripherals ger values; words are used for integer values, in-
needing service_ Traps are synchronous events re- structions and nonsegmented addresses; long
sulting from the execution of certain instructions. words are used for long integer values and seg-·
Both are processes in a similar manner by the CPU. men ted addresses. All data elements except strings
The CPU supports three types of interrupts can reside either in registers or momory. Strings
(non-maskable, vectored and non-vectored) and are stored in memory only.
four traps (system call, Extended Process The basic data element is the byte. The number
Architecture instruction, privileged instructions of bytes used when manipulating a data element is
and segmentation trap). The vectored and non- either implied by the operation or-for strings and
vectored interrupts are maskable. Of the four multiple register operations-explicitly specified in
traps, the only external one is the segmentation the instruction .
.-.-----..~-SHARP-~-------
321
------.-,....... ...........,---
Z8001 IZ8001 A/Z8002/Z8002Al Central Pr6cessingUnit LH8001 ILH80001 AlLH8002/LH~OO2A
.-,.-,.-,-.-,
• Addressing Modes
Mode Operand Addressing Operand Value
In the Instruction In a Register In Memory
Register The content of the

IREGISTER ADDRESS HOPERANDI register'
(R)
Immediate
IOPERANDI In the instruction
(1M)
Indirect The content of the location

Register IREGISTER ADDRESS HADDRESSI ;.1 OPERAND I whose address is in the
(IR) register
Direct The content of the location

Address IADDRESSI ;.1 OPERAND I whose address is in the
(DA) instruction
The content of the location

Index IREGISTER ADDRESS DISPLACEMENT whose address is the
address in the instruction.
(X)
I BASE ADDRESS + OPERAND I offset by the content of
the reg ister
The content of the loclltion

whose address is the
I I '~OPERANDI
Relative PC VALUE content of the program
Address
(RA) I DISPLACEMENT
counter. offset by the
displacem ent in the
instruction

Base IREGISTER ADDRESS ASE ADDRES whose address is the
address in the res ister •
Address
(BA)
I DISPLACEMENT + OPERAND I offset by the displacement
-in the instruction

Base IREGISTER ADDRESS BASE ADDRESS whose address is the
Index address in the register.
(BX)
I REGISTER ADDRESS DISPLACEMENT + OPERANDI offset by the displacement
in the reg ister
Z8001 IZ8001 AlZ8002/Z8002A Centra.! Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
.-.-.-.-..-.-.-..-.-..-..-..-.-..-.--.-.-..-
• Instruction Set Summary

The 28000 provides the following types of in- Instruction Set
_ Bit Manipulation
structions :
- Load and Exchange - Rotate and Shift
- Arithmetic _ Block Transfer and String Manipulation
-Logical _ Input/Output
- Program Control - CPU Control
Clock Cycles 1 *
Mnemonics Operands Addr. Word Byte Long Word Operation
Modes NS SS SL NS SS SL
Load CLR dst R 7 Clear
,and CLRB IR 8 dst +- 0
Exchange DA 11 12 14
X 12 12 15
EX R, src R 6 Exchange
EXB IR 12 R ++ src
DA 15 16 18
X 16 16 19
LO R, src R 3 5 Load into Register
LOB 1M 7 11 R +- src
LOL 1M 5 (Byte only)
IR 7 11
DA 9 10 12 12 13 15
X 10 10 13 13 13 16
LO dst, R
BA
BX
IR
14
14
8
17
17
11 Load into Memory (Store)
&
LOB DA 11 12 14 14 15 17 dst +- R
LOL X 12 12 15 15 15 18
BA 14 17
BX 14 17
LO dst, 1M IR 11 Load Immediate into Memory
LOB DA 14 15 17
X 15 15 18 dst +- 1M
LOA R, src DA 12 13 15 Load Address
X 13 13 16 R +- source address
BA 15
BX 15
LOAR R, src RA 15 Load Address Relative
R <- source address
LOK R, src 1M 5 Load Constant
R <- n (n=0"'15)
LOM R, src, n IR 11 Load Multiple
DA 14 15 17 +3n R <- src (n consecutive words)
X 15 15 18 (n=1...16)
LOM dst, R, n IR 11 Load Multiple (Store Multiple)
DA 14 15 17 +3n dst +- R (n consecutive words)
X 15 15 18 (n=1...16)
LOR R, src RA 14 17 Load Relative
LORB R +- src
LORL (Ran~e -32,768"'+32,7671
Note
dst: destination cc: flag PS: program status
8rc: source b,n nemerical value ®: indirect register
flag: flag SP stack pointer
PC program counter
*1: NS= Non Segmented SS = Segmented Short Offset SL=Segmented Long Offset
~'-'----'-~-SHARP'---'--'------
323
- .............__....._--..........- ..........................
Z8001/Z800tAlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 AI LH8002/LH8002A
Clock Cycles 1*
Load and LDR dst, R RA 14 17 Load ·Relative (Store Relative)
Exchange LQRB dst - R
(Continued) LDRL (Range - 32, 768'" + 32, 767)
POP dst,IR R 8 12 Pop
POPL IR 12 19 dst - IR
DA 16 16 18 23 23 25 Autoincrement contents of R
X 16 16 19 23 23 26
PUSH IR, src R 9 12 Push
PUSHL 1M 12 Autodecrement contents of R
IR 13 20 IR - sr.c
DA 14 14 16 21 21 23
X 14 14 17 21 21 24
Arithmetic ADC R, src R 5 Add with Carry
ADCB R - R+src+carry
ADD R, src R 4 8 Add
ADDB 1M 7 14 R - R+src
ADDL IR 7 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
CP R, src R 4 8· Compare with Register
CPB 1M 7 14 R·src
CPL IR 7 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
CP dst, 1M IR 11 Compare with Immediate
CPB DA 14 15 17 dst·IM
X 15 15 18
DAB dst R 5 Decimal Adjust
DEC dst, n R 4 Decrement by n
DECB IR 11 dst-dst·n
DA 13 14 16 (n=1"'16)
X 14 14 17
DIV R, src R 107 744 Divide (signed)
DIVL 1M 107 744 Word: Rn+ 1 - Rnm -;- src
IR 107 744 Rn - remainder
DA 108 109 111 745 746 748 Long Word: Rn+2m +3 - Rn... n7src
X 109 109 112 74'6 746 749 Rn,n+l - remainder
EXTS dst R 11 11 Extend Sign
EXTSB Extend sign of low order half of dst
EXTSL through high order half of dst
INC dst, n R 4 Increment by n
INCB IR 11 dst - dst+n
DA 13 14 16 (n=1"'16)
X 14 14 17
MULT R, src R 70 282*2 Multiply (Signed)
MULTL 1M 70 282*2 Word: Rmn + 1 - Rn+1"src
IR 70 282*2 Long Word: Rn"'n+3 - Rn~2m+3"SrC
DA 71 72 74 283 *2 284 *2 ·286 *2 * 2: Plus seven cycles for each 1
X 72 72 75 284 *2284 *2 287 *2 in the multiplicand
324
--........__...._............- ............_....-
Z8001 IZ8001 A/Z8002/Z8002A Central Processing
, , '
Unit LH8001/LH8001A/LH8002/LH8002A
Clock Cycles*l
Arithmetic NEG dst R 7 Negate
(Continued) NEGB 1R 12 dst +- O-dst
DA 15 16 18
X 16 16 19
SBC R, src R 5 Subtract with Carry
SBCB R +- R-src-carry
SUB R, src R 4 8 Subtract
SUBB 1M 7 14 R +- R-src
SUBL 1R 7 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
Logic AND R, src R 4 AND
ANDB 1M 7 R +- RAND src
1R 7
DA 9 10 12
X 10 10 13
COM dst R 7 Complement
COMB 1R 12 dst +- NOT dst
DA 15 16 18
~
X 16 16 19
OR R, src R 4 OR
ORB 1M 7 R +- R OR src
1R 7
DA 9 10 12
X 10 10 13
TEST dst R 7 13 Test
TESTB 1R 8 13 dst OR 0
TESTL DA 11 12 14 16 17 19
X 12 12 15 17 17 20
TCC cc, dst R 5 Test Condition Code
TCCB Set LSB if cc is true
XOR R, src R 4 Exclusive OR
XORB 1M 7 R +- R XOR src
1R 7
DA 9 10 12
X 10 10 13
Program CALL dst 1R 10 15 Call Subroutine
Control DA 12 18 20 Autodecrement SP
X 13 18 21 @SP +- PC
PC +- dst
CALR dst RA 10 15 Call Relative
Autodecrement SP
@SP +- PC
PC +- PC+dst (Range
-4,094- +4,096)
DJNZ R, dst RA 11 Decrement and Jump if Non-Zero
DBJNZ R +- R-l
If R=/ 0 : PC +- PC+dst
(Range-254-0)
325
_........ .-: ...
Z8001/Z8001 AlZ8002/Z8002A Central Processing Unit, LH8001/LH8001AlLH8002/LH8002A
.-.-,............................................
Clock Cycles *1
Program IRET*3 13 16 Interrupt Return
Control SP +- SP+2
(Continued) PS +- @SP
Autoincrement SP
JP cc, dst IR 10 15 (taken) Jump Conditional
IR 7 7 (not taken) If cc is true : PC +- dst
DA 7 8 10
X 8 8 11
JR cc, dst RA 6 Jump Conditional Relative
If cc is true : PC +- PC + dst
(Range -256-+254)
RET cc 10 13 (taken) Return Conditional
7 7 (n,ot taken) If cc is true : PC +- @ SP
Autoincrement SP
SC src 1M 33 39 System Call
Autodecrement SP
@ SP +- old PS
Push instruction
PS +- System Call PS
Bit BIT dst, b R 4 Bit Test Static
Manipulation BITB IR 8 Z flag +- NOT dst bit specified
DA 10 11 13 by b
X 11 11 14
BIT dst, R R 10 Bit Test Dynamic
BITB Z flag +- NOT dst bit specified
by contents of R
RES dst, b R 4 Reset Bit Static
RESB IR 11 Reset dst bit specified by b
DA 13 14 16
X 14 14 17
RES dst, R R 10 Reset Bit Dynamic
RESB Reset dst bit specified by con·
tents of R
SET dst, b R 4 Set Bit Static
SETS IR 11 Set dst bit specified by b
DA 13 14 16
X 14 14 17
SET dst, R R 10 Set Bit Dynamic
SETS Set dst bit specified by contents
of R
TSET dst R 7 Test and Set
TSETB IR 11 S flag +- MSB of dst
DA 14 15 17 dst +- allis
X 15 15 18
*3: Privileged instruction. Executed system mode only.
---~---~"""""'-~-SHARP ~_-..-r _ _ . - . ___ . -_ _

326
Z8001/Z8001A1Z8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
---------~------~---~~~---~----'---~....,
Clock Cycles *1
Rotate RLOB R, src R 9 Rotate Digit Left
and RROB R, src R 9 Rotate Digit Right
Shift RL dst, n R 6 for n= 1 Rotate Left
RLB R 7 for n=2 by n bits (n=l, 2)
RLC dst, n R 6 for n=1 Rotate Left through Carry
RLCB R 7 for n=2 by n bits (n=l, 2)
RR dst, n R 6 for n=1 Rotate Right
RRB R 7 for n=2 by n bits (n=l, 2)
RRC dst, n R 6 for n= 1 Rotate Right through Carry
RRCB R 7 for n=2 by n bits (n= 1,2)
SOA dst, R R (15+3n) (Hj+3n) Shift Dynamic Arithmetic
SOAB Shift dst left or right
SOAL by contents of R
SOL dst, R R (15+3n) (15+3n) Shift Dynamic Logical
SOLB Shift dst left or right
SOLL by contents of R
SLA dst, n R (13+3n) (13+3n) Shift Left Arithmetic
SLAB by n bits
SLAL
~
SLL dst, n R (13+3n) (13+3n) Shift Left Logical
SLLB by n bits
SLLL
SRA dst, n R (13+3n) (13+3n) Shift Right Arithmetic
SRAB by n bits
SRAL
SRL dst, n R (13+3n) (13+3n) Shift Right Logical
SRLB by n bits
SRLL
Block CPO R" src, Ry, cc IR 20 Compare and Decrement
Transfer CPOB Rx-src
and String Autodecrement src address
Manipulation Ry+-Ry-l
CPOR Rx, src, Ry, cc IR (11+9n) Compare, Decrement and Repeat
CPORB Rx-src
Autodecrement src address
Ry+-Ry-l
Repeat until cc is true or Ry=O
CPI Rx, src, Ry, cc IR 20 Compare and Increment
CPIB Rx-src
Autoincrement src address
Ry +-Ry- l
CPIR Rx, src, Ry, cc IR (11+9n) Compare, Increment and Repeat
CPIRB Rx-src
Autoincrement src address
Ry +- Ry- l
Repeat until cc is true or Ry = 0
CPSO dst, src, R, cc IR 25 Compare String and Decrement
CPSOB dst-src
Autodecrement dst and src
addresses
R+-R-l
~""-''------SHARP-----'---''-'
327
............... -................. -............-..-........-..-.........................
Z8001/Z8001A1Z8002/Z8002A Central "Processing Unit LH8001/LH8001 A/LH8002/LH8002A
Clock Cycles*l
Block CPSDR dst, src, R, cc IR (11 + 14n) Compare String, Decr. and Repeat·
Transfer CPSDRB dst-src
and String Autodecrement dst and src
Manipulation addresses
(Continued) R +- R-l
Repeat until cc is true or R= 0
CPSI dst, src, R, cc IR 25 Compare String and Increment
CPSIB dst-src
Autoincrement dst and src
addresses
R +- R-l
CPSIR dst, src, R, cc IR (11+14n) Compare'String, Iner. and Repeat
CPSIRB dst·src
addresses
R +- R-l
Repeat until cc is true or R= 0
LDD dst, src, R IR 20 Load and Decrement
LDDB dst +- src
addresses
R +- R-l
LDDR dst, src, R IR (11+9n) Load, Decrement and Repeat
LDDRB dst +- src
addresses
R- R-l
Repeat until R= 0
LDI dst, src, R IR 20 Load and Increment
LDIB dst +- src
addresses
R -R-l
LDIR dst, sre, R IR (11+9n) Load, Increment and Repeat
LDIR~ dst +- src
addresses
R - R-l
Repeat until R=O
.fROB dst, sre, R IR 25 Translate and Decrement
dst - src (dst)
Autodecrement dst address R +-
R-l
-----.-~----SHARP -.-..-.--------"--
328
Z8001 IZ8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 AlLH8002/LH8002A
Clock Cycles *1
Block TRDRB dst, stc, R IR (11 + 14n) Translate, Decrement and Repeat
Transfer dst .... stc (dst)
and String Autodecrement dst address R ....
Manipulation R-1
(Continued) Repeat until R = 0
TRIB dst, src, R IR 25 Translate and Increment
dst .... src (dst)
Autoincrement dst address R ....
R-l
TRIRB dst, src, R IR (11 + 14n) Translate, Increment and Repeat
dst .... src (dst)
Autoincrement dst address R ....
R-l
Repeat until R = 0
TRTDB srcl, src 2, R IR 25 Translate and Test, Decrement
PHI .... src2 (src 1)
Autodecrement src 1 address R
.... R-1
TRTDRB src1, src2, R IR (11 + 14n) Translate and Test, Decr. and
Repeat
RH1 .... src 2 (src 1)
Autodecrement src 1 address
R .... R-1
Repeat until R = 0 or RH 1 = 0
TRTIB src1, src2, R IR 25 Translate and Test, Increment
RH1 .... src2 (src n
Autoincrement src 1 address R
.... R-1
TRTIRB src1, src2, R IR (11 + 14n) Translate and Test, Incr. and
Repeat
RH1 .... src 2 (src 1)
Autoincrement src 1 address
R .... R-1
Repeat until R = 0 or RH 1 = 0
Input! IN*3 R, src IR 10 ,Input
Output INB*3 DA 12 R .... src
IND*3 dst, src, R IR 21 Input and Decrement
INDB*3 dst .... src
Autodecrement dst address
R+-R-l
INDR*3 dst, src, R IR (11 + IOn) Input, Decrement and Repeat
INDRB*3 dst .... src
Autodecrement dst address
R .... R-1
Repeat until R = 0
INI*3 dst, src, R IR 21 Input and Increment
INIB*3 dst .... src
Autoincrement dst address
R .... R-1
* 3: Privileged instructions. Executed in system mode only.
.-.--------SHARP-----------
329
Z8001/Z8001A/Z8002JZ8002A Central Processing Unit LH8001/LH8001 A/LH8002/LH8002A
,.....,.....,.....,..-......,.....,.-.....,..-...-...-......, .....................-......,
Clock Cycles *1
Input! ' INIR*3 dst, src, R IR (11 + IOn) Input, Increment and Repeat
Output INIRB,!3 dst - src "
(Continued) Autoincrement dst address

R- R-1
Repeat until R= 0
OUT*3 dst, R IR 10 Output
OUTB*3 DA 12 dst - R
OUTO *3 dst, src, R IR 21 Output and Decrement
OUTDB*3 dst - src
R- R-1
OTOR*3 dst, src, R IR (11 + IOn) Output, Decrement and Repeat
OTDRB*3 dst - src
R -R-1
Repeat until R= 0
OUTI*3 dst, src, R IR 21 Output and Increment
OUTIB*3 dst - src
R-R-1
bTIR*3 dst, src, R IR (11 + IOn) Output, Increment and Repeat
OTIRB*3 dst - src
R-R-1
Repeat until R= 0
/ SIN*3 R, src DA 12 Special Input
SINB*3 R - src
SIND*3 dst, src, R IR 21 Special Input and Decrement
SINOB*3 dst - src
Autoincrement dst address'
R -,R·1
SINOR*3 dst, src, R IR (11 + IOn) Special Input, Decrement and

SINORB*3 Repeat
dst - src
R -R-1
Repeat until R= 0
SINI*3 dst, src, R IR 21 Special Input and Increment
SINIB*3 dst - src
R-R-1
SINIR*3 dst, src, R IR (11 + IOn) Special Input, Increment and
SINIRB*3 Repeat
dst - src
R- R-1
Repeat until R= 0
SOUT*3 dst, src DA 12 Special Output
SOUTB*3 dst - src
*3: Privileged instructions. Executed in system mode only.
- - - - - - - - - - - - - - - S H A R P - - - - - - - - - - - - - . - . .........- -
330
Z8001/Z8001 AlZ8002/Z8002A Central Processing Unit LH8001 ILH8001 A/LH8002/LH8002A
.-..-..-..-...-..-..-...-..-...-...-..-..-...-..------.-.
Clock Cycles *1
Input! SOUTD*3 dst, sre, R IR 21 Special Output and Decrement
Output SOUTDB dst - sre
(Continued) *3 Autoincrement dst address
R-R-1
SOTDR*3 dst, sre, R IR (11 + IOn) Special Output, Deer. and Repeat
SOTDRB*3 dst - sre
Autoinerement dst address
R -R-1
Repeat until R = 0
SOUTI*3 dst, src, R IR 21 Special Output and Increment
SOUTIB*3 dst - src
R -R-1
SOTIR*3 dst, src, R R (11 +10n) Special Output, Incr. and Repeat
SOTIRB*3 dst - src
Autoin~rement dst address
R -R-1
Repeat until R = 0
CPU COMFLG flags 7 Complement Flag
~
Control (Any combination of C, Z, S, P/V)
-DI*3 int 7 Disable Interrupt
(Any combination of NVI, VI)
EI*3 int 7 Enable Interrupt
(Any combination of NVI, VI)
HALT*3 (8+3n) HALT
LDCTL *3 CTLR, src R 7 Load into Control Register
(TLR - src
LDCTL *3 dst, CTLR R 7 Load from Control Register
dst -- CTLR
LDCTLB FLGR, src R 7 Load into Flag Byte
Register
FLGR -- src
LDCTLB dst, FLGR R 7 Load from Flag Byte
Register
dst -- FLGR
LDPS*3 src IR 12 16 Load program Status
DA 16 20 22 PS - src
X 17 20 23
MBIT*3 7 Test Multi·Micro Bit
Reset S if M] is Low; set S if M]
is High.
MREQ*3 dst R (12+7n) Multi-Micro Request
MRES*3 5 Multi-Micro Reset
MSET*3 5 Multi-Micro Set
NOP 7 No Operation
RESFLG flag 7 Reset Flag
(Any combination of C, Z, s, P/V)
SETFLG flag 7 Set Flag
(Any combination of C, Z, s, PI V)
* 3: Privileged instructions_ Executed in system mode only_
----~-~-.-.--SHARP.-.-.--~---~
331
Z80101Za010A Memory Management Unit UW01 O/lH801 OA·
LH8010/LH8010A zao IOlZaO lOA Memory

Management Unit
The Z8010 Memory Management Unit (MMU)
manages the large 8M byte addressing spaces of
the Z8001 CPU. The MMU provides dynamic DMASYNC 2
segment relocation as well as numerous memory SEGT 3
protection feature. SUP 4
Dynamic segment relocation makes user software RESET 5
addresses independent of the physical memory
addresses, there by freeing the user from specify·
ing where information is actually located in the
physical memory. It also provides a flexible, effi-
cient method for supporting multi-programming
systems. The MMU uses a translation table to
transform the 23-bit logical address' output from
the Z8001 CPU into a 24-bit address for the
physical memory. (Only logical memory addresses
go to an MMU for translation: 110 addresses and
data, in general, must bypass this component.)
RESERVED 23
• Features
1. Dynamic segment relocation makes software Top View
addresses indepe~dent of physical memory
addresses.
2. Sophisticated memory management features in-
clude access validation that protects memory
areas from unauthorized or unintentional ac-
cess, and a write-warning indicator that pre-
dicts stack overflow.
3. 64. variable-sized segments from 256 to
65,536 bytes can be mapped into a total
. physical address space of 16M bytes; all 64
segments are random~y accessible.
4. Multiple MMUs can support several translation
tables for each Z8001 address space. <
5. MMU architecture supports multiprogramming

systems and virtual memory implementations.
332
Z8010/Z8010A Memory Management Unit LH801 O/LH801 OA
• Block Diagram
Address/Data Bus Physical Address

r -____ ~A~________ ~
A
Physical
16 Address
Segment
Number
Violation
Checker
Segment Tr ap Request
Normal/System Mode
Vee
Reset
• Pin Description
16 most-significant bits of the physical memory loca-
As -A 23 Address bus 3-state 0
tion.
Bidirectional 8 most-significant bits of the multiplexed system
AD s -AD 15 Address/ data bus 3·state address/ data bus.
AS Address strobe I Active "Low". Addresses are valid.
DS Data strobe I Active "Low". Data are valid.
R/W Read/write I Read at "High", Write at "Low".
N/S Normal/system I Normal mode at "High", System mode at "Low".
ST o-ST 3 Status I Specifies 28001 CPU status.
SN o-SN 6 Segment number I Designates segments to be accessed.
--- Active "Low". Indicates any access violation except
SUP Suppress Open drain
write warning.
---- Active "Low". Detects an access violation or write
SEGT Segment trap reguest 0
warning.
CS Chip select I Active "Low". Selects an MMU for a control command.
DMA/segment number
DMASYNC I Active "High". Segment numbers are valid.
Synchronization strobe
RESET Reset I Active "Low". Resets the MMU.
Standard 28000 system clock used as internal sync
CLK System clock I
signal.
333
Z801 O/Z801 OA Memory Management Unit . LH801 O/LH801 OA
. - . . - ............ - . . - . . - - . -.........._ _M_.:. . . . . . . . .: -. . . .. - .
+5V
Parameter Symbol Ratings Unit 2;2kO
Input voltage VIN -0.3-+7.0 V From
Output voltage VOUT -0.3-+7.0 V output under test
Operating temperature Topr 0-+70 "C
Storage temperature Tst~ -65-+150 "C
• DC Characteristics (Vcc=5V±5%, Ta=0-70"C)

Driven by external
Clock input high voltage VCH Vcc-OA Vcc+ 0.3 V
clock oscillator
Driven by external
Clock input low voltage VCL -0.3 0045 V
clock oscillator
Input high voltage VIR 2.0 Vcc+ 0.3 V
Input low voltage V1L -0.3 O.S V
Output high voltage VOH IOH = -250,uA 204 V
Output low voltage VOL IOL =+2.0rnA 004 V
Input leakage current 1 In... 1 OA~VIN~2AV 10 ,uA
Output leakage current 1 IOL 1 OA~VouT~2AV 10 ,uA
The on-chip back-bias voltage oscillator takes approximately 20 ms to pump the back-bias voltage to -2.5V after the power
has been turned on. The performance of the Z8010 Z-MMU is not guaranteed during this period.
LHS010 LHS010A
No. Symbol Parameter Unit Note
MIN. MAX. MIN. MAX.
1 TcC Clock cycle time 250 165 ns
2 TwCh Clock width (high) 105 70 ns
3 TwCI Clock width (low) 105 70 ns
OS ~ (acknowledge) to read data
6 TdOSA (ROv) 100 SO ns 1
valid delay
OS t (acknowledge) to read data
7 TdOSA(ROf) 75 60 ns
float delay
S TdOSR (ROv) OS ~ (read) to AO output driven delay 100 SO ns 1
9 TdOSR(ROf) OS t (read) to read data float delay 75 60 ns 1
10 TdC (WOv) eLK t to write data valid delay 125 SO ns
CLK ~ to write data not valid
11 TdC (WOn) 30 ~O ns
hold time
12 TwAS Address strobe width 60 50 ns
13 TsOFF (AS) Offset valid to AS t setup time 45 35 ns
14 ThAS (OFFn) AS t to offset not valid hold time 60 40 ns.
15 TdAS (C) AS ~ to CLK t delay 110 I 90 ns
16 TdOS (AS) OS t to AS ~ delay 50 30 ns
334
Z801 0/Z801 OA Memory Management Unit LH801 0/LH801 OA
LH8010 LH8010A
MIN. MAX. MIN. MAX.
17 TdAS (OS) AS t to OS ~ delay 50 40 ns
18 TsSN (C) SN data valid to CLK t setup time 100 40 ns
19 ThC (SNn) CLK f to SN data not valid hold time 0 0 ns
20 TdOMAS (C) OMASYNC valid to CLK t delay 120 80 ns
Status (ST o·ST 3, NIS, R/W) valid to
21 TdSTNR (RS) 50 30 ns
AS t delay
22 Tdc (OMA) CLK f to OMASYNC ~ delay 20 15 ns
23 TdST (C) Status (ST o·ST 3) valid to CLK t delay 100 60 ns
24 TdOS (STn) OS f to status not valid delay 0 0 ns
Offset valid to address output -
25 TdOFF (Av) 175 90 ns 1
valid delay
Status valid to address output
26 TdST (Ad) 155 75 ns 1
driven delay
27 TdOS (Af) OS ·t to address output float delay 160 130 ns 1
28 TdAS (Ad) AS ~ to add res output driven delay 145 70 ns 1
29 TdC (A v) CLK t to address output valid delay 255 155 ns 1
30 TdAS (SEGT) CLK t to SEGT t delay 160 100 ns I, 2
31 TdC (SEGT) AS f to SUP ~ delay 300 200 ns 1,2
32 TdAS (SUP) OS t to SUP ~ delay 150 90 ns 1,2
Chip select input valid to AS t
33 TdDS (SUP) 155 100 ns 1,2
setup time
AS t to chip select input not valid
34 TsCS (AS) 10 10 ns
hold time
35 ThAS (CSn) AS t to CLK t delay 60 40 ns
36 TdAS (C) AS t to SEGT t delay 0 0 ns
Chip select input valid to RESET t
37 TsCS (RST) 150 100 ns
setup time
RESET t to chip select input not valid
38 ThRST (CSn) 0 0 ns
hold time
39 TwRST RESET width (low) 2TcC 2TcC ns
40 TdC (RDv) CLK t to read data valid delay 460 300 ns 1
41 TdDS (C) OS t to CLK t delay 30 20 ns
42 TdC (OS) CLK ~ to OS f delay 0 0 ns
t Rising edge, ! Falling edge.
Note 1: 50pF Load
Note 2: 2.2k n Pull·up
.-...-.-------SHARP----------
335
Za()1\O/Z8010A Memory Management Unit LH80tO/LH8010A
• Composite AC Timing Chart
CLOCK
TRAP
ACKNOWLEDGE
READ MMU
WRITE MMU
AS
SIOI
!'c!NO!.L,!D~E ,
---
DS
{ MEMORY 16
ACCESS ~.++~---H~~~
-......t...-----'I
SNo-SNs
DMASYNC
ST o -ST 3
N/S, R/W
SUP
CS
~~-------SHARP------~~"'--'----~~
336
• MMU Register Organization structure of the segment, and two encode the tYpes
of access that have been made to the segment. A
The MMU contains three types of registers: Seg-
flag is set when its value is 1. The following brief
ment Descriptor, Control and Status. A set of 64
descriptions indicate how these flags are used.
Segment Descriptor Registers supplies the informa-
( i ) Read-Only (RD) When this flag is set,
tion needed to map logical memory addresses to
the segment is read only and is protected against
physical memory locations. The segment number of
any write access.
a logical address determines which Segment De-
(ii) System-Only (SYS) When this flag is
scriptor Register is used in address translation.
set, the segment can be accessed only in System
Each Descriptor Register also contains the neces-
mode, and is protected against any access in Nor-
sary information for checking that the segment
mal mode.
location referenced is within the bounds of the seg-
(iii) CPU-Inhibit (CPU!) When this flag is
ment and that the type of reference is permitted. It
set, the segment is not accessible to the currently
also indicates whether the segment has been read
executing process, and is protected against any'
or written.
memory access by the CPU. The segment is, howev-
In addition to the Segment Descriptor Registers,
er, accessible under DMA.
the Z8010 MMU contains three 8-bit control reg-
(iv) Execute-Only (EXC) When this flag is
isters for programming the device and six 8-bit
set, the segment can be accessed only during an in-
status registers that record information in the'
struction fetch or access by the relative addressing
event of an access violation.
mode cycle, and thus is protected against any ac-
(1) Segment Descriptor Registers cess during other cycles.
Each of the 64 Descriptor Registers contains a (v) DMA-Inhibit (DMAI) When this flag is
16-bit base address field and an 8-bit attribute set, the segment can be accessed only by the CPU,
field (Fig. 1). The base address field is subdivided and thus is protected against any access under
into high- and low-order bytes that are loaded one DMA.
byte at a time when the descriptor is initialized. (Vi) Direction and Warning (DIRW) When
The limit field contains a value N that indicates N this flag is set, the segment memory locations are
+ 1 blocks of 256 bytes have been allocated to the considered to be organized in descending order and
segment. each write to the segment is checked for access to
The attribute field contains eight flags (Fig. 2). the last 256-byte block. Such an access generates a
Five are related to protecting the segment against trapto warn of potential segment overflow, but no
certain types of access, one indicates the special Suppress signal is generated.
(vii) Changed (CHG) When this flag is set,
BASE ADDRESS LIMIT ATTRIBUTE the segment has been changed (written). This bit is
FIELD FIELD FIELD set automatically during any write access to this
,----".---~,
15 87 07 07 o segment if the write access does not cause any
violation.
SDRO BAHO BALO LO AO
(vii~ Referenced (REF) When this flag is
SDRI BAH I BAll Ll Al
set, the segment has been referenced (either read or
SDR2 BAH2 BAL2 L2 A2 written). This bit is set automatically during any
access to.the segment if the access does not cause a
violation.
(2) Control Registers
,, The three user-accessible 8-bit control registers
,
i in the MMU direct the functioning of the MMU
SDR63 BAH63 ,I BAL63 L63 A63 (Fig. 3 ).The Mode Register provides a sophisti-
cated method for selectively enabling MMUs in
Fig_ 1 Segment description registers multiple-MMU configurations. The Segment
7 0 Address Register (SAR) selects a particular Seg-
I
I REF I CHG DIRWI DMAII EXC I CPUI I SYS I RD
ment Descriptior Register to be accessed during a
control operation. The Descriptor Selection Coun-
ter Register points to a byte within the Segment De-
Fig. 2 Attribute field in segment description scriptor Register to be accessed during a control
registers operation.
337
28010/28010A Memory Management Unit LH8010/LH8010A
The Mcide Register contains a 3~bit identifica- abies or disables the MMU from performing its
tion field (ID) that distinguishes among eight en- address translation and memory prote.ction func-
abled MMUs in a multiple-MMU configuration. tions. When this flag is set, the MMU performs
This field is used during the segment trap acknow- these tasks ; when the -flag is clear the Address
ledge sequence (refer to the section on Segment lines of the MMU remain 3-stated.
Trap and Acknowledge). In addition, the Mode Reg- The Segment Address Register (SAR) points to
ister contains five flags. . one of the 64 segment descriRtors. Control com-
mands to the MMU that access segment descriptors
7 3 2 o impliCitly use this pointer to select one of the de-
scriptors. This register has an auto-incrementing
ID
capability so that multiple descriptors can be
MODE REGISTER (MR) accessed in a block read/write fashion.
7 6 5 0 The Descriptor Selection Counter Register holds
I~EGMENT
- I
DESCRIPTOR' NUMBER
I I I I
I
_
a 2-bit counter that indicates which byte in the de-
scriptor is being accessed during the reading or
writing operation. A value of zero in this counter
,SEGMENT ADDRESS
'i 2 o indicates the high-order byte of the base address
field is to be accessed, one indicates the low-order
DSC
I I I I I I
byte of the base address, two indicates the limit
DESCRIPTOR SELECTION COUNT REGISTER (DSCR) field and three indicates the attribute field.
(3) Status Registers
Fig. 3 Countrol registers Six 8-bit registers contain information useful in
recovering from memory access violations (Fig. 4).
(i) Multiple Segment Table (MST) This
The Violation Type Register describes the condi-
flag indicates whether multiple segment tables are
tions that generated the trap. The Violation Seg-
present in the hardware configuration. When this
ment Number and Violation Offset Registers record
fla[ is set, more than one table is present and the
the most-significant 15 bits of the logical address
N/S line must be used to determine whether the
that causes a trap. The Instruction Segment Num-
MMU contains the appropriate table.
ber and Offset Registers record the most-signific-
(ii) Normal Mode Select (NMS) This flag
ant 15 bits of the logical address of the last in-
indicates whether the MMU is to translate addres-
struction fetched before the first accessing viola-
ses when the NlS line is High or Low. If. the MST
tion. These two registers can be used in conjunc-
flag is set, the N/S iine must match the NMS flag
tion with external circuitry that records the low-
for the MMU to translate segment addresses, other-
order offset byte. At the time of the addressing
wise the NMU Address lines remain 3-stated.
violation, the Bus Cycle Status Register records the
(iii) Upper Range Select (URS) This flag
bus cycle status (status code, read/write mode and
is used to indicate whether the MMU contains the
normal/system mode).
lower-numbered segment descriptors or the high-
The MMU generates a Trap Request for two
er-numbered segment descriptors. The most signi-
general reasons: either it detects an access viola-
ficant bit of the segment number must match the
tion, such' as an attempt to write into a read-only
URS flag for the MMU to translate segmentaddres-
segment, or it detects a warning condition, which is
ses, otherwise the MMU Address lines remain
a write into the lowest 256 bytes of a segment with
3-stated.
the DIRW flag set. When a violation or warning
(IV) Translate (TRNS) This flag indicates
condition is detected, the MMU generates a Trap
whether the MMU is to translate logical program
Request and automatically sets the appropriate'
addresses to physical memory locations or is to
flags. The eight flags in the Violation Type Regis-
pass the logical addresses unchanged to the mem-
ter describe the cause of a trap.
ory and without protection checking; In the non-
translation mode, the most significant byte of the Read-Only Violation (RDV) Set when the
output is the 7-bit segment number and the most CPU attempts to access a read-only segment and
significant bit is O. the 'R/W line is Low.
When this flag is set, the MMU performs address System Violation (SYSV) Set when the CPU
translation and attribute checking. accesses a system-only segment and the N/S line
(v) Master Enable (MSEN)' This flag en- is High.
338
CPU-Inhibit Violation (CPUIV) Set when the routine. Once set, no Trap Request signals are
CPU attempts to access a segment with the CPU- generated on subsequent violations. However, Sup-
inhibit flag set. press signals are generated on this and subsequent
Execute-Only Violation (EXCV) Set when CPU violations until the FA TL flag has been reset.
the CPU attempts to access an excute-only segment
in other than an instruction fetch or load relative • Memory Protection
instructions cycle_ Each memory segment is assigned several attri-
Segment Length Violation (SLV) Set when butes that are used to provide memory access pro-
an offset falls outside of the legal range of a seg- tection. A memory request from the Z8001CPU is
ment. accompanied by status information that indicates
Primary Write Warning (PWW) . Set when an the attributes of the memory request. The MMU
access is made to the lowest 256 bytes of a seg- compares the memory request attributes with seg-
ment with the DIRW flag set. ment attributes and generates a Trap Request
Secondary Write Warning (SWW) Set whenever it detects an attribute violation. Trap Re-
when the CPU pushes data into the last 256 bytes quest informs the Z8001 CPU and the system con-
of the system stack and EXCV, CPUIV, SL V, trol program of the violation so that appropriate
SYSV, RDV or PWW is set. Once this flag is set, action can be taken to recover. The MMU also
subsequent write warnings for accessing the sys- generates the Suppress signal SUP in the event of
tem stack do not generate a Segment Trap request. an access violation. Suppress can be used by a
Fatal Condition (FATL) Set when any other memory system to inhibit stores into the memory
flag in the Violation Type Register is set and either and thus protect the contents of the memory from
a violation is detected or a write warning condition erroneous changes.
6I:::::'=':=: :
occurs in Normal mode. This flag is not set during Five attributes can be associated with each seg-
a stack push in System mode that results in a ment. When an attempted access violates anyone of
warning condition. This flag indicates a memory the attributes associated with a segment, a Trap
access error has occurred in the trap processing Request and a Suppress signal are generated by the
MMU. These attributes are read only, execute only,
7 0 system access only, inhibit CPU accesses and in-
IFATLlswwlpwwlEXCVfPUlVI SLY ISYSVI RDV I hibit DMA accesses.
Segments are specified by a base address and a
VIOLATION TYPE range of legal offsets to this base address. On each
7 6 o access to a segment, the offset is checked against
SEGMENT NUMBER this range to insure that the access falls within the
o
allowed range. If an access that lies outside the seg-
ment is attempted, Trap Request and Suppress are
VIOLATION SEGMENT NUMBER generated.
7 o
Normally the legal range of offsets within a seg-
ment is form 0 to 256N + 255 bytes, where 0 ;:;;;
, ,
UPPER OFFSET
I
, N ~ 255. However, a segment may be specified so
VIOLATION OFFSET
5 4 3 0 that legal offsets range from 256N to 65,535
7 6
bytes, where 0 ~ N ~ 255. The later type of seg-
0 0 I N/S I R/W I CPU STATUS
I
ment is useful for stiJcks since the Z8000 stack
manipulation instructions cause stacks to grow
BUS CYCLE STATUS towerd lower memory locations. Thus when a stack
7- 6 0
grows to the limit of its allocated segment, addition-
0 SEGMENT NUMBER al memory can be allocated on the correct end of
I I I the segment. As an aid in maintaining stacks, the
INSTRUCTIONS, SEGMENT NUMBER MMU detects when a write is perfQrmed to the .
7 0
lowest allocated 256 bytes of these segments and
UPPER OFFSET generates a Trap Request. No Suppress signal is
generated so the write is allowed to proceed. This
INSTRUCTION OFFSET write warning can then be used to indicate that
more memory should be allocated to the segment.
Fig. 4 Status registers
339
Z8010/Z80tOA Memory Management Unit LH801 0/LH801 OA
• Segmented Addressing software. A translation table in the MMU associ-

ates the 7 - bit segment number with the base
The 8M bytes Z8001 addressing spaces are di- address of the physical memory segment. The
vided into 128 relocatable segments of up to 64K 16-bit logical address offset is added to the physic-
bytes each. A 23-bit segmented address uses a al base address .to obtain the actual physical mem-
7 -bit segment address to point to the segment, and. ory location. Because a base address always has a
a 16-bit offset to address any byte relative to the low byte equal to zero,
- beginning of the segment. The two parts of the seg-
mented· address may be manipulated separately. • Segment Trap and Acknowledge
The MMU divides the physical memory. into The Z8010 MMU generates a Segment Trap
256-byte blocks. Segments consist of physically when it detects an access violation or a write warn-
contiguous blocks. Certain segments may be desig- ing condition~ In the case of an ac·cess violation, the
nated so that writes into the last block generate a MMU also activates Suppress, which can be used to
warning trap. If such a segment is used as a stack, inhibit memory writes and to flag special data to be
this warning can be used to increase the segment returned on a read access. Segment Trap remains
size and prevent a stack overflow error. Low until a Trap Acknowlege signal is.received. If
The addresses manipulated by the programmer, a CPU -generated violation occurs, Suppress is
used by instructions and output by the Z8001 are asserted for that cycle and all subsequent CPU in-
called logical addresses. The MMU takes the logic- struction execution cycles until the end of the in-
al addresses and transforms them into the physical struction. Intervening DMA cycles are not suppres-
addresses required for accessing the memory (Fig. sed, however, unless they generate a violation.
4). This address transformation process is called· Violations detected during DMA cycles cause Sup-
relocation. press to be asserted during that cycle only-no Seg-
The relocation process is transparent to user ment Trap Requests are ever generated during
DMA cycles.
23 BIT LOGICAL ADDRESS Segment traps to the Z8001 CPU are handled
~~~~~~~~ ~__________A~______~ similarly to other types of interrupts. To service a
segment trap, the CPU issues a segment trap ack-
nowledge cycle. The acknowledge cycle is always
preceded by an instruction fetch cycle that is
IrsE"G."Nol ignored (the MMU has been designed so that this
r _ _ _ _ _~~USR USRI dummy cycle is ignored). During the acknowledge
=0 =11 cycle all enabled MMU s use the AddresslData lines
TABLE OF 64 o1 64\
65
DESCRIPTOR to indicate their status. An MMU that has gener-
SEGMENT 2 : I
: I ated a Segment Trap Request outputs a 1 on the AI
REGISTERS
: I D line associated with the number in its ID field ;
n n+6~
an MMU that has not generated a segment trap re-
n+1 I
r quest outputs a 0 on its associated AID line. AID
I lines for which no MMU is associated remain
I
. . I 3-stated.
~______-+__~6~~:~ Note: The ID field is used with multiple MMUs. In the multiple
organization one of the 8 ENABLE·state MMUs can be de-
tected. During a segment trap acknowledge cycle, an
MMU outputs a 1 on the AID line associated with this
bit, and a 0 on the other associated AID line. If two or
more violations occur while an instruction is being ex·
ecuted, the CPU uses the data (high-order byte) on· this
AID line as the distinguishing information, enabling an
MMU analysis in the segment trap handling routine.
Following the acknowlege cycle the CPU auto-
matically pushes the Program Status onto the sys-
tem stack and loads another Program Status from
c=====~v~~~------ the Program Status Area. The Segment Trap line is
24-BIT PHYSICAL ADDRESS reset during the segment trap acknowledge cycle.
Suppress is not generated during the stack push. If
Fig. 5 Logical-to-physical address translatior:"! the store creates a write warning condition~ a Seg-
ment Trap Request is generated and is serviced at
340
Z8010/Z8010A Memory Management Unit LH801 O/LH801 OA
the end of the Program Status swap. The SWW flag • MMU Commands
is also set. Servicing this second Segment Trap Re-
quest also creates a write warning condition, but Table 1 Segment descriptor register
because the SWW flag is set, no Segment Trap Re- commands
quest is generated. If a violation rather than a Code
Instruction
write warning occurs during the Program Status (Hex)
swap, the FA TL flag is set rather than the SWW 08 Read/write base field
flag. Subsequent violations cause Suppress to be 09 Read/write limit field
asserted but not Segment Trap Request. Without OA Read/write attribute field
the SWW and FA TL flags, trap processing 08 Read/write descr\ptor (all fields)
routines that generate memory violations would re- Read/write base field;
OC
peatedly be interrupted and called to process the Increment SAR
trap they created. Read/write limit field;
OD
The CPU routine to process a trap request Increment SAR
should first check the FA TL flag to determine if Read/write attribute field;
OE
a fatal system error has occurred. If not, the SWW Increment SAR
flag should be checked to determine if more mem- Read/write descriptor;
OF
ory is required for the system stack. Finally, the Increment SAR
trap itself should be processed and the Violation 15 Set All CPU-inhibit attribute flags
Type Register reset. 16 Set All DMAI-inhibit attribute flags
Three commands are used to read and write the
control registers.
Table 2 Control register commands

Code
Instruction
(Hex)
00 Read/write mode register
01 Read/ write segment address register
Read/write descriptor selector
20
counter register
The Status Registers are read-only registers,
although the Violation Type Register (VTR) can be
reset. Nine instructions access these registers.
Table 3 Status register commands

Code
Instruction
(Hex)
02 Read violation type register
Read violation segment
03
number register
Read violation offset
04
(high-byte) register
05 Read bus status register
Read instruction segment
06
number register
Read instruction offset
07
(high-byte) register
11 Reset viol ation type register
13 Reset SWW flag in VTR
14 Reset FA TL flag in VTR
341
Z8030/Z8030A Serial Communications Controller LH8030/LH8030A
LH8030/LH8030A
.
Z80301Z8030ASerial
Communications Controller
'The Z8030 Z-SCC Serial Communications Con-
troller is a dual-channel, multi-protocol data com-
munications peripheral designed for use with the o
Zilog Z-Bus. The Z-SCC Junctions as a serial-
to-parallel, parallel-to-serial converterl
controller. The Z-SCC can be software-con-
figured to satisfy a wide variety of serial com-
munications applications. The device contains a
variety of new, sophisticated internal functions in-
cluding on-chip baud rate generators, Digital INTACK 8
Phase-Locked Loops, and crystal oscillators that +5V 9
dramatically reduce the need for external logic. W/REQA
The Z-SCC handles asynchronous formats, syn-
chronous byte-oriented protocols such as IBM RTxCA
Bisync, and Synchronous bit-oriented protocols
RxDA
such as HDLC and IBM SDLC. This versatile de-
TRxCA
vice supports virtually any serial data transfer ap-
plication (cassette, diskette, tape drives, etc.). TxDA
The device can generate and check CRC codes in DTR/REQA
any Synchronous mode and can be programmed to RTSA
check data integrity in various modes. The CTSA
Z-SCC also has facilities for modem controls in DCDA
both channels. In applications where these con- PCLK
trols in both channels. In applications where Top View
these controls are not needed, the modem controls
can be used for general-purpose I/O.
The Z-Bus daisy-chain interrupt hierarchy is
also supported as is standard for Zilog peripheral
components.
The LH8030A Z8030A SCC is the high speed
version which can operate at 6MHz system clock.
• Features 4. Synchronous mode with internal or external

character synchronization on one or two syn-
1. Two independent, 0 to 1M bit/second, full-du-
plex channels, each with a separate crystal chronous characters and CRC generation and
checking with CRC-16 or CRC-CCITT preset
oscillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery. to either 1 s or Os.
5. SDLC/HDLC mode with comprehensive frame-
2. Multi-protocol operation under program con-
level control, automatic zero insertion and
trol ; programmable for NRZ, NRZI, or FM
delection, I-field residue handing, abort gen-
data encoding.
3. Asynchronous mode with five to eight bits and eration and detection, CRC generation and
one, one and one-half, or two stop bits per checking, and SDLC Loop mode operation.
character ; programmable clock factor ; break 6. Local Loopback and Auto Echo modes.
detection and generation; parity, overrun, and
framing error detection
---------.--SHARP.-----.-.-~--.-.
342
• Block Diagram
Baud Rate
Generator
A
Address/ 16 Data Terminal Ready/Request

Data
1 Request To Send
18 Clear to Send
Data Carrier Detect

2 Clear to Send
2 Request To Send
24 Data Terminal Ready/Request
30 Wait/Request
.-~------SHARP-'-------'---"""""
343
Z8Q30/Z8030A Serial Communications Controller LH8030/LH8030A
• Pin Description
AD o-AD 7 Address/ data bus Bidirectional Multiplexed systerri address/data bus.
3-state
AS Address strobe I Active "Low". Addresses are valid,
DS Data strobe I Active "Low". Data are valid.
R/W Read/write I Read at "High", Write at "Low",
CS o Chip select 0 I Active "Low", Selects an MMU for a control command,
CS 1 Chip select 1 I Active "High". Selects an MMU for a control command,
INT Interrupt request 0 Active "Low", Requests an interrupt.
--- Active "Low". Indicates an active interrupt acknowledge
INTACK Interrupt acknowledge I
cycle.
Active "High", Forms an interrupt daisy chain to give an
interrupt priority.
Active "High". Forms an interruptdaisy chain to give an
lEO Interrupt enable output 0
interrupt priority.
W/REQA Active "Low". Programmed as Request lines for a DlyIA
--- Wait/request Open drain
W/REQB controller or as Wait lines to synchronize the CPU.
CTSA Active "Low". Enables the respective transmitters to
-- Clear to send I
STSB send signals. Can be used as general·purpose input pins.
RTSA Active "Low". Goes High after the transmitter is empty.
-- Request to sen'd 0
RTSB Can be used as general·purpose output pins,
TxDA,TxDB Transmit data I Transmits data,
DCDA Active "Low", Enables the receiver to receive signals.
-- Data carrier detect I
DCDB Can be used as general·purpose input pins,
RxDA, RxDB Receive data I Receives data.
RTxCA, RTxCB Recive/transmit clocks I Transmission·purpose, clocks.
TRxCA, TRxCB Transmit/ receive clocks 110 Transmission·purpose clocks.
DTR/REQA Data terminal Active "Low". Request lines for a DMA controller. Can
----- 0
DTR/REQB Ready /request be used as general·purpose output pins,
--- Active "Low", Indicates a synchronization mode. Switch·
SYNCA
--- Synchronization 110 es synchronization mode. Switches to input or output de·
SYNCB
pending on modes,
Single· phase clock, Not required tobe the same as for the
PCLK Clock J
CPU.
Note: When AS and DS are at "Low" at the same time, the Z·SCC resets.
+5V
Parameter Symbol Ratings Unit 2.2kO
Input voltage V IN -0,3-+7.0 V Output pin O-~-'''1'IIH
Output voltage V OUT -0.3-+7.0 V

Operating tern perature Tope 0-+70 °c
Storage temperature T stg -55-+150 °c
Standard test load
+5V
I2.2kO
Output Pin~
J; 50pF
Open drain test load
............. . . . . . - - - - - - - - . - . - . - S H A R P - - . - - - - - . - . . . . , - -
344

Input high voltage VIH 2.0 Vcc+ 0.3 V
Input low voltage VIL -0.3 O.S V
Output high voltage VOH IOH = -250/LA 2.4 V
Output low' voltage VOL IOL=+2.0mA 0.4 V
Input leakage current I IlL I OA~VIN~2AV 10.0 /LA
Output leakage current I IOL I OA:S:V OUT :S:2AV 10.0 /LA
• Capacitance (f=lMHz, Ta=0-+70"C)

Unmeasured pins
returned to ground
Bidirectional capacitance CliO 20 pF
LHS030 LHS030A
MIN. MAX. MIN. MAX.
1 TwAS AS low width 70 50 ns
2 TdOS (AS) OS t to as ! delay time 50 25 ns
3 TsCSo(AS) CS o to AS t setup time 0 0 ns 1
4 ThCS o (AS) CS o to AS t hold time 60 40 ns 1
5 TsCS 1 (OS) CS 1 to OS ~ setup time 100 SO ns 1
6 ThCS 1 (OS) CS 1 to OS t hold time 55 40 ns 1
7 TsIA (AS) INT ACK to AS t setup time 0 0 ns
S ThIA (AS) INT ACK to AS t hold time 250 250 ns
9 TsRWR (OS) R/W (read) to OS ! setup time 100 SO ns
10 ThRW (OS) R/W to OS t hold time 55 40 ns
11 TsRWW (OS) R/W (write) to DS ! setup time 0 0 ns
12 TdAS (OS) AS t to OS ~ delay time 60 40 ns
13 TWOS1 OS low width 390 250 ns
14 TrC Valid access recovery time 6TcPC+200 6TcPC+l30 ns 2
15 TsA (AS) Address to AS t setup time 30 , 10 ns 1
16 ThA (AS) Address to AS t hold time 50 30 ns 1
17 TsOW (OS) Write data to OS ~ setup time 30 20 ns
IS ThOW (DS) Write data to OS t hold time 30 20 ns
19 TdOS (DA) OS ~ to data active delay time 0 0 ns
20 TdDSr (OR) DS t to read data not valid delay 0 0 ns
21 TdDSf (DR) DS ! to read data valid delay time 250 ISO ns
22 TdAS (OR) AS t to read data valid delay time 520 335 ns
23 TdOS (ORz) OS t to read data float delay time 70 45 ns 3
Address required valid to read
24 TdA (OR) 570 420 ns
data valid delay
25 TdOS (W) OS ~ to wait valid delay 240 200 ns 4
26 TdOSf (REQ) OS ! to W IREQ not valid delay 240 200 ns
27 TdOSr (REQ) OS t to OTR/REQ not valid delay 5TcPC+300 5TcPC+250 ns
345
-
.-..-..-.~ ................. .....
za030/Z8030A Serial Communications Controller
.
~ ~.-..-. ..............
LH8030/LH8030A
~.-.
-
LH8030 LH8030A
MIN. MAX. MIN. MAX.
28 TdAS (I NT) AS t to INT valid delay 500 500 ns 4
29 . TdAS (DSA) AS t to OS ! (acknowledge) delay ns 5
30 TwDSA DS (acknowledge) low width 390 250 ns
DS ! (acknowledge) to read data
31 TdDSA (DR) 250 180 ns
valid delay
32 TslEI (DSA) lEI to OS l (acknowledge) setup time 120 100 ns
33 ThIEl (DSA) lEI to DS t (acknowledge) hold time 0 0 ns
34 TdIEI (lEO) lEI to lEO delay 120 100 ns
35 TdAS (lEO) AS t to lEO delay 250 250 ns 6
DS l (acknowledge) to INT inactive
36 TdDSA (INT) 500 500 ns 4
delay
37 TdDS (ASQ) DS t to AS l delay for no reset 30 15 ns
38 TdASQ (DS) AS t to OS l delay for no reset 30 30 ns
39 TwRES AS and DS coincident low for reset 250 250 ns
40 TwPCI PCLK low width 105 2000 70 1000 ns
41 TwPCh PCLK high width 105 2000 70 1000 ns
42 TcPC PCLK cycle time 250 4000 165 2000 ns
43 TrPC PCLK rise time 20 15 ns
44 TfPC PCLK f:ill time 20 10 ns
Note : f Rising edge,
~ falling edge.
Note 1:
Parameter does not apply to interrupt acknowledge transactions.
Note 2:
Parameter applies only between transactions involving the Z-SCC.
Note Float delay is defined as the time required for a ± 0.5 V change in the output with a maximum dc load and minimum ac load.
3:
, Note 4:
Open-drain output, measured with open-drain test load.
Note 5:
Parameter is system dependent. For any Z-SCC in the daisy chain, TdAS (DSA) must be greater than the sum of TdAS (lEO) for the
highest priority device in the daisy chain, TslEI (DSA) for the Z-SCC, and TdlElf (lEO) for each device separating them in the daisy
chain.
Note 6: Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
Interrupt acknowledge timing
'-'-~~----SHARP-~--~---'-"-
346
Z8030/Z8030A Serial Communications Controller' LH8030/LH8030A
AS
CSo
CS 1
INTACK
R/W
READ
R/W
WRITE
DS
ADo-AD7
WRITE
ADo-AD7
READ
W/REQ
WAIT
W/REQ
REQUEST
~
DTR/REQ
REQUEST
INT
Read and write timing
Reset timing
PCLK
Cycle timing
---~------SHARP""-'-'-'----~
347
• General Timing
LH8030 LH8030A
MIN. MAX. MIN. MAX.
1 TdPC (REQ) PCLK ! to W IREQ valid delay 250 250 ns
2 TdPC (W) PCLK ! to wait inactive delay 350 350 ns
3 TsRXC (PC) RXC t toPCLK .t setup time 50 50 ns 1, 4
4 TsRXD (RXCr) RXD to RXC t setup time (X 1 mode) 0 0 ns 1
5 ThRXD (RXCr) RXD to RXC t hold time (X 1 mode) 150 150 ns 1
6 TsRXD (RXCf) RXD to RXC ! setup time (X 1 mode) 0 0 ns 1,5
7 ThRXD (RXCf) RXD to RXC ! hold time (X 1 mode) 150 150 ns 1,5
8 TsSY (RXC) SYNC to RXC t setup time -200 -200 ns 1
9 ThSY (RXC) SYNC to RXC t hold time 3TcPCt200 3TcPCt200 ns 1
10 . TsTXC .(pC) TXC ! to PCLK t setup time 0 0 ns 2,4
11 TdTXCf (TXD) TXC ! to TXD delay (X 1 mode) 300 300 ns 2
TdTXCr
12
(TXD)
TXC t to TXD delay (X 1 mode) 300 300 ns 2,5
13 TdTXD (TRX) TXD to TRDC delay (send clock echo) ns

14 TwRTXh RTXC high width 180 180 ns
15 TwRTXI RTXC low width 180 180 ns
16 TcRTX RTXC cycle time 400 400 ns
17 TcRTXX Crystal oscillator period 250 1000 250 1000 ns 3
18 TwTRXh TRXC high width 180 180 ns
19 TwTRXI TRXC low width 180 180 ns
20 TcTRX TRXC cycle time 400 400 ns
21 TwEXT DCD or CTS pulse width 200 200 ns
22 TwSY SYNC pulse width 200 ns
Note: t~sin~, ~ Falling edge.
Note 1: RxC is RTxC or TRxC, whichever is supplying the receive clock.
Note 2: TxC is TRxC or RTxC, whichever is supplying the transmit clock.
Note 3: Both RTxC and SYNC have 30 pf capacitors to the ground connected to them.
Note 4: Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK
or TxC and PCLK is required.
Note 5: Parameter applies only to FM encoding/ decoding
PCLK
W/REQ ------------+----------+~~
REQUEST "-;----------
WWAIT
IREQ ----------t-,--+,..",..-----------J
RTxC, TRxC ----,,..,....~_rl

RECEIVE
RxD ----~~~~+-+_~r----~~~-~~~------
SYNC ----~~~~~~~~~---------------
EXTERNAL ----J~-~4---~f~--------------
-TR-x-C.-RT-x-C ----------.,.
TRANSMIT
TxD ____~~~~~_~~''--------~~-----
TRxC ---~==~~~~r--------------------
OUTPUT
RTxC
====~--~~~~~~~~~~====~-----~
CTS,DCD ________-oJ
SYNC
INPUT - - -_ _ _ _'1
348
• System Timing
LH8030 LH8030A
MIN. MAX. MIN. MAX.
1 TdRXC (REQ) RxC t to W IREQ valid delay 8 12 8 12 TcPC 2
2 TdRXC (W) RxC t to wait inactive delay 8 12 8 12 TcPC 1,2
3 TdRXC (SY) RxC t to SYNC valid delay 4 7 4 7 TcPC 2
t -INT valid delay

- 8 12 8 12 TcPC
4 TdRXC (INT) RxC 1,2
+2 +3 +2 +3 AS t
5 TdTXC (REQ) TxC ~ to W IREQ valid delay 5 8 5 8 TcPC 3
6 TdTXC (W) TxC ~ to wait inactive delay 4 8 5 8 TcPC 1,3
7 TdTXC (DRQ) TxC ~ to DTR/REQ valid delay 4 7 4 7 TcPC 3
- 4 6 4 6 TcPC
8 TdTXC (INT) TxC ~ to INT valid delay 1,3
+2 +3 +2 +3 AS t
9 TdSY (INT) SYNC transition to INT valid delay 2 3 2 3 AS t 1
DCD or CTS transition to INT -
10 TdEXT (I NT) 2 3 2 3 AS t 1
valid delay
Note: t Rising edge, l Falling edge.
Note 1: ~n·drain output measured with open·drain test load.
Note 3: TxC is TRxC or RTxC whichever is supplying the transmit clock.
RTxC,TRxC
RECEIVE
W/REQ --------------~----~
REQUEST
W/REQ _____________~~_,~-J
WAIT
SYNC
OUTPUT ______________~~~~~
INT
RTxC,TRxC
TRANSMIT
Vi IREQ --------------~----~
REQUEST
W/REQ
WAIT ----------------f----~--'I
DTR/REQ ---------------+--"""'.../ __________________
REQUEST ~~
INT ----------------f~~~~
CTS,DCD K
------------~~-------------------------
SYNC ------------~--~~~r----------------------
INPUT ------------+---~~-r.9~~--~-------------
INT ------------+---~~.~~~
--@}-----!
.-.~-~----SHARP-.---.----..-,
349
., Z8030/Z8030A Serial Communications Controller LH80301LH8030A
• Data Communications Capabilites Any secondary st;ltions without messages to send

merely echo the incoming messages and are prohi-
The Z-SCC provides two independent fulf-du-
bited from placing messages on the loop (except
plex channels programmable for use in any com-
upon recognizing an EOP).
mon Asynchoronous or Synchronous datacommu-
SDLC Loop mode is a programmable option in
nication protocol. Fig_ 1 illustrates these protocols.
the Z-SCC. NRZ, NRZI, and FM coding may all be
used SDLC Loop mode,
! . l1
START
PARITY .---.
CONTROLLER
TOP
MA""""'RKI=N""G~1..I£&ill j ~~A~T""'A
'"TT1j l.lli&&]"
UNE ASYN~HRONOUS
1SYNC 1DATA 1 ::)-~ID""A"""T""ATIC-R-C-,'-1C-R-C"'"
MONOSYNC
1'"S:-:-:Y~Nc~Ir-SY-N~C""TID""A"""T~ATI
:1 ;..;;..;;.,;; 1DATA 1CRC, 1 CRc,1
SIGNAL~NC '
~,;.;:~ID""A"""T""ATI~CR~c"",r.1C==R~c2"'1
EXTERNAL SYNC
Ir.::F:;-LA7':G:::1IAD=DR::::E:::!s.i-'~: > 1 CRC" CRC,jFLAGI Fig. 2 An SDLC loop
SDLC/HDLC/X.25 "INFORMATION
•. Data Encoding
Fig. 1 Some Z-SCC protocols
The Z-SCC may be programmed to encode and
decode the serial data in four different ways (Fig.
• SOLe Loop Mode 3). In NRZ encoding, a 1 is represented by a High
The Z-SCC supports SDLC Loop mode in addi- level and a 0 is represented by a Low level. In
tion to normal SDLC. In an SDLC Loop, there is a NRZI encoding, a 1 is represented by no change in
primary controller station that manages the mes- level and a 0 is represented by a change in level. In
sage traffic flow on the loop and any number of FM1 (more properly, bi-phase mark) a transition
secondary stations. In SDLC Loop mode, the Z-SCC occurs at the beginning of every bit cell. A 1 is rep-
performs the functions of a secondary station while resented by an additional translation at the center
a Z-SCC operating in regular SDLC mode can act of the bit cell and a 0 is represented by no addi-
as a controller (Fig. 2). tional transition at the center of the bit cell. FMO
A secondary station in an SDLC Loop is always (bi-phase space), a transition occurs at the begin-
listening to the messages being sent around the ning of every bit cell. A 0 is represented by an
loop, and in fact must pass these messages to the additional transition at the center of the bit cell,
rest of the loop by retransmitting them with a and a 1 is represented by no additional transition
one-bit-time delay. The secondary station can at the center of the bit cell. In addition to these four
place its own message on the loop only at specific methods, the Z-SCC can be used to decode Man-
times. The con,troller signals that .secondary stati- chester (bi-phase level). data by using the DPLL in
ons may transmit messages by sending a special ch- the FM mode and programming the receiver for
aracter, called an EOP (End Of Poll), around the loop. NRZ d~ta. Manchester encoding always produces a
The EOP character is the bit pattern 1111111 0. transition at the center of the bit cell. If the transi-
Because of zero insertion during messages, this bit tion is 0 to 1, the bit is a O. If the transition is 1 to '
pattern is unique and easily recognized. 0, the bit is a 1.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it DATA --''--_-''-,
NRZ
chages the last binary 1 of the EOP to a 0 before
transmission. This has the effect of turning the NRZI
EOP into a flag sequence. The secondary station FMl
now places its message on the loop and terminates
the message with an EOP. Any secondary stations FM
further down the loop with messages to transmit MANCHESTER
can then append thier messages to the message of
Fig. 3 Data encoding methods
'the first secondary station by the same process.
350
• Auto Echo and Local Loopback used as either the transmit clock, the recieve clock,
The Z-SCC is capable of automatically echoing or both. It can also drive the Digital Phase-Locked
everything it receives. This feature is useful main- Loop (see next section).
ly in Asynchronous modes, but works in Synchro- If the receive clock or transmit clock is not prog-
nous and SDLC modes as well. In Auto Echo mode, rammed to come from the TRxC pin, the output of
TxD is RxD. Auto Echo mode can be used with the baud rate generator may be echoed out via the
NRZI or FM encoding with no additional delay, be- TRxC pin.
cause the data stream is not decoded before re- The following formula relates the time constant
transmission. In Auto Echo mode, the CTS input is to the baud rate (the baud rate is in bits/second
ignored as a transmitter. enable (although transi- and the BR clock period is in seconds) :
tions on this input can still cause interrupts if 1
programmed to do so). In this mode, the transmitter baud rate = 2 (time constant + 2) X (BR clock period)
is actually bypassed and the programmer is re-
sponsible for disabling transmitter interrupts and • Digital Phase-Locked Loop
WAIT /REQUEST on transmit.
The Z-SCC contains a Digital Phase-Locked
The Z-SCC is also capable of Local Loopback . In
Loop (DPLL) to recover clock information from a
this mode TxD is RxD, just as in Auto Echo mode.
data stream with NRZI or FM encodling. The DPLL
However, in Local Loopback mode, the internal
is driven by a clock that is nominally 32 (NRZI) or
data is tied to the internal receive data and RxD is
16 (FM) times the data rate. The DPLL uses this
ignored (except to be echoed out via TxD). The CTS
clock, along with the data stream, to construct a
and DCD inputs are also ignored as transmit and
clock for the data. This clock may then be used as
receive enables. However, transitions on these in-
the Z-SCC receive clock, the transmit clock, or
puts can still cause interrupts. Local Loopback
both.
works in Asynchronous, Synchronous and SDLC
For NRZI encoding, the DPLL counts the 32x
modes with NRZ, NRZI or FM coding of the data
clock to create nominal bit times. As the 32x clock
stream. is counted, the DPLL is searching the incoming
data stream for edges (either 1 to 0 or 0 to 1).
• Baud Rate Generator Whenever an edge is detected, the DPLL makes a
Each channel in the Z-SCC contains a programm- count adjustment (during the next counting cycle),
able band rate generator. Each generator consists producing a terminal count closer to the center of
of two 8-bit time constant registers that form a the bit cell.
16-bit time constant, a 16-bit down counter, and a For FM encoding, the DPLL still counts from 0
flip-flop on the output producing a square wave. to 31, but with a cycle corresponding to two bit
On startup, the flip-flop on the output is set in a times. When the DPLL is locked, the clock edges in
High state, the value in the time constant register is . the data stream should occur between counts 15
loaded into the counter, and the counter starts and 16 and between counts 31 and O. The DPLL
counting down. The output of the baud rate gener- looks for edges only during a time centered on the
ator toggles upon reaching 0, the value in the time 15 to 16 counting transition.
constant register is loaded into the counter, and the The 32x clock for the DPLL can be programmed
process is repeated. The time constant may be to come from either the RTxC input or the output of.
changed at any time, but the new value does not the baud rate generator. The DPLL output may be
take effect until the next load of the counter. programmed to be echoed out of the Z-SCC via the
The output of the baud rate generator may be TRxC pin (if this pin is not being used as an input).
------------SHARP---.------
351
Z803QJZ8030A Serial Communications Controller LH8030/LH8030A
• Read Registers
Read Register 0 . Read Register 10 .
~~~-r~~-r~~'-~~RxCHARACTER
AVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD o
SYNC/HUNT LOOP SENDING
CTS o
Tx UNDERRUN /EOM· TWO CLOCKS MISSING
BREAK/ABORT ONE CLOCK MISSING
Read Register 1 Read Register 12
I D7 I D6 I Ds I D. I D3 I D, I DJ I Do I
ALL SENT
RESIDUE CODE 2 [ LOWER BYTE OF
RESIDUE CODE 1 TIME CONSTANT
RESIDUE CODE 0
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)
Read Register 2 Read Register 13
I~I~I~I~I~I~I~I~I 1~lllilllil~I~I~I~I~1
[INTERRUPT VECTOR' [UPPER BYTE OF
• MODIFIED IN B CHANNEL TIME CONSTANT
Read Register 3* Read Register 15
CHANNEL B
EXT/STAT IP'
o
CHANNEL B Tx IP'
CHANNEL B Rx II" o
CHANNEL A EXT/STAT IP' DCDIE
SYNC/HUNT IE
CHANNEL A Tx IP'
CTS IE
CHANNEL A Rx IP'
Tx UNDER RUN / EOM IE
o BREAK/ABORT IE
o
• ALWAYS 0 IN B CHANNEL
'-'---~---SHARP-'------'---
352
• Write Registers Write Register 2

Write Register 0
1071 061 051 0./ 03/ 02/ 01/ Do /
1I
NULL CODE
NULL CODE
SELECT SHIrr LEFT MODE'
SELECT SHIFT RIGHT MODE'
I ~~~
~--------------Vs
~------------------V6
INTERRUPT
VECTOR
o ~--------------------V7
0 0 0 NULL CODE
0 0 1 NULL CODE
0 1 0 RESET EX T/STATUS INTERRUPTS
0 1 1 SEND ABO RT
1 0 0 ENABLE IN T ON NEXT Rx CHARACTER
1 0 1 RESET Tx I NT PENDING
1 1 0 ERROR RES ET
1 1 1 RESET HIG HEST IUS Write Register 3
0 0 NULL CODE
0
1
1
0
RESET Rx CRC CHECKE R
RESET Tx CRC GENERA TOR
/ 071 061 051 04/ 031 02 / 01 Do I I
II~
1 1 RESET Tx UNDERRUN / EOM LATCH Rx ENABLE
SYNC CHARACTER LOAD INHIBIT
'B CHANNEL ONLY
Rx CRC HUNT
ENTER ENABLE
AUTO ENABLE
MODE 5
ADDRESS SEARCH MODE (SDLC) ~
===_"
0 0 Rx 5 BITS /CHARACTER
Write Register 1 Write Register 4
I 07 I061 051 0.1 031 021 01 I Do I I 071 061 051 04/ 03/ 021 01 I Do I
~ 1I ~PARITY
EXT INT ENABLE ENABLE
Tx INT ENABLE PARITY EVEN/ODD
PARITY IS SPECIAL 0 0 SYNC MODES ENABLE
CONDITION 0 1 STOP BIT/CHARACTER
1
0 0 Rx INT DISA BLE 1 0 1112 STO P BITS/CHARACTER
Rx INT ON FI RST CHARACTER 1 1 2 STOP BITS/CHARACTER
0 1 OR SPECIAL CONDITION
INT ON ALL Rx CHARACTERS
1 0 OR SPECIAL CONDITION
1 1 Rx INT ON SPE CIAL CONDITION ONLY
0 0 8 BIT SYNC CH ARACTER
0 1 16 BIT SYNC C HARACTER
WAIT /0 MA REQUEST ON 1 0 SDLC MODE (01 111110 FLAG)
RECEI VE/TRANSMIT
1 1 EXTERNAL SY NC MODE
WAIT /0 MA REQUEST
FUNCT ION 0 0 xl CLOCK MODE
WAIT /0 MA REQUEST 0 1 x16 CLOCK MODE
ENABLE 1 0 x32 CLOCK MODE
1 1 x64 CLOCK MODE
. . . . - . - - - - - - - - - - - - S H A R P ...--~--.-------
353
. .......... ~...., .......................... ..........................
Z8030/Z8030A Serial Communications Controller
~~ ~
- LH8030lLH8030A
. ~
Write Register 5
I D71 Dsl Ds I D.I D31 D2 I Dl I Do I
I~
Tx CRC ENABLE
RTS
SDLC/CRC 16
Ti ENABLE
SEND BREAK
0 0 Tx 5 BITS (OR LESS )/CHARACTER

0 1 Tx 7 BITS/CHARAC TER
1 0 Tx 6 BITS /CHARAC TER
1 1 Tx 8 BITS /CHARAC TER
DTR
Wrl!e Register 6
I D7! Dsl Dsl D.I D31 D21 Dl I Dol
SYNC7
SYNCl
FFJ~~~
SYNCs
SYNCs
SYNCs
SYNCs
SYNC.
SYNC.
SYNC3
SYNC3
SYNC2
SYNC2
SYNCl
SYNCl
SYNCo
S'yNCo
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
SYNC7 SNNCs SYNCs SYNC. SYNC3 SYNC2 SYNCl SYNCo BISYNC, 16 BITS
SYNC3 SYNC2 SYNCl SYNCo 1 1 1 1 BISYNC, 12 BITS
ADR7 ADRs ADRs ADR. ADR3 ADR2 ADRl ADRo SDLC ADDRESS, 8 BITS
ADR7 ADRs ADRs ADR. x x x x SDLC ADDRESS, 4 BITS
Write Register 7
ID71 Dsl Dsl D.I D31 D21 Dl I Do I
SYNC7
SYNCs
F,J~~~
SYNCs
SYNC.
SYNCs
SYNC3
SYNC. SYNC3 SYNC2 SYNCl
I
SYNCo MONOSYNC, 8 BITS
SYNC2 SYNCl SYNCo X X MONOSYNC, 6 BITS
SYNCls SYNC14 SYNCls SYNCl2 SYNCll SYNClo SYNCg SYNCs BISYNC, 16 BITS
SYNCll SYNClO SYNCg SYNCs SYNC7 SYNCs SYNCs SYNC. BISYNC, 12 BITS
0 1 1 1 1 1 1 o SDLC,FLAG
354
Write Register 9 Write Register 12
I D71 D61 D51 D41 D31 D21 D, I Dol
I~ I I LL=~TgCC:3'
VIS
NV
DLC
MIE
I LOWER
BYTE OF
STATUS HIGH/STATUS LOW TC4 TIME
o L---------------TC5 CONSTANT
L-_________________ TC6
0 0 NO RESET L---------------------TC7
0 1 CHANNEL RESET B
1 0 CHANNEL RESET A Write Register 13
1 1 FORCE HARDWARE RE SET
I D71 D61 D51 D41 D31 D21 D, I Dol
Lm ~~~~"oF
Write Register 10
I D71 D61 D51 D41 D31 D21 DI I Dol II II

I~
6 BIT /8 BIT SYNC TC'2 TIME
LOOP MODE L--------------TC 13 CONSTANT
ABORT/ FLAG ON UNDERRUN '------------------- TC 14
MARK/FLAG-IDLE '---------------------- TC 15
GO ACTIVE ON POLL
0 0 NRZ Write Register 14
0 1 NRZI
1 0 FMI (TRANSITION =1) ID71 D61 D51 D41 D31 D21 D, I Do I
I~
1 1 FMO (TRANSITION =0)
BR GENERATOR ENABLE
CRC PRESET I/O BR GENERATOR SOURCE
DTR/REQUEST FUNCTION
AUTO ECHO-
LOCAL LOOPBACK
Write Register 11
0 0 0 NULL COMMAND
ID71 D6 ID51 D41 D3 ID21 D, IDo I 0 0 1 ENTER SEARCH MODE
0 1 0 RESET MISSING C LOCK
I] TIUC OUT=XTAL OUTPUT 0 1 1 DISABLE DPLL

TIUC OUT=TRANSMIT CLOCK 1 0 0 SET SOURCE=BR GENERATOR
TIUC OUT=GTGENERATOR OUTPUT 1 0 1 SET SOURCE = --C
RTx
TIUC OUT= DPLL OUTPUT 1 1 0 SET FM MODE
1 1 1 SET NRZI MODE
TRxC 0/1
0 0 TRANSMIT CL OCK=RTxC PIN
0 1 TRANSMIT CL OCK=TRxC PIN Write Register 15
1
1
0
1
TRANSMIT
TRANSMIT
CL OCK= BR GENERATOR OUTPUT
CL OCK=DPLL OUTPUT ID71 D6[ D5[ D4[ D3[ D2[ D, [ Do [
0 0 RECEIVE CLOCK = RTxC PIN
I I ~:ERO COUNT IE
~DCDIE
0 1 RECEIVE CLOCK = TRxC PIN
1 0 RECEIVE CLOCK = BR GENERATOR OUTPUT
1 1 RECEIVE CLOCK = DPLL OUTPUT SYNC!HUNT IE
'----------------CTS IE
RTxC XTAL/NO XTAL ' - - - - - - - - - - - - - - Tx UNDERRUN/EOM IE
L--------'-----BREAK/ABORT IE
.--..-------SHARP---------
355
Z8036/Z8036ACounter/Timer and Parallel 1/0 Unit LH8036/LH8036A
LH8036/lH8036A
-Z8036/Z8036A Counter/Timer and Parallel I/O Unit
The Z8036 Z-CIO Counter/Timer ~nd Parallel
. 110 elemeniis ,a general-purpose peripheral cir-
cuit, satisfying most counter/timer and parallel 110 o
needs encountered in system designs. This versa-
tile device contains three 110 ports and three coun-
ter/timers. Many progra\llmable options tailor its
configuration to specific applications. The use of
the device is simplified by making all internal reg-
isters (command, status, and data) readable and'
(except for status bits) writable. In addition, each
'register is given its own unique address so that it
can be accessed directly-no special sequential op-
erations are required. The Z-CIO is directly
Z-Bus compatible.
• ' Features
1. Two independent 8-bit, double-buffered,
bidirectional 110 ports plus a 4-bit speci,d-
purpose 110, port. 110 ports feature pro-
Top View
grammable polarity, programmable direction
(Bit mode), "pulse catchers," and programm-
able opendrain outputs
2. Four handshake modes, including 3-Wire (like
the IEEE-488) .
3. REQUEST /W AIT signal for high-speed data
transfer
4. Flexible pattern-recognition logic, programm-
able as a 16-vector interrupt controller
5. Three independent 16-bit counter/timers with
up to four external access lines per counter/
timer (count input, output, gate, and trigger),
and three output duty cycles (pulsed, one-shot,
and s'quarewave), programmable as retrigger-
able or nonretriggerable.
6. Easy to use since all registers are read/write
and directly addressable.
356
Z8036/Z8036A Counter/Timer and Parallel I/O Uni.t LH8036/LH8036A
• Block Diagram
Interrupt Enable In
Int erupt Enabl e Out
Interrupt Request C24l--f
Interrupt Acknowledge
Address/Data
Bus
Data Strobe
Read/Write
Address Strobe 3
Chip Select {
• Pin Description
Bidirectional
AD o-AD 7 Address/ data bus MUltiplexed system address/data bus.
3-state
AS Address strobe I Active low. AS determines address while low.
- Active low. DS providies timing for data transfer
DS Data strobe I
while low.
- R/W indicates that the CPU is reading froln (high) or
R/W Read/write I
writing to (low) the Z-CIO.
CSo Chip select 0 I Active low. Chip select signal
CS 1 Chip select 1 I Active high. Chip select signal
-- Active low. INT is pulled low when the Z·CIO
INT Interrupt request Open-drain
requests on interrupt.
Active low. INT ACK indicates that an Interrupt
acknowledge cycle is in progress.
Acvtive high. lEI is used to form an interrupt daisy
lEI Interrupt enable in I
chain that determines the priority order of interrupts.
Active high. lEO is used to form an interrupt daisy
chain that determines the priority order of interrupts.
Bidirectional These eight I/O lines transfer information between the
PAo-PA 7 Port A I/O lines
3-state Z·CIO's port A and external devices.
Bidirectional These eight I/O lines transfer information between the
PBo-PB 7 Port B I/O lines
3-state Z-CIO's port B and external devices.
Bidirectional These four I/O lines transfer information between the Z-
PC O-PC 3 Port C I/O lines
3-state CIO's port C and external devices.
PCLK Clock I Single-phase clock, need not be same as CPU clock.
Note: When AS and DS are detected "Low" at the same time, the Z-CIO is reset.
-.-------SHARP--------~--
357
---___....._. . . ,. . . . . . . . .
za036/Z8036A CQunter/Timer and Parallel. 1/0 Unit

~~-,..-I':- . . ......,------.----
LH8036/LH8036A

Input voltage VIN -0.3-+7.0 V 1
Output voltage VOUT -0.3-+7.0 V 1
Operating temperature T= 0-+70 "C
Storage temperature Tilic -65-+150 "C
Note. 1: The maximum applicable voltage on any pin with respect to GND.
+5V +5V
1R
~'2kO
From output under test . . ,
i T.2kO
I
From output under test
50pF I 25
~A lSOPF
Standard test load Open drain test load
• DC Characteristics (V cc =5V±5%, Ta=0-+70"C)

Input high voltage VIH , 2.0 Vcc+ 0.3 V
Output high voltage VOH IoH =-250,uA 2.4 V
IOL=+2.0mA 0.4 V
Output low voltage VOL
IOL=+3.2mA 0.5 V
Input leakage current I IlL I 0.4";;:V IN ";;:2.4V 10.0 ,uA
Output leakage current I IOL I 0.4 ~VouT~2.4V 10.0 ,uA
.!
Supply current Icc 250 mA
Capacitance (f=lMHz, Ta=0-+70"C)

Input capacitance CIN 10. pF
Unmeasured pins
Output capacitance' CO\!L 15 pF
returned to ground
....-..-..-.-~-.-.--SHARP -..-.-..--------
358
Z8036/Z8036A Counter/Timer and Parallel I/O Unit Ui8036/LH8036A
(1) Interface timing
LH8036 LH8036A
MIN. MAX. MIN. MAX.
1 TwAS AS low width 70 2000 50 2000 ns
2 TsA (AS) Address to AS f setup time 30 10 ns 1
3 ThA (AS) Address to AS f hold time 50 30 ns 1
4 TsA (OS) Address to OS ! setup time 130 100 ns 1
5 TsCSO (AS) CS o to AS f setup time 0 0 ns 1
6 ThCSO (AS) CS o to AS f hold time 60 40 ns 1
7 TdAS (OS) AS f to OS ! delay 60 40 ns 1
8 TsCSI (OS) CS 1 to OS ! setup time 100 80 ns
9 TsRWR (OS) R/W (read) to OS ! setup time 100 80 ns
10 TsRWW (OS) R/W (write) to OS ! setup time 0 0
11 TwOS OS low width 390 250 ns
12 TsOW (OSf) Write data to OS ! setup time 30 20 ns
13 TdOS (ORV) OS (read) ! to address data bus driven 0 0
14 TdOSf (OR) OS ! to read data valid delay 250 180 ns
15 ThOW (OS) Write data to DS f hold time 30 20 ns
16 TdOSr (OR) OS f to read data not valid delay 0 0
17 TdOS (ORz) OS f to read data float delay 70 45 ns 2
18 ThRW (OS) R/W to OS f hold time 55 40 ns
19 ThCSI (OS) CS 1 to OS f hold time 55 40 ns
20 TdOS (AS) OS f to AS ! delay 50 25 ns
21 Trc Valid access recovery time 1000 650 ns 3
- lAs cycle
22 TdPM (INT) Pattern match to INT delay (bit port) 1 1
+ns
ACKIN to INT delay lAS cycle
23 TdACK (INT) 4 4 4
(Port with handshake) +ns
Counter input to INT delay lAs cycle
24 TdCI (INT) 1 1
(Counter mode) +ns
- lAs cycle
25 TdPC (INT) PCLK to INT delay (Timer mode) 1 1
+ns
26 TdAS (I NT) AS to INT delay ns
27 TsIA (AS) INT ACK to AS f setup time 0 0 ns
28 ThIA (AS) INT ACK to AS f hold time 250 250 ns
29 TsAS (OSA) AS f to OS (acknowledge) ! setup time 350 250 ns 5
OS (acknowledge) ! to read data
30 TdOSA (OR) 250 180 ns
valid delay
31 TwOSA OS (acknowledge) low width 390 250 ns
32 TdAS (lEO) AS f to lEO ! delay (INT ACK cycle) 350 250 ns 5
33 TdlEI (lEO) lEI to lEO delay 150 100 ns 5
34 TslEI (OSA) lEO to OS (acknowledge) ! setup time 100 70 ns 5
35 ThlEI (OSA) lEI to OS (acknowledge) t hold time 100 70 ns
36 TdOSA (INT) OS (acknowledge) ! to INT t delay 600 600 ns
Note: • t " indicates a rising edge -and •. ! .. a falling edge.
Note 1: Parameter does not apply to Interrupt Acknowledge transactions.
Nate 2: Float delay is measured to the time when the output has changed 0.5 V from steady state with minimum ac load and maximum de
load.
Note 3: This is the delay from DS t of one CIa access to DS ! of another CIa access.
Note 4: The delay is from DAV ! for 3-Wire Input Handshake. The delay is from DAC t for 3-Wire Output Handshake. One additional
AS cycle is required for ports in the Single Buffered mode.
Note 5: The parameters for the devices in any particular daisy chain must meet the following constraint: the delay from AS t to DS !
must be greater than the sum of TdAS (lEO) for the highest priority peripheral, TsIEI (DSA) for the lowest priority peripheral, and
TdlEI (lEO) for each peripheral separating them in the chain.
359
Z8036/Z8036A Counter I Timer and Parallel 1/0 'Unit LH8036lLH8036A
AS
R/W
Read
R/W
Write -----++----4l'..,.-t------t-'-------
DS
Address
ADo - AD7 Z-CIO Write
\. Z-CIO Read
CPI,J interface timing
P~ttern
Blt~rt
match input ~_ _ _ _match
~~ ___ input
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
r:==-@--
----'----.
Counter input
PCLK
INT
Interrupt timing
360
Z8036/Z8036A Counter/Timer and Parallel 110 Unit LH8036/LH8036A
___ ---'XUndefined)>-----@-~ Vector)
lEI
lEO
(2) Handshake timing

LH8036 LH8036A
MIN. MAX. MIN. MAX.
1 TsDI (ACK) Data input to ACKIN ~ setup time 0 0 ns
Data input to ACKIN ~ hold
2 ThDi (ACK) ns
time-strobed handshake
3 TdACKf(RFD) ACKIN ~ to RFD ~ delay 0 0 ns
4 TwACKI ACKIN low width-strobed handshake ns
5 TwACKh AGKIN high width-strobed handshake ns
6 TdRFDr(ACK) RFD t to ACKIN ~ delay 0 0 ns
7 TsDO (DAV) Data out to DA V ~ setup time 25 20 ns 1
8 TdDA Vf (ACK) DA V ~ to ACKIN ~ delay 0 0 ns
9 ThDO (ACK) Data out to ACKIN ~ hold time 1 1 AS cycle
10 TdACK (DAV) ACKIN ~ to DA V t delay 1 1 [As cycle
Data input to RFD ~ hold
11 ThDi (RFD) 0 0 ns
time-interlocked handshake
RFD ~ to ACKIN t
12 TdRFDf(ACK) 0 0 ns
delay-interlocked handshake
ACKIN t (DAV t) to RFD t
13 TdACKr(RFD) 0 0 ns
delay-interlocked and 3-wire handshake
DA V t to ACKIN t (RFD t)
14 TdDAVr (ACK) 0 0 ns
ACKIN t (RFD t) to DAV ~
15 TdACK (DAV) 0 0 ns
DAV ~ to DACt
16 TdDA Vif (DAC) 0 0 ns
delay-input 3-wire handshake
Data input to DAC t hold
17 ThDi (DAC) 0 0 ns
time-3-wire handshake
DAC t to DAV t
18 TdDACOr(DA V) 0 0 ns
DAV t to DAC ~
19 TdDA VIr (DAC) 0 0 ns
361
Z8036/Z8036A Counter/Timer and Parallel I/O Unit LH8036/LH8036A
LH8036 LH8036A
No. SymboL Parameter Unit Note
MIN. MAX. MIN. MAX.
DAV! toDAC t
20 TdDA VOf (DAC) 0 0 ns
delay-output 3-wire handshake
Data output to DAC t hold
21 ThDO (DAC) 1 1 AS cycl€
time-3-wire handshake
"
DAC t to DAV t
22 TdDAClr (DA V)
1 1 \As CyclE
DAV t to DAC !
23 TdDA VOr(DAC) 0 0 ns
Note 1: This time can be extended through the use of the deskew timers.
I--'--®
Data
ACKIN
Input (Input)
RFD--------------~
(Output)
Data ==x:~valid ®J:5=®==I

data
Output ACKIN ; \
(Input) ® ~~ '-----
DAV - - - -
(Output)
Strobe handshake
Data
Input ACKIN
(In"ut)
RFD
(Output)
Data
Output ACKIN
(Input)
DAV
(Output)
Interlock handshake
'-'--~-~--SHARP-'-'-'--'-""'-""",
362
Data
DAV
(Input)
Input
RFD
(Output)
DAC
(Output)
Data
DAC
(Input)
Output
RFD
(Input)
DAV
(Output)
3-Wire handshake
(3) Counter/timer timing
LH8036 LH8036A
MIN. MAX. MIN. MAX.
1 TcPC PCLK cycle time 250 4000 165 4000 ns 1
3 TwPCl PCLK low width 105 2000 70 2000 ns
4 TfPC PCLK fall time 20 10 ns
6 TcCI Counter input cycle time 500 330 ns
7 TClh Counter input high width 230 150 ns
8 TwCIl Counter input low width 230 150 ns
9 TfCI Counter input fall time 20 15 ns
10 TrCI Counter input rise time 20 15 ns
Trigger input to PCLKt
11 TsTI (PC) ns 2
setup time (Timer mode)
Trigger input to counter input ~
12 TsTI (CI) ns 2
setup time (Counter mode)
13 TwTI Trigger input pulse"width (High or Low) ns
Gate input to PCLK ~
14 TsGI (PC) ns 2
setup time (Timer mode)
Gate input to counter input !
15 TsGI (CI) ns 2
setup time (Counter mode)
Gate input to PCLK !
16 ThGI (PC) ns 2
hold time (Timer mode)
Gate input to counter input !
17 ThGI (CI) ns 2
hold time (Counter mode)
PCLK to counter output delay
18 TdPC (CO) ns
(Timer mode)
Counter input to counter output delay
19 TdCI (CO) ns
(Counter mode)
Note 1: PCLK is only used with the counter/timers (in Timer mode), the "deskew timers, and the REQUEST/WAIT logic. If these functions
are not used, the PCLK input can be held low.
Note 2: These parameters must be met to guarantee that trigger or gate are valid for the next counter/timer cycle.
363
Z8036/Z8036A .counter/Timer and Parallel 110 Unit LH8036/LH8036A
PCLK
PCLK/2 internal
Counter input
Trigger input
-------1'
Gate input _ _ _ _ _- . J
Counter output
---------------~
Counter/timer timing
(4) REQUEST/WAIT timing

LH8036 LH8036A
MIN. MAX. MIN. MAX.
I TdDS (REQ) DS ~ to REQ ~ delay ns
2 TdDS (WAIT) DS ~ to W AlT ~ delay ns
- 3 TdPC (REQ) PCLK ~ to REQ t delay ns
4 TdPC (WAIT) PCLK ~ to WAIT f delay ns
AScyc1es+
5 TdACK (REQ) ACKIN ~ to REQ f delay PCLK 1
cyc1es+ns
-- PCLK
6 TdACK (WAIT) ACKIN ~ to WAIT t delay
cyc1es+ns
Note 1: The Delay is from DAV ! for the 3-wire input handshake_ Delay from DAC t for 3-wire handshake output mode.
REQUEST/WAIT tim~ng
364
(5) Reset timing

LH8036 LH8036A
MIN. MAX. MIN. MAX.
1 TdDSQ (AS) Delay from DS t to AS ! for no reset 40 15 ns
2 TdASQ (DS) Delay from AS t to DS ! for no reset 50 30 ns
Minimum width of AS and DS both
3 TwRES 250 170 ns
low for reset
Reset internal ____________________ ~r
Reset timing
(6) Miscellaneous port timing
LH8036 LH8036A
MIN. MAX. MIN. MAX.
1 Trl Any input rise time 100 100 ns
2 Tfl Any input fall time 100 100 ns
3 Twl's 1 's catcher high width 250 170 ns 1
4 TwPM Pattern match input valid (Bit port) 750 500 ns
Data latched on pattern match
5 TsPMD 0 0 ns
setup time (Bit port)
Data latched on patter,n match
6 ThPMD 1000 650 ns
hold time (Bit port)
Note 1: If the input is programmed inverting, a low-going pulse of the same width will be detected.
Any input
1's catcher input

--------'
Pattern match input _ _ _ _--::-:--..J
@'iE---+;.---
Data to be latched to - - - - - ' " \ J.-'--------~ r-----
pattern match
Miccellaneous port timing

• Functional Description handshake, they provide 16 input or output bits
with the data direction programmable on a bit--
(1) 1/0 port operations by- bit basis. Port B also provides access for
Of the Z-CIO's three 110 ports, two (Ports A and Counter/Timers 1 and 2. In all configurations,
B) are general-purpose, and the third (Port C) is a Ports A and B can be programmed to recognize
special-purpose 4:-bit port. Ports A and B can be specific data patterns and to generate interrupts
configured as input, output or bidirectional ports when the pattern is encountered.
with handshake (Four different handshakes are The four bits of Port C provide the handshake
available.). They can also be linked to form a sig- lines for Ports A and B when required. A RE-
nal 16-bit port. If they are not used as ports with QUEST /W AIT line can also be provided so that
~....-.-...-----SHARP---'--------
365
- Z8036/Z8036ACounter/Timer and Parallel 1/0 Unit LH8036/LH8036A
Z-CIO transfers can be synchronized with DMAs logic. Port C provides the handshake lines as
or CPUs. Any Port C bits not used for handshake shown in Table 1. Any Port C lines not used for
or REQUEST/WAIT can be used as input or out- handshake can be used as simple I/O lines or as
put bits (individually data direction programmable) access lines for Counter/Timer 3.
or external access lines for Counter/Timer3. Port When Ports A and B are configured as ports
C does not contain any pattern-recognition logic. It with handshake, they are double-buffered. This
is, however, capable orbit-addressable writes. allows for more relaxed interrupt service routine
With this feature, any combination of bit can be set response time. A second byte can be input to or
and/or cleared while the other bits remain undis- output from the port before the interrupt for the
turbed without first reading the register. first -byte is serviced. Normally, the Interrupt
(2) Bit port operations Pending (IP) bit is set and an interrupt is generated
In bit port operations, the port's Data Direction when data is shifted into the Input register (input
register specifies the direction of data flow for port) or out of the Output register (output port).
each bit. A 1 specifies an input bit, and a 0 speci- For input and output ports, the IP is automatically
fies an output bit. If bits are used as I/O bits for a cleared when the data is read or written. In
counter/timer, they should be set as input or out- bidirectional ports, IP is cleared only by command.
put, as required. When the Interrupt on Two Bytes (ITB) control bit
The Data Path Polarity register provides the is set to 1, interrupts are generated only when two
capability of inverting the data path. A 1 specifies bytes of data are available to be read or written.
inverting, and a 0 specifies noninverting. All dis- This allows a minimum of 16 bits of information to
cussions of the port operations assume that the be transferred on each interrupt. With ITB set, the
path is noninverting. IP is not automatically cleared until the second
The value returned when readin~ an input bit re- byte of data is read or written.
flects the state of the input just prior to the read. A When the Single Buffer (SB) bit is set to 1, the
1 's catcher can be inserted into the input data path port acts as if it is only single-bufferd. This is use-
by programming a 1 to the corresponding bit posi- ful if the handshake line must be stopped on a
tion of the port's Special 110 Control register. byte-by-byte basis.
When a 1 is detected at the 1 's catcher input, its Ports A and B can be linked to form a 16-bit
output is set to a 1 until it is cleared. The 1 's port by programming a 1 in the Port Link Control
catcher is cleared by writing a 0 to the bit. In all (PLC) bit. In this mode, only Port A's Handshake
other cases, attempted writes to input bits are Specification and Command and Status registers
ignored. are used. Port B must be specified as a bit port.
When Ports A and B include output bits, reading When linked, only Port A has pattern-match capa-
the Data register returns the value being output. bility. Port B's pattern-match capability must be
Reads of Port C return the state of the pin. Outputs disabled. Also, when the ports are linked, Port B's
can be specified as open-drain by writing a 1 to Data register must be read or written before Port
the corresponding bit of the port's Special I/O Con- A's.
trol register. Port C has' the additional feature of When a port is specified as a port with hand-
bit-addressable writes. When writing to Port C, the shake, the type of port it is (input, output, or bid-
four most significant bits are used as a write pro- rectional) determines the direction of data flow.
tect mask for the least significant bits (0-4, 1-5, The data direction for the bidirectional port is de-
2-6, and 3-7). If the write protect bit is written termined by a bit in Port C (Table 1). In all cases,
with a 1, the state of the corresponding output bit the contents of the Data Direction register are
is not changed. r ignored. The contents of the Special I/O Control
(3) Ports with handshake operation register apply only to output bits (3-state Of
Ports A and B can be specified as 8-bit input, open -drain). Inputs may not have 1 's catchers ;
output, or bidirectional ports with handshake. The therefore. those bits in the Special I/O Control reg-
Z-CIO provides four different handshakes for its ister are ignored. Port C lines used for handshake
ports : Interlocked, Strobed, Pulsed, and 3-Wire. should be programmed as inputs. The handshak~
When specified as a port with handshake, th~ specification overrides Port C's Data Direction reg-
transfer of data into and out of the port' and inter- ister for bits that must be outputs. The contents of
rupt generation is under control of the handshake Port C's Data Path Polarity register still apply.
366
Z8036/Z8036A Counter/Timer and Parallel I/O Unit LH8036(LH8036A
Table 1. Port C bit utilization
Port AlB Configuration PC3 PC2 PC. PCo

Ports A and B : Bit ports Bit I/O Bit I/O Bit I/O Bit I/O
Port A : Input or output port --
-- -- REQUEST IW AIT
(Interlocked, strobed, or pulsed RFD or DA V (0) ACKIN (I) Bit I/O
or Bit I/O
handshake) *
Port B : Input or output port --
REQUEST IW AIT -- --
(Interlocked, strobed, or pulsed Bit 110 FD or DAV (0) ACKIN (I)
or Bit I/O
handshake) *
Port A or B : Input port (3·wire -- REQUESTlW AIT
RFD (0) DAV(I) DAC(O)
handshake) or Bit 110
Port A or B : Output port (3·wire -- REQUEST IW AIT
DAV(O) DAC (I) RFD (I)
Port A or B : Bidirectional port -- REQUEST IW AIT --
RFD or DA V (0) ACKIN(I) INIOUT
(Interlocked or strobed handshake) or Bit 110
*Both ports A and B can he specified input or output with interlocked, strobed, or pulsed handshake at the same time if neither uses RE·
QUESTlW AlT.
(4) Interlocked handshake that data overflows or underflows do not occur.

In the Interlocked Handshake mode, the action of
the Z-CIO must be acknowledged by the external
device before the next action can take place. Fig. 1
shows timing for Interlocked Handshake. An output
port does not indicate that new data is available INPUT HANDSHAKE
until the external device indicates it is ready for
the data. Similarly, an input port does not indicate
that it is ready for new data until the data source
DATA =x VALID XI..________
ACKIN
indicates that the previous of the data is no loger
available, thereby acknowledging the input port's RFD INTERLOCKED
acceptance of the last byte. This allows the Z-CIO DATA MOVED HANDSHAKE
to interface directly to the port of a Z8 micro- DATA LATCHED IN TO INPUT
BUFFER REGISTER REGISTER
computer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-bit deskew timer can be inserted in the Data OUTPUT HANDSHAKE
Available (DA V) output for output ports. As data is
transferred to the Buffer register, the deskew timer DATA NEXT BYTE
is triggered. After the number of PCLK cycles spe-
ACKIN DESKEW TIME
cified by the deskew timer time constant pi use one,
DA V is allowed to go Low. The deskew timer
therefore guarantees that the output data is valid
for a specified minimum amount of time before
DAV
BUFFER REGISTER
.,-----
\
STROBED HANDSHAKE
DA Vgoes Low. Deskew timers are available for "EMPTIED"
NEXT BYTE SHIFTED FROM OUTPUT
output ports independent of the type of handshake REGISTER TO BUFFER REGISTER
employed.
(5) Strobed handshake Fig. 1 Interlocked and strobed handshakes
In the Strobed Handshake mode, data is "strobed"
into or out of the port by the external logic. The falling
edge of the Acknowledge Input (ACKIN) strobes data (6) 3-wire handshake
into or out of the port Fig. 1 shows timing for the The 3-Wire Handshake is designed for the situa-
Strobed Handshake. In contrast to the Interlocked tion in which one output port is communicating
Handshake, the signal indicating the port is ready for with many input ports simultaneously. It is essen·
another data transfer operates independently of the tially the same as the Interlocked Handshake, ex-
ACKIN input It is up to the external logic to ensure cept that two signals are used to indicate if an in-
------------SHARP-----..-......----
367.
,
_.-: -~
.
Z8036/Z8936A Counter/Timer and ParalleVIIQUnit
put port is ready for new data or if it has accepted

the present data. In the 3-Wire Handshake (Fig. 2),
INPUT PORT
-
.....- ............... .......... ' LH8036/LR8036A
~- ..........
ACKiN ACKIN
~he rising edge of one status line indicates that the
cEXT~ERNAL) ~(INTERNAL)
port is read'y for data, and the rising edge of , TRIGGER COI!mR r~l
another status line indicates that the data has been INPUT ,QUTPlIT L .J
CIT 3 . -
accepted. With the 3-Wire Handshake, the output • , I '
lines of many input ports can be bussed together OUTPUT PORT

with open-drain drivers; the output port knows
when all the ports have accepted the data and are TRIGGER COUNTER
INPlIT OlITPlIT DAV
ready. This is the same handshake as is used on
CIT 3
the IEEE-488 bus. Because this handshake re-
quires'three lines, only one port (either A or B) can Fig. 3 Pulse handshake
be a 3-Wire Handshake port at a time. The 3-Wire gers the timer and its output used as the Interlock-
Handshake is not available in the bidirectional ed Handshake's normal acknowledge input. If the
mode. Because the port's direction can be changed port is an outP\1t port, the timer is placed in the
under software control, however, bidirectional Data Available (DAV) output path. The timer is
IEEE-488-type transfers can be performed. triggered when the ilOrmal Interlocked Handshake
DA V output goes Low and the timer output is used
as the actual DAV output. The counter/timer main-
INPUT HANDSHAKE
tains all of its normal capabilities. This handshake
DATA ~_______________ is not available to bidirectional ports.
(8) REQUEST/WAIT line operation
DAV Port C can be programmed to provide a status
INPUT
RFD -~~
signal output in addition to the normal handshake
OUTPUT '-------+---J DATA SHIFTED lines for either Port A or B when used as a port
DAC TO INPUT REGISTER with handshake. The additional signal is either a
OUTPUT REQUEST or WAIT signal. The REQUEST signal
DATA LATCHED I indicates when a port is ready to perform a data
IN BUFFER REGISTER
transfer via the Z-Bus. It is intended for use with a
DMA -type device. The WAIT signal provides syn-
OUTPUT HANDSHAKE chronization for transfers with a CPU. Three bits
in the Port Handshake Specification register pro-
piA T A _ _ _ _ _ _ _ -JI,~ _ _BYTE
NEXT ___ vide controls for the REQUEST /W AIT logic. Be-
RFD cause the extra Port C line is used, only one port
INPUT __________J can be specified asa port with a handshake and a
DAC REQUEST /W AIT line. The other port must be a
INPUT LAST ONE
bit port.
DAV
Operation of the REQUEST line is modified by
OUTPUT the state of the port's Interrupt on Two Bytes (ITB)
BUFFER REGISTER NEXT BYTE SHIFTED FROM OUTPUT control bit. When ITB is 0, the REQUEST line goes
"EMPTIED" REGISTER TO,BUFFER REGI~TER active as soon as the Z-CIO is ready for a data
transfer. If ITB is 1, REQUEST does not go active
Fig. 2 3-wire handshake until two bytes can be transferred. REQUEST
stays active as long as a byte is available to be
(7) Pulsed handshake read or written.
The Pulsed Handshake (Fig. 3) is designed to in- The SPECIAL REQUEST function is reserved
terface to mechanical-type devices that require for use with bidirectional ports only., In this case,
data to be held for long periods of time and need the REQUEST line indicates the status of the regis-
relatively wide pulses to gate the data into or out of ter not being used in the data path at that time. If
the device. The logic is the same as the Interlocked the IN/OUT line is High, the REQUEST line is '
Handshake mode, except that an internal counter / High when the Output register is empty. If IN/OUT
timer is linked to the handshake logic. If the port is is Low, the REQUEST line is High when the Input
specified in the input mode, the timer is inserted in
the' ACKIN path,. The external ACKIN input trig-
. - - . - - - - - - - - - - S H A R P ---~----..-.-.--
368
register is full. error condition exists. If the Interrupt On Error bit

(9) Pattern-recognition logic operation (IOE) is 0, the match is ignored. However, if IOE is
Both Ports A and B can be programmed to gener- 1, after the first IP is cleared, it is automatically
ate interrupts when a specific pattern is recognized set to 1 along with the Interrupt Error (ERR). flag.
at the port. The pattern-recognition logic is inde- Matches occurring while ERR is set are ignored.
pendent of the port application, thereby allowing ERR is cleared when the corresponding IP is
the port to recognize patterns in all of its con- cleared. .
figurations. The pattern can be independently spe- When a pattern-match is pressent in the OR-
cified for each bit as 1, 0, rising edge, falling edge, Priority Encoded Vector mode, IP is set to 1. The
or any transition. Individual bits may be masked IP cannot be cleared until a match is no longer pre-
off. A pattern-match is defined as the simultaneous sent. If the interrupt vector is allowed to include
satisfaction of all non masked bit specifications in status, the vector returned during Interrupt Ack-
the AND mode or the satisfaction of any non- nowledge indicates the highest priority bit match-
masked bit specifications in either of the OR or ing its specification at the time of the Acknowledge
OR-Priority Encoded Vector modes. cycle. Bit 7 is the highest priority and bit 0 is the
The pattern specified in the Pattern Definition lowest. The bit initially causing the interrupt may
register assumes that the data path is programmed not be the one indicated by the vector if a higher
to be non inverting. If an input bit in the data path priority bit matches before the Acknowledge. Once
is programmed to be inverting, the pattern detected the Acknowledge cycle is initiated, the vector is
is the opposite of the one specified. Output bits frozen until the corresponding IP is cleared. Where
used in the pattern-match logic are internally sam- inputs that cause interrupts might change before
pled before the invert/noninvert logic. the interrupt is serviced, the 1 's catcher can be
(10) Bit port pattern-recognition operations used to hold the value. Because a no-match to
During bit port operations, pattern-recognition match transition is not required, the source of the
may be performed on all bits, including those used interrupt must be cleared before IP is cleared or
as I/O for the counter/timers. The input to the pat- else a second interrupt is generated. No error de-
tern-recognition logic follows the value at the pins tection is performed in this mode and the Interrupt
(through the invert/noninvert logic) in all cases ex- On Error bit should be set to O.
cept for simple inputs with 1 '1) catchers. In this (11) Ports with handshake pattern-
case, the output of the 1 's catcher is used. When recognition operation
operating in the AND or OR mode, it is the transi- In this mode, the handshake logic normally con-
tion from a nomatch to a match state that causes trols the setting of IP and, therefore, the generation
the interrupt. In the "OR" mode, if a second match of interrupt requests. The pattern-match logic con-
occurs before the first match goes away, it does not trols the Pattern Match Flag (PMF). The data is
cause an interrupt. Since a match condition only compared with the match pattern when it is shifted
lasts a short time when edges are specified, care from the Buffer register to the Input register (input
must be taken to avoid losing a match condition. Bit port) or when it is shifted from the Output register
ports specified in the OR-Priority Encoded Vector to the Buffer register (output port). The pattern-
mode generate interrupts as long as any match match logic can override the handshake logic in
state exists. A transition from a no-match to a certain situations. If the port is programmed to in-
match state is not required. terrupt when two bytes of data are available to be
The pattern-recognition logic of bit ports oper- read or written, but the first byte matches the spe-
ates in two basic modes: Transparent and Latched. cified pattern, the pattern-recognition logic sets IP
When the Latch on Pattern Match (LPM) bit is set and generates an interrupt. While PMF is set, IP
to 0 (Transparent mode), the interrupt indicates cannot be cleared by reading or writing the data
that a specified pattern has occurred, but a read of registers. IP must be cleared by command. The in-
the Data register does not necessarily indicate the put register is not emptied while IP is set, nor is
state of the port at the time the interrupt was the output register filled until IP is cleared.
generated. In the Latched mode (LPM = 1), the If the Interrupt on Match Only (IMO) bit is set,
state of all the port inputs at the time the interrupt IP is set only when the data matches the pattern.
was generated is latched in the input register and This is useful in DMA-type applications when in-
held until IP is cleared. In all cases, the PMF indi- terrupts are required only after a block of data is
cates the state of the port at the time it is read. transferred.
If a match occurs while IP is already set, an
----.--.---SHARP---~---~.-.-r--
369
Z8036/Z8036A Countertfimer and Parallel 110 Unit LH8036/LH8036A
(12) Counter/timer operation 'counter reaches O. When the square -wave output
the three independent 16-bit counter/timers duty cycle is spec-ified, the counter/timer goes
consist of a presettable 16-bit down counter, a through two full sequences for each -cycle. The ini-
16-bit Time Constant register, a I6-bit Current tial trigger causes the down-counter to be loaded
Counter register,art 8-bit Mode Specification reg- and the normal countdown sequence to begin. If a 1
ister, an 8-bit Command and Status register, and count is detected on the down-counter's clocking
the associated control logic that links these regis- edge, the output goes High and the time constant
ters. value is reloaded. On the clocking edge, when both
The flexibility of the counter/timers is enhanced the down-counter and the output are 1 's, the output
by the provision of up,to four lines per counter / is pulled back Low.
timer (counter input, gate input, trigger input, and The Countinuous/Single Cycle (elSe) bit in the
counter/timer output) for direct external control Mode Specification register controls operation of
and status. Counter/Timer l's external I/O lines the down-counter when it reaches terminal count.
are provided by the four most significant bits of If C/SC is 0 when a terminal count is reached, the
Port B. Counter/Timer 2's are provided by the 'countdown sequence stops. If the C/SC bit is 1
four least significant bits of Port B. Counter/Timer each time the countdown counter reaches 1, the
3's external I/O lines are provided by the four bits next cycle causes the time constant value to be re-
of Port C. The utilization of these lines (Table 2) is loaded. The time constant value may be changed by
programmable on a bit-by-bit basis via the Coun- the CPU, and on reload, the new time constant
ter /Timer Mode Specification registers. value is loaded.
When external counter/timer I/O lines are to be Counter/timer operations require loading the
used, the associated port lines must be vacant and time constant value in the Time Constant register
programmed in the proper data direction. Lines and initiating the countdown sequence by loading
used for counter/timer I/O have the same charac- the down-counter with the time constant value.
teristics as simple input lines. They can be speci- The Time Constant register is accessed as two
fied as inverting or noninverting ; they can be read 8-bit registers. The registers are readable as well
and used with the pattern-recognition logic. They as writable, and the access order is irrelevant. A 0
can also include the 1 's catcher input. in the Time Constant register' specifies a time con-
Counter/Timers 1 and 2 can be be linked internal- stant of 65,536. The down-counter is loaded in
ly in three different ways. Counter/Timer 1 's out- one of three ways :
put (inverted) can be uS'ed as Counter/Timer 2's (1) By writing a 1 to the Trigger Command Bit
trigger, gate, or counter input. When linked, the (TCB : write-only),
(2) On the rising edge of the external trigger in-
Table 2 Counter/timer external access put, or,
Function 'C/T! C/T 2 C/T 3 (3) For Counter/Timer 2 only" on the rising
Counter/timer output PB4 PBO peo edge of Counter/Timer l's internal output if
Counter input PB5 PBl PCl
the counters are linked via the trigger input.
Trigger input PB6 PB2 PC2
Once the down-counter is loaded, the countdown
Gate input PB7 PB3 PC3
sequence continues toward terminal count as long
as all the counter/timers' hardware and software
gate inputs are High. If any of the gate inputs goes
counter/timers have the same capabilities as when Low (0), the countdown halts. It resumes when all
used separately. The only restriction is that when gate inputs ate 1 again.
Counter/Timer 1 drives Counter/Timer 2's count The reaction to triggers occurring during a
input, Counter/Timer 2 must be programmed with countdown sequence is determined by the state of
its external count input disabled. the Retrigger Enable Bit (REB) in the Mode Speci-
There are three duty cycles available for the tim' fication register. If REB is 0, retriggers are ignored
er/counter output: pulse, one-short, and square and the countdown continues normally. If REB is 1,
-wave. Fig. 4 shows the counter/timer waveforms. each'trigger causes the down-counter to be re-
When tte Pulse mode is specified, the output goes loaded and the count-down sequence starts over
High for one clock cycle, beginning when the down- again. If the output is programmed in the Square
-counter leaves the count of 1. In the One-Shot -Wave mode, retrigger causes the sequence to start
mode, the output goes High when the counter/timer over from the initial load of the time constant.
is triggered and and goes Low when the ddwn-
------~-----SHARP-.-.--~.---.-.
370
The rate at which the down-countor counts is (1) By reading the contents of the down-counter
determined by the mode of the counter/timer. In via the Current Count register, or
the Timer mode (the External Count Enable IECE] (2) By testing the Count In Progress (CIP) sta-
bit is 0), the down-counter is clocked internally by tus bit in the Command Status register.
a signal that is half the frequency of the PCLK in- The CIP status bit is set when the down-counter
put to the chip. In the Counter mode (ECE is 1), the is loaded; it is reset when the down-counter reaches
down-counter is decremented on the rising edge of O. The Current Count register is a 16-bit register,
the counter/timer's counter input. accessible as two 8-bit registers, which mirrors
Each time the counter reaches terminal count, its the contents of the down-counter. This register can
Interrupt Pending (IP) bit is set to 1, and if inter- be read anytime. However, reading the register is
rupts are enabled (IE= 1), an interrupt is gener- asynchronous to the counter's counting, and the
ated. If a terminal count occurs while IP is already value returned is valid only if the counter is stop-
set, an internal error flag is set. As soon as IP is ped. The down-counter can be reliably read "on
cleared, it is forced to a 1 along with the Interrupt the fly" by the first writing of a 1 to the Read
Error (ERR) flag. Errors that occur after the inter- Counter Control (RCC) bit in the counter/timer's
nal flag is set are ignored. Command and Status register. This freezes the
The state of the down-counter can determined in value in the Current Count register until a read of
two ways: the least significant byte is performed.
PCLK/20R ~~
COUNTER INPUT
TRIGGER~
GATE U fI
TC
1 TC ITC-1ITC-1I TC- 21 .. ·1.1 I OaR I
PULSE OUTPUT ------------1r~
ONE SHOT [J
OUTPUT - - - - '
SQUARE WAVE OUTPUT
FIRST HALF _ _ _ _ _ _ _ _ _ _ --j;c~1 _ _--l
SQUARE WAVE OUTPUT-----------------jfff------,
SECOND HALF '----
Fig. 4 Counter/timer waveforms
..--.~------SHARP----------
371
Z8036/Z8036A Gounter/Timer and Parallel I/O. Unit LH8036/LH8036A
• Internal Registers
The followings' illustrate the contents of the Reg-
isters and, in addition, give to register address
summary
• Maste~ Interrupt C.ontrol Register (MICR)
Address : 000000
(Read/Write)
II l:
107 1 06 1 Os 1041 03 1 Dd 011 Do I
MASTERINTERRUPT~
ENABLE (MIE)
1 LRESET
L'RIGHT JUSTIFIED ADDRESSES
O=SHIFT LEFT (Ao from ADl)
DISABLE LOWER CHAIN (DLC) I=RIGHT JUSTIFY (Ao from ADo)
NO VECTOR (NV) COUNTER/TIMERS VECTOR
PORT A VECTOR INCLUDES------" INCLUDES STATUS (CT VIS)
STATUS (PA VIS) '-------PORT B VECTOR INCLUDES
STATUS (PB VIS)
• Master Configuration Control Register (MCCR)

Address: 000001
(Read/Write)
107106/051 D41 031021011 Dol
PORT
ENABLE (PBE)
oj I I ---CCOUNTERITIMER LINK
CONTROLS (LC)
LCI LCO
COUNTER/TIMER 1 0 0 COUNTER/TIMERS INDEPENDENT
ENABLE (CTIE) 0 1 CIT 1's OUTPUT GATES CIT 2
1 0 CIT 1'8 OUTPUT TRIGGERS CIT 1
COUNTER/TIMER 2 l I C I T l's OUTPUT IS CIT 2's
ENABLE (CT2E) COUNT INPUT
PORT C AND COUNTER/------" '------PORTA ENABLE (PAE)
TIMER 3 ENABLE
(PCE AND CT3E) '-------PORT LINK CONTROL (PLC)
O=PORTS A AND B OPERATE INDEPENDENT
I=PORTS A AND B ARE LINKED
• Port Mode Specification Registers (PMSR)

Addresses: 100000 Port A
101000 Port B
(Read/Write)
I
L
1071 D61 Os 1D41 D31 D21 01 Do 1
PORT TYPE~ LLATCH ON PATTERN MATCH (LPM)

SEL~CTS (PTS) (BIT MODE)
DESKEW TIMER ENABLE (DTE)
PTSI PTSO
(HANDSHAKE MODES) .
o 0 BIT PORT
o 1 INPUT PORT PATTERN MODE SPECIFIC~TION
1 0 OUTPUT PORT BITS (PMS)
1 1 BIDIRECTIONAL
PMSI PMSO
PORT - 0 - --0- DISABLE PATTERN MATCH
INTERRUPT ON TWO------' o 1 "AND" MODE
BYTES (ITB) 1 0 "OR" MODE
1 1 "OR PRIORITY ENCODED
SINGLE BUFFERED--------'--" VECTOR" MODE
MODE (SB) '------INTERRUPT ON MATCH ONLY elMO)
--.-.-----------SHARP ---....-.--------
372
• Port Handshake Specification Registers (PHSR)

101001 Port B
(Read/Write)
! D7! D61 D5! D.I Da! D2! D, IDol

HANDSHAKE TYPE SPECIFICATION~ LDESKW TIME SPECIFICATION
BiTS (HST) BITS
HSTl HSTO SPECIFIES THE MSB's OF
o 0 INTERLOCKED HANDSHAKE DESKEW TIMER TIME CONSTANT
o 1 STROBED HANDSHAKE LSB IS FORCED 1.
1 0 PULSED HANDSHAKE
1 1 THREE WIRE HANDSHAKE
REQUEST/WAIT SPECIFICATION-----'
BITS (RWS)
RWS2 RWSI RWSO FUNCTION
- 0 - --0- --0- REQUEST WAIT DISABLED
o 0 1 OUTPUT WAIT
o 1 1 INPUT WAIT
1 0 0 SPECIAL REQUEST
1 0 1 OUTPUT REQUEST
1 1 1 INPUT REQUEST
• Port Command and Status Registers (PCSR)

001001 Port B
(Read/Partial Write)
! D71 D6! D5! D4! Da! D21 Dl ! Dol
jJ
~
INTERRUPT UNDER INTERRUPT ON ERROR (IOE)
SERVICE (IUS)
PATTERN MATCH FLAG (PMF)
INTERRUPT ENABLE {IE} I I (READ ONLY)
I I
INTERRUPT PENDING {IP} I I INPUT REGISTER FULL (IRF)
I I
I I (READ ONLY)
IUS, IE, AND IP ARE WRITTEN USING
THE F:0LLOWING CODE:
NULL CODE 0
II 0 0
OUTPUT REGISTER EMPTY (ORE)
(READ ONLY)
CLEAR IP & IUS 0 0 1

SET IUS 0 1 0
CLEAR IUS 0 1 1
SET IP 1 0 0
CLEAR IP 1 0 1
SET IE 1 1 0
CLEAR IE 1 1 1
INTERRUPT ERROR (ERR)

(READ ONLY)
-----------........,.-----.--SHARP~---------
373
.............................. .....
Z8036/Z8036A Counter/TImer and Parallel I/O Unit
, ~ ~~ .......... ~~~ ..... .....
LH8036/LH8036A
~
• Data Path Polarity Registers (DPPR) • Special 1/0 Control Registers (SIOCR)

101010 Port B Adclresses: 100100 Port A
000101 Port C (4 LSBs only) 101100 Port B
(Read/W rite) 000111 Port C (4 LSBs only)
(Read/W~ite)
1~1~1~1~1~I~t~I~1 I~I~I~I~I~I~I~I~I
I I
DATA PATH POLARITY (DPP)
SPECIAL INPUT /OUTPUT (SIO)
0= NON -INVERTING
0= NORMAL INPUT OR OUTPUT
1 = INVERTING
1 = OUTPUT WITH OPEN DRAIN OR
INPUT WITH I's CATCHER
• Data Direction Registers (DDR) • Port Data Registers (PDR)

Addresses: 100011 Port A 001110 Port B
101011 Port B (Read/Write)
ooono Port C (4 LSBs only)
(Read/Write)
I~I~I~I~I~I~I~I~I
DATA DIRECTION (DD) • Port C Data Register (PCDR)
0= OUTPUT BIT
1 = INPUT BIT Address: 001111
(Read/Write)
4 MSBs
0= WRITING OF CORRESPONDING LSS ENABLED
1 = WRITING OF CORRESPONDING LSS INHIBITED
(READ RETURNS 1)
• Pattern Polarity Registers (PPR)
101101 Port B
(Read/Write)
ID71 D61 D51 D41 D31 Dzi D, IDo I
I
• Pattern Transition Registers (PTR)

Addresses: 100110 Port A PM PT PP PATTERN SPECIFICATION
101110 Port B
(Read/Write)
ID71 D61 Dsl D41 D31 Dzi D, IDo I o
O· 0
1
X BIT MASKED OFF
X ANY TRANSITION
1 0 0 ZERO
1 0 lONE
1 1 0 ONE-TO-ZERO TRANSITION (\.)
1 1 1 ZERO-TO-ONE TRANSITION (,i')
• Pattern Mask Registers (PMR)
I~I~I~I~I~I~I~I~I
101111 Port B
(Read/Write)
I
- ........ ------~ .......... -SHARP . - . - . - - - - - - - - - - - -

374
• Counter/Timer Command and Status Registers (CTCSR)
Addresses 0 0 1 0 1 0 Counter /Timer 1

o 0 1 0 1 1 Counter /Timer 2
o 0 1 1 0 0 Counter/Timer 3
I~I~I~I~I~I~I~I~I
Interrupt under service (IUS)-.J~
(Read/Write)
II LCooo ' • "'","" (CIP)
(Read only)
Interrupt enable (IE) - - Trigger command bit (TCB)
(Read/Write) (Write only. Read returns 0)
Interrupt pending (IP) Gate command bit (GCB)
(Read/Write) (Read/Write)
IUS, IE, IP are written using the following code Read counter control (RCC)
OOO=Null code (Read/Set only cleared by reading CCR Ls)
001 = Clear IP & IU S
010=Set IUS
011=ClearlUS ' - - - - - - - - Interrupt error (ERR)
100 = Set IP (Read only)
101 = Clear IP
110 = Set IE
111 = Clear IE
• Counter/Timer Mode Specification Registers (CTMSR)
Addresses 0 1 1 1 0 0 Counter /Timer 1

o1 1 1 0 1 Counter /Timer 2
o1 1 1 1 0 Counter /Timer 3
(Read/Write)
C~H"OOM ,mg" ,,''(C/SC)~

External output enable (EOE)
I I II I L 0."., ,.".,.,. ,.,.,"
00 = Pulse output .
External count enable (ECE) 01 = One -shot output
External trigger enable (ETE) 10 = Sq'uarew ave output
External gate enable (EGE) 11 = Do not specify
Retrigger enable bit (REB)
• Counter/Timer Current Count Registers (CTCCR)
Address 0 1 0 0 0 0 Counter/Timer 1's MSB

o 1 0 0 0 1 Counter/Timer l's LSB
o 1 0 0 1 0 Counter /Timer 2's MSB
o 1 0 0 1 1 Counter/Timer 2's LSB
o 1 0 1 0 0 Counter /Timer 3's MSB
o 1 0 1 0 1 Counter/Timer 3's LSB
(Read only)
I I
D71 Dol Dsl D41 D31 D,I Dl Do I D71 Dol Dsl D41 D31 Dzi Dl I Do I
Most significante byte---_--'f ,--I ----Least significant byte
375
Z.8036/Z8036A Gounter/Timer and Parallel. I/O Unit L.,H8036/LH8036A
• Counter/Timer Time Constant Registers (CTTCR)
Addresses: 010110 Counter/Timer 1's MSB

010111 ·Counter/Timer 1's LSB
011000 Counter/Timer 2;s MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/Timer 3's LSB
(Read/Write)
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I
MOST SIGNIFICANT------.JI L-I--~--LEAST
BYTE SIGNIFICANT
BYTE
• Interrupt Vector Register (lVR)

• Counter/Timer Status
D2 D1
Addresses: 000010 Port A 0 0 C/T3
000011 Port B .0 1 C/T2
000100 Counter /Timers 1 0 C/Tl
(Read/Write)
1 Error
I~I~I~I~I~I~I~I~I
I
INTERRUPT VECTOR
• Port Vector Status • Current Vector Register (CVR)
(1) P encoded vector mode

Address: 011111
(Read Only)
I~I~I~I~I~I~I~I~I
X(X X Number of highest priority
bit with a watch
I
INTERRUPT V~CTOR BASED
ON HIGHEST PRIORITY
(2) All other modes UNMASKED IP.
IF NO INTERRUPT PENDING
ALL 1'8 OUTPUT.
ORE IRF PMF Normal
o 0 0 Error
~----------SHARP-~------
3.76
Z8038/Z8038A FlO Input/Output Interface Unit LH8038/LH8038A
LH8038/LH8038A Z80381Z8038A FlO I~putl

Output Interface Umt

The LH8038 Z8038 FlO provides an asynchro-
nous 128 byte FIFO buffer between two CPUs or +5V
between a CPU and a peripheral device_ This buf- o [AJ
fer interface expands to a 16-bit or wider data rnJ
path and expands in depth to add as many FIFOs
~
(and an additional LH8038) as are needed.
The LH8038 manages data transfers by assum-
mJ
ffi]
ing Z-BUS, non-Z-BUS microprocessor (a general-
ized microprocessor interface), Interlocked 2-Wire [f]
,Handshake, and 3-Wire Handshake operating modes. [Q]
These modes interface dissimilar CPUs or CPUs llil
and peripherals running under differing speeds or rn
protocols, allowing asynchronous data transactions
and improving I/O overhead by as much as two
rn
00
orders of magnitude.
OJ
The LH8038 supports the Z-BUS interrupt pro-
02
tocols, generating seven sources of interrupts upon
~
any of the following events: a write to a message 03
register, change in data direction, pattern match, O.
status match, over/underflow error, buffer full and 05
buffer empty status. Each interrupt source can be 0&
enabled or disabled, and can also place an inter- 07
rupt vector on the port address/data lines.
GNO Mo
The LH8038A Z8038A 1"10 is the high speed
Top View
• Features 4. Seven sources of vectored/nonvectored inter-

1. 128-byte FIFO buffer provides asynchronous rupt which include pattern-match, byte count,
bidirectional CPU/CPU or CPU/peripheral in- empty or full buffer status; a dedicated "mail-
terface, expandable to any width in byte incre- box" register with interrupt capability pro-
ments by use of multiple FIOs. vides CPU/CPU communication.
2. Interlocked 2-Wire or 3-Wire Handshake logic 5. REQUEST /W AIT lines control high-speed
port mode; Z-BUS or non-Z-BUS interface. data transfers.
3. Pattern-recognition logic stops DMA transfers 6. All functions are software controlled via directly
and/or interrupts CPU; preset byte count can addressable read/write registers.
initiate variable-length DMA transfers.
377
Z8038/z8038A FlO Input/Output Interface Unit LH8038/LH8038A
• Block Diagram
Status Logic
Pattern and Registers Pattern
Match Match
Logic Logic
Data Bus Data Bus

Data 128X8 Data
Buff~r FIFO Buffer Buffer
Register Register
Port 1 Side I Port 2 Side

I
I
:-~------SHARP ....------...-.-----------
378
• Pin Description
(1) Pins common to both ports 1 and 2
Pin Pin signal Meaning I/O Function
Mo Mo Multimicro output 0 Ml and Mo program Port 1 side
Ml Ml Multimicro input I CPU interface
(2) Z-bus low byte mode

Bidirectional
Do-D 7 AD o-AD 7 Address/ data bus Multiplexed bidirectional bus, Z-BUS compatible
3-state
Active low. open-drain output with WAITselected ;
-----
A REQ/WAIT Request/wait 0 REQUEST line for DMA transfer; WAIT line for
data transfers to and from CPU.
Active low. Provides timing for data transfer to and
B DMASTB DMA strobe I
from the FIFO buffer.
- Active low. Provides timing for data transfer to or
C DS Data strobe I
fn?m Z·FIO.
- Active high signals CPU to head from Z-FIO ; active
D R/W Read/write I
Low signals CPU to write to Z-FIO.
- Active low. Enables Z-FIO. Latched on the rising
E CS Chip select I
edge of AS.
- Active low. Addresses. CS and INT ACK are sampled
F AS Address strobe I -
while AS is Low.
G INTACK Interrupt acknowledge I Active low. Latched on the rising edge of AS.
Active high. Sends interrupt enable to lower priority
H lEO Interrupt enable output 0
device lEI pin.
Active high. Receives interrupt enable from higher
I lEI Interrupt enable input I
priority device lEI pin.
- Active low, open-drain output.
J INT Interrupt request 0
Interrupt request signal to CPU.
(3) Z-bus high byte mode

Bidirectional
Do-D 7 ADo-;-AD7 Address/ data bus Multiplexed bidirectional bus, Z-BUS compatible.
3-state I
Active low, open-drain output when WAIT selected;
-----
A REQ/WAIT Request/wait 0 REQUEST line for DMA transfer; WAIT line for
data transfers to and from CPU.
Active low. Strobes DMA data to and from the FIFO
B DMASTB DMA strobe I
buffer.
- Active low. Provides timing for data transfer to or
C DS Data strobe I
from Z-FIO.
- Active high signals CPU to read from Z-FIO ; active
D R/W Read/write I
low signal CPU to write to Z-FIO.
- Active low. Enables Z-FIO. Latched on the rising
E CS Chip select I
edge of AS
- Active low. Addresses, CS and INT ACK are sampled
F AS Address strobl· I -
while AS is low.
G-J Ao-Aa Address bits I Active high. Specify Z=FIO internal registers.
379
l8038/Z8038A FlO Input/Output Inter:tace Unit LH8038/LH8038A
(4) Non-Z-bus mode

Pin Pin signal Meaning 110 Function
Bidirectional
Do -D 7 Do-D 7 Data bus Bidirectional data bus.
3-state
Active low, open-drain output when WAIT is select-
-----
A REQ/WAIT Req uestl wait 0 ed ; REQUEST line for DMA transfer; WAIT line
for data transfer to and from CPU.
B DACK DMA acknowledge I Active low. DMA acknowledge signal.
C RD Read I Active low. Timing signal for reading.
D WR Write I Active low. Timing signal for writing.
E CE Chip select I Active low. Signal that is used to select Z-FIO.
- Active high identifies control byte on Do-D7, active
F C/D Controll data I
low identifies data byte on Do- D7
G INTACK Interrupt acknowledge I Active low. acknowledges an interrupt.
Active high. Sends interrupt enable to lower priority
H lEO Interrupt enable output 0
device IEI pin.
Active high. Receives interrupt enable from higher
I lEI Interrupt enable input I
priority device lEO signal.
- Active low, open drain. Signals Z-FIO interrupt to
J INT Interrupt 0
CPU.
(5) Port 2-1/0 port mode

Bidirectional
Do -D 7 Do-D 7 Data bus Bidirectional data bus.
3-state
For input handshake, RFD (active High) signals that
-- Ready for datal
A RFD/DAV 0 Z-FIO is ready to receive data. For output handshake,
data available
DA V (active Low) signals that output data is valid
~: Active low. Signals that input data is valid in the case
---
B ACKIN Acknowledge input I of input handshake or that output data is received by
peripherals in the case of output handshake.
For input handshake, DA V (active low) signals that
-- Data availablel
B DAV/DAC I input data is valid. For output handshake, DAC (ac-
data accepted
tive high) signals that listener has received data.
Active high, open drain. Signals that FIFO buffer is
C FULL Full 0
full.
Both active high. For input handshake, DAC (an out-
Data acceptedl put) signals that data has been received from talker.
C DAC/RFD 110
ready for data For output handshake, RFD (an input) signals that
the listeners are ready for data.
Active high, open drain. Signals that FIFO buffer is
D EMPTY Empty 0
empty.
--- Active low. Can clear data from FIFO buffer in the
E CLEAR Clear 110
case of input.
Data direction is controllable for input. Active high
F DATA DIR Data direction I/O signals data input to ports 2 ; Low signals data out-
put from Port 2.
G INo Input I Input line to bit 0 (Do) of control register 3.
H OUT l Output 0 Output line from bit (D l ) of control register 3.
- Actiye low. When low, enables bus drivers. When
I OE Output enable 0
high, floats bus drivers at high inpedance .
J OUTa Output 0 . Output line from bit 3 (D3) of control register 3_
---.-.------SHARP-------------
380
Z8038/Z8038A FlO Input/OLitput Interface Unit LH8038/LH8038A

Input voltage * V IN -0.3-+7 V
Output voltage * VOUT -0.3-+7 V
Operating temperature Top, 0-+70 "C
Storage temperature ' T s'" -6S-+1S0 "C
Note The maximum applicable voltage on any pin with respect to GND.
+5V +5V
2.2kn
From test output 0--..-+-1......
From test output i 12.2k!l
Standard test load

r 50PF
Open-drain test load
• DC Characteristics (Vcc=SV±S%, Ta=0-+70"C)

Input high voltage VlH 2 Vcc+ 0.3 V
Output high voltage VOH Ion =-2S0,uA 204 V
IOL =+2mA 004 V
IOL=+3.2mA O.S V
In put leakage current I IIIL I Oo4~VIN<204V 10 ,uA
Output leakage current IloL I Oo4~VotJT~204V 10 ,uA
Mode pins input leakage ILM O<VIN<V CC -100 10 ,uA
• Capacitance (f=IMHz, Ta=0-+70"C)

Unmeasured pins
Output capacitance COUT IS pF
returned to ground
Bidirectional capacitance CI/O 20 pF
(f=lMHz, Ta=O-+70"C)
• Inputs
Any input rise ti!lle t, 100 ns
Any input fall time t, 100 ns
--~'-------SHARP-'-------------
, 3.81
(1) Z-bus CPU interface timing

LH8038 LH8038A
No. . Symbol Parameter Unit Note
MIN. MAX. MIN. 'MAX.
1 TwAS AS low width 70 50 ns 1
2 TsA (AS) \ Address to AS t setup time 30 10 ns 1
3 ThA (AS) Address to AS t hold time 50 30 ns 1
4 TsCSO (AS) CS to AS t setup time 0 0 ns 1
5 ThCSO (AS) CS to AS t hold time 60 40 ns 1
6 TdAS (DS) AS t to DS ~ delay 60 40 ns 1
Address to DS ~ setup time
7 TsA (DS) 120 100 ns
(with AS t to DS ~ =60ns)
8 TsRWR (DS) R/W (Read) to DS ~ setup time 100 80 ns
9 TsRWW (DS) R/W (Write) to DS ~ setup time . 0 0 ns
10 TwDS DS low width 390 250 ns
11 TsDW (DSf) Write data to DS ~ setup time 30 20 ns
DS (Read) ~ to address data bus driven
12 TdDS (DRV) 0 0 ns
delay
13 TdDSf (DR) DS ~ to read data valid delay 250 180 ns
14 ThDW (DS) Write data to DS t hold time 30 20 ns
15 TdDSr (DR) DS t -to read data not valid delay 0 0 ns
16 TdDS (DRz) DS t to read data float delay 70 45 ns 2
17 ThRW (DS) R/W to DS t hold time 55 40 ns
18 TdDS (AS) DS t to AS ~ delay 50 25 ns
Note .. t " indicates a rising edge and" l .. a falling edge.
Note 1 Parameter does not apply to interrupt acknowledge transactions.
N9te 2 Float delay is measured to the time when the output has changed 0.5 V from steady state with minimum ac load and maximum dc
load,
Note 3 This is the delay from DS of one cia access to DS of another FlO access (either read or write).
AS
CS
R/W
READ
R/W
WRITE
DS
FlO
ADo-ADI5 WRITE
FlO
READ
Z-bus CPU interface ttming
-----.-~...--.-~-SHARP --------.-~-,-
382
(2) Z-bus CPU interrupt acknowledge timing

LH8038 LH8038A
MIN. MAX. MIN. MAX.
20 TsIA (AS) INT ACK low setup time to AS t 0 0 ns
21 ThlA (AS) INT ACK low hold time to AS t 250 250 ns
22 TdDSA (DR) DS (acknowledge) ! to vector valid delay 250 180 ns
23 TwDSA DS (acknowledge) low width 390 250 ns
24 TdAS (lEO) AS t to lEO ! delay (INT ACK cycle) 350 250 ns 4
25 TdlEI (lEO) lEI to lEO delay 150 100 ns 4
26 TsIEI (DSA) lEI to OS (acknowledge) ! setup time 100 70 ns
27 ThIEl (OSA) lEI to OS (acknowledge) t hold time 50 30 ns 4
28 TdOS (INT) OS (INT ACK cycle) to INT delay 900 800 ns
29 TdOCST Interrupt daisy chain settle time ns 4
- -
Note 4: The parameters for the devices in any particular daisy chain must meet the following constraint: The delay from AS to DS must
be greater than the sum of TdAS (lEO) for the highest priority peripheral, TsIEI (DSA) for the lowest ,priority peripheral and
TdlEI (lEO) for each peripheral, ,separating them in the chain.
ADo-AD7 -V
J\.
~ndefined »------------~-
@J Vector
/
'-----
~
INTACK
i-----@--'---+f 1 - - - -
lEI
lEO
Z-bus CPU interrupt acknowledge timing
383
za03S/Z803SA FlO Input/Output Interface' Unit LHS03S/LHS03SA.
(3) Non-Z-bus CPU Interface timing

LH8038 LH8038A
MIN. MAX. MIN. MAX.
1 TsCD (RD) C/D setup time to RD ~ 80 80 ns' 5
2 TsCD (WR) C/D setup time to WR ! 80. 80 ,ns
3 ThCD (RD) C/D hold time to RD t 0 0 ns 5
4 ThCD (WR) C/D hold time to WR t 0 0 ns
5 TsCEI (RD) CE low setup time to RD ! O. 0 ns , 5
6 TsCEI (WR) CE low setup time to WR ! 0 0 ns
7 ThCEI (RD) CE low hold time to RD t 0 0 ns 5
8 ThCEI (WR) CE low hold time to WR t 0 0 ns
9 TsCEh (RD) CE high setup time to RD ~ 100 70 ns 5
10 TsCEh (WR) CE high setup time to WR ! 100 70 ns
11 TwRDl RD low width 390 250 ns
12 TdRD (DRA) RD ! to read data active delay 0 0 ns
13 TdRDf (DR) RD ! to valid data delay 250 180 ns
14 TdRDr (DR) RD t to read data not valid delay 0 0 ns
15 TdRD (DRz) RD t to data bus float delay 70 45 ns 6
16 TwWRl WR low width 390 250 ns
17 TsDW (WR) Data setup time to WR ~ 0 0 ns
18 ThDW (WR) Data hold time to WR t 30 20 ns
Note 5: Parameter does not apply to interrupt acknowledge transactions.
Note 6: Float delay is measured to the time the output has changed O~V from~ady state with minimum ac load and maximum dc load.
Note 7: This is the delay from RD f to WR f of one FlO access to RD ! or WR ! of another FlO access.
c/o
Do-D7
FlO READ
Do-D7
FlO WRITE
Non-Z-bus CPU interface timing
CE ~
RD,QR WR
J \
Non-Z-bus interface timing
------.-.......---SHARP--.-~.---
/
384
ZS03S/ZS03SA FlO Input/Output Interface Unit LHS03S/LHS03SA
(4) Non-Z-bus interrupt acknowledge timing

LH8038 LH8038A
MIN. MAX. MIN. MAX.
20 TdIEI (lEO) IEI to lEO delay 150 100 ns 8
21 TdI (lEO) INT ACK ! to lEO ! delay 350 250 ns 8
22 TsIEI (RDA) IEI setup time to RD (acknowledge) ! 100 70 ns 8
23 TdRD (DR) RD ! to vector valid delay 250 180 ns
24 TwRDI (IA) Read low width (interupt acknowledge) 390 250 ns
25 ThIA (RD) INT ACK low hold time to RD f 30 20 ns
26 ThIEl (RD) lEI 'hold time to RD f 20 10 ns
27 TdRD (INT) RD f to INT f delay 900 800 ns
28 TdDCST Interrupt daisy chain settle time 350 250 ns 8
Note 8: The parameter for the devices in any particular daisy chain must meet the following constraint: The delay from INTAC ~ to RD ~
must be greater than the sum of TdlNA (lEO) for the highest priority peripheral, TslEl (RD) for the lowest priority peripheral, and
TdlEl (lEO) for each peripheral separating them in the chain.
INTACK
lEI
lEO
Non-Z-bus interrupt acknowledge timing
(5) Port 2 side operation

LH3038 LH3038A
MIN. MAX. MIN. MAX.
I TwCLR Width clear to reset FIFO 700 700 ns
2 TdOE (DO) OE ! to data bus driven 0 0 ns
3 TdOE (DRZ) OE f to data bus float ns
CLEAR INPUT
~r:=CD4J
\ . . . - --J-
\-
I:=®,r-.____'---:;®--"j~
{
DATA OUT -t Valid data )------
Port 2 side operation
385
Z8038/Z8038AFIO Input/Output Interface Unit LH8038/LH8038A
(6) 2-wire handshake (port 2 side only) output

LH8038 LH8038A
MIN. MAX. MIN. MAX.
1 TsDI (ACK) Data input to ACKIN l setup time 50 50 ns
2 TdACKf (RFD) ACKIN l to RFD l delay 0 500 0 500 ns
3 TdRFDr (ACK RFD t to ACKIN l delay 0 0 ns
4 TsDO (DAV) Data output to DAV l setup time 50 25 ns
5 TdDA Vf (ACK) DA V l to ACKIN l delay 0 0 ns
6 ThDO(A+K) Data output t to ACKIN hold time 50 50 ns
7 TdACK (DAV) ACKIN l to DA V t delay 0 500 0 500 n's
8 ThDI (RFD) ! Data input from RFD l hold time 0 0 ns
9 TdRFDf (ACK) RFD l to ACKIN t delay 0 0 ns
10 TdACKr (RFD ACKIN t to RFD t delay 0 400 0 400 ns
11 TdDAVr (ACK) DA V t to ACKIN t delay 0 0 ns
12 TdACKr (DA V) ACKIN t to DA V l delay 0 800 0 800 ns
13 TdACKf (EMPTY) ACKIN l to EMPTY t delay 0 0 ns
14 TdACKf (FULL) ACKIN l to FULL l (FULL t ) delay 0 0 ns
15 TcACK ACKIN cycle time 1 1. ns
DATA
ACKIN
INPUT
RFD
OUTPUT
----~==~--@------~
EMPTY
FULL
~7r-----'----
2-wire handshake (Port 2 side only) output
DATA
ACKIN
INPUT
DAV
OUTPUT
EMPTY
FULL
2-wire handshake (Port 2 side only) input
.------~.-----,.--SHARP ....-.-------.-----
386
ZS038/ZS03SA FlO Input/Output Interface Unit LH803S/LHS03SA·
(7) 3-wire handshake timing

LH3038 LH3038A
MIN. MAX. MIN. MAX.
1 TsDI (DAV) Data input to DA V ~ setup time 50 50 ns
2 TdDAVIf (RFD) DAV ~ to RFD ~ delay 0 500 0 500 ns
3 TdDA VIf (DAC) DA V ~ to DAC t delay 0 500 0 500 ns
4 ThDi (DAC) Data input from DAC t hold time 0 0 ns
5 TdDACIr (DA V) DAC t to DA V t delay 0 0 ns
6 TdDA VIr (DAC) DAV t to DAC ~ delay 0 500 0 500 ns
7 TdDA VIr (RFD) DA V t to RFD t delay 0 500 0 500 ns
8 TdRFDI (DA V) RFD t to DA V ~ delay 0 0 ns
9 TsDO (DAC) Data output to DA V ~ setup time ns
10 TdDA VOf (RFD) DA V ~ to RFD ~ delay 0 0 ns
11 TdDA VOf (DAC) DA V ~ DAC t delay 0 0 ns
12 ThDO (DAC) Data output from DAC t hold time ns
13 TdDACOr (DA V DAC t to DA V t delay 400 400 ns
14 TdDAVOr (DAC DA V t to DAC ~ delay 0 0 ns
15 TdDAVOr (RFD) DA V t to RFD t delay 0 0 ns
16 TdRFDO (DA V) RED t to DA V ~ delay 0 800 0 800 ns
DATA
( PIN) DAV
38 INPUT
( PIN) RFD
39 OUTPUT
( PIN\
37) DAC
OUTPUT
3-wire handshake (Port 2 side only) input
DATA Valid data
( PIN) DAC
38 INPUT _ _+ ___ ~I
( PIN) RFD
37 INPUT
(PIN) DAV
\ 39 OUTPUT
3-wire handshake (Port 2 side only) output
387
Z80.38fZ8038A FlO Input/Output Interface Unit LH8038/LH8038A
• Operating Modes The pins on the LH8038's Port 1 side are iden- _
KH 8038 operates in any of twelve combinations tical to those on the Port 2 side, except for two pins
of operating modes, listed in Table 1. Port 1 func- (Mo and MI ), which select that port's operating
tions in either the Z- bus or non-Z- bus micro- mode. Port 2's operating mode is programmed by
processor· modes, while Port 2 functions in Z-BUS; two bits (BO and B1) in Port l:s Control register O.
non-Z-bus, Interlocked 2-Wire Handshake, and
3-Wire Handshake modes_ Table 2 describes the
signals and their corresponding pins in each of
these modes.
Table 1 Operating modes

Mode Ml M2 Bl Bo Port 1 Port 2
0 0 0 0 0 Z-bus low byte Z-bus low byte
1 0 0 0 1 Z-bus low byte Non-Z-bus
2 0 0 1 0 Z-bus low byte 3-wire handshake
3 0 0 1 1 Z-bus low byte 2-wire handshake
4 0 1 0 0 Z-bus high byte Z-bus high byte
5 0 1 0 1 Z-bus high byte Non-Z-bus
6 0 1 1 0 Z-bus high byte 3-wire handshake
7 0 1 1 1 Z-bus high byte 2 - wire handshake
8 1 0 0 0 Non-Z-bus Z-bus low byte
9 1 0 0 1 Non-Z-b-us Non-Z-bus
10 1 0 1 0 Non-Z-bus 3-wire handshake
11 1 0 1 1 Non-Z-bus 2 - wire handshake
Table 2 Pin assignments

Signal pins Z-bus low byte Z-bus high byte Non-Z-bus Interlocked HS port * 3-wire HS port*
[AI REQ/WAIT REQ/WAIT REQ/WAIT RFD/DAV RFD/DAV
lliI DMASTB DMASTB DACK ACKIN DAV/DAC
IQ DS DS RD FULL DAC/RFD
[f2] R/W R/W WR EMPTY' EMPTY
lEI CS CS CE CLEAR CLEAR
lEI AS AS C/D DATA DIR DATA DIR
IGl INTACK Ao INTACK INo INo
IHI lEO Al lEO OUT l OUT I
rn lEI A2 IEI OE OE
ITl INT A3 INT OUT 3 OUT 3
Port 2 side only
---'-~'---""-"-SHARP --.---------.-.
388
CHANNEL A
CHANNEL B
PORT 2
<8>
PORT 3
<8>
Z80 bus
I/O
Z80
} HANDSHAKE
SIGNALS
MEMORY
Z-bus Z80 bus
Fig. 1 CPU to CPU configuration Fig. 2 CPU to 110 configuration
• CPU Interface
The LH8038 is designed to work with both The non-Z-bus configuration is used for CPUs
Z-bus and non-Z-bus-type CPUs on both Port 1 where the address and data buses are separate. An
and Port 2. The Z-bus configuration interfaces Example of this type of CPU is the Z80. The RD
CPUs with time·multiplexed address and data in· (Read) and WR (Write) pins are used to time reads
formation on the same pins. The Z8001, Z8002, and writes from the CPU to the FlO (Fig. 5 and 6).
and Z8 are examples of this type of CPU. The AS The C/O (Cantrall Data) ~n is used to directly ac·
(Address Strobe) pin is used to latch the address cess the FIFO buffer JC/D = Low) and to access
and chip select information sent out by the CPU. the other register (C/D = High).
The RIW (Read/Write) pin and the DS (Data
Strobe) pin are used for timing reads and writes
from the CPU to the LH8038 (Fig. 3 and 4).
Address valid To CPU
ADo-AD, --<'-_....1)>-----«'-_....1)>----
AS
CS~
R/W :J ,
DS ,'-_ _ _....J/
Fig. 3 Z-bus read cycle timing
389
2-8038/Z8038A' FlO Input/Output Interface Unit· LH8038/LH8038A
Addre.ss valid
ADo-AD7 --cJ-< Data from CPU }--
AS~
CS
R/W \ c
DS ''-__--II
Fig. 4 Z-bus write cycle timing
c/n :==x x:=

(ToCPU~
CE \I.-_ _ _ _ _ _ _-JI
RD \1.-_ _ _ _-J1
Fig. 5 Non-Z-bus read cycle timing
c/n
Do- D7
X
From CPU )
x==
<
CE
WR
\
, I
I
Fig. 6 Non-Z-bus write cycle timing
• CPU-CPU Operation • CPU to I/O Operation

(1) DMA operation When Port 2 is programmed in the Interlocked
The LH8038 is particularly well suited to work 2-Wire Handshake mode or the 3-Wire Handshake
with a DMA in both Z-bus and non-Z-bus mod- mode, and Port 1 is programmed in Z-bus or
es. A d~ta transfer between the LH8038 and sys- non-Z-bus Microprocessor mode, the LH8038 in-
tem memory can take place durring every machin~ terfaces a CPU and a peripheral device.
cycle on both sides of the LH8038 simultaneously. (1) Interlocked 2-wire handshake
(2) Message registers In the Interlocked Handshake, the action of the
Two CPUs can communicate through a dedicated LH8038 must be acknowledged by the other half of
"mailbox" register without involving the 128 X 8 the handshake before the next action can take
bit FIFO buffer. This mailbox approach is useful place. In output mode, Port 2 does not indicate that
for the transferring control parameters between new data is available until the external device indi-
the interfacing devices on either side of the cates it is ready for the data. Similarly, in input
LH8038 without using the FIFO buffer. mode, Port 2 does not indicate that it is ready for
(3) Direction of data transfer operation new data until the data source (external device) in-
The Data Direction bit controls the direction of dicates that the previous byte of the data is no lon-
data transfer in the FIFO buffer. This bit reads ger available, thereby acknowledging Port 2's
correctly when read by either port's CPU. For ex- acceptance of the last byte by Port 2's Ready for
ample, if Port l's CPU reads Ii 0 (CPU output) in Data Signal (RFD -+ High).
its Data Direction bit, then Port 2's CPU reads a 1
(input to CPU) in its Data Direction bit.
390
(2) 3-wire handshake

The 3-Wire Handshake is designed for applica- Data Direction pin of Port 2 as an input (Control
tions in which one output port is communicating Register 3, bit 5 = 1).
with many input ports simultaneously. It is essen- For cascading purposes, the Data Direction pin
tially the same as the Interlocked Handshack, ex- can also be defied as an output (Control Register 3,
cept that two signals are used to indicate that an bit 5 = 0) pin which reflects the current state of
input port is ready for new data or that it has the Data Direction bit. It can then be used to con-
accepted the present data. With 3- Wire Hand- trol the direction of data transfer for other
shake, these lines (RFD, DAC) of many input ports LH8038s or for external logic.
can be bussed together with open-drain drivers
and the output port knows when all of the ports are • Programming
ready and have accepted the data. This handshake The programming of the LH 8038 is greatly sim-
is the same handshake used in the in IEEE-488 In- plified by the efficient grouping of the various op-
struments. Since the port's direction can be changed eration modes in the control registers. Since all of
under software control, bidirectional IEEE-488-type the control registers are read/write, the need for
transfers can be performed. maintaining thier image in system memory is eli-
(3) Data direction control minated. Also, the read/write feature of the regis-
In CPU -to- I/O mode, the direction of data trans-
ters aides in system debugging.
fer can be controlled by the CPU side (Port 1)
Each side of the LH 8038 has 16 registers. All
under software control. The data direction can also
16 registers are used by the Port 1 side ;
be determined by hardware control by defining the
Table 1 Z-FIO register address summary

Non-Z-bus DT D4 D3 D2 D, Do
Z-bus high A3 A2 A, Ao
IRJA=O ADT AD 5 AD4 AD3 AD2 AD, ADo
Z-bus low
RJA=l ADTAD4 AD" AD2 AD, ADo
Register
Control Register 0 X 0 0 0 0 X
Interrupt Status Register 0 X 0 0 1 0 X
Interrupt Vector Register X 0 1 1 0 X
Byte Count Register X 0 1 1 1 X
Byte Count Comparsion
X 1 0 0 0 X
Register
Control Register 2 * X 1 0 0 1 X
Message Output Register X 1 0 1 1 X
Message Input Register X 1 1 0 0 X
Pattern Match Register X 1 1 0 1 X
Pattern Mask Register X 1 1 1 0 X
Data Buffer Register X 1 1 1 1 X
x = Don't Care bit (0, 1)
* Register is only 0 Port 1 side
---.--.------~-SHARP---------
391
Z80S.8/Z8038A FlO Input/Output Interface Unit LH8038/Lhl8038A
• Control Register 0
Address:, 0000
(Read/Write)
I D7 I D6 I D51 D41 D3 I' D2 I DI I Do I

1 = INTERRUPTS E~ABLED
(MIE)J
1 = DISABLE LOWER DAISY CHAIN (DLC)
1 J I'---r
Lin I L I ~ RESET .
' - 1 = RT.JUST.ADDRESS (RJA)
1 = NO VECTOR ON INTERRUPT ( N V ) ' (BI) (Bo)· }
1 = VECTOR INCLUDES STATUS (VIS)
o0 01 == NON-Z-BUS
Z-BUS CPU
CPU
,PROGRAMS
PORT 2 MODE
1 0 = 3-WIRE HS I/O '
. 1 1 = INTERLOCKED HS
·READ-ONLY FROM
· PORT 2 SIDE
Address: 0001
(Read/Write)
I D71 D61 D51 D41D31 D21 DI IDol
(MUST BE PROGRAMMED 0)
NOT USED
1 = FREEZE STATUS REGISTER COUNT
J
1 = MESSAGE MAILBOX REGISTER FULL·
I JU ~L= 01 == WAIT
REQUEST/WAIT ENABLED
1 = REQUEST
1 = MESSAGE MAILBOX REGISTER UNDER 1 = START DMA ON BYTE COUNT
SERVICE· 1 = STOP DMA ON PATTERN MATCH
• READ-ONL Y BITS
• Control Register 2*
Address: 1001
(Read/Write) I D71 D61 Dsl D41 D31 D21 DI I Do I
BITS 2-7 NOT USED
MUST BE PROGRAMMED 0
I L L1 = PORT 2 SIDE ENABLED
1 = PORT 2 SIDE ENABLE HANDSHAKE
·THIS REGISTER READS ALL
O'S FROM PORT 2 SIDE
Address: 1010
(Read/Write)
I D7 I D6 I D5 I D4 I D3 I D2 I DI I Do I
o~ PORT 1510E CONTROL S
1 = PORT 2 SIDE CONTROLS '
CLEARJ·I I I 1 I Lpo RT 2SlOE-INPUT LINE· (PIN 33)"
PORT 2 SIDE-OUTPUT LINE (PIN 32)··
0= CLEAR FIFO BUFFER NOT USED (MUST BE PROGRAMMED 0)
0= PORT 1 SIDE CONTROLS PORT 2 SIDE-OUTPUT LINE (PIN 30)··
1 = PORT 2 SIDE CONTROLS DATA DIRECTION BIT
1 = INPUT TO CPU
0= OUTPUT FROM CPU
• READ-ONL Y BITS
··ONLY WHEN PORT 2 IS AN I/O PORT
392
ZS03S/ZS03SA FlO Input/Output Interface Unit LHS03S/LHS03SA
• Interrupt Status Register 0

Address: 0010 (Read/Write)
I D7 ID6 I D5 I D4 I D3 I D2 I DJ I Do I
MESSAGE INTERRUPT UNDER SERVICE (IUS}j
MESSAGE INTERRUPT ENABLE (IE) :
II
•
[ NOT USED
(MUST BE PROGRAMMED 0)
MESSAGE INTERRUPT PENDING (IP): :
IUS, IE, AND IP ARE WRITTEN USIN
THE FOLLOWING COMMAND: GI I I
NULL CODE 0 0 0
CLEAR IP & IUS 0 0 1
SET IUS 0 1 0
CLEAR IUS 0 1 1
SET IP 1 0 0
CLEARIP 1 0 1
SET IE 1 1 0
CLEAR IE 1 1 1

I D7 I D6 1 D5 1 D41 D31 D21 DJ 1 Do I

DATA "''''''ON
UNDER C~NGE
'NTER'"",.J:
SERVI<::E (IUS)
DATA DIRECTION CHANGE INTERRUPT '
I I I I I I L, ~ PATTERN NATC' FLAG·
PATTERN MATCH INTERRUPT
• PENDING (I P)
ENABLE (IE) : : : PATTERN MATCH INTERRUPT
DATA DIRECTION CHANGE INTERRUPT: : , :: ENABLED IE)
PENDING (Ip) NOT USED: : : .' PATTARN MATCH INTERRUPT
I~
(MUST BE PROGRAMMED 0 ) UNDER SERVICE (IUS)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE
I
0
I I
0 0 0
II 0 0
US, IE, AND IP ARE WRITTEN USING
HE FOLLOWING ,COMMAND:
NULL CODE
CLEAR IP & IUS 0 0 1 0 0 1 CLEAR IP & IUS
SET IUS 0 1 0 0 1 0 SET IUS
CLEAR IUS 0 1 1 0 1 1 CLEAR IUS
SET IP 1 0 0 1 0 0 SET IP
CLEARIP 1 0 1 1 0 1 CLEAR IP
SET IE 1 1 0 1 1 0 SET IE
CLEAR IE 1 1 1 1 1 1 CLEAR IE
*READ-ONL Y BITS
393
Z8038/Z8038A FIO.lnput/Output Interface Unit .. LH8038/LH8038A

~tdJ lliER~
BYTE COUNT COMPARE INTERRUPT UNDER
SERVICE (IUS ) , . UNDERFLOW ERROR·
BYTE COUNT COMPARE INTERRUPT ENABLE (IE); : OR INTERRUPT PENDING (ID)
.
BYTE COUNT COMPARE INTERRUPT PENDING (IP): : , ' : ERR OR INTERRUPT ENABLED (IE)
I t t~~~
OVERFLOW ERROR ,I : : R INTERRUPT UNDER SERVICE (IUS)
IUS,IE,AND IP ARE WRITTEN USIN E,AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND: GI FOLLOWING COMMAND:
I I
NULL CODE 0 0 0 0 0 0 NU LL CODE
CLEAR IP & IUS 0 0 1 0 0 1 CL EAR IP & IUS
SET IUS 0 1 0 0 1 0 SE T IUS
CLEAR IUS 0 1 1 0 1 1 CL EAR IUS
SET IP 1 0 0 1 0 0 SE TIP
CLEARIP 1 0 1 1 0 1 CL EARIP
SET IE 1 1 0 1 1 0 SE TIE
CLEAR IE 1 1 1 1 1 1 CL EARlE
·READ-ONLY BITS

I D7 I Ds I D5 I D. r D3 I D2 I Dl I Do I
FUll mTERRDPr ~ER
SERVICE
FULL INTERRUPT ENABLE (IE);
IIUSl~ IIIIIL
: :
LBUFFER EMPTY·
EMPTY INTERRUPT PENDING (IP)
FULL INTERRUPT PENDING (IP): :, . , : EMPTY INTERRUPT ENABLE (IE)
. BUFFER FULL": :: :: EMPTY INTERRUPT UNDER SERVICE (IUS)
IUS, IE, AND IP ARE WRITTEN USI
THE FOLLOWING COMMAND ~GI I I I I I
IUS,IE,AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE 0 0 0 0 0 0 NULL CODE
CLEAR IP & IUS 0 0 1 0 0 1. CLEAR IP & IUS
SET IUS 0 1 0 0 1 0 SET IUS
CLEAR IUS 0 1 1 0 1 1 CLEAR IUS
SET IP 1 0 0 1 0 0 SET IP
CLARIP 1 0 1 1 0 1 CLEARIP
SET IE 1 1 0 1 1 0 SETIE
CLEAR IE 1 1 1 1 1 1 CLEAR IE
·READ-ONLY BITS
394
• Interrupt Vector Register

I D7 I D6 I Ds I D. I D3 I D2 I Dl I Do I
I I I I ~
NOINTERRU PTS PENDING 0 0 0
BU FFER EMPTY 0 0 1
B UFFER FULL 0 1 0
OVER/UNDER FLOW ERROR 0 1 1
VECTOR STATUS
BYTE C OUNT MATCH 1 0 0
PAT TERN MATCH 1 0 1
DATA DIREC TION CHANGE 1 1 0
MAILB OX MESSAGE 1 1 1
• Byte Count Register • Pattern Match Register

Address: 0111 (Read Only) Address: 1101 (Read/Write)
I D7 I D61 Ds I D.I D3 I D2 I Dl I Do I I D7 I D6 I Ds I D. I D31 D2 I Dl I Do I

REFLECTS NUMBER OF BYTES IN BUFFER
I I I I I I I I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER
• Byte Count Comparison Register
Address: 1000 (Read/Write) • Pattern Mask Register
I D7 I D6 I Ds I D, I D3 I D2 I Dl I Do I
I D7 I D6 I Ds I D. I D3 I D, I Dl I Do I
I I I I I I I I
CONTAINS VALUE COMPARED TO BYTE COUNT
REGISTER TO ISSUE INTERRUPTS ON MATCH
I I I I I I I I
IF SET,BITS 0~7 MASK BITS 0~7
(BIT 7 ALWAYS 0.)
IN PATTERN MATCH REGISTER.
MATCH OCCURS WHEN ALL
NON~MASKED BITS AGREE.
• Message Output Register
• Data Buffer Register
I D7 I D6 I Ds I D. I D3 I D2 I Dl I Do I Address: 1111 (Read/Write)
I I I I I I I I
STORES MESSAGE SENT TO MESSAGE
I D7 I D6 I Dsl D. I D3 I D2 I Dl I Do I
IN REGISTER ON OPPOSITE PORT OF FlO
I I II I I I I
CONTAINS THE BYTE TRANSFERRED
• Message Input Register TO OR FROM FIFO BUFFER RAM
Address: 1100 (Read Only)
I D7 I D6 I Ds I D. I D3 I D2 I Dl I Do I
I I I I I I I I
STORES MESSAGE RECEIVED FROM MESSAGE
OUT REGISTER ON OPPOSITE PORT OF CPU
-~------SHARP---------
395
za060FIFO Buffer Unit and Expander LH8060
LH8060 Z8060 FIFO Buffer Unit and ·Expander

• ,.Description • Pin Connections
The LH8060 First-In, First-Out (FIFO) buffer
unit consists of a 128-bit-by-8-bit memory, RFD/DAVA I 0
bidirectional data transfer and handshake logic. The ACKINA 2
structure of the FIFO unit is similar to that of other FULL 3
available buffer units. LH8060 is a general-pur- A B
EMPTY 4
pose unit; its handshake logic is compatible with that·
OEA
of other members of Z8, Z8000 family and Z8500
family.
DOH
DIH
D2B
• Features
1. Bidirectional, asynchronous data transfer capa-
bility
2. Large 128-bit-by-8-bit buffer memory
3. Two-'wire, interlocked handshake protocol GND
4. 3-state data outputs Top Vie.w
5. Wire-ORing of empty and full output for sens-
ing of multiple-unit buffers
6. Connects any number of LH8060 in series to
form buffer of any desired length
7. Connects any number of LH8060 in parallel to
form buffer of any desired width
• Block Diagram
128X8
RAM
Buffer
Data Memory I---.J\J Data
Data Bus A Buffer Buffer Data Bus B
A B
Ready-for· Datal
DataAvaiiable
Control
Logic
396
Z8060 FIFO Buffer Unit and Expander LH8060
• Pin Description
Bidirectional
Do -D 7 Data bus Bidirectional data bus.
3-state
Active low.
--- Input handshake indicates that input data is valid; out·
ACKIN Acknowledge input I
put handshake indicates that output data has been reo
ceive by peripherals
Input handshake indicates RFD (active High) : Z-FIFO is
--
RFD/DAV Ready·for·data/data valid 0 ready to receive data. Output handshake indicates DA V
(active low) : Output data is valid.
Active low.
---
CLEAR Clear I When set to low, this line causes all to be cleared from
the FIFO buffer.
This line allows control of the input data direction.
-
DIR AlB Data direction I When high, data is to be inputted through port B, when
low, data is to be intputted through port A.
Active high, open -drain. Indicates that the FIFO buffer
EMPTY Empty 0
is empty
Active high, open -drain. Indicates that the FIFO buffer
FULL Full 0
is full.
Active low.
OE A, when high, causes the bus drive~or port A to
----
OEA,OE B Output enable I float to a high impedance level input. OE B controls the
bus drivers for port B in the same manner as OE A con·
troIs those for port A

Input voltage VIN -0.3-+7 V 1
Output voltage VOUT -0.3-+7 V 1
Storage temperature T~ -65-+150 "C
+SV
+SV
~
2S0pA
From output o----1>--,.,~...
under test
F_ "0'"" 2.2kn
under test o--f
Standerd test load Open-drain test load
r SOPF
'-~-------'--SHARP--'-----~~
397
• DC Characteristics (Vcc=5V±5%, ra=0~+70"C)

Input high voltage VIH 2 Vcc +0.3 V
Output high voltage VOH IOH = -250 f1A 204 V
Output low voltage VOL IOL = + 2mA, IOL = + 3.2mA 004,0.5 V
Input'leakage current 1IlL I OA:S::VIN <2AV 10 p.A
Output leakage current I IOL I OA~VouT<2AV 10 p.A
• Capacitance (f=lMHz, Ta=0-+70"C)

Unmeasurred pins retured
to ground
(1) Input pin , (f=IMHz, Ta=0-+70"C)
Input rise time tr 100 ns
/ Input fall time 100 ns
tf
(2) 2-wire interlocked handshake timing

No. Symbol Parameter MIN. MAX. Unit
1 TsDI (ACK) Data input to ACKIN ~ to setup time ns
2 TdACKf (RFD) . ACKIN ~ to RFD ~ delay 0 ns
3 TdRFDr (ACK) RFD t to ACKIN t delay 0 ns
4 TsDO (DAV) Data out to DA V t set'up time 25 ns
5 TdDAVf (ACK) DA V t ACKIN t delay ns
6 ThDO (ACK) Data out from ACKIN t hold time ns
7 TdACK (DAV) ACKIN t to DA V t delay 0 ns
8 ThDI (RFD) Data input from RFD t hold time 0 ns
9 TdRFDf (ACK) RFD ~ to ACKIN t delay 0 ns
10 TdACKr (RFD) ACKIN t to RFD t delay 0 ns
11 TdDAVr (ACK) DA V t to ACKIN t delay 0 ns
12 TdACKr (DA V) ACKIN t to DA V t delay 0 ns
(Input) ACKIF t to EMPTY t delay,
13 TdACKINf (EMPTY) ns
(Output) ACKIN ~ to EMPTY ~ delay
(Input) ACKIN t to FULL t delay,
14 TdACKINf (FULL) ns
(Output) ACKIN ~ to FULL t delay
15 ACKIN Clock Rate (Input or Output) 1.0 MHz
16 TdACKINf (DAVQ ACKIN t to DA V ~ delay ns
17 TwCLR CLEAR "Low" hold.tiine to reset Z-FIFO 700 ns
18 TdOE (DO) OE ~ to data bus driven delay 0 ns
19 TdOE (DRZ) OE t to data bus float delay ns
Note: All timing references assume 2.0 V for a logic 1 and 0.8 V for a logic 0
398
DATA
RFD
EMPTY
FULL
Input timing
DATA
EMPTY
FULL
Output timing
DAV
Time from ACKIN! to DAV !
CLEAR
INPUT \11"-------_®_....JI}/
OE
DATA OUT
Output enable and clear
.-.-.-.--.-.-..--SHARP -..-...----------
399
Z8060:FIFO Buffer Unit and Expander LH8060
• Interlocked 2-Wire Handshake This contorol feature allows the LH8060, with
no external logic, to directly interface with port of:
The LH8060 uses interlocked handshake opera- eZ8 '
tions for data trasfer. In interlocked handshake op-
eZ-CIO
eration, the action must be acknowledged by the
ez-uPC
other half of the handshake before the nextactton
eZ-FIO
can occur. The following describs the handshake
e Another FIFO
timing in input and output modes.
(1) Input mode ,.
In an Input Handshake mode, RFD (output) and •. Resetting and Clearing the FI FO
ACKIN (input) are used as the handshake control
The CLEAR input signal is used to reset and clear
lines. Unless the FIFO buffer is full, RFD is set
the LH8060 FIFO. A Low level on this input clears
High and signals to the peripherals involved that
all data from the FIFO buffer and disallows any
the FIFO buffer is ready to receive data. When the
data transfer.
acknowledge signal ACKIN from the external de-
vice is set Low, the LH8060 takes the input data
into the buffer and sets RFD Low to signal to the • Bidirectional Transfer Control
peripherals that the input signal has been received.
The LH8060 has bidirectional data transfer
This process is repeated until the FIFO is full,
capability ~nder control of the DIR AlB input.
RFD is kept low.
When DIR AlB is set Low, data transfers are made
from Port A to Port B.
DATA IN =x Valid data X:::==::XValid dataL
Setting DIR AlB High reverses the handshake
assignments and the direction of transfer.
ACKIN-
Table 1 Bidirectional control function table
RFD
- Port A Port B
DIR AlB transfer
Fig. 1 2-wire interlocked handshake timing handshake handshake
(input) 0 Input Output A to B
1 Output Input Bto A
DATA OUTJ Valid data C=X:Valid data><=:: • Empty and Full Operation
ACKIN The EMPTY and FULL. output lines can be
wire-ORed with the EMPTY and FULL lines of
DAV--"""""' - -_ _oJ other LH8060s and LH8038s. This capability en-
ables the user to determine the emptylfull status of
Fig. 2 2-wire interlocked handshake timing a buffer consisting of multiple FIFOs, FIOs, or a
(output) combination of both.
• Interconnection EXl;I.mple
(2) Output mode
Fig. 3 illustrates a simplified block diagram
~,output handshake mode, DA V (output) and
showing the manner iIi which LH8060s can be in-
ACKIN are used as the control lines. If the LH8060 terconnected to extend an LH8038 buffer.
has data in the FIFO buffer and if ACKIN is high
(indicating that the external device is ready to re- Table 2 Signals EMPTY and FULL operation
ceive data), it sets DA V Low to signal to the exter- table
nal device that the output data is available.
.When the external device sets ACKIN low to indi- Number of
EMPTY FULL
cate that it has received the data, LH8060 sets bytes in. FIFO
DA V back to a high level. In response, the external 0 High Low
device sets ACKIN high to request the LH8060 for 1-127 Low Low
the next data. This process repeats till the FIFO 128 Low High
buffer becomes empty. when it becomes empty,
DAVis kept high.
----....-~.-.---.---SHARP,-.-.-.- ......... - - - - - - - -
400.
• Output Enable Operation Table 3 Output control function table

The FIFO provides a separate Output Enable DIR AlB DEA DEA Function
(OE) signal for each port of the buffer. An OE out-
Disable port A output
put is valid only when its port is in the Output 0 X 0
Enable port B output .
Handshake mode. The control of this output func-
tion is sh~n in Table 3-Signal OE operates with 0 X 1
Enable port B output
lines DIR AlB.
Enable port A output
1 0 X
Disable port B output
1 1 X
Disable port B output
Note: X=Don't care
FULL SYSTEM FULL
EMPTY SYSTEM EMPTY

DATA I DATA BUS
I
A BUS"
EMPTY FULL EMPTY FULL
PORT 2
of
Z8038
V
1'\
-
"-
v/
K
~ '"
/
K=> DATA BUS
LH8060 LH8060
FIFO FIFO
--- -- ---
R FD/DAV ACKINA RFD/DAVB ACKINA RFD/DAVs
-
HANDSHAKE
} SIGNALS
ACKIN RFD/DAVA ACKINB RFD/DAVA ACKINs
OE
Dr OEA
CLEAR
1
DIR AlB
OEB
nr OEA
CLEAR
1
DIR AlB
OEB OUTPUT CONTROL
CLEAR SYSTEM CLEAR
DA TA DIR SYSTEM DIRECTION
Fig. 3 Connection diagram
401
Serial Parallel Combination Controller LH8071
LH8071 Serial Parallel Combination Controller
• Description' • Pin Connections

The LH8071 (SPCC71) is a peripheral device for
general purpose microcomputers, with control RxD
functions for RS232C interface and Centronics in- o TxD
terface, within a single LSI chip.
DTR
The LH8071 pr<;>vides a serial port for transfer-
CTS
ring data in asynchronous mode and also an 8-bit
parallel port with handshaking function as a Cen- DCD
tronics interface. RTS
The LH8071 has 24 commands for controlling SLCT
these ports. The commands not only control the op- INPUT PRIME
eration of RS232C terminal units and printers, but
handle various utilities (e.g., code conversion) neces- FAULT
sary for these units. Accordingly, the CPU needs
ACKNLG
. merely to specify an operation through the com-
WAIT DATA STROBE
mand, thus significantly reducing the CPU's load in
handling 110 units through the program, and even- AD7 DATAs
tually reducing the amount of memory needed for AD6 DATA7
storing the program. AD5 DATA6
The LH8071 controls the peripheral unit control AD. DATA5
lines (e.g., RTS and CTS of RS232C interface) AD3 DATA.
according to the status of the units, instead of by
AD2 DATA3
software control from the CPU. Consequently, the
ADI DATA2
system designer can configure the interface merely
by connecting buffer devices and connectors. ADo DATAl
In conclusion, the LH8071 not only easily imple- Top View
ments the RS232C interface and Centronics inter-
face, but achieves superior performance and space
reduction.
• Features
1. Asynchronous data transfer serial port 5. 128-byte data transfer buffer
• RS232C interface can easily' be realized • Useful for the serial port and parallel port
• Programmable data: format and Baud rate 6. Z-bus interface
2. Printer control parallel port , 7. 40-pin dual-in-line package
• Centronics interface can easily be realized 8. Single + 5V power supply
3. Data transfer and conversion functions by com-
mand
• 24 commands
4. Data conversion function
• Serial-parallel conversion
• Binary-ASCII conversion
• Intel hex, format acceptable for data input!
output
402
• Block Diagram
Address! Data Bus Data Bus
"'"
·2
o
!;
Address Strobe 9 Internal
Control Logic u"
'"
Interruput Request 5 Buffer

Interruput Acknow ledge 6 128
Interruput Enable In 4 Bytes
Interruput Enable Out 3
-~----"'-'---SHARP'-'---'---'----
403
Seriat Parallel 'Combination Controller LH8071
• Pin Description
AD o -AD 7 Bidirectional Multiplexedsystem address/data bus as address.

Address/ data bus
3 state
- Active low. Fetch iiiformation on address/data bus as
AS Address strobe I
address.
- Active low. Transact information on address/data bus
DS Data strobe I
as data.
High at reading. Output contents of internal register
-
R/W Read/write I onto address/data bus; Low at writing. Fetch data on
address/ data bus.
CS Chip select I Active low. Chip selection signal
WAIT Wait a Active low, open-drain. Used to synchronize with CPU.
-- Active low, open-drain. Indicate interrupt request to
INT Interrupt request a CPU.
INTACK Interrupt acknowledge I Active low. Indicate interrupt acknowledge cycle.
lEO Interrupt enable output a Active high. Used to form daisy chain.
DATAI-DATA g Output data a Output data
DATA STROBE Data strobe a Active low. Indicate settlement of data.
BUSY Busy I Active high. Indicate printer in operation.
ACKNLG Acknowledge I Active high. Acknowledge signal from printer.
FAULT Fault I Active low. Indicate printer inoperable.
INPUT PRIME Prime input a Active low. Printer initializing signal.
SLCT Select I Active low. Printer selection signal.
RxD Recei ved data I Receiving data line.
TxD Transmitted data a Transmitting data line.
RTS Transmission request a Active low. Indicate readiness for data transmission.
CTS Transmission enable I Active low. Indicate data transmission is possible.
DTR Data terminal ready a Active low. Data transmission request signal.
DCD Reception enable I Active low. Indicate data reception is possible.
PCLK Clock I Single-phase clock, need not be same as CPU clock.

Input voltage * V IN -0.3-+7 V
Output voltage * VOliT -0.3-+7 V
* The maximum applicable voltage on any pin except for VBB with respect to GND.
+5V
2.2kO
Output terminal o---1~....

under test
"""I--"
Standard tellt load
- - - - - - - - - - - - - - - - - - - - - S H A R P - . . . . - , - ........ . - . - - - - -
404
·Serial Parallel Combination Controller LH8071
• DC Characteristics (Vcc=5V±5%. Ta=0-+70"C)

Clock input high voltage VCH 2.4 Vcc V
Input high voltage VIH 2 Vcc V
Output high voltage VOH 10H= -250 pA 2.4 V
Output low voltage VOL 10L =2mA 0.4 V
Input leakage current I IlL I 0:5::V IN :5::5.25V 10 pA
Output leakage current I 10L I 0~VIN~5.25V 10 pA
(1) CPU interface timing (Vcc=5V±5%. Ta=0-+70"C)
No. Symbol Parameter MIN. MAX. Unit Note
1 TrC Clock rise time 20 ns
2 TwCh DSClock pulse high width 105 ns
3 TfC Clock fall time 20 ns
4 TwCl Clock pulse low width 105 ns
5 TpC Clock period 250 ns
6 TsCS(AS) CS setup time to AS t 0 ns 1
7 ThCS(AS) CS hold time from AS t 60 ns 1
8 TsA(AS) Address setup time to AS t 30 ns 1 51~
I~
9
10
ThA(AS)
TwAS
Address hold time from AS t
AS low pulse width
50
70
ns
ns
1
-
Delay time from OS t to invalid
11 TdDS(DR) 0 ns
readout data
Delay time from DS t to readout
12 TdDS(DRz) 70 ns 2
data floating
13 TdAS(DS) Delay time from AS t to OS ~ 60 2095 ns
14 TdDS(AS) Delay time from OS t to AS ~ 50 ns
15 ThDW(DS) Written data hold time from OS t 30 ns 1
Delay time from OS ~ to readout
16 TdDS(DR) ns 3
data settlement
17 TdAz(DS) Delay time from address floating to DS ! 0 ns
18 TwOS OS low pulse width 390 ns
19 TsRWR(DS) R/W high (read) setup time to OS ~ 100 ns
20 TsRWW(OS) R/W low (write) setup time to OS ! 0 ns
21 TsDW(OSf) Written data setup time to OS l 30 ns
22 TdAS(W) Delay time from AS t to WAIT ! 1.95 ns
23 ThWR(OS) R/W hold time from OS t 60 ns
24 TsDR(W) Time from valid readout data to WAIT t 0 ns
t indicates rising edge. ~ indicates falling edge. The reference voltage levels for timing measurement are 2.0 volts for
'high'; O.S volts for 'low'.
Note 1: This does not apply to the interrupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not apply to the interrupt acknowledge operation,
Note 3: The delay time depends on the status of LHS071 at the time of access by CPU.
405
I I
Serial Parallel Combination Controller L:.H8071
PCLK
ADo-AD7
CPU (read)
AS
R/W
(write)
R/W
(read)
ADo-AD7
CPU (write) ----.....f"l-t~..;...",,-~).---~=_+_----...:f,-
CPU interface timing

25 TsIA(AS) INT ACK setup time to AS t 0 ns
26 ThIA(AS) INT ACK low hold time from AS t 250 ns
Delay time from AS t to DS ~
27 TdAS(DSA) 940 ns
(acknowledge)
Delay time from DS ~ (acknowledge)
28 TdDSA(DR) 360 ns
to vector settlement
29 TwDSA DS (acknowledge) low pulse width 475 ns
30 TdAS(IEO) Delay time from AS t to lEO 290 ns
31 TdIEIf(IEO) Delay time from IEI to lEO 120 ns
32 TsIEI(DSA) lEI setup time to DS ~ (acknowledge) 150 ns
33 TdDS(INT) Delay time from DS ~ to INT 500 ns
34 ThIEI(DS) lEI hold time from DS t 100 ns
---'-~~------SHARP----'-----'---
406
(3) Reset timing

Delay time from DS t
35 TdRDQ(AS) - 40 ns
(for suppressing reset) to AS ~
Delay time from AS t
36 TdWRQ(DS) 50 ns
(for suppressing reset) to DS ~
Minimum low width of AS and DS
37 TwRES 250 ns 4
(for setting)
Note 4: The internal reset signal lags by 112 to 2 clocks behind external reset conditions.
Reset timing
(4) Serial port timing

Delay time from sending clock transition
38 TdTxC(TxD) 19000 ns 5
to output data transition
Note 5: Applies to all baud rates (110-9800 B) serial port timing
TxC /
TxD
Serial port timing
(5) Parallel port timing

39 TdACK(D) Time from ACKNLG ~ to data output 13000 18000 ns
Time from data output to
40 TdD(DSTR) 6000 ns
DATA STROBE ~
41 TwDSTR DATA STROBE pulse width 6000 ns
ACKNLG
DATAl
\
. DATAs
DATA STROBK
Parallel port timing
----------SHARP--.--------~
407
Sericil Parallel Combination Controller LH8071
• Registers Table 1 Register adpress

The LH8071 has the following registers which Register Register address Register Register address
can be accessed externally (from CPU). DSCO X XOOOOOX DSC5 XX00101X
e Master interrupt control register (MIC) DSC1 X X00001 X DSC8 X X01000X
e Data indirect address register (DIND) DSC2 X XOO010X DIND X X10101X
eData status command registers (DSCO, DSCl, DSC3 XXOOO11X MIC X X11110X
DSC2, DSC3, DSC4, DSC5 and DSC8) DSC4 X ):(00100 X
Table 1 shows the register addresses assigned to Note: A15- A6 is decoded and applied to cs, so that the location in
these registers. the input/output address space is determined. Bits marked by 'x'
The master interrupt control register (MIC) is are underfined.
used to control the interrupt operation (see Fig. 2).
Writing into the MIC register falls into two
groups.
Group 2 uses the write code shown in Table 2.
DSC31 D71 D6 I D51 D41 D31 D21 D1 I Dol

-~-~-~-~ [ Co 1 Buffer area over
1 0 Input characters are other than 0-F
(Intel format only) ,
1 1 Check - sum error
, 0 1 Printer not select
1 0 Printer paper empty
(requires external circuit)
1 1 Printer fault
L -_ _ _ _ _ _ _ Transter error
' - - - - - - - - - - Limit error
' - - - - - - - - - - - - Parity error
'---------~----Illegal command
Fig. 1 Error flag (DSC3)
MIC I IE I IUS I IP I IDLC I ICST I
TTT _
T ~Command execution start
Lower chaining prohibited
' - - - - - - - - - - - Interrupt holding
' - - - - - - - - - - - - - Interrupt under service
Interrupt enabled
Fi'g. 2 Master interrupt control register
Table 2 MIC register write code

Group 2 Group 1
Function
D7 D6 D5 D2 Do
0 0 0 X X Writing to Do and D2
0 0 1 0 0 Reset IP (D5) and IUS (D6)
0 1 0 0 0 Set IUS (D6)
I
,0 1 1 0 0 Reset IUS (D6)
1 0 0 0 0 Set IP (D5)
1 0 1 0 0 Reset IP (D5)
1 1 0 0 0 Set IE (D7)
1 1 1 0 0 Reset IE (D7)
408
• Programming
Use the registers, DSCO, DSCl, DSC2, DSC3,
°
mand. Command is used in specifying serial data
format using DSC2 (Fig. 3).
DSC4, DSC5, and DSC8, to specify operation mode. The result of command execution is indicated on
The 24 types of commands are made valid by first DSCO and DSC3. DSC3 indicates error status as
writing a value corresponding to the desired com· show in Fig. 1. DSC8 is used as a buffer register
mand number into DSCO, then setting the CST bit after command 22 or 23 is executed.
on MIC. The registers DSCl, DSC2, DSC4, and Tables 3 and 4 show command functions versus
DSC5 are used to specify parameters for each com- registers.
OSC2
-,---,
1
I 07 I 061 051 041 031 021 OJ I 00 I
LPu'"m'"
o : even parity
1 : odd parity
Number of data bits
o : 7 bits
1 : 8 bits
' - - - - - - - B a u d rate (see Note)
o 0 0 : nOB
o 0 1 : 150 B
010:300B
011:600B
1 0 0 : 1200B
lOl:2400B
110:4800B
111:9600B
Number of stop bits of transmission
L -_ _ _ _ _ _ _ _ _
o : 1 stop bit
1 : 2 stop bit
L -_ _ _ _ _ _ _ _ _ _ _ Interrupt mode
o : Interrupt enabled
1 : Interrupt disabled
L -_ _ _ _ _ _ _ _ _ _ _ _ Echo back
Note: Baud rate at PCLK = 4.0MHz o : Echo back mode
1 : Echo back disable
Fig. 3 Serial data format (DSC2)
.-----.---~--SHARP.-..-..-~.----
409
Table 3 Command function and writing register contents
~
Code Parameter
. Function Remarks
Cornman DSCO DSCI DSC2 DSC4 DSC5
Transfer Sepcify transfer format .
0 OOH format and and operating mode.
operating mode
Output serial-input data Stop character is
Stop
1 01 H to Centronics printer until specified by DSC2.
character
the stop character arrives
Output seriaI-input data Operation stops
Number of
2 02 H to Centronics printer. upon detection of
putput byte
Control C (hex 03).
Output buffer area Address information
Number of Load address Load address
3 03 H contents to serial port of data is appended.
putput byte high order byte (low order byte)
in Intel format.
Read Intel format data on \
4 04 H serial port and store in
buffer area.
Number of Initialize block transfer
5 05 H bytes of between master CPU and
block transfer buffer
Output Output data in buffer area Operation stops
Number of
6 06 H starting via serial port. upon detection of
putput byte!
address Control C (hex 03).
Output Output data in buffer area Operation stops
Number of
7 07 H starting to printer. upon detection
putput byte! -,
address of Control C (hex
.".
03).
Output Convert binary data in
Number of
8 08 H starting buffer area into ASCII and
output byte!
address area.
Output Display Display Convert binary data in Address information
Number of
9 09 H starting address address buffer area into ASCII and of data is appended.
output byte!
address (High order) (Low order) output via serial port.
Output Convert binary data in
Number of
10 OA H starting buffer area into ASCII,
output byte!
address and output to printer.
Number of Output Display Display Convert binary data in Address information
11 OB H output byte starting address address buffer area into ASCII, of data is appended.
address (High order) (Low order) and output to printer.
Read ASCII data on serial
Number of Output
12 OCH port, and store in buffer
input bytes character
area.
Read Intel format data on Used when reader is
13 OD H serial port and store in connected to serial
buffer area. port.
Read ASCII data on serial After CR reception,
Output port until arrival of CR CR and LF codes are
14 OE H
character eode. sent out via
serial port.
Convert data in buffer Used when a pun-
Number of Load Load
15 OFH area into Intel format and cher is connected to
putput byte! address address
output via serial port. serial port.
- - - - . - . . . - - - - - - ! ? H A R P .-~-------------
410
~
Code Parameter
Function Remarks
Comman DSCO DSCI DSC2 DSC4 DSC5
Read binary data on serial Used when a reader
Number of Output
16 10 H port into buffer area for is connected to serial
input bytes character
storage. port.
Output data in buffer Used when a puncher
Output area via serial ports. is connected to serial
Number of
17 llH starting port. Operation stops
putput bytes
address upon detection of
hex 03.
Output null codes via 256 null codes
18 12H
serial port. outputted.
Output EOF in Intel
19 13 H format ( :OOOOOOOlFF)
via serial port.
Output null codes via Used when a puncher
20 14H serial port. is connected to serial
port.
Output EOF in Intel Used when a puncher
21 15 H format ( :OOOOOOOlFF) is connected to serial
via serial port. port.
Read I-byte data on serial Data is stored in
22 16 H
port. DSC8.
.,
Output data written in Data needs to be set
DSC8 by CPU via serial in DSC8 prior to ex-
23 17H
port. ecution (high order
byte)
--------------SHARP .---------------..
411
Table 4 Register contents after command execution (readout register)

Code Parameter
'S
Command
0
1*
OOH
DSCO
2*
80 H
3*
C;OH
DSCI DSC2
Error
DSC3
status flag
DSC4 DSC5
1 01 H 81H CI H Error status Hag

2 02 H 82H C2 H Error status flag
3 03 H 83 H C3 H Error status flag
Number of inputted Load address Load address
bytes pluse hex 20 (High order byte) (Low order byte)
5 05 H . S5 H C5 H Error status flag
6 06 H 86 H C6H Error status flag
8 08 H 88 H C8 H Error status fl'ag
10 OA H 8AH CA H Error status flag
11 OB H 8B H CB H Error status flag
12 OC H 8C H CC H Error status flag
Number of inputted Load address Load Adress
13 OD H 8D H CD H Error status flag
bytes plus hex 20 (High order byte) (Low order byte)
Number of inputteq
14 OE H 8E H CE H Error status flag
byte pulse hex 20
15 OF H 8F H CF H Error status flag
16 10 H 90 H DOH Error status flag
17 llH 91H DIH Error status flag
18 12H 92Ii D2H Error status flag
19 13 H 93 H D3 H Error status flag
20 14H 94 H D4H Error status flag
23 17H 97 11 D7H Error status flag
Note 1 1*: V,alue before command execution (command code value)
2*: Value upon normal completion of command execution.
3*: Value upon abnormal completion (error) of command execution.
These are common to all commands. .
Note 2 For error status flag value, see Fig. l.
Note 3 If FAULT input becomes low (printer error) during command execution, LH8071 suspends operation until FAULT returns to high
(error recovery). At this time, DSCO has bit 6 set and bit 7 reset.
412

The LH80n (SPCCn) is a peripheral device for
general purpose microcomputer systems to perform RxD
asynchronous serial data transfers and control of o TxD
Centronics compatible printers.
DTR
It supports full duplex asynchronous serial data
CTS
transfers. The transfer conditions such as the baud
rate and character length can be set by the DCD
program. Further, it is equipped with a control I/O INTACK 6 RTS
terminal for simple organization of the various types DS NC
of modem interfaces. The Receive Buffer has a dou- R/W INPUT PRIME
ble buffer structure so that the master CPU can easi- AS BUSY
ly perform reading and writing of data.
CS FAULT
A printer control I/O terminal is available for
GND ACKNLG
easy connection to any printer which is Centronics
compatible. A handshake line and control for WAIT DATA STROBE
other I/O lines is supported. A 128-byte printer AD, DATA,
data buffer memory having an FIFO structure is AD6 DATA,
provided within the LH80n. Efficient use of the AD; DATA"
printer unit by the master CPU is made possible AD, DATA"
with this buffer. AD3 DATA.
In this way, the LH80n peripheral device for
AD, DATA:.
Z8000 family, was developed to efficiently perform
AD! DATA,
serial data transfer and printer output control
within a compact pacil:age. It is suitable for use in ADo DATA.
small systems such as personal computers which Top View
use printer units, RS232C terminal units and mod-
em units.
• Features · Furnishes printer interface signals compati-

ble with Centronics specifications
1. Asynchronous Full Duplex Data Transfer
· Built-in handshake function for data output
• Character length of 5""8 bits
· Internal buffer: 128-byte FIFO structure
· 1 or 2 stop bits
• Error detection: Printer fault error/Paper
· No parity bit or odd/even parity
empty error
• F.alse start bit or rejection (rejects spike
3. Vector Interrupt
noise in the mark line to prevent malfunc-
· Able to generate an interrupt on various
tion.)
condition such as Transmit Buffer empty,
• Full duplex
validity of received character, and printer
• Transmit buffer has double buffer structure.
Output Buffer empty.
• Receive buffer has FIFO structure.
• Interrupt vectors for Transmit, Receive,
• Error detection function, Parity error detec-
Printer and Error detection can be set indi-
tion, Framing error detection, and Overrun
vidually.
error detection
· Baud rates: 75, 110, 150,300,600,1200,
5. Z-bus interface
2400, 4800 baud selectable
2. Centronics Compatible Printer Control
..-.-----.--....-SHARP-------·-.-~--
413
• Block Diagram
Data Bus Internal

Address! Data Bus Control Logic Data Bus
Interface
ERR
MSR
CTL-
Address Strobe 9
Data Strobe 7 TxS
Print RxS
Chip Select 10 FIFO
Read!Write 8 PRS
128 Bytes
Wait 12 TxB
RxB
PRB
Interrupt Request
Interrupt Acknowledge 6
Interrupt Enable In
---------SHARP -.....---....-.~----.-
414
• Pin Description
Pin Signal 110 Function
Bidirectional
ADo-AD? Address/ data blls 3-state Multiplexed system address/data bus
- Active low. Fetch information on address/data bus as
AS Address strobe I
address.
DS Data strobe I -
as data.
High at reading. Output contents of internal register
-
R/W Read /write I onto address/data bus; Low at writing. Fetch data on
address/data bus.
WAIT wait 0 Active low, open·drain. Used to synchronize with CPU.
- Active low, open-drain. Indicate interrupt request to
INT Interrupt request 0
. CPU.
Active high. Used to form interupt priority arbitration
lEO Interrupt enable output 0 Active high. Used to form daisy chain.
DATAI-DATA s Output data 0 Output data
DATA STROBE Data strobe 0 Active low. Indicate settlement of data.
INPUT PRIME Prime input 0 Active low. Printer initializing signal.
RxD Receivived data I Receiving data line.
TxD Transmitted data 0 Transmitting data line.
RTS Transmission request 0 Active low. Indicate readiness for data transmission.
DTR Data terminal ready 0 Active low. Data transmission request signal.
PCLK Clock I Signal·phase clock; need not be same as CPU clock.

Parameter Symbol Ratings Unit +5V
Input voltage * VIN -0.3-+0.7 V
Output voltage * VOUT -0.3-+0.7 V
Operating temperature 0-+70 t 2.2kO
Topr
Storage temperature Tst~ -65-+150 t
Output terminal o---+--~r-MI--'"
*The maximum applicable voltage on any pin with respect to GND. under test
Standard test load
415
/
Serial Parallel Combination Controller tH8072
• DC Characteristics (Vee=5V±5%, Ta=0-+70"C)
Parometer Symbol Condition, MIN. MAX. Unit Note

Input high voltage, VlH 2.0 Vee V
Output high voltage VOH IoH =-250 pA 2.4 V
Output low voltage VOL IOL=+2.0mA 0.4 V
Input leakage current I IlL I 0~VIN~5.25V 10 pA
Output leakage current I IOL I , 0~VIN~5.25V 10 pA
Current consumption Icc 250 mA
(1) 'CPU interface timing
2 TwCh Clock pulse width, high 105 ns
4 TwCI Clock pulse width, low 105 ns
5 TpC Clock period , 250 ns
6 TsCS (AS) / CS setup time to AS t 0 ns, 1
7 ThCS (AS) CS hold time from AS t 60 ns 1
8 TsA (AS) Address setup time to AS t 30 ns 1
9 ThA (AS) Address hold time from AS t 50 ns 1
10 TwAS AS low pulse width 70 fiS
Delay time from DS t to invalid
11 TdDS (DR) 0 ns
readout data
12 TdDS (DRz) 70 ns 2
data fioating
i3 TdAS (DS) Delay time from AS t to DS ! 60 2095 ns
14 TdDS (AS) Delay time from DS t to AS !, 50 fiS
15 ThDW (DS) Written data hold time from DS t 30 ns 1
I
Delay time from DS ! to readout
16 TdDS (DR) 3
data settlement
17 TdAz (DS) Delay time from address floating to DS 0 ns
18 TwDS DS low pulse width 390 ns
19 TsRWR (DS) R/W high (read) setup time to DS ! 100 ns
20 TsRWW (DS) R/W low (write) setup time to DS ! , 0 ns
21 TsDW (DSf) Written data setup time to DS ! 30 ns
22 TdAS (W) Delay time from AS t to WAIT ! 195 ns
23 ThRW (DS) R/W hold time from DS t 60 ns
24 TsDR (W) Time from vaild readout data to WAIT 0 ns
f indicates rising edge, ! indicates falling edge. The reference voltage levels for timing measurement are 2.0 volts
'high' ; 0:8 volt for 'low'.
Note1: This does not apply to the interupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not apply to the interrUpt acknowledge operation.
Note 3: The 'delay time depends on the status of LH8072 at the time of access by CPU.
. . . - - - - - - - - - - - - - - - - S H A R P - - - - - - - - - - - - - ..........- -
416
PCLK
ADo-AD7
CPU (read)
DS
R/W
(write)
R/W
(read) _ _ _---::,---++-_--'
ADo-AD7
CPU (write)

25 TsIA (AS) INT ACK setup time to AS t 0 ns
26 ThIA (AS) INT ACK low hold time from AS t 250 ns
Delay time from AS t to DS ~
27 TdAS (DSA) 940 ns
(acknowledge)
Delay time from D~ ~
28 TdDSA (DR) 360 ns
(acknowledgge) to vector settlement
29 TwDSA DS (acknowledgge) low pulse width 475 ns
30 TdAS (lEO) Delay time from AS t to lEO 290 ns
31 TdIElf (lEO) Delay time from lEI to lEO 120 ns
32 TsIEI (DSA) lEI setup time to DS ~ (acknowledge) 150 ns
33 TdDS (INT)· Delay time from DS ~ to INT 500 ns
34 ThlEI (DS) lEI hold time from DS t 100 ns
-'-~~-~--SHARP'--'-"-'-------
417

Delay time from sending clock transition
38 TdTxC (TxD) 35000 ns 4
to output data transistion
Note 4:· Applies to all baud rates (75-4800 B)
TxC /
TxD
Serial port timing

39 TaACK (D) Time from ACKNLG l to data output 24000 ns
Time from data output to
40 TdD (DSTR) 6500 ns ,
DATA STROBE l
41 TwDSTR DAT A STROBE pulse width 6500 ns
AKCNLG \
DATAl
I
DATAs
DATA STROBE
• Registers Table 1 Register input/output address

The LH80n uses 64 bytes in the system input! Address Register
output address space. Within this area, 14 bytes X XOOOOOX Error status register(ERR)
are assigned to the I-byte registers (including data XXOOO01X Mode setting register (MSR)
buffer, status, register, control register, etc.) which X XOO010X Control register (CTL)
can directly be accessed by master CPU. X XOOOllX Transmission status register (TxS)
Table 1 lists the registers used for data transac- X X00100X Reception status register (RxS)
tion with the maser CPU and their addresses. XX00101X Printer status register (PRS)
X XOOllOX Transmission buffer (TxB)
XXOOlllX Reception buffer (RxB)
X XOIOOOX Printer buffer (PRB)
Transmission interrupt vector
XXOIOOIX
register (Tx V)
Reception interrupt vector register
X X01010X
(RxV)
Printer interrupt vector register
X XOIOll X
(PRV)
X XOllOOX Error interrupt vector register (ERV)
Master interrupt control register
X X 11l10X
(MIC)
Note: AIs-A6 is decoded and applied to CS, so that the location
in the input/output address space is determined. Bits
marked by 'x' are undefined .
....-.-----------SHARP---------.-.
418
• Programming Note: Registers marked by. can be set or revised even

during the operation of LH8072.
The LH80n has 14 read/write registers which (2) Data inpuVoutput
can be accessed directly by the master CPU. Data transfer between LH80n and CPU is car-
(1) Initialization ried out in accordance with the following proce-
The device is initialized in accordance with the dure.
following procedure. (1) Poll the status registers (transmission, re-
(1) Following power-on reset, or master reset ception and printer status register) and wait
by software, set the mode register is prog- until they become "1". In case interrupt
rammed for character format, baud rate, (transmission, reception and printer inter-
stop bit and parity mode. Subsequently data rupt) is used, interrupt occurs as soon as
required by control register· and interrupt the value of each status register becomes
vector registers· (transmission, reception "I", and polling is not necessary.
and printer error interrupt vector registers) (2) After the status register has been set to "I"
is programmed. (or after interrupt has occurred), begin data
(2) Clear the error status register. transfer via the buffers (transmission, re-
(3) Wait until the data transfer enable bit in the ception and printer buffers).
master interrupt control register is set to (3) Clear the status register. If the above opera-
"I", making the LH80n operable. tion is implemented using an interrupt
In case interrupt is used, the above polling op- routine, the interrupt-under-service (IUS)
eration is unnecessary. When transmission, recep- bit must be reset immediately before the end
tion and printer output become enable, interupt re- of each interupt routine.
quest is forwarded to the master CPU, indicating
that the LH80n has become operable.
I D7 I D61 D5 I D. I D3 I D2 I D, I Do I
II I L~:;:,~= Frammg error
Overrun error
L -_ _ _ _ _ _ _ _ Printer fault
' - - - - - - - - - - - Paper out
' - - - - - - - - - - - - - Unused
' - - - - - - - - - - - - - - - Master reset
Fig. 1 Error status register (ERR)
I D7 I D6 I D5 I D.I D3 I D2 I D, I Do I
0
0
0
0
0
1
0
1
0
mo
1
1
75B
nOB
150B
1
0
1
5
6
7
8
bits / character
bits / character
bits / character
bits / character
0 1 1 300B
1 0 0 600B
1 0 1 1200B
1 1 0 2400B
1 1 1 4800B
Stop-bit-2/Stop-bit -1
Odd -parity/Even -parity
With - parity/Without -parity
Fig. 2 Mode setting register (MSR)
'-~--'------SHARP--'----------~
419
I DrlDGI DsID.1 D31 Dzi DI I Do I I Drl DG I Ds I D.I D31,D21 DI I Do I
~ I"L=~~~, IL-.---,----Reception
. data
~Transmission enabled Fig. 8 Reception buffer (RxB)

Reception enabled
Printer o~tput ,enabled'
'----------Transmission interrupt enabled I Drl D61 Dsl D. I D3 I Dzi DI I Do I
'-----------Reception interrupt enabled
' - - - - - - - - - - - - P r i n t e r interrupt enabled I<------printer output data
Fig. 3 Control register (CTL) Fig. 9 Printer buffer (PRB)
I Dr I DG I Ds I D4 I D3 I Dz I D I I Do I
I I Dr I DGI Ds I D4 I D3 I Dzi DI I Do I
~. --------0
LTransmission buffer empty
I .
L-.---Transmission interrupt vector
Fig. 4 Transmission status register (TxS)
Fig. 10 Transmission Interrupt vector register
I Dr I DGI Dsl D41 D31 Dzi Dd Dol (TxV)
I LReception character valid

'-----0
I Drl D6 I Dsl ~41 D31 Dz I DI I Do'
Fig. 5 Reception status register (RxS)
~1----RecePtion interrupt vector
Fig. 11 Reception interrupt vector register (RxV)
I Dr I D6 I Ds I D41 D31 Dz I DI I Do ,
, I Lprinter buffer empty I Drl D61 Dsl D41 D31 Dzi DI I Dol
~'--------o
I'-----Printer interrupt vector
Fig. 6 Printer status re~ister (PRS) Fig, 12 Printer interrupt register (PRV)
I Dr I D61 Dsl D41 D31 Dzi Dl I Dol I Dr I D61 Dsl D41 D3 I Dz I DI I Do "
L-I------·Transmission data I
'-----~-Error interrupt vector
Fig. 7 Transmission buffer (TxB) Fig. 13 Error interrupt vector register (ERV)
. I D7 I D61 Dsl D41 D31 D2 I DI I Do I ' .

enable(MlE)~
Master interrupt Atreadmg±u I ~L" ',""0 at wrItmg
~ U~defmedat readm,g: ..
Interrupt under service(IUS) I ' . DIsabled lower chaIning (DLC)
. Interrupt pending(IP) :I :' , Data transfer enable ( reading only )
: : : Undefined at reading/"O" at writing
At writing l ! :
0 0 0 Writing to Do, DI, Dz, D3 and D4
0 0 1 Reset IP a~d IUS
0 1 0 Set IUS
0 1 1 Reset IUS
1 0 0 Set IP
1 0 1 Reset IP
1 ' 1 0 Set MIE
1 1 1 Reset MIE
Fig. 14 Master interrupt control register (MIC)
420
General Purpose Interface Bus Controller LH8073
LH8073 General Purpose Interface Bus Controller

The LH8073 (GPIB73) is a microcomputer peri-
pheral device used to control interface buses con-
+5V 1 40 SRQ/REN IN
forming to IEEE Std. 488-1978* (will be termed
PCLK 2 39 REN/SRQ OT
simply "GPIB") The GPIB is used extensively as a
linkage bus between data gathering instrumentation lEO 3
devices and a microcomputer system.

The LH8073 incorporates three functions of lNT 5
talker, listener and controller, all integrated in one lNTACK 6

chip. Using this device, the GPIB interface can be DS 7
provided for various instrumentation equipment, R/W 8
personal computers and office computers.
The LH8073 is applicable to a CPU bus where
address and data are multiplexed. There is a com-
plementary device LH8573 which is applicable for
WAIT 12
a CPU bus where address and data are not multi-
plexed.
*Note : The standard disclosed in IEEE Std.

488-1978 "IEEE Standard Digital Inter-
face for Programmable Instrumentation"
issued by IEEE, U.S.A.
Top View
• Features
1. Built-in talker, listener and controller. Talker
function, listener function and controller func-
tion are integrated in one chip.
2. Built-in buffer memory. Talker or listener can
use 160-byte on-chip buffer.
3. EOI automatic transmission. Upon detection of
the last byte of or EOS in talker mode, EOI sig-
nal is transmitted automatically.
4. EOS automatic detection. Upon reception of
EOS in listener mode, the CPU is informed.
5. Built-in timer. The bus time-out period for
handshaking can be set by the on-chip timer in
the range of 200 p.s -12 ms at 50 p.s interval.
6. Interrupt function. Daisy-chain type interrupt
arbitration facility is provided, allowing vec-
tored interrupt to CPU.
7. Z-bus interface.
421
• Block Diagram
GPm
Da~Bus
Address/ ir
Data Bus I
l IFC IN
IFC OT
Data Strobe SRQ/RENIN
Read/Write' 9 REN/SRQOT
Address Strobe CONTI
Chip Select TE
Wait ATN
DAV
NDAC
NRFD
Interrupt Enable Out 3 EOI
Interrupt Enable In 4 CONT2
Interrupt Request 5
+5V 1
PCLK 2
GND
, ,
--~------SHARP'-''''''-'-'''''''-'---
422
Multi Task Support Processor LH8075
LH8075 Multi Task Support Processor

The LH8075 (MTSP 7 5 ) is the stand alone type
multitask support processor providing multitask P30
capabilities for any simple microcomputer system. a P33
The concept of this multitask processing is similar
to a conventional real time OS (operating system). P27
The devices perform task management (creating, P26
deleting, etc.) independently of the master CPU, and P2s
carry out multi task processing for systems bus INTACK 6 P2.
with arbitrary CPU architectures merely by con- P23
necting to the system bus. P2,
User's programs are scheduled on a priority or
P2l
time-sliced basis. Tasks are switched by an inter-
rupt caused by the LH8075, and commands are P20
given to the LH8075 by writing parameters and P3l
command numbers in the specified register in the WAIT P3,
LH8075. AD7 Pb
AD6 Ph
ADs' Ph
• Features AD. Pl.
AD3 PI:.
1. Task management
· Up to eight tasks can be controlled con- AD, PI.
currently. By using the task creating and de- AD! PIl
leting technique, a maximum of 255 tasks can ADo Plo
be handled. Top View
· Tasks can be controlled on a priority basis by
the assignment of 255 priority levels.
2. Inter-task communication
· Inter-task communication is possible using the
"mail box" provided within the LH8075.
· Inter-task synchronization is possible using
the "mail box".
3. Built-in timer
· Timers with ranges from lOms to 255 hours
can be used for time-sliced processes and
checking I/O wait time.
• These times can be set independently for each
task.
4. Bulit-in clock. Time (hours, minutes and
seconds) can be set and read out.
5. 20-bit general-purpose I/O port
· Two 8-bit ports operable in bit input/output
• 2-bit input ports and 2-bit output ports.
· Tasks can be resumed using the 2-bit input
ports.
6. Memory assignment
• Working memory areas can be assigned to
each task.
--------..-.---SHARP ------.--..-.----
423
Multi, Task Support Processor , LH8075
• Block Diagram
Port 1
Data Bus
Address! Data Bus
TeBl
Data Strobe 7 MBXl Internal

Control Logic Port .2
Read! W ri te 8
Data Bus
Address Strobe 9
Chip Select 10
I nterrupt Request 0
Interrupt Enable Out 3
Interrupt Enable In 4
SPB2
• Pin Description
Bidirectional
AD o-AD 7 Address/ data bus Multiplexed system address/data bus.
3-state
- Active low. Fetch information on address!data ,bus as
AS Address strobe I
address.
DS Data strobe I
as data.
High at reading. Output contents of internal register on
-
R/W Read/write I address/ data bus ; Low at writing.
Fetch data on address/data bus.
WAIT Wait 0 Active low, open-drain. Used to synchronize CPU.
-- Active low, open·drain. Indicate interrupt request to
INt Interrupt request 0
CPU.
IN TACK Interrupt acknowledge I Active low. Indicate interrupt acknowledge cycle
Pl o-P1 7 I/O port lines 110 Parallel input/output
P2 o-P2 7 I/O port lines I/O Parallel input/output
P3 0 -P3 3 I/O port lines 110 Parallel input/output
PCLK Clock I Single· phase clock, need not be same as CPU clock.
424
+SV
Parameter Symbol Ratings Unit 2.2kO
Input voltage VIN -0.3-+7 V Output pin
Output voltage VOUT -0.3-+7 V under test o--~-'--I~'"
:r
I
Operating temperature opr 0-+70 "C SOpF
Storage temperature T"2 . -65-+150 "C Standard test load 1
• DC Characteristics (Vee=5V±5%, GND=OV, Ta=0-+70"C)

Input high voltage VIH • 2 Vee V
Output low voltage VOH IoH =-250,uA 2.4 V
Output low voltage VOL IOL =2mA 0.4 V
Inptt leakage current I IlL I 0~VIN~5.25V 10 ,uA
Output leakage current I IOL I 0;;;;V IN ;;;;5.25V 10 ,uA
Current consumption lee 250 rnA
• AC Characteristics'
(1) Master CPU interface timing
4 TwCl Clock pulse width, low 105 ns
6 TsCS (AS) CS setup time to AS t 0 ns 1
7 ThCS (AS) CS hold time from AS t 60 ns 1
8 TsA (AS) Address setup time to AS t 30 ns 1
9 ThA (AS) Address hold time from AS t 50 ns 1
10 TwAS AS low pulse width 70 ns
Delay time from DS t to invalid
11 TdDS (DR) 0 ns
readout data
12 TdDS (DRz) 70 ns 2
data floating
13 TdAS (DS) Delay time from AS t to DS l 60 2095 ns
14 TdDS (AS) Delay time from DS t to AS l 50 ns
15 ThDW (DS) Written data hold time from DS f 30 ns 1
Delay time from DS l to readout data
16 TdDS (DR) ns 3
settlement
17 TdAz (DS) Delay time from address floating to DS l 0 ns
18 TwDS DS low pulse width 390 ns
19 TsRWR (DS) R/W high (read) setup time to DS l 100 ns
20 TsRWW (DS) R/W low (write) setup time to DS l 0 ns
21 TsDW (DSf) Written data setup time to DS l 30 ns
22 TdAS(W) Delay time from AS t to WAIT l 195 ns
23 ThRW (DS) R/W hold time from DS t 60 ns
24 TsDR (W) Time from valid readout data to WAIT t 0 ns
The reference voltage levels for timing measurement are 2.0 volts for 'high' ; O.S volt for ·Iow'. All output paramaters are
measured under the stated load conditions.
Note 1: This does not apply to the interrupt acknowledge operation.
Note 2: The Max. value of TdAS (DS) does not to the interrupt acknowledge operation.
Note 3: The delay time depends on the status of LHS075 at the time of access by master CPU.
425
PCLK
ADo-AD7
Master CPU
(read)
AS
R/W
(writ!!)
R/W
(read)
ADo-AD7
Master CPU
(write)
WAIT
Master CPU interface timing
'-'~~----~-SHARP .-..-.-.-.-.------
426
................... -............. -....... - . - . -....... - . - . -......
Multi Task Support Processor
I
LH8075
.-~

No. Symbol Parameter MIN. MAX. Unit
25 TsIA (AS) INT ACK setup time to AS t 0 ns
26 ThlA (AS) INT ACK low hold time from AS t 250 ns
Delay time from AS t to DS !
27 TdAS (DSA) 940 ns
(acknowledge)
Delay time from DS !
28 TdDSA (DR) 360 ns
(acknowledge) to vector settlement
29 TwDSA DS (acknowledge low pulse width 475 ns
30 TdAS (lEO) Delay time from AS t to lEO 290 ns
31 TdIEif (lEO) Delay time from lEI to lEO 120 ns
32 TsIEI (DSA) lEI setup time to DS ! (acknowledge) 150 ns
33 TdDS (INT) Delay time from DS ! to INT t 500 ns
34 ThIEl (DS) IEI hold time from DS t 100 ns
(3) Reset timing

No. Symbol Parameter - MIN. MAX. Unit Note
Delay time from DS t
1 TdRDQ (WR) - 40 ns
(for suppressing reset) to AS !
Delay time from AS t
2 TdWRQ (RD) - 50 ns
(for suppressing reset) to DS !
Minimum low width of AS and DS
3 TwRES 250 ns 1
(for resetting)
Note 1: The internal reset signal lags 112 to 2 clocks behind external reset conditions.
Reset timing
~--------------SHA.RP ------------.-....
427
Ml..\lti :Task Support Processor LH8075
(4) Handshaking timing

1 TsDI (DA) Data setup time 0 ns
2 ThDA(DI) Data hold time 230 ns'
3 TwDA DAV width 175 ns 1,2
-- 20 175 ns 1,2
4 TdDAL(RY) Delay, time from DA V low to RDY
0 ns 2,3
-- 150 ns 1,2
5 TdDAH(RY) Delay time from DAV high to RDY
0 ns 2,3
6 TdDO(DA) Delay time from data output to ,DA V 50 ns 2
7 TdRY(DA) Delay time from RDY to DA V 0 205 ns 2
. Note 1: Input handshaking
Note 2: Measured under the stated load conditions.
Note 3: Output handshaking
Data input
DAV input
RDYoutput
'---''--_ _ _ _ _..;;r Port read
Input handshaking timing
__~>t
Data output
-®--I Port
Valid output data
om. :--r 1
1I--@~~
! \ >or?I®J. . .~. . .-
,DAVoutput
RDY input
..... __ ...
Serial port timing
• Basic Specifications
Table 1 LH8075 basic spec,ifications
Parameter Performance
Task control function
Number of tasks registered Max. 255; task number: hex 01-FF
Number of tasks controlled
Max. 8
simultaneously
Priority level Max. 255; priority level: hex 01-FF
Mail box Max. 5; mail box number: hex 01-05
Unit clock 10 ms
Scheduling Priority order or time division; Task is switched by interrupt from LH8075.
User's RAM is segmented in units of hex 100 bytes; Arbitrary area ranging
Memory allo,cation
hex OOOO-FFFF' can be controlled.
Clock function Time (hour, minute, second) setting and readout
Parallel data input/output function Two '8-bit I/O ports and 'one 4-bit I/O port
428
• Registers Teble 2 Register address

The LH8075 has the following registers which Register Address
can be accessed externally (from CPU). PID XXOOO01X
(1) Task control P2D X XOO010X
CPIO (Command parameter register) P3D X XOOOllX
This register writes the writing parameter pre- CNST X XOOllOX
vious to command writing. The readout parameter SPN1 X XOOlll X
is placed in CPIO upon completion of command ex- SPN2 X X01000X
ecution. SPB1 X X01001X
CNST(Commandl status register) SPB2 X X01010X
This register is used to write a command. Ex- CPIO X X 10101 X
ecution information of executed command is placed MIC X X11110X
in CNST upon completion of command execution.
Note 1: Bits marked by 'x' may be either '0' or '1'.
SPN1, SPN2 (New task stack pointer registers) Note 2: LH8075 uses 64 input/output address locations.
At occurrence of interrupt for task switching,
execution starting address information for the new
task is placed 'in this register.
~
SPB1, SPB2 (Old task stack pointer registers)
TIMR
At occurrence of interrupt for task switching, TSPO
PEND
execution end address information for the executed
~
T~
task is written in this register.
MIC (Master CPU interrupt control register) . {.SM
Interrupt related parameters including interrupt ~~g~T ~~~~ ~__~
enable (IE), interrupt pending (IP) and interrupt- ~ TSPO (Wait)
under-service (IUS) bits are set or reset in this ~ TCRT TOEL ./
register.
TOEL ~ ~TOEL
(2) 1/0 ports
P1D, P2P, P3D (port 1, 2, 3 data registers)
These registers are used to transact data via
GD
(1) Task in execution releases CPU.
port 1, port 2, and port 3. (2) 0 Higher ranking ta,sk becomes ready.
Table 2 lists the register addresses. o Time-up by time division
o TNXT
Fig. 1 Task status
MIC I D, I 061 051 0.1 031 021 01 I 00 I
-~--~TTT L Undefined at reading/"O" at writing
_ ~isabled lower chaining (OLC)
o (unused)
Non -vector (NV)
\ - - - - - - - - - - I n t e r r u p t pending (IP)
! - - + - - - - - - - - - Interrupt under service (IUS)
,!----'--+----------Interrupt enable (IE)
,
At writing· :,
0 0 0 Writing to 02 and O.
0 0 1 Reset IP and IUS
0 1 0 Set IUS
0 1 1 Reset IUS
1 0 0 Set IP
1 0 1 Reset IP
1 1 0 Set IE *: IP, IUS and IE bits are set or reset' by writing in
1 1 1 Reset IE these codes_
Fig. 2 MIC bit configuration
....-...-----.-...---SHARP~---..-.-..--
429
• Programming
Task starting address and initial values for all reg-
The following describes the task control proce-
isters are written at the top of each stack area.
dure using LH8075.
(3) LH8075 is initialized. Table 3 lists the in-
(1) Initialization
itialization information to be written in LH8075.
(1) The LH8075eauses interrupt for task swi-
(4) When necessary, the clock is set and the
tching
port mode is specified.
'However, in order to process, a separate inter-
(5) Initialization completed. To transfer control
rupt processing routine must be prepared.
from the initialization routine to a task, the task ex-
(2) Each task is provided with a stack area.
ecution command (TSTR) must be executed.
Table 3 System information registered at initialization

Order Item Contents
1 Vector LH8075 interrupt vector for task switching
2 User RAM start address (high order byte)
RAM table
3 User RAM end address (high order byte)
4 Task number (hex 01-FF)
5 Task Priority level (hex 01 - FF)
6 1 Task stack pointer (high order or low order byte)
7 Task stack pointer (low order or high order byte
Task table
4n Task number (hex 01-FF)

4n+1 Task Priority level (hex 01 - FF)
4n+2 n Task stack pointer (high order or low order byte)
4n+3 Task stack pointer (low order or high order byte)
(2) Command execution For commands without readout parameter, proce-

Table 4 lists the commands of LH8075, and dure is completed and the following procedures are
Table 5 lists the command execution information. unnecessary. Commands with readout parameter
In writing commands into LH8075 the following (CGET, MALC and PEND) further require the fol-
data entry procedure applies. lowing procedures.
(1) Write parameters needed in writing com- (4) When D6=1 in CNST (indicating the readout
mand into CPIO in the order shown in Table 4. parameter is prepared in CPIO), parameter is read
Commands with blank parameter field in Table 4 out from ePIO.
do not require writing (5) Upon completion of parameter readout,
(2) Write the command number in CNST. PRME command must be executed to notify
(3) It is necessary to confirm the completion of LH8075 of the parameter readout completion.
command execution by polling D7 in CNST (D 7 be- (6) Wait until CNST D7 becomes "I" to confirm
comes "I" upon completion of command execution). the completion of command execution.
430
Table 4 Command table

No. Command name Function Writing parameter Readout parameter Remarks
OOH INIT LH8075 initialization 1. Total number of tasks
OlH TSTR Termination of LH8075
initialination and start of
task execution
02 H TCRT Task creation 1. Task number
2. Priority level
3. SP (high order or low
order byte)
4. SP (low order or high
order byte)
03 H TDEL Task deletion 1. Task number
04 H TRSM Task resumption 1. Task number
05 H TSPD Task suspension 1. Task number See
2. control switch paragraph(1)
06 H TPRI Task priority change 1. Task number

2. New priority
07 11 TSLI Task time-slicing process 1. Priority See
2. Time base paragraph(2)
3. Count
08 H TNXK Swapping of task during
time-sliced execution
09 H TIMR Timer setting 1. control code See
2. Count paragraph(3)
OAII CSET Clock setting 1. Hour

2. Minute
3. Second
OBII CGET Clock readout 1. Hour
2. Minute
*
3. Second
OCII MALC Memory allocation 1. Number of memory 1. Allocated memory
blocks required address
*
0011 MREL Memory release
OEII POST Message transmission 1. Mail box number See
2. Message data 1 paragraph(4)
3. Message data 2
4. Message data 3
5. Message data 4
OFII PEND Message reception I.-Mail box number 1. Message data 1
2. Message data 2 *
3. Message data 3
4. Message data 4
10H PMOO Port mode setting 1. Port-l mode See
2. Port-2 mode paragraph(5)
3. Port-3 mode
1111 PRME End of parameter readout
Note 1: *'
Commands marked by require PRME command execution at parameter readout completion.
Note 2: Numerals given in 'writing parameter' and 'readout parameter' indicate the order of writing and reading.
Note 3: Numerals in 'remarks' indicate the reference number of supplementary explanation .
.------..-.--SHARP.-..-.-.-..-.---
431
MultiTask Support Prcx:iessor· . LH8075
Table 5 Command el(ecution information

Command Command
Code Execution Code Execution
name name
OOH IN IT 0 Normal termination 06 H TPRI 0 Normal termination
1 Task number or priority setting error 1 Task number or priority setting error
2 Double specification of same task 2 Specified task not yet created
number 07 H TSLI 0 Normal termination .
3 Total number of tasks equal to o or 1 Ptiority error or data error
larger than 8, Initialized information 5 Cancellation without setting
error, RAM table error 08 H TNXT 0 Normal termination
01 H TSTR 0 Normal termination 09 H TIMR 0 Normal termination
3 Initial information not yet set 1 Data error
02 H TCRT 0 Normal termination 5 Cancellation without setting
1 Ta~k number or priority setting error 8 Resuming by TRSM
2 Already created OA H CSET 0 Normal termination
3 Control tasks more than 8 1 Data error
03 H TDEL 0 Normal termination OB H CGET 0 Normal termination
1 Task number error OC H MALC 0 Normal termination
2 Specified task not yet created 6 Allocation disabled
4 Specify self OD H MREL 0 Normal termination
04 H TRSM 0 Normal termination 5 Memory not yet allocated
1 Task number error OE H POST 0 Normal termination
2 Specified task not yet created 1 Mail box number error or message
4 Specify self data error
5 Specification of task in ready s,tatus 7 Mail box busy
05H TSPD 0 Normal termination OF H PEND 0 Normal termination
1 Task number or control switch num- 1 Mail box number error
ber error 8 TRSM command issued by other task
2 Specified task not yet created or time out
3 Control switch setting error 10 H PMOD 0 Normal termination
5 Specification· of task ill halt staus 11H PRME 0 Normal termination
• Supplement for writing parameter

(1) 2. Controi switch
I 07 1061 05 1O. 103 102 10, 100 1

IL-------Control switch
o : Bring to complete stop
1 : Halt until external event 1 (fall of P 3,)
2 : Halt until external event 2 (fall of P 30)
(2) 2. Time base
1071 06 1Ds 1o. 103 1D2 10, 1Do I

...- - - - - - T i m e base
1
o : Hour
1 : Minute
2 : Second
3 : 1/100 second
4 or above : Cancellation
432
.-.-.- ..... - . -..... -..... -...
Multi Task Support Processor
_-_.. LH8075
:.-...-...-...-...-...-
(3) 1. Control code
0: Hour
1 : Minute
2 : Second
3 : 1/100 second
' - - - - - - - - Unused
' - - - - - - - - - - - - W a i t switch
0: Wait
1 : Time out period setting only
2. Count
I 0, I 06 I Os I o. I 03 I 02 I01 I 00 I
LI------Count (Count multiplied by time base
becomes setup time)
(4) 2. Only in message data I, '0' is not allowed.
(5) 1. Port-1 mode

Ir-0-,""T,-0-6
T", 0-s-',""'0-."T,-0-3...-,o-,""T,-O-IT",0-0"""',
...
I - - - - - - P o r t - l bit I/O definition
(1 for input; 0 for output)
2. Port-2 mode
Ir o-,""T,-0-6T"10-s-'l-o-."T,-03-,ro-,""T,-o-IT"lo-o-',
LI------Port-2 bit I/O definition
(1 for input; 0 for output)
3. Port-3 mode
IrO-i""T,-O-6T"I-os-'I-0-."TI-O-alr 0-,""T1-0-1T"10-o"",
~~~~TTTLP~'" p.,h-,.n/"oo-'_
Port 1 : Push -pull/open -drain
P31 : External event 1 input
P 30 : External event 2 input
' - - - - - - - - Port -1 handshaking
( P31=OAVI/ROYl)
P32=ROYI/OAVI
' - - - - - - - - - - - Port -2 handshaking
( P30=OAV2/ROY2)
P33 = ROY2/0AV2
'------------Unused
--,-------SHARP-.....-,---------
433
........... -.............................. -.......... ................. .
Z8090/Z8090A Universal Peripheral Controller
.-.- ,
LH8090/LH8090A
~,
LH8090/LH8090A za0901Z8090A Universal

Peripheral Controller

The LH8090 Universal Peripheral Controller
(UPC) is an intelligent peripheral controller: for c\is- P31
tributed processing applications. The LH8090 o P3.
unburdens the host processor by assuming tasks
IEOI P37 3 P27
traditionally done by the host (or by added hard-
ware), such as performing arithmetic; translating IEIIP30 4 P2.
or formatting data, and controlling I/O devices. INT IP35 5
Based on the 28 microcomputer architecture and iN'l'ACK I P32 6 P2.
instruction set, the LH8090 contains 2K bytes of DS 7 P23
internal program ROM, a 256-byte register file, R/W 8 P22
three 8-bitI/0 ports, and two counter/timers. P21
The LH8090 offers fast execution time; an effec-
P20
tive use of memory; and sophisticated interrupt, 1/
0, and bit manipulation. Using a powerful and ex-
tensive instruction set combined with an efficient WAIT P3.
internal addressing scheme, the LH8090 speeds AD7
program execution and efficiently packs program AD. Pl.
code into the on-chip ROM. AD5 PIs
AD. Pl.
AD3 PIa
AD2 P12
• Features AD1
ADo Plo
1. Complete slave microcomputer, for distributed
processing 2- bus use Top View
2. Unmatched power of 28 architecture and in-
struction set
3. Three prpgrammable I/O ports, two with option-
al 2-Wire Handshake'
4. Six levels of priority interrupts from eight
sources: six from external sources and two
from internal sources
5. Two programmable 8-bit counter/timers each
with a 6-bit prescaler. Counter/Timer TO is
driven by an internal source, and Counter/
Timer Tl can be driven by internal or external
sources. Both counter/timers are indepen-
dent of program execution
6. 256-byte register file, accessible. by both the
master CPU and LH8090, as allocated in the
LH8090 program
7. 2K bytes of on-chip ROM for efficiency and
versatility
434
Z8090/Z8090A Universal Peripheral Controller LH8090/{'H8090A
• Block Diagram
Program
Memory
Address/ 2KX8
Data Bus Port 1
Read.' Write 8
Address Strobe 9
Chip Select IRP
Wait l'ort2
Register
File
256X8
15=
• Pin Description
ADo-AD 7 . Address data bus Bidirectional Multiplexed system address/data bus .
- Active low. Causes information on the address/data bus
AS Address strobe I
to be fatched as address
- Active low. Causes information on the address/data bus
DS Data strobe I
to be sent/received as data
A high level indicates a read cycle : Data is output from
- the internal register to the address/data bus. A low
R/W Read/write I
level indicates a write cycle : Data is fetched from the
address/ data bus.
CS Chip select I Active low, Chip select signal.
-- Active low, open-drain. For synchronizaion with the
WAIT Wait 0
CPU.
Pl o-P1 7 I/O port lines I/O Parallel I/O
P2 o-P2 7 I/O port lines I/O Parallel I/O
P3 0 -P3 7 I/O port lines I/O Parallel I/O (4-bit input, 4-bit output)
Signal-phase clock, not need to be related to the CPU
PCKL Clock I
clock.
-~'-'---""'--SHARP'-'-'--~----
435
Z8090/Z8090A Universal Peripheral Controller LH8090/LH8090A
__Nl_._'-'-''-'-:''_''__ '-'-:''-~ ___ ~''''''~

Input voltage· VIN -0.3-+7.0 V
Output voltage· VOUT -0.3-+7.6 V
Operating temperature Topr 0-+70 °C
Storage temperature Tstg -65-+150 °C
* The maximum applicable voltage on any pin except for VBB, with respect to GNO.
• Standared Test Conditions

The characteristics below apply for the follow- 4.75V~Vcc~5.25V
ing standard test conditions, unless otherwise Vss=GND=OV
noted. All volta~es are referenced to GND. Positive O°C::;;;Ta;£ +70°C
current flows into the reference pin. Standard con·
ditions are as followes .
+5V +5V
2.2kO 18kO
From output 0---<P--...--HI-.... From output O----<p--__--foI_._..

under test under test
100
IlA
Standard test load 1 Standard test load 2
• DC Characteristics (Vcc=5V±5%, Ta=O-+70"C)

Parameter Symbol Conditions MIN. TYP MAX. Unit Note
Clock input high voltage VCH 2.4 Vcc V
Input high voltage VlH 2.0 Vcc V
Output high voltage VOH IOH = -250pA 2.4 V 1
Output low voltage VOL 102 = +2.0rnA 0.4 V 1
Input leakage current ihLi o ~ VIN ~ 5.25V 10 pA
Output leakage current iloLi o ~ VIN ~ 5.25V 10 pA
Vee supply current Icc 250 rnA
Note 1: For Ao-Al1. DO-07, MOS, SYNC, MA:;>, and MR/W/IACK of the device for 64-pin development, IOH=100 Il A and 10L 1mA
---------SHARP-----.--------'.-
436
(1) Master CPU interface timing

LH8090 LH8090A
MIN. MAX. MIN. MAX.
2 TwCh Clock high width 105 1855 70 1855 ns
4 TwC1 Clock low width 105 1855 70 1855 ns
5 TpC Clock period 250 2000 165 2000 ns
6 TsCS(AS) cs to AS t setup time 0 0 ns 1
7 ThCS(AS) CS to AS t hold time 60 40 ns 1
8 TsA(AS) Address to AS t setup time 30 10 ns 1
9 ThA(AS) Address to AS t hold time 50 30 ns 1
10 TwAS AS low width 70 50 ns
11 TdOS(OR) OS t to read data not valid 0 0 ns
12 TdOs(ORz) OS t to read data float delay 70 45 ns 2
13 TdAS(OS) AS t OS ~ delay 60 2095 40 2095 ns
14 TdOS(AS) OS t AS ~ delay 50 35 ns
15 ThOW(OS) Write data to OS t hold time 30 20 ns 1
16 TdOS(OR) OS ~ to read data valid delay ns 3
17 TdAz(OS) Address float to OS delay 0 0 ns
18 TwOS OS low width 390 250 ns
19 TsRWR(OS) R/W(read) to OS ~ setup time 100 80 ns
20 TsRWW(OS) R/W(write) to OS ~ setup time 0 0 us
21 TsOW(OSf) W rite data to OS ~ setup time 30 20 ns
22 TdAS(W) AS t to W AIT ~ valid delay 195 160 ns
23 ThRW(OS) R/W to OS t hold time 60 40 ns
24 TsOR(W) Read data valid to WAIT t 0 0 ns
Note : The timing characteristics given reference 2.0V as High and O.8V as Low.
All output AC parameters use test load l.
Note 1: Parameter does apply to interrupt acknowledge transactions.
Note 2: The maximum value for TdAS (DS) does not apply to interrupt acknowledge transcations.
Note 3: This parameter is dependent on the state of UPC at the time of master CPU access.
'-~--------SHARP----~------
437
Z8090/Z8090A Universal Peripheral Controller . LH8090/LH8090A
PCLK
ADo-AD7
MASTER CUP
READ
AS
R/W
(WRITE)
R/W
(READ)
ADo-AD7
MASTER CPU
WRITE
WAIT
438

LH8090 LH8090A
No. Symbol Parameter Unit
MIK MAX. MIN. MAX.
25 TsIA(AS) INTACK to AS t setup time 0 0 ns
26 ThIA(AS) INTACK to AS t hold time 250 250 ns
27 TdAS(DSA) AS t to DS ! (acknowledge) delay 940 200 ns
28 TdDSA(DR) DS ! (acknowledge) to read data valid delay 360 180 ns
29 TwDSA DS ! (acknowledge) low width 475 250 ns
30 TdAS(IEO) AS t to lEO delay 290 250 ns
31 TdIElf(IEO) lEI to lEO delay 120 100 ns
32 TsIEI(DSA) lEI to DS ! (acknowledge) setup time 150 120 ns
33 TdDS(INT) DS ! to INT delay 500 500 ns
34 ThlEI(DS) lEI to DS t hold time 100 100 ns
ADo-AD7 =:x Undefined )>-------- "f-----J

INTACK
lEI
lEO
439
Z8090/Z80gpA ~niver5al Peripheral Controller LH8090/LH8090A

LH8090 LH8090A
MIN. MAX.. MIN. MAX.
1 TsDi(DA) Data in setup time 0 0 ns
2 ThDA(DI) Data in hold time 230 230 .ns
3 TwDA Data available width 175 175 ns 1,2
20 175 20 175 ns 1,2
4 TdDAL(RY) Data available low to ready delay time
0 0 ns 2,3
.150 150 ns 1,2
5 TdDAH(RY) Data available high to ready delay time
0 0 ns 2,3
6 TdDO(DA) Data out to data available delay time 50 50 ns 2
7 TdRY(DA) Ready to data available delay time 0 205 0 205 ns 2
Note 1: Input handshake Note 2: Test load 1 Note 3: ·Output handshake
DATA IN
DAV INPUT
RDY OUTPUT
Port read
Input handshake timing
DATA OUT
-~t=®
r Data out valid
DAV OUTPUT
\
RDY INPUT \
~--@---->.:\,~
"
Output handshake timing
----~.-.----.---SHARP .--.-.---.----
440
Z8090/Z8090AUniversai Pe~ipheral Controller LH8090/LH8090A
• Functional Description structions. All general-purpose registers can

(1) Address space function as accumulators, address pointers, or
On the 40-pin UPC, all address space is com- index registers. In instruction execution, the
mitted to on-chip memory. There are 2048 bytes . registers are read when are defined as sources
of mask programmed ROM and 256 bytes of and written when defined as destinations.
register file. I/O is memory-mapped to three UPC instructions may access registers direct-
registers in the register file. Only the Protopack ly or indirectly using an 8-bit address mode or
version of the UPC can access external program a 4-bit address mode and a Register Pointet.
memory. See the section entitled "Special Con- For the 4-bit addressing mode, the file is di-
figurations" for a complete description of the vided into 16 working register groups, each
Protopack version. occupying 16 contiguous locations (Fig. 3). The
Program memory: Fig. 1 is a map of the 2K Register Pointer (RP) addresses the starting
on-chip program ROM. The first 12 bytes of point of the active working. register group, and
program memory are reserved for the LH8590 the 4-bit register designator supplied by the in-
interrupt vectors. In the RAM version addres- struction specifies the register within the group.
ses OCH through 2FH are reserved for on-chip Any instruction altering the contents of the reg-
ROM. ister file can also alter the Register Pointer. The
Register file: This 256-byte file includes UPC inst~uction set has a special Set Register
three I/O port registers (1-3H), 234 general-
IDENTIFIER
purpose registers (6H-EFH), and 19 control, LOCATION (UPC Side)
Status and special I/O registers (OH,4H,5H and STACK POINTER SP
FO-FFH). The functions and mnemonics assigned MASTER CUP INTERRUPT CONTROL MIC
to these register address locations are shown in
:~AGS~
FDH REGISTER POINTER
Fig. 1. Of the 256 UPC registers, 19 can be di- FCH PROGRAM CONTROL FLAGS
rectly accessed by the master CPU; the others
are accessed indirectly via the ·block transfer
FBH UPC INTERRUPT MASK REGISTER IMR ~
FAH UPC INTERRUPT REQUEST REGISTER IRQ
mechanism.
F9H UPC INTERRUPT PRIORITY REGISTER IPR
The I/O port and control registers are in-
F8H PORT 1 MODE PIM
cluded in the register file without differentia-
F7H PORT 3 MODE P3M
tion. This allows any UPC instruction to pro-
F6H PORT 2 MODE P2M
cess I/O or control information, thereby elimi-
nating the need for special I/O :and control in- F5H ToPRESCALER PREO
F4H TIMER/COUNTER 0 TO
2047
F3H T,PRESCALER PREI
F2H TIMER/COUNTER 1 T1
USER
FI H TIMER MODE TMR
ROM
FOH MASTER CPU INTERRUPT VECTOR REG. MIV
EFH
12 ~~~~HPlD °lFn\SftE~};ll OF INSTRUCTION
11 IRQ 5 LOWER BYTE
10 IRQ 5 UPPER BYTE GENERAL-PURPOSE
9 IRQ 4 LOWER BYTE REGISTERS
8 IRQ 4 UPPE R BYTE
7 IRQ 3 LOWER BYTE
6 IRQ 3 UPPER BYTE
5 IRQ 2 LOWER BYTE DATA INDIRECTION REGISTER DlND
4 IRQ 2 UPPE R BYTE LIMIT COUNT REGISTER LC
3 IRQ I LOWER BYTE PORT 3 P3
2 IRQ I UPPER BYTE PORT 2 P2
J IRQ 0 LOWER BYTE PORT I PI
0 IRQO UPPER BYTE DATA TRANSFER CONTROL REGISTER DTC
Fig 1 Program memory map Fig 2 Register file organization
-----------SHARP----.----------
441
downs, compatible with TTL loads. In addition,

FDH
r- 011 1 I o 000 FOH
Port 1 and Port 2 may be configured as opendrain
EFH outputs. Data in each port can be .known by reading
EOH a corresponding Port Mode register in the same
DFH way as acc~ssing the register.
DOH Port 1: Individual bits of port 1 can be confi·
CFH
COH gured as input or output. This port can also be
BFH programmed as 110 Handshake Line. This port is
BOH accessed as general register 1H. It is written by
AFH
specifying address 1H as the destination of any in-
AOH
9FH' struction used to store data in the output registers.
90H The port is read by specifying address 1H as the
8FH source of an instruction.
80H Port 2: lndividual bits of Port 2 can be confi- .
1-...,,0 7 5 H (01110101) ~
70H
gured as inputs or outputs. This port is accessed as
6FH general register 2H, and its functions and methods
60H of programming are the same as those or Port 1.
5FH Port 3: This port can be configured as 1/0 or
50 H
4FH control lines. Port 3 is accessed as general register
40H 3H. The directions of the eight data lines are fixed.
3FH Four lines, P30 through P33, are inputs, and the
30H . other four, P3. through P37, are outputs. The con-
2FH
20 H
trol fun~tions performed by Port 3 are listed in
IFH Table 1.
10 H
OFH
Table 1 Port 3 control functions
0
'1: The 4-bit register pointer provides the upper nibble of the Function Line 110 signal
register file address for the 4-bit address mode. P31 I DAV2/RDY,
'2: The lower nibble of the register file address (010 1) is pro· --
vided by the instruction. P33 I DAVdRDY,
Handshake --
Fig. 3 Register pointer mechanism P3. 0 RDYdDAV,
--
P36 0 RDYzlDAV2
Pointer (SRP) instruction for iiIitializing or alte-
P30 I IRQ3
ring the pointer contents. UPC Interrupt
P3, I IRQ,
Stacks: An 8-bit stack Pointer (SP), register Request *
P33 I IRQ,
R255. is used for addressing the stack, residing
P3, I TIN
within the 234 general-purpose regisgers. address Counter ITimer
P36 0 TOUT
location 6H through EFH.
P35 0 INT
PUSH and POP instructions can save and restore ---
P32 I INTACK
any register in the register file on the stack. During Master CPU
P30 I lEI
CALL instructions, the Program Counter is auto-
P37 0 lEO
matically saved on the stack. During UPC interrupt
cycles, the Program Counter and the Flag register * P3o. P3" and P33 can always be used as upe interrupt reo
quest inputs, regardless of the configuration programmed.
are automatically saved on the stack. The RET and
IRET instructions pop the saved values of the (3) Counter/timers
Program Counter and Flag register. The LH8090 contains two 8-bit programmable
(2) Ports counter/timers, each driven by an internal 6-bit
The LH8090 has 24 lines dedicated to input and programmable prescaler.
output. These are grouped into three ports eight The T1 prescaler can' be driven by internal or
lines each and can be configured under software external clock sources. The TO prescaler is driven
control as inputs, outputs or special control sig· by an internal clock source. Both counter Itimers
nals. operate independently of the processor instruction
They can be programmed to provide Parallel 110 sequence to relieve the program from time-critical
with or without handshake and timing signals. oPerations like event counting or elapsed-time cal-
All outputs can have active pullups and pull· culation.
442
The counters can be started, stopped, restarted the interrupt request needs service.
to continue, or restarted from the initial value., (5) Master CPU register file access
They can be programmed to stop upon reaching There are two ways in which the master CPU
end-of-count (Single-Pass mode) or to automatical· can access the LH8590 register file: direct access
ly reload the initial value and continue counting and block access.
(Modulo-n Continuous mode). Direst Access: Three LH8090 registers - the
(4) Interrupts Data transfer Control, the Master Interrupt Vector,
The LH8090 allows six interrupts from eight and the Master Interrupt Control - are mapped
different sources as follows: directly into the master CPU address space.
• Port 3 lines P3o, P31, and P33. The registers can directly be accessed in 16
• The master CPU (3). bytes.
• The two counter/timers. Block Access: The masteJ;" CPU may be trans-
These interrupts can be masked and globally en- mit or receive blocks of data via address X X X
abled or disabled. The order of their priority can 10101 (X X 10101 X for shift address). When the
be specified. All interrupts are vectored. master CPU accesses this address, the LH8090
Table 2 lists the LH8090's interrupt sources, register pointed to by the Data Indirection register
their types, and their vector locations in program (DIND) is read or written.
ROM. The number of bytes is set in the Limit Count
The LH8090 also supports polled systems. register (LC). The LH8090 controls everything in
To acommodate a polled structure, any or all of the block transfer and is therefore allowed to pro-
the interrupt inputs can be masked and the inter- tect itself from master CPU errors.
rupt request register polled to determine which of
Table 2 Interrupt types, sources, and vector locations

, Name Source Vector Location Comments
IRQO EOM, XERR, LERR 0, 1 Internal (RO Bits 0, I, 2)
IRQl DAVl, IRQl 2, 3 External (P33) ! edge triggerd
--
IRQ2 DA V2, IRQ2, TIN 4, 5 External (P31) ! edge triggerd
IRQ3 IRQ3, lEI 6, 7 External (P3o) ! edge triggerd
IRQ4 TO 8, 9 Internal
IRQ5 T1 10, 11 Internal
443
Z8090lZ8090A Universal Peripheral Controller LH8090lLH8090A
• Instruction IMR Interrupt mask register (control regis-

ter FBH)
(1 ) Addressing modes Assignment of a value is, indicated by the sym'
The following notation is used to describe the bol "+-n. For example.
addressing modes and instrucion operations. dst +- dst + src
IRR Indirect register pair or indirect work· indicates that the source data is added to the des-
ing-register pair address tination data and the result is stored in the des-
Irr Indirect working-register pair only tination location. The notation "addr(n)" is used to
X Indexed address refer to bit "nn of a given location. For example.
DA Direct address dst (7)
RA Relative address refers to bit 7 of the destination operand.
1M Immediate (3) Flags .
R Register or working-register address Control Register FCH contains the following six flags:
r Working-register address only C Carry flag
IR Indirect-register or indirect working- Z Zero flag
register address S Sign flag
Ir Indirect working-register address only V Overflow flag
RR Register pair or working-register pair D Decimal-adjust flag
address H Half-carry flag
(2) . Symbol Affected flags are indicated by:
dst Destination location or contents o Cleared to zero
src Source location or contents 1 Set to one
Condition code (see list) Set or clear.ed according to operation
cc
@ Indirect address prefix' * Unaffected
PC Program Counter X Undefined
SP Stack Pointer (control register FFH) (4) Condition codes
FLAGS Flag register (control register FCH) Table 3. shows condition codes.
RP Register Pointer (control register FDH)

1000 Always true .........
0111 C Carry C=l
0110 2 Zero Z=l
1110 NZ Not zero Z=O
1101 PL Plus S=O
0101 MI Minus S=l
0110 EQ Equal Z=l
1110 NE Not equal 2=0
1001 GE Greater than or equal (S XOR V)=O
0001 LT Less than (S XOR V)=l
1010 GT Greater than [2 OR(S XOR V)) =0
0010 LE Less than or equal [2 OR(S XOR V)) = 1
0111 ULT Unsigned less than C=l
1011 UGT Unsigned greater than (C=O AND 2=0)= 1
0011 ULE Unsigned less than or equal (C OR 2)=1
0000 Never true .........
-~--------.-.....-SHARP---.------
444
?:8090/Z8090A Universal Peripheral Controller LH8090/LH8090A
(5) Opcode Map

Lower Nibble (Hex)
o 2 3 4 5 6 7 8 9 A B C o E F
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.5 6.5 12110.5 12110.0 6.5 12110.0 6.5
o DEC DEC ADD ADD ADD ADD ADD ADD LD LD DJNZ JR LD JP INC
R. IR. TI, T2 fl,ITZ Rz. R\ IRz, RI RI.IM IR,.IM Rz RA ce, RA r"IM ce, DA
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5
flo f2. RI TI.
" I---
RLC
R.
RLC
IR.
ADC ADC ADC ADC ADC
fl, T2 n, IT! Rz. RI IRz. RI R •• IM
ADC
IRI.IM
I
I---
6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5
R. IR. T],TZ T\,IT2 Rz. RI IR 2• R, RI.IM IR •• IM
I---
H.n 6.1 6.5 6.5 10.5 10.5 10.5 10.5
3 JP SRP SBC SBC SBC SBC SBC SBC
IRRI 1M n, T2 Tt, IT! Rz. RI IRz, RI RI.IM IR •• IM
I---
8.5 8.5 6.5 6.5 10.5 10.5 10.5 10.5
xIII R. IR. TI,T2 TIoIT2 Rz, RI IRz. R, R •• IM lRI.IM
10.5
I---
.= 5 10.5
POP
R.
10.5
POP
IR.
6.5 6.5
AND AND AND AND AND AND
10.5 10.5
Rz. RI . IR2• Rl
10.5
RI.IM IR •• IM
III r"r2 TI.IT2
:c
.Q 6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5
I---
Z 6 COM COM TCM TCM TCM TCM TCM TCM
Gi R. JR. TI,T2 fI, IT! R2. RI IR2. R\ R1. IM IR1.IM
Q. I---
Q. 10112.1 12114.1 6.5 6.5 10.5 10.5 10.5 10.5
::::l 7 PUSH PUSH TM TM TM TM TM TM
R, IR, TI,T2 TIoIT! Rz• R, IR 2• RI RI.1M IR\.IM
I---
lO,:} 10.3 12.0 18.0 6.1
8 DECW DECW LDE lOEI 01
RR. IR. T\, IrT2 In. lIT!
I---
6,5 6.5 12.0 18.0 6.1
9 RL RL lOE LDEI EI
R. IR • T2,lrrl Irz.lrrl
I---
w.;) 10.;) 6.5 6.5 10.5 10.5 10.5 10.5 14,0
RR. IR. n.T2 n.lr! R2. R, IR z• RI Rt.IM IR1. 1M
6.5 6.5 6,5 6.5 10.5 10.5 10.5 10.5 ~
R. IR. TI,T2 n.lr! R2. RI IR2. RI R],IM IR!, 1M
I---
6,5 6.5 12.0 IS.O 10.5 6.5
C RRC RRC LDC LOCI LD RCF
R. JR. TI,lrn ITI,lrr! Tl, x, R2
I---
6.5 6.5 12.0 18.0 20.0 20.0 10.5 6.5
0 SRA SRA LDC lOCI CALL" CALL LD SCF
R. JR. f2.Irf! In.ITT\ IRR, DA f2, X, RI
-
6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.5
E RR RR LD LD LD LD LD CCF
R. IR. T\,In R2• RI lRz. RI RJ,IM IR!, 1M
-
8,5 8.5 6.5 10.5 6.0
F SWAP SWAP LD LD NOP
R. IR. lrl,TZ Rz,IR,
~--------~------~~------~--------~~----------~----------~~~
2 3 2 3
Bytes per
Instruction
Lower Opcode Nibble Legend:

R = 8-Bit Address
Execution Cycles Pipeline Cycles r = 4 - Bit Address
Rl or n = Dst Address
R2 or r2 = Src Address
Upper Sequence:
Opcode Nibble~ A 4 - - Mnemonic
Opcode. First Operand. Second Operand
Note: The blank areas are not defined.
First Operand Second Operand
----.-------.---SHARP - - - - - - - - - - - . - . . .
445
Z8090/Z8090A 'Universal Peripheral Controller LH8090/LH8090A
Instruction Summary
Instruction Opcode Flags Affected Instruction Opcode Flags Affected
and I Addr. mode and I Addr. mode
Operation I dst src (Hex) CZSVDH Oparatlon I dst src (Hex) CZSVDH
ADC dst, src (Note 1) 10 ****·0* LDEI dst, src Ir Irr· 83
dst....dst + src + C dst....src Irr Ir 93
ADD dst, src (Note 1) 00 ****0* r .... r+ 1; rr ....rr+ 1
dst ....dst + src NOP FF
AND dst, src (Note 1) 50 -**0-- OR dst, src (Note 1) 40 -**0--
dst ....dst AND src dst.... dst OR src
SP....SP-2 IRR D4 dst....@SP IR 51
@SP.... PC· PC ....dst SP....SP+l
CCF EF *--- - PUSH src R 70
C.... NOT C Sp....SP-l· @SP ....src IR 71
CLR dst R BO ------ RCF CF 0 ----
dst....O IR Bl C.... O
COM dst R 60 -**0-- PET AF - --
dst....NOT dst IR 61 PC ....@Sp· Sp....SP+2
CP dst, src (Note 1) AD ****-- 4RL dst R
dst....src
R 40
~7 O~ IR
90
91
****--
DA dst ***X--
dst ....DA dst IR 41 RLC dst R 10 ****--
DEC dst R 00 -***-- ~7 O~ IR 11
dst.... dst-l IR 01
DECWdst RR 80 -***-- RR dst R EO
dst....dst-l
01
IR 81
8F
4947 O~ IR El
****
R CO
~7 O~
IMR(7) .... 0 RRC dst ****
DJNZ r,dst RA rA - ---- IR Cl
r .... r-l r=O-F
if r+O PC .... PC+dst
sec dst, src (Note 1) 3D ****1*
dst....dst - src - C
Range; + 127--128 DF 1
------ SCF
EI 9F C.... l
IMR(7) .... 1 ~
* * * 0
L,g ell t P
INC dst r rE -***-- SRA dst DO
dst....dst+ 1 r=O-F Dl
R
IR
20
21
SRP src 1M 31 ------
RP ....src
INCW dst RR AO -***-- SUB dst, src (Note 1) 2D ****1*
dst....dst+ 1 IR Al dst.... dst - src
IRET BF ******
~
FLAGS ....@SP;SP....SP+ 1 SWAP dst R FO X* *X--
PC ....@Sp·SP ....SP+2;IMR(7).... 1 IR Fl
JP cc, dst DA cD ------ TCM dst,src (Note 1) 60 * * 0
if cc is true c=O-F I(NOT ds!) AND src
PC ....dst IRR 30 TM dst,src (Note 1) 70
------ * * 0
JR cc, dst RA cB dst AND src
PC .... PC+dst dst.... dst XOR src
Range: +127--128
LD dst, src r 1M rC ------ Note 1: These instructions have an identical set of' addressing
dst ....src r R r8 modes, which are encoded for brevity. The first opcode nibble is
R r r9 found in the instruction set table above. The second nibble is ex·
r X C7 in the following table to the left of the applicable addressing
X r D7 mode paie.
r Ir E3 For example, to determine the opcode of an ADC instruction
Ir r F3 using the addressing modes r (destination) and Ir (source) is 13.
R R E4
R IR E5 Addr Mode Lower
R 1M E6 dst src Opcode Nibble
IR 1M E7
IR R F5 r r !2J
LDC dst, src r Irr C2 ------ r Ir 11I
dst....src Irr r D2 Ii]
LOCI dst, src Ir Irr C3 ------ R R
dst-src Irr r D3 R IR lID
r-r+ l' rr-rr+ 1 R 1M [ill
LDE dst, src r Irr 82 ------
dst-src Irr r 92 IR 1M [Z]
446
Z8090/Z8090A Universal Periph~Hal Controller LH8090/LH8090A
• Register
RO (DTC)
upe Register Address (Hex): 00
I D7 I D61 D51 D,I D31 D21 DI I Dol
I/O REGISTER POINTER ORP)I I I(EOM) . 0=-

_ _ _ _ _ _(_E_D_X---..J). I=END OF MESSAGE
DISABLE DATA TRANSFER=O' (LERR)
ENABLE DATA TRNSFER=1 O=NO LIMIT ERROR
NO TRANSFER ERROR =0 (XERR) 1 = LIMIT ERROR
TRANSFER ERROR = 1
R4 (LC) R5 (DIND)
upe Register Address (Hex): 04 upe Register Address (Hex): 05
I D7 I D6 I Dsl D,I D31 D21 DJ I Do I I D71 Ds! D51 D,I D31 D21 Dd Dol
<-I- _ _ _ _ LIMIT COUNT VALUE LINDIRECTION ADDRESS

(RANGE:0-255 DECIMAL (Do= LSB)
00- FF HEX)
R240 (MIV)
upe Register Address (Hex): f1
I D7 I D61 D5 I D4 I D31 D2 I DI I Do I
I VECTOR DATA (Do = LSB)
R241 (TMR)
upe register address (Hex): Fl
I D71 D61
TOUT MODES=::::J
RESERVED = 00
To OUT = 01
I L
D5 I D41 D31 D2 I DI I Do I
O = NOFU~CTION
1 = LOAD To
C O = DISABLE To COUNT
TJ OUT = 10 1 = ENABLE To COUNT
INTERNAL CLOCK OUT = 11 0 = NO FUNCTION
TIN MODES - - - - - - ' 1 = LOAD TI
EXTERNAL CLOCK INPUT = 00
GATE INPUT =01 ' - - -_ _ _ 0 = DISABLE TI COUNT
TRIGG ER INPUT = 10 1 = ENABLE TI COUNT
(NON -RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
R242 (T1) R243 (PRE1)
upe Register Address (Hex): F3
l
Counter/Timer 1 Register
upe Register Address (Hex): F2 I D71 D61 D5 1 D41 D31 D21 DIlDo 1
I D71 D61 D51 D41 D31 D21 DIlDo I LCOUNT MODE

C=:TI INITIAL VALUE 0 = TI SINGLE PASS
(RANGE: 1-2 5 6 DECIMAL 1 = TI MODULO· N
CLOCK SOURCE
01-00 HEX) 0 = EXTERNAL TIMING IN
(TIN) MODE
1 = TI INTERNAL
'---------PRESCALER MODULO
01-00 HEX)
.-----.----------SHARP - - - - - . - . - - - - - -
447
Z8090/Z8090A Uhh,ersal Peripheral Controller LH8090/LH8090A
R244 (TO) R245 (PREO)

Counter/Timer 0 Register Prescaler 0 Register
UPC Register Address (Hex): F 4 UPC Register .Address (Hex): F5
1 071 061 Dsl 04 1 03 1 02 I 01 I Do I

C=To INITIAL VALUE
01-00 HEX)
1 07
I L'
I 061 Os I 041 031 02 I 0 1 I Do I
COUNT MODE
O=To SINGLE-PASS
1 = To MODULO· N
RESERVED
R246 (P2M) '-------PRESCALER MODULO
Port 2 Mode Register (RANGE: 1-64 DECIMAL
01-00 HEX)
UPC Register Address (Hex): F6
I 07 I 06 I Os I 04 I 031 02 I 01 I Do I
L P20- P27 I/O DEFINITION
o DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
R247 (P3M)
I 07 I 061 Os I 041 03 I 02 I 01 I Do I
LS Lo PORT 2 PULL-UPS OPEN DRAIN

o PORT I PULL-UPS OPEN DRAIN
1 PORT I PULL-UPS ACTIVE
o P3S =
OUTPUT
I P3S = INT
RESERVED
o P33= INPUT P34 = OUTPUT
I P3F DAV1/RDYI P34 = ROY l/DA V I
'-----0 P31= INPUT (TIN) P36 = OUTPUT (TOUT)
I Pl!= DAV2/RDY2 P36 = RDY2/DAV2
~-------'OP30=INPUT P37 = OUTPUT
I P30 = lEI P37 = IEO
L----------OP32=INPUT
I P3F INTACK
R248 (P1 M)
1 07 I 061 05 I 04 I 031 021 01 I Do I

I'----Plo-Ph I/O DEFINITION
I DEFINES BIT AS INPUT
.-.---.---------$HARP-----------
448
R249 (lPR)
Interrupt Priority Register
upe Register Address (Hex): F9 (write only)
1 D71 D61 D51 D.I D31 D21 Dl I Do I
RESERVED~ IRQl,IRQ4 PRIORITY (GROUP C)
INTERRUPT GROUP PRIORITY--+---'----t------' o =IRQl>IRQ4
RESERVED=OOO I =IRQ4>IRQI
C>A>B=OOI ~---IRQO,IRQ2 PRIORITY (GROUP B)
A>B>C=OIO o =IRQ2>IRQO
A>C>B=OII 1 =IRQO>IRQ2
B>C>A=IOO ~-------IRQ3,IRQ5 PRIORITY (GROUP A)
C>B>A=lOI
B>A>C=IIO
o =IRQ5>IRQ3
1 =IRQ3>IRQ5
RESERVED =111
R250 (IRQ) R251 (lMR)

Interrupt Request Register .Interrupt Mask Register
upe Register Address (Hex): FA upe Register Address (Hex): FB
I D7 I D6 I D5 I D.I D3 I D2 I Dl I Do I I D71 D61 D5 I D.I D3 I D2 I DJ I Do I
Uk~
IRQO=MASTER CPU
COMMUNICATIONS
I I I~L I1 ENAIlLES !ROO
B
ENABLES IRQI
QI=P3, INPUT 1 ENABLES IRQ2
Q2=P31 INPUT 1 ENABLES IRQ3
Q3=P3, INPUT ~-----1 ENABLES IRQ4
IR Q4=To ' - - - - - - - - 1 ENABLES IRQ5
IR Q5=Tt ' - - - - - - - - - RESERVED
RESERVED ' - - - - - - - - - - - - - 1 ENABLES INTERRUPTS
R252 (FLAGS) R253 (RP)

Flag Register Register Pointer
upe Register Address (Hex): Fe upe Register Address (Hex): FD
I D71 D61 D5 I D.I D31 D21 Dt! Do I I D71 D61 D51 D.I D31 D21 DJ I Do I
LS I
LUSER FLAG Fl
~USER
FLAG F2
HALF CARRY FLAG
DECIMAL ADJUST FLAG
I
~.-------REGISTER
LDON'T CARE
(r.-n)
'-------OVERFLOW FLAG
~-------SIGN FLAG
~--------ZEROFLAG .
'------------CARRYFRAG
-----~--.---SHARP--.-.---~----
449
R~54 (MIC)
Master CPU Interrupt Control Register
UPC Register Address (Hex): FE
I D71 D6 I Dsl D41 Dal D21 DI I Dol

~I
o INTERRUPT REQUEST DISABLEDJ
o INTERRUPT REQUEST ENABLED
o NO INTERRUPT UNDER SERVICE
II L: ;NO OF MESSAGE
o WAIT ENABLE WHEN WRITE
1 INTERRUPT UNDER SERVICE 1 WAIT DISABLE WHEN WRITE
o NOMASTER CPU INTERRUPT. PENDING o ENABLE LOWER CHAIN
1 MASTER CPU INTERRUPT PENDING 1 DISABLE LOWER CHAIN
o VECTOR OUTPUT - - - - - - ' ' - - - - - - - 0 DISABLE DATA TRANSFER
1 NO VECTOR OUTPUT 1 ENABLE DATA TRANSFER
R255 (SP)
Stack Pointer
UPC Register Address (Hex): FF
I D7 I D61 Ds I D. I Da I D2 I DI I Do I
II-----STACK POINTER
Table 4. Control register reset conditions

Control Register D7 D6 Ds D4 D3 D2 DI Do Comments
OOH Data transfer control register X X X X 0 0 0 0 Disable data transfer from master CPU
04 H Limit count register Not defined
05 H Data indirection register Not defined
FO H Interrupt vector register Not defined
FIH Timer mode 0 0 0 0 0 0 0 0 Stops TO and T1
F2H Tl register Not defined
F3 H T 1 prescaler X X X X X X 0 0 Single-pass mode
F4H TO register Not defined
F5 H TO prescaler X X X X X X 0 Q Single-pass mode external clock source
F6 H Port 2 mode 1 1 1 1 1 1 1 1 Port 2 lines defined as inputs
F7H port 3 mode 0 0 0 0 X 1 0 0 Port 1. 2 open drain output
P3 s = INT
P3 o• P3 10 P3 2. P3 3 defined as' input
P3 4• P3 6• P3 7 defined as output
F8 Hport 1 mode 1 1 1 1 1 1 1 1 Port 1 lines defined as inputs
F9 HInterrupt priority Not defined
FAH Interrupt request X X 0 0 0 0 0 0 Reset interrupt request
EBH Interrupt mask 0 X X X X X X X Interrupts disabled
FC HFlag register Not defined
FDH Register pointer Not defined
FEH Master CPU interrupt control 0 0 0 0 0 0 0 0 Master CPU interrupt disabled: wait
register enable when write: lower chain enabled
FFH Stack pointer Not defined
Note: X means not defined.
---------.-.-..--SHARP -....--....-..-----
450
Z8091/Z8091 A Development Device LH8091/LH8091 A
LH8091/LH8091A ~~:;:~;!DeViCe
The 64-pin LH8091 is the development version
of LH8090 (Z8090) UPC with internal mask- +5V 1
programmed ROM. This device allows the user to PCLK 2
the prototype systems in hardware without an
actual device and to develop the code that is even-
tually mask-programmed into the on-chip ROM of
the LH8090.
The LH8091 is identical to the LH8090 with the
following exceptions.
• The internal ROM has been removed .
ered and brought out to external pins.
• Control lines for the memory have been added.
The LH8091A is the high speed version which
can operate at 6MHz system clock.
Top View
451
Z8091fZ8091 A Development Device LH8091/LH8091A
• Block Diagram
Program Memory Address Output

,
Address/Data
Bus I/O
Address Strobe 9
Data Strobe 7
Read/W rite 8 I/O
Chip Select 10
Interrupt Request 5
Interrupt Enable In
Interrupt Enable
Out
Interrupt Acknowledge 24)---------------'----------'

Output/Memory Read
• Pin Description
LH8091 has the same functions as those of a 40-pin device LH8090, and the functions of the additional 24
Symbol Meaning I/O Function
Ao'- All Program memory address 0 Used for the access to the external memory of 4K bytes.
Do -D 7 Program data I Reads the data through these lines from the external memory.
Interrupt acknowledge Active high. This signal becomes high during interrupt or in·
IACK/MR 0
Imemory read. struction fetch cycle of LH8591.
-~
Active low. This signal is output every memory fetch cycle
MAS Memory address strobe 0
for the interface with the external ROM.
Active low. This signal becomes low during instruction fetch
MDS Memory data strobe 0
cycle or write cycle.
-- Active low. This signaJ becomes low at the clock cycle just
SYNC Synchronization 0
before Op-code fetching.
-------------SHARP,....-.-..--------
452
Z8092/Z8092A Development Device LH8092/LH8092A
Z80921Z8092A
LH8092/LH8092A Development Device

The 64-pin LH8092 is the development version
of LH8090 (Z8090 UPC) with internal mask- +5V 1
programmed ROM. This device allows the user to PCLK 2
the prototype systems in hardware with an actual P37/IEO 3
device and to develop the code that is eventually P3o/IEI •
mask-programmed into the on-chip ROM of the P35/INT 5
LH8090. P3,fINT ACK 6 5 P2.
The LH8092 is identical to the LH8090 with the P23
following exceptions. P22
• The internal ROM has been removed (But
there are 36 bytes of internal ROM for a boot-
strap program) .
• Control lines for the memory have been added.
Top View
.-----~--.-.--SHARP --.-------------
453
• Block Diagran
.
Program Memory Address Output
Address/Data
Bus I/O
Address Strobe 9
Data Strobe 7
Read/Write 8 I/O
Chip Select 0
Wait 11
Interrupt Request 5 o
Interrupt Enable In
Interrupt Enable
Out
Interrl!!t Acknowledg 241}-------~--------------'

&~ti~~t Memory/Read/ ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
• Pin Description
LH8092 has the same functions as those of a 40-pin device LH8090, and the functions of additional 24
pins are' as follows.
Symbol Meaning I/O Function
Ao-Au Program memory address 0 Used for the access to the external memory of 4K bytes.
Reads for data through these lines from the external memory.
00-07 Program data I And it is possible to write into an external RAM through
these lines.
Active high. This signal is always active during interrupt cy-
LACK Interrupt acknowledge 0
cle of LH8092.
Active low. This signal is output every memory feich cyclefor
interfacing with the external RAM.
-- Active low. This signal is outptt eyery memory fetch cycle for
MOS Memory data strobe 0
- This signal is high during instruction fetching by LH8092,
MR/W Memory read/write 0
or low while writing into the external memory.
Active low. This signal becomes low during clock cycle just
before OP code fetching.
- - - - - - - - - - - - - - S H A R P - - - . - - - - - , - - - - - - - ........
454
Z8093/Z8093A Protopack Emulator LH8093/LH8093A
LH8093/ LH809 3A ~:::1!093A Protopack

The LH8093 (28093) is a ROMless version of
the standard LH8090, housed in a pin compatible P31
40-pin package. o P36
The LH8093 carries a 40-pin soket for a direct
P37/IEO 3 P27
interface to program memory. 2716 type EPROM
can be used for program memory. P30/IEI 4 P26
The LH8093 allows the user to build the pro- P3s/INT 5 P2s
totype and pilot production units. When the final P32/INTACK 6 P2.
program is established, the user can then switch P23
over the LH8090. P22
The LH8093A is the high speed version which P21
P33
P3.
Ph
PIs
PIs
Pl.
Pb
Ph
Ph
ADo
Top View
455
Z8093/ZS093A Protopack Emulator LH8093/LH8093A
• Block Diagram
Program Data Input Program Memory Address Output

*1*2*3' " •
Address/Data
Bus I/O
Address Strobe 9
Data Strobe 7
Read/Write 8 I/O
Chip. Select 10
Interrupt Request
Interrupt Enable In
Interrupt Enable
Out

*3 Instruction Sync Output
• Pin Description
LH8093 pins are compatible with those of LH8090. For pin descriptions of LH8093, refer to those of
LH8090.
456
LH8094/LH8094A ~~=094AProtopaCk
The LH8094 (28094) is a RAM version (16K
bits RAM) of the standard LH8090, housed in a pin P31
compatible 40-pin package.
o P36
interface to program memory, and has 36 bytes of P37/IEO 3 P2,

internal ROM for a bootstrap program. P30/IEI 4 P26
The LH8094 allows the user to build the pro- P35/INT 5 P25
totYPe and when the final program is established, P32/INT ACK 6 P2.
the user can then switch over the LH8090. P23
The LH8094A is the high speed version which P2,
P21
P33
P3.
PI6
PIs
Pl.
PIa
PI,
Ph
ADo
Top View
457
/
.Z8094/Z8094A· Protopack Emulator LH8094/LH8094A
• Block Diagram

*1*2*3,~-----'~----~"r--------~'~--------~
Address/Data
Bus
Address Strobe 9
Data Strobe 7
Read/Write 8
Chip Select 10
Interrupt Request
Interrupt Enable In
Interrupt Enable
Out

C : This is equipped with RAM
• Pin Description
LH8094 pins are compatible with those of LH8090. For pin descriptions of LH8094, refer to those of
LH8090.
458
Peripheral LSls for Microcomputers
Z8530/Z8530A Serial Communications Controller !-H 85301 LH 8530A
LH8530/LH8530A
Z8S301Z8S30A Serial Communications Controller
The LH8530 Z8530 SCC Serial Communications
Controller is a dual-channel, multi-protocol data
communications peripheral designed for use with On
conventional non-multiplexed buses. The LH8530
0 02
functions as a serial-to-parallel, parallel-to-serial O.
converter controller. The LH8530 can be software- 06
configured to satisfy a wide variety of serial com- RO
munications applications. The device contains a WR
variety of new, sophisticated internal functions in-
cluding on-chip baud rate generators, Digital
AlB
INTACK 8 CE
Phase- Locked Loops, and crystal oscillators that
dramatically reduce the need for external logic. +5V 9 o/e
The LH8530 handles asynchronous formats, W/REQA GNO
Synchronous byte-oriented protocols such as IBM SYNCA W/REQB
Bisync, and Synchronous bit-oriented protocols RTxCA SYNCB
such as HDLC and IBM SDLC. This versatile de- RxOA RTxCB
vice supports virtually any serial date transfer ap- TRxCA RxllB
plication (cassette, disk tape drives, etc).
TxOA TRxCB
The device can generate and check CRC codes in
OTR/REQA TxllB
any Synchronous mode and can be programmed to
check data integrity in various modes. The RTSA IlTR/R};qB
LH8530 also has facilities for modem controls in CTSA RTSB
both channels. In applications where these controls DCDA CTSB
are not needed, the modem controls can be used for PCLK
general-purpose I/O.
Top View
The daisy-chain interrupt hierarchy is also sup-
ported by the LH8530.
The LH8530 is packaged in a 40-pin ceramic
DIP and uses a single+ 5V power supply.
The LH8530A Z8530A SCC is the high speed
character; programmable clock factor, break
detection and generation; parity, overrun, and
framing error detection.
4. Synchronous mode with internal or external
character synchronization on one or two syn-
chronous characters and CRC generation and
checking with CRC-16 or CRC-CCITT preset
• Features to either Is or Os.
1. Two independent, 0 to 1.5M bit/second, full- 5. SDLC/HDLC mode with comprehensive frame-
duplex channels, each with a separate crystal level control, automatic zero insertion and de-
oscillator, baud rate generator, and Digital letion. I-field residue handling, abort genera-
Phase-Locked Loop for clock recovery. tion and detection, CRC generation and check-
2. Multi-protocol operation under program con- ing, and SDLC Loop mode operation.
trol; programmable for NRZ, NRZI, or FM data 6. Local Loopback and Auto Echo modes.
encoding.
3. Asychronous mode with five to eight bits and
one, one and one-half, or two stop bits per
----------$HARP-----~-.-.--
460
• Block Diagram
Serial Data
Baud Rate
Generator
A
11 Synchronization
10 Wait/Request
Data Bus 16 Data Terminal
Ready /Request
17 Request To Send
18 Clear to Send
23 Request To Send
24 Data Terminal
Ready / Request
30 Wait/Request
Baud Rate Synchronization

Generator
B Channel Clock
Serial Data
...
"o
U
461
.............................,..... ..........,.....
• Pin Description
~ .-..---.. --~ ..........,
LH8530/LH853t>A
Pin Meaning 'I/O Function

- Channel AI ""
AlB I Channel select signal.
Channel B select
- Active low. Enables the CPU to transmit ,and 'receive
CE Chip enable I
command and data when low.
CTSA
Clear to send I Active low. Enables the respective transmitters.
CTSB
- This signal defines the type of information on the data
D/C Datal control select I
bus. High means data; Low indicates a command.
DCDA
-- Data carrier detect I Active low. Enables the respective receivers.
DCDB
Bidirectional
3-state
DTI3/REQA Data terminal Active low. These outputs follow the state programmed
0
DTR/REQB ready I request into the DTR bit.
Active high. lEI is used to form a daisy chain that deter·
mines the interrupt priority order.
Active high. lEO is used to form a daisy chain that de·
termines the interrupt priority order.
-- Active low, open·drain. Indicates an interrupt request to
INT Interrupt request Open-drain
the CPU.
--- Active low. This signal indicates an active interrupt
acknowledge cycle.
RD Read I Active .low. This signal indicates a read operation.
RXDA
Receive data I Active high. These are receive data lines.
RXDB
RTXCA
- - Receive/transmit clocks I Active low. These are communication clock lines.
RTXCB
RTSA
-- Req uest to send 0 Active low. Goes high after the transmitter is empty.
RTSB
SYNCA Active low. Indicates that a synchronization pattern has
--- Synchronization 1/0
SYNCB been recognized.
TXDA
Transmit data 0 Active high. These are transmit data lines.
TXDB'
TRXCA
- - Transmitl receive clocks 1/0 These are communication clocks.
TRXCB
WR Write I Active low. This signal indicates a write operation.
--- Active low. Operate as request lines when the DMA is
W/REQA
--- Waitl request Open-drain the bus master or as wait lines when the CPU is the bus
W/REQB
master.
Single-phase clock. It does not have to be the CPU clock.,
PCLK Clock I
+5V
From output
Parameter Symbol Ratings Unit +5V
under test 0--.-.-114-..
Input voltage
Output voltage
Operating temperature
VIN
VOUT
Topr
-0.3~+7
-0.3-+7
0-+70
V
V
·C
From output
under test
o--{2.2kO
J;5OpF
Open-drain test load
462
• DC Characteristics (Vcc=5V±5%, Ta=0-+70"C )

Input high voltage VlH 2 Vcc+0.3 V
Output high voltage VOH IOH=-250pA 2.4 V
Output low voltage VOL IOL=+2mA 0.4 V
Input leakage current I hL I 0.4 ;;;; VIN ;;;; 2.4V· 10 pA
Output leakage current I IOL I 0.4 ;;;; VOUT ;;;; 2.4V 10 pA
• Capacitance ( f= IMHz. Ta=O- +70"C )

Output capacitance "COUT Unmeasured Pins Returned to Ground 15 pF
Bidirectional
CliO 20 pF
capacitance
(1) CPU interface timing, interrupt timing, and interrupt acknowledge timing
LH8530 LH8530A
MIN. MAX. MIN. MAX.
1 TwPCl PCLK low width 105 2000 70 1000 ns
6 TsA(WR) Address to WR l setup time 80 80 ns
7 ThA(WR) Address to WR t hold time 0 0 ns
8 TsA(RD) Address to RD l setup time 80 80 ns
9 ThA(RD) Address to RD t hold time 0 0 ns
10 TsIA(pC) INT ACK to PCLK t setup time 0 0 ns
11 TsIAi(WR) INT ACK to WR l setup time 200 .200 ns 1
12 ThIA(WR) INT ACK to WR t hold time 0 0 ns
13 TsIAi(RD) INT ACK to RD l setup time 200 200 ns 1
14 ThIA(RD) INT ACK to RD t hold time 0 0 ns
15 ThIA(PC) INT ACK to PCLK t hold time 100 100 ns
16 TsCEl(WR) CE low to WR l setup time 0 0 ns
17 ThCE(WR) CE to WR t hold time 0 0 ns
18 TsCEh(WR) , CE high to WR l setup time 100 70 ns
19 TsCEl(RD) CE low to RD l setup time 0 0 ns i
20 ThCE(RD) CE to RD t hold time 0 0 ns 1
21 TsCEh(RD) CE high to RD l setup time 100 70 ns 1
22 TwRDl RD low width 390 250 ns 1
23 TdRD(DRA) RD l to read data active delay 0 0 ns
24 TdRDr(DR) RD t to read data not valid delay 0 0 ns
25 TdRDf(DR) RD ! to read data valid delay 250 180 ns
26 TdRD(DRz) RD t to read data float delay 70 45 ns 2
27 TdA(DR) Address required valid to read data valid delay 590 420 ns
28 TwWRI WR low width 390 250 ns
29 TsDW(WR) Write data to WR ! setup time 0 0 ns
.-.--.-----SHARP--..-r---~.-.~-..
463
.Z85~O/Z8530A Serial Communications Controller LH8530/LH8530A
LH8530 LH8530A
No. Symbol Parameter Unit· Note
MIN. MAX. MIN. MAX.
30 ThDW(WR) W rite data to WR t hold time 0 0 ns
31 TdWR(W) WR ! to wait valid delay 240 200 ns 4
32 TdRD(W) RD! to wait valid delay 240 200 ns 4
33 TdWRf(REQ) WR ! to W IREQ not valid delay 240 200 ns
34 TdRDf(REQ) RD ~ to W IREQ not valid delay 240 200 ns
35 TdWRr(REQ) WR t to DTR/REQ not valid delay 5Tcl'Ct300 5TcPCt250 ns
36 TdRDr(REQ) RD t to DTR/REQ not valid delay 5TcPCt300 5TcPCt250 ns
37 TdPC(INT) PCLK ! to INT valid delay 500 500 ns 4
38 TdIAi(RD) INT ACK to RD ! (acknowledge) delay ns 5
39 TwRDA RD (acknowledge) width 285 250 ns
40 TdRDA(DR) RD ! (acknowledge) to read data valid delay 190 180 ns
41 TsIEI(RDA) IEI to RD ! (acknowledge) setup time 120 100 ns
42 ThIEI(RDA) IEI to RD t (acknowledge) hold time 0 0 ns
43 TdIEI(IEO) IEI to IEO delay time 120 100 ns
44 TdPC(IEO) PCLK t to lEO delay 250 250 ns
45 TdRDA(INT) RD ~ to INT inactive delay 500 500 ns 4
46 TdRD(WRQ) RD t to WR ~delay for no reset 30 15 ns
47 TdWRQ(RD)' WR t to RD ! delay for no reset 30 30 ns
48 TwRES WR and RD coincident low for reset 250 250 ns·
49 Trc Valid access recovery time 6TcPCt200 6TcPCt 130 ns 3
Note 1: Parameter does not apply to Interrupt Acknowledge transactions.
Note 2: Float delay is defined as the time required for a ±O.5V change in the output with a maximum DC load and minimum AC load.
Note 3: Parameter applies only between transactions involving the SCC.
Note 4: Open·drain output, measured with open·drain test load.
Note 5: Parameter is system dependent. For any SCC in the daisy chain, TdlAi (RD) must be greater than the sum of TdPC (lEO) for the
highest priority device in the daisy chain, TslEI (RDA) for the SCC, and TdlEIf (lEO) for each device separating them in the daisy
chain.
PCLK
A/B,D/C-J'~~+-____~__-4__________~~~~~~______
INTACK
W/REQ (WAIT)
W/REQ (REQUEST) ________ ~--~~-J
DTR/REQ (REQUEST) ________ ~ ____ ~~~ __ ~ __ ~--J
Read and write timing
. . . . . - . - - - - - - - - - - - - S H A R P -----~---~----
464
Z8530lZ8530A Serial Communications Controller LH8530/LH8530A
PCLK
IN TACK ________~=t~:3~~~------~~~::==~:::
RD
IEI __~~~__~~~.~~________~.~______-
lEO -------"'F-
INT __________________________- J
Reset timing
Cycle timing
(2) System timing

LH8530 LH8530A
MIN. -MAX. MIN. MAX.
1 TdRxC(REQ) RxC t to W IREQ valid delay 8 12 8 12 TcPC 2
2 TdRxC(W) RxC t to wait inactive delay 8 12 8 12 TcPC 1,2
3 TdRxC(SY) RxC t to SYNC valid delay 4 7 4 7 TcPC 2
4 TdRxC(INT) RxC t to INT valid delay 10 16 10 16 TcPC 1,2
5 TdTxC(REQ) TxC ~ to W IREQ valid delay 5 8 5 8 TcPC 3
6 TdTxC(W) TxC ~ to wait inactive delay 5 8 5 8 TcPC 1,3
7 TdTxC(DRQ) TxC ~ to DTR/REQ valid delay 4 7 4 7 TcPC 3
8 TdTxC(INT) TxC ~ to INT valid delay 6 10 6 10 TcPC 1,3
9 TdSx(INT) SYNC transition to INT valid delay 2 6 2 6 TcPC 1
10 TdExT(INT) DCD or CTS transition to INT valid delay 2 6 2 6 TcPC 1
Note 1: Open·drain output, measured with open·drain test load.
Note 3: TxC is TRxC or RTxC, whichever is supplying the transmit clock.
----.-----~---SHARP--.-.-------
465
Z8530/Z8530A Serial Communication Controller LH8530/lH8530A
RTxC, TRxC {RECEIVE)
W/REQ (REQUEST)
W/REQ (WAIT)
SYNC (OUTPUT) ====::::I:=~

INT
RTxC, TRxC (TRANSMIT)
W/REQ (REQUEST)
W/REQ (WAIT)
DTR/REQ(REQUEST)
CTS'DCD@'
SYNC (INPUT) :
INT
--+-----I:.C£~________________ ~~~'
System timing
(3) General timing

LH8530 LH8530A
MIN. MAX. MIN. MAX.
1 TdPC(REQ) PCLK l to W IREQ valid delay 250 250 ns
2 TdPC(W) PCLK l to wait inactive delay 350 350 ns
3 TsRXC(PC) RxC t to PCLK t setup time (PCLK 7 4 case only) 80 70 ns. 1,4
4 TsRXD(RXCr) RxD to RxC t setup time (Xl mode) 0 0 ns 1
5 ThRXD(RXCr) RxD to RxC t hold time (Xl mode) 150 150 ns 1
6 TsRXD(RXCf) RxD to RxC l setup time (Xl mode) 0 0 ns 1,5
7 rhRXD(RXCf) RxD to RxC l hold time (Xl mode) 150 150 n~ 1,5
8 TsSY(RXC) SYNC to RxC t setup time -200 -200 ns 1
9 ThSY(RXC) SYNC to RxC t hold time 3TcPC+200 3TcPC+200 ns 1
10 TsTXC(PC) TxC L to PCLK t setup time 0 0 ns 2,4
11 TdTXCf(TXD) TxC l to TxD delay (Xl mode) 300 300 ns 2
12 TdTXCr(TXD) TxC t to TxD delay (Xl mode) 300 300 ns 2,5
13 TdTXD(TRX) TxD to TRxC delay (send clock echo) 200 200 ns
14 TwRTXh RTxC high width 180 180 ns' 6
15 TwRTXI RTxC low width 180 180 ns 6
16 TcRTX RTxC cycle time 400 400 ns 6
17 TcRTXX Crystal oscillator period 250 1000 250 1000 ns 3
18 TwTRXh TRxC high width 180 180 ng- ,3
19 TwTRXI TRxC low width 180 180 ns 6
20 TcTRX TRxC cycle time 400 400 ns 6
21 TwEXT DCD or CTS pulse width 200 200 ns
22 TwSY SYNC pulse width 200 200 ns
~'---~'-'---SHARP .-~-.....-.-----.-.--
466
Note 1: RxC is RTxC or TRxC. whichever is supplying the receive clock.

Note 2: TxC is TRxC or RTxC. whichever is supplying the transmit clock.
Note 3: Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
Note 4: Parameter applies only if the data rate is one· fourth the PCLK rate. In all other cases. no phase relationship between RxC and
PCLK or TxC and PCLK is required.
Note 5: Parameter applies only to FM encoding/decoding.
Note 6: Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK
requirements.
PCLK
W /REQ (REQUEST)
Vi /REQ(WAIT) _ _ _ _-=:-~-------'.
RTxC, TRxC(RECEIVE) _ _ _..."...,.....J['1
. RxD ____~~~~~~-~~~--~--------
SYNC (EXTERNAL)
----J~--~r---~'~-----------------
TRxC, RTxC (TRANSMIT)
. -----j
TxD ~@==-:ii 1<""---"';'-~-.I '-_ ____
TR.C (OU:E~ ESj,,----.~ ---J~ .

CTS,DCD ~ ~ 1-
-------........., i-@--i k=@~
SYNC (INPUT) ~ ~ 1~------
, i--@----I i:=@~
General timing
~~....-.--------SHARP-.---.-.-.---
467
, ................._-_............................................._,._.......................
ZS,5301Z8530A Serial Communications Contr.oIler LH8530/LH8530A
• Data Communications Capabilities first secondary station by the same process. Any
The LH85'30 provides two independ~nt fullduplex secondary stations without messages to send merely
channels programmable for use in any common echo the incoming messages and are prohibited from
Asyncl1ronous or Synchron~)Us data communication placing messages on the loop (except upon recogniz-
protocol. Fig. 1 illustrates th~se protocols. ing an EOP).
SDLC Loop mode is a programmable option in the
LH8530. NRZ, NRZI, and FM coding may all be used
START in SDLC Loop mode.
1
PARITY
l~TOP
lli&ilJ
::":M'"="A":::R':':KI::"N:-::G:-IW@[]jl@illjr-DA
....r-Ar"T"I"Ij II
LINE
I SYNC IDATA I
ASYNCHRONOUS
::
MONOSYNC
IDATAI CRe, I CRC, I -----
. CONTROLLER
~IS-:-Y-NC~I-SY-N-C-rID~A....T....:1\TI~:; IDATAI CRC, I CRC, I

SIGNAL~YNC
~:~~I-:::DA~T~A~I....c~R~C~d....C-:::RC~,~I
EXTERNAL SYNC
Ir.:F=-LA-:-G=-I""AD--DR--ESS-.!~INFqRM.1 CRC, I CRc,lFLAGI
SDLC/HDLC/X.25
Fig. 1 Some see protocols

Fig. 2 An SOLe loop
• SDLC Loop Mode

The LH8530 supports SDLC Loop mode in addi-
tion to normal SDLC. In an SDLC Loop, there is a • Data Encoding
primary controller station that manages the message Tile LH8530 may be programmed to encode and
traffic flow on the loop and any number of secondary decode the serial data in four different ways
stations. In SDLC Loop mode, the LH8530 per- (Fig. 3). In NRZ encoding, a 1 is represented by a
forms the functions of a secondary station while an High level and a 0 is represented by a Low level. In
LH8530 operating in regula~ SDLC mode can act as NRZI encoding, a 1 is represented by no change in
a controller (Fig. 2). level and a 0 is represented by a change in level. In
A secondary station in an SDLC Loop is alway FMi (more properly, bi-phase mark), a transition
listening to the messages being sent a~ound the loop, occurs at the beginning of every bit cell. A 1 is rep-
and in· fact must pass these messages to the rest of resented by an additional transition at the center of
the loop by retransmitting them with a one-bit-time the bit cell and a 0 is represented by no additional
delay. The secondary station can place its own mes- transition at the center of the bit cell. In FMO (bi-
sage on the loop only at specific times. The con- phase space), a transition occurs at the beginning of
troller signals that secondary stations' may transmit every bit cell. A 0 is represented by an additional
messages by sending a special character, called an transition at the center of the bit cell, and a 1 is rep-
EOP (En,d Of Poll), around the loop. The EOP char- resented, by no additional transition at the center of
acter is the bit pattern 11111110. Because of zero the bit cell. In addition to these four methods, the
insertion during messages, this bit pattern is unique LH8530 can be used to decode Manchester (bi-phase
and easily recognized. . level) data by using the DPLL in the FM mode and
When a secondary station has a message to trans- programming the receiver for NRZ data. Manches-
mit and recognizes an EOP on the line, it changes ter encoding always produces a transition at the
the last binary 1 of the EOP to a 0 before trans- center of the bit cell. If the transition is 0 to 1, the
mission. This has the effect of turning the EOP bit is a o. If the transition is 1 to 0, the bit is a 1.
into a flag sequence. The secondary station now
places its message on. Hie 10QP and terminates the
message with an EOP. Any secondary stations
further down the lO\Jp with Ijlessages to transmit can
then append their messages to the message of the
468
~~~ .....
~~.....,~ ............... ...............- .....
~
LH8530/LH8530A
~
time constant may be changed at any time , but the
DA T A -...:.'-----'''----. o new value does not take effect until the next load
NRZ ~______~
of the counter.
NRZI The output of the baud rate generator may be
FMl used as either the transmit clock, the receive clock,
or both. It can also drive the Digital Phase-
FMO Locked Loop (see next section).
MAN-
If the receive clock or transmit clock is not
CHESTER
programmed to come from the TRxC pin, the out·
Fig. 3 Data encoding methods
put of the baud rate generator may be echoed out
via the TRxC pin.
The following formula relates the time constant
• Auto Echo and Local Loopback
to the baud rate (the baud rate is in bitsl second
The LH8530 is capable of automatically echoing
and the BR clock period is in seconds).
everything it receives. This feature is useful
mainly in Asynchronous modes, but works in Syn- 1
baud rate
chronous and SDLC modes as well. In Auto Echo 2(time constant +2) X(BR clock period)
mode, TxD is RxD. Auto Echo mode can be used
• Digital phase-Locked Loop
with NRZI or FM encoding with no additional de-
The LH8530 contains a Digital Phase-Locked
lay, because the data stream is not decoded before
Loop (DPLL) to recover clock information from a
retransmission. In Auto Echo mode, the CTS in-
data stream with NRZI or FM encoding. The
put is ignored as a transmitter enable (although
DPLL is driven by a clock that is nominally 32
transitions on this input can still cause interrupts
(NRZI) or 16 (FM) times the data rate. The DPLL
if programmed to do so). In this mode, the trans-
uses this clock, along with the data stream, to con-
mitter is actually bypassed and the programmer is
struct a clock for the data. This clock may then
responsible for disabling transmitter interrupts
be used as the SCC receive clock, the transmit
and WAIT IREQUEST on transmit.
clock, or both.
The LH8530 is also capable of local loopback.
For NRZI encoding, the DPLL counts the 32X
In this mode TxD is RxD, just as in Auto Echo
clock 60 create nominal bit times. As the 32X
mode. However, in Local Loopback mode; the in-
clock is counted, the DPLL is searching the incom·
ternal transmit data is tied to the internal receive
ing data stream for edges (either 1 to 0 or 0 to 1).
data and RxD is ignored (except to be echoed out
Whenever an edge is detected, the DPLL makes a
via TxD). The CTS and DCD inputs are also
count adjustment (during the next counting cycle),
ignored as transmit and receive enables. However,
producing a terminal count closer to the center of
transitions on these inputs can still cause inter·
the bit cell.
rupts. Local Loopback works in Asynchronous,
For FM encoding, the DPLL still counts from 0
Synchronous and SDLC modes with NRZ, NRZI or
to 31, but with a cycle corresponding to two bit
FM coding of the data stream.
times. When the DPLL is locked, the clock edges
in the data stream should occur between counts 15
• Baud Rate Generator and 16 and between counts 31 and O. The DPLL
Each channel in the LH8530 contains a prog-
looks for edges only during a time centered on the
rammable baud rate generator. Each generator
15 to 16 counting transition.
consists of two 8·bit time constant registers that
The 32X clock for the DPLL can be programmed
form a 16·bit time constant, a 16·bit down coun-
to come from either the RTxC input or the output
ter, and a flip· flop on the output producing a
of the baud rate generator. The DPLL output may
square wave. On startup, the flip-flop on the out-
be programmed to be enchoed out of the LH8530
put is set in a High state, the value in the time con-
via the TRxC pin (if this pin is not being used as
stant register is loaded into the counter, and the
an input).
counter starts counting down. The output of the
baud rate generator toggles upon reaching 0, the
value in the time constant register is loaded into
the counter, and the process is repeated. The
...--....-.------SHARP--------
469
Z8530/Z8530ASeriai Communicatipns· Controller LH8530/LH8530A
• Read Regi/sters
• Read Register 0 • Read Register to
Rx CHARACTER
AVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD o
SYNC/HUNT LOOP SENDING
CTS o
Tx UNDERRUN /EOM TWO CLOCKS MISSING
BREAK/ABORT ONE CLOCK MISSING
• Read Register 1 • Read Register 12
I~I~I~I~I~I~I~I~I
RESIDUE CODE 0 [ LOWER BYTE OF

RESIDUE CODE 1 TIME CONSTANT
RESIDUE CODE 2
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)
• Read Register 2 • Read Register 13
ID7 ID6 1 Ds 1 D. 1 D3 1 D2 1 DIlDo 1 I D71 D6 1 Ds I D. I D3 I D2 I DII Do I

[ INTERRUPT VECTOR" [UPPER BYTE OF
TIME CONSTANT
"MODIFIED IN CHANNEL B
• Read Register 3· • Read Register 15
CHANNEL B
EXT/STAT Ip·
o
ZERO COUNT IE
CHANNEL B Tx IP"
CHANNEL B Rx Ip·
o
DCD IE
CHANNEL A EXT/STAT IP" SYNC/HUNT IE
CHANNEL A Tx Ip·
CTS IE
CHANNEL A Rx Ip·
TxUNDERRUN/EOMIE
o BREAK/ABORT IE
·ALWAYS 0 IN CHANNEL B
--------SHARP--------
470
.28530/Z8530A Serial Communications Controller LH8530/LH8530A
• Write Registers
• Write Register 0 • Write Register 2
D7 D6 D5 D. D3 D2 Dl Do
I~I~I~I~I~I~I~I~I
0 0 0 REGISTER 0
0 0 1 REGISTER 1 [INTERRUPT
0 1 0 REGISTER 2 VECTOR
0 1 1 REGISTER 3
1 0 0 REGISTER 4
1 0 1 REGISTER 5
1 1 0 REGISTER 6 • Write Register 3
1 1 1 REGISTER 7
0 0 0 REGISTER 8
0 0 1 REGISTER 9
0 1 0 REGISTER 10
0 1 1 REGISTER 11 * Rx ENABLE
1 0 0 SEGISTER 12
1 0 1 REGISTER 13 SYNC CHARACTER LOAD INHIBIT
1 1 0 REGISTER 14 ADDRESS SEARCH MODE (SDLC)
1 1 1 REGISTER 15 Rx CRC ENABLE
ENTER HUNT MODE
0 0 0 NULL CODE AUTO ENABLES
0 0 1 POINT HIGH
0 1 0 RESET EXT /STAT INTERRUPTS o 0 Rx 5 BITS/CHARACTER
0 1 1 SEND ABOR T (SDLc) o 1 Rx 7 BITS/CHARACTER
1 0 0 ENABLE INT ON NEXT Rx CHARACTER 1 0 Rx 6 BITS/CHARACTER
1 0 1 RESET TxIN T PENDING 1 1 Rx 8 BITS/CHARACTER
1 1 0 ERROR RES ET
1 1 1 RESET HIG HEST IUS
0 0 NULL CODE
0 1 RESET Rx CRC CHECKE R
1 0 RESET Tx CRC GENERA TOR • Write Register 4
1 0 RESET Tx UNDERRUN/E OM LATCH
·WITH POINT HIGH COMMAND (D 5D.D3=00I)
D7 D6 D5 D. D3 D2 Dl I Do I
L Lp ARITY ENABLE
PARIT Y EVEN/ODD
1 1
0 0 SYNC MO DES ENABLE
0 1 1 STOP BIT /CHARACTER
1 0 11/2 STOP BITS/CHARACTER
EXT INT ENABLE 1 1 2 STOP BITS/CHARACTER
Tx INT ENABLE 0
0 8 BIT SYNC CHA RACTER
PARITY IS SPECIAL CONDITION
0 1 16 BIT SYNC CH ARACTER
o 0 Rx INT DISABLE 1 0 SDLC MODE (011 11110 FLAG)
o ~R I§lJ'A~'i'AtI~~~8fi.1~~CTER 1 1 EXTERNAL SYN C MODE
I-"--t-"-O"WRT SO::E~h.LL RCOCNHD1~tocNTERS
1 1 Rx!NT ON SPECIAL CONDITION 0 0 Xl CLOCK MODE
L.....:O....L.....::.....JONLY
WAIT/DMA REQUEST ON RECEIVE/TRANSMIT 0 1 x16 CLOCK MODE
1 0 X32 CLOCK MODE
WAIT/DMA REQUEST FUNCTION
WAIT/DMA REQUEST ENABLE 1 1 X64 CLOCK MODE
-~-~----SHARP'-'---------'
471
Z85.30/Z8530A Serial Communications Controller ,LH8530/LH8530A
Tx CRC ENASLE
RTS
SDLC/CRC·16
Tx ENABLE
SEND BREAK
Tx 5 BITS (OR LEssl/CHARACTER
~-+-7-I
1---:'--+-7-1 Tx 7 BITS/CHARACTER
1, 0 Tx 6 BITS/CHARACTER
1 1 Tx 8 BITS/CHARACTER
DTR
Write Register 6
ID,I"' I D'~' ID~", ID, ID.I

I I I I I I
. SYNC 7 SYNC,
I
SYNCs SYNC. SYNC3 SYNC2
I SYNC!
1
SYNCo MONOSYNC, 8 BITS
SYNC! SYNCo SYNCs SYNC. SYNC3 SYNC2 SYNC! SYNCo MONOSYNC, 6 BITS
SYNC7 SYNCs SYNCs SYNC. SYNC3 SYNC2 SYNC! SYNCo BISYNC, 16 BITS
SYNC3 SYNC2 SYNC! S.YNCo 1 1 1 1 BISYNC, 12 BITS
ADR7 ADRs ADRs ADR. ADR3 ADR2 ADRI ADRo SDLC,8 BITS
ADR7 ADRs ADRs ADR. x x x x SDLC,4 BITS
(ADDRESS RUN)
ID, ID.I D'~<I D~' ID, ID·I

I I I I I I
SYNC7 SYNCs
I
SYNCs SYNC. SYNC3
I
SYNC2 SYNC! SYNCo MONOSYNC, 8 BITS
SYNCs SYNC. SYNC, SYNC2 syNc! SYNCo X x MONOSYNC, 6 BITS
SYNC!s SYNC 14 SYNC;3 SYNC!2 SYNCll SYNC!o SYNCg SYNCs BISYNC, 16 BITS
SYNCI! . SYNC!o SYNCg SYNCs SYNC7 SYNCs' SYNCs SYNC. BISYNC, 12 BITS
0 1 1 1 1 1 1 o SDLC FLAG
472
Z8530/Z8530A Serial Communic~ions Controller LH8530/LH8530A
• Write Register 9 • Write Register 12
I D7 ID6 I Ds I D. IDa I D2 I DJ I Do I
NV
VIS
I
LOWER BYTE OF TIME CONSTANT
DLC (IEO="Low")
MIE
STATUS HIGH/STATUS LOW
o • Write Register 13
o 0 NO RESET
o 1 CHANNEL B RESET
o CHANNEL A RESET I~I~I~I~I~I~I~I~I
1-='-+--=-1-1 FORCE HARDWARE RESET
I
UPPER BYTE OF TIME CONSTANT
\
Write Register 14
I D7 D6 Ds D. I D3 I D2 I DJ IDo I D7 I D6 I Ds I D. I 0 3 I D2 I DJ I Do I
LL~
6 BIT /8 BIT SYNC
P MODE
,-ABORT/ FLAG ON UNDERRUN
L BRG'-BR GENERATOR ENABLE
ENERATOR SOURCE
=PC LK/RTxC PIN INPUT
_DTR/RE QUEST
'--MARK/FLAG IDLE FUNCTI ON
......AUTO ECHO
-GO ACTIVE ON P OLL
'-LOCAL LOOPBAC K
0 0 NRZ
0 0 0 NULL COMMAND
0 1 NRZI
0 0 1 ENTER SEARCH MO DE
1 0 FMl (TRANSITION = 1) 0 1 0 RESET MISSING CL OCK
1 1 FMO (TRANSITION = 0) 0 1 1 DISABLE DPLL
"-,CRC PRESET I/O 1 0 0 SET SOURCE = BR GENERATOR
1 0 1 SET SOURCE = --C
RTx
1 1 0 SET FM MODE
1 1 1 SET NRZI MODE
Write Register 15
I D7 D6 Ds D. D3 D2 DJ Do'
I I
0 0 TRxC OUT=XTAL OUTPUT
0 1 TRxC OUT = TRANSMIT CLOCK o
1 0 11IxC 00f= BR GENERATOR 00I'IUl'
1 1 TRxC OUT = DPLL OUTPUT o
'-- TRxC 0 /1 DCD IE
SYNC/HUNT IE
0 0 TRANSMIT C LOCK = RTxC PIN CTSIE
0 1 TRANSMIT C LOCK = TRxC PIN Tx UNDERRUN /EOM IE
1 0 TRANSMIT CLOCK = BR GENERATOR OUTPUT BREAK/ABORT IE
1 1 TRANSMIT CL OCK = DPLL OUTPUT
0 0 RECEIVE CLOCK = RTxC PIN

0 1 RECEIVE CLOCK = T RxC PIN
1 0 RECEIVE CLOCK = BR GENERATOR OUTPUT
1 1 RECEIVE CLOCK = D PLL OUTPUT
' - - RTxC XTAL/NO XTAL
473
Z8536/Z8536A Counter/Timer and Parallel 110 Unit LH8536/LH85.36A
LH8536/LH8536A
CounterlTimer and Parallel 110 Unit
Z8536/Z8536A
The LH8536 Z8536 CIO Counter/Timer and /'
Parallel I/O element is a general-purpose 03
peripheral circuit, satisfying 1I10st counter/timer 0 .02
and parallel 110 needs encountered in system
designs. This versatile device contains three I/O 01
ports and three counter/timers. Many progrllmm- Do
able options tailor its configuration to specific CE
'applications. The use of the device is simplified Ao
by making all internal registers (command, status, Al
and data) readable and (except for status bits) PAo
writable. In addition, each register is given its
PAl
own unique internal address, so that any register
can be acces\ed in two operations. All data regis-
ters can be directly accessed in a single opera- PA3
tion. The LH8536 is easily interfaced to all popular PA.
microprocessors_ PAs
The LH8536A Z8536A CIO is the high speed PAs
version which can~ operate ,at 6 MHz system clock. PA7
INTACK
INT
• Features +5V
PC3
1. Two independent 8-bit,' double-buffered,
bidirectional 110 ports plus a 4-bit special-
purpose 110 port. 110 ports feature pro- Top View
grammable polarity, programmable direction
(Bit mode),"pulse catchers," and progra1l1I1labie
open drain outputs.
2. Four handshake modes, including 3-Wire (like
the IEEE-488).
3. REQUEST /W AIT signal for high -speed data
transfer.
4. Flexible pattern-recognition logic, program-
mable as a "l6-vector interrupt controller.
5. Three independent 16-bit counter/timers with
up to four external access lines per counter /
timer (count input, output, gate, and trigger),
and three output duty cycles (pulsed, one-shot,
and squarewave), programmable as retrigger-
able or nonretriggerable.
6. Easy to use since all registers are read/write.
--~--""-'--SHARP""'-'-''---'-'-,'-'
474
• Block Diagram
Interrupt Enable In
Interrupt Enable Out Interrupt
Control
Interrupt Req~est Logic
Data Bus
Read
Write
An
AI
Chip Enable
Clock
GND Port B
+5V
• Pin Description
Ao. Al Address select I Register select lines
- Active low. A low level on this input enables the CIO to
CE Chip enable I
be read from or written to.
Bidirectional
Do-D 7 Data bus System data bus
3-state
Active high. lEI is used to form an interrupt daisy chain
IEI Interrupt enable input I
which determines the interr1)pt priority order.
Active high. lEO is used to form an interrupt daisy
chain which determines the interrupt priority order.
-- Active low. open-drain. Indicates an interrupt to the
CPU.
--- Active low. Indicates that an interrupt acknowledge cy·
cle is in progress.
Bidirectional
PA o-PA 7 I/O ·port lines Parallel 110
3-state
Bidirectional
PB o-PB 7 liD port lines Parallel I/O
3-state
Bidirectional
PC O-PC 3 I/O port lines Parallel I/O
3-state
RD Read I Active low. Indicates that a CPU is reading.
WD Write I Active low. Indicates that a CPU is writing.
PCLK Clock I Single-phase clock. It does not have to be the CPU clock.
475
Z8536/Z8536A Couter/Timer and Parallel I/O Unit LH8536/LH8536A
. ' Absolute Maximum Ratings

Input voltage VIN -0.3-+7 V 1
Output voltage VOUT -0.3-+7 V 1
Note 1: The maximum applicable voltage on any pin ,with respect to GND.
+5V +5V
~'2kfl
2.2kfl .
From output
under test O-......_.-Jo.-~
From output
under test
;+;50PF
Standard test load Open-drain test load
• DC Characteristics (Vcc=5V±5%. Ta=0-+70·C )

Input high voltage VIH 2 Vcc+0.3 V
Output high voltage VOH IOH=-250pA 2.4 V
IOL=2mA 0.4 V
IOL=3.2mA 0.5 V
Input leakage current I hL I 0.4 ;£ VIN ;£ 2.4 V 10 pA
Output leakage current I IOL I 0.4 ;£ VOUT;£ 2.4V 10 pA
• Capacitance (f=IMHz.,Ta=0-+70·C)

Unmeasured Pins
Returned to Ground
Bidirectional capacitance CI/O 20 pF
(1) CPU interface timing, interrupt timing, and interrupt acknowledge timing
LH8536 LH8536A
No. Symbol Conditions Unit Note
MIN. MAX. MIN. MAX.
2 TwPCh PCLK width (high) 105 2000 70 2000 ns
3 TwPCI PCLK width (low) 105 2000 70 2000 ns
6 TsIA(PC) INT ACK to PCLK t setup time 100 100 ns
7 ThIA(PC) INT ACK to PCLK t hold time 0 0 ,', ns
8 TsIA(RD) INT ACK to RD l setup time 200 200 ns
9 ThIA(RD) INT ACK to RD t hold time 0 0 ns
10 TsIA(WR) INTACK to WR l setup time 200 200 ns
-----.--~-------SHARP ----------
476
Z8536/Z8536A Counter/Timer and Parallel I/O Uuit LH8536/LH8536A
LH8536 LH8536A
MIN. MAX. MIN. MAX.
11 ThIA(WR) INTACK to WR t hold time 0 0 ns
12 TsA(AD) Address to RD ! setup time 80 80 ns
13 ThA(RD) Address to RD t hold time 0 0 ns
14 TsA(WR) Address to WR ! setup time 80 80 ns
15 ThA(WR) Address to WR t hold time 0 0 ns
16 TsCEI(RD) CE low to RD ! setup time 0 0 ns 1
17 TsCEh(RD) CE high to RD ! setup time 100 70 ns 1
18 ThCE(RD) CE to RD t hold time 0 0 ns 1
19 TsCEI(WR) CE low to WR! setup time 0 0 ns
20 TsCEh(WR) CE high to WR ! setup time 100 70 ns
21 ThCE(WR) CE to WR t hold time 0 0 ns
22 TwRDl RD low width 390 250 ns 1
23 TdRD(DAR) RD ! to read data active delay 0 0 ns
24 TdRDf(DR) RD ! to read data valid delay. 255 180 ns
25 TdRDr(DR) RD t to read data not valid delay 0 0 ns
26 TdRD(DRz) RD t to read, data float delay 70 45 ns 2
27 TwWRI WR low width 390 250 ns
28 TsDW(WR) Write data to WR ! setup time 0 0 ns
29 ThDW(WR) W rite data to WR t hold time 0 0 ns
31 TdPM(INT) Pattern match to INT delay(bit port) 2+800 2 ns 6
32 TdACK(INT) ACKIN to INT delay(port with handshake) 10+600 10 ns 4,6
33 TdCI(INT) Counter input to INT delay(counter mode) 2+700 2 ns 6
34 TdPC(INT) PCLK to INT delay(time mode) 3+700 3 ns 6
35 TsIA(RDA) INT ACK to RD ! (acknowledge)setup time 350 250 ns 5
36 TwRDA RD(acknowledge)width 350 250 ns
37 TdRDA(DR) RD ! (acknowledge)to read data valid delay 250 180 ns
,
38 TdIA(IEO) INT ACK ! to lEO ! delay 350 250 ns 5
39 TdIE(IEO) lEI to lEO delay 150 100 ns 5
,
40 TslEl(RDA) lEI to RD ! (acknowledge) setup time 100 70 ns 5
41 ThlEl(RDA) lEI to RD t (acknowledge) hold time 100 70 ns
42 TdRDA(INT) RD ! (acknowledge)to INT t delay 600 600 ns
Note 1: Paramater does not apply to, Interrupt Acknowledge
transactions.
Note 2: Float delay is measured to the time when the output has
changed 0.5 V with minimum AC load and maximum DC
load. '
Note 3: Trc is the specified number or 3 TcPC, whichever is
longer. ".
Note 4: The delay is from DAV l for 3·Wire Input Handshake.
The delay is from DAC t for 3·Wite OutP~t Hand·
shake.
Note 5: The parameters for the devices in any particular daisy
chain must meet the following constraint: The delay
from INT ACK l to RD l must be greater than the
sum of TdIA(IEO)for the highest priority peripheral.
TsIEI(RDA)for the lowest priority peripheral, and
TdIEI(lEO)for each peripheral separating them in the
chain,
Note 6: Units are equal to TcPC plus ns.
477
Z8536/Z8536A Counter/Ti~er and pa:r~lIell/OUnit"', , LH853EVLH8536A
PCLK
{fl ®
®,
eD
®
"
,',
,@®
INTACK
Do-D7 (WRITE) _ _ _ _J
CE I l~
RD or WR .JI+.::-.::---------.;-\=~~@_-_-..J-r-'
-,-~--~~,
"':"':':--
Interface timing
PATTERN MATCH~
Pattern matches
INPUT(S)
BIT PORT
._
-----®----.~I ---:----:---
ACKIN --..!:.::~~-
Note 4 ~------oj-------
, COUNTER _ _ _J
INPUT ~_~:§@~=~_ _ _ _ __
PCLK
Interrupt timing
478
....., ....
.Z8536/Z8536A Counter and Parallel 110 Unit
.....,..-.....,.....,
INTACK
.........,...... .... ..-
LH8536/LH8536A
.....,..-.---.....,..--
Do-D1
IEI ______~~~~~~-4--------~f~----__
lEO ------JI"'--- 1\._+-_____________

-@1---

LH8536 LH8536A
MIN. MAX. MIN. MAX.
1 TsDI(ACK) Data input to ACKIN ~ (DA V ~ ) setup time a a ns
Data input to ACKIN ~ hold time strobed.
2 ThDI(ACK) ns
handshake
3 TdACKf(RFD) ACKIN ~ (DA V ~) to RFD ~ delay a a ns
4 TwACKI ACKIN low width strobed handshake ns
5 TwACKh ACKIN high width strobed handshake ns
6 TdRFDr(ACK) RFD t to ACKIN l (DAV l) delay a a ns
7 TsDO(DAV) Data out to DA V l setup time 25 2a ns 1
8 TdDAVf(ACK) DAV l to ACKIN l delay a a ns
9 ThDO(ACK) Data out to ACKIN 'l hold time 2 2 ns 2
1a TdACK(DAV) ACKIN l to DAV t delay 2 2 ns 2
Data input to RFD ~ hold time interlocked
11 ThDI(RFD) ns
handshake
RFD ~ to ACKIN t delay interlocked hand-
12 TdRFDf(ACK) a a ns
shake
ACKIN t (DA V t) to RFD t delay interlock-
13 TdACKr(RFD) a a ns
ed and 3-wire handshake
DA V t to ACKIN t (RFD t) interlocked and
14 TdDAVr(ACK) a a ns
3-wire handshake
ACKIN t (RFD. t ) to DAV ~ delay 'inter-
15 TdACK(DAV) a a ns
locked and 3-wire handshake
16 TdDA VIf(DAC) DAV l to DAC t delay input 3-wire handshake a a ns
17 ThDI(DAC) Data input to DAC t hold time 3-wire handshake a a ns
DAC t to DAV t delay input 3-wire hand-
18 TdDACOr(DA V) a, a ns
shake
19 TdDA Vlr(DAC)
DAV t to DAC l delay input 3-wire hand-
a a ns
shake
DAV l to DAC t delay output 3-wire hand-
2a TdDAVOf(DAC) a a ns
shake
Data output to DAC t hold time 3-wire hand-
21 ThDO(DAC) 2 2 ns 2
shake
DAC t to DAV t delay output 3-wire hand-
22 TdDAClr(DA V) 2 2 ns 2
shake
DAV t to DAC l delay output 3-wire hand-
23 TdDA VOr(DAC) a a ns
shake
Note 1: This time can be extended through the use of deskew timers.
Note 2: Units equal to lfcPC.
~..-..------SHARP-"":-------'-'
479
Z8536/Z8536A Counter/Timer and Parallel I/O Unit .LH8536/lH8536A
DATA ~.
.. Data va.lid ~_ _ _ _ _ _ _ _ _ _ _ _ __
----Jl=m @~' ~_____ @____~~I
ACKIN
-----.I
INPUT (INPUT)
RFD
(OUTPUT)
DATA
f-----@-----I
ACKIN
OUTPUT (INPUT)
DAV
(OUTPUT)
Strobed handshake
DATA
ACKIN
INPUT (INPUT)
RFD
(OUTPUT)
DATA Data valid
ACKIN
OUTPUT (INPUT)
DAV
(OUTPUT)
Interlocked handshake
--~------------SHARP----~---------
480
DATA
DAV ----~I
(INPUT)
INPUT
RFD ------+--,J
(OUTPUT)
DAC
(OUTP_UT...;..) _ _ _ _ _J
DATA
DAC
(INPUT-')_ _-+_ _ _ _I
OUTPUT
RFD
(INPUT)
DAV ---...;...~
(OUTPUT)
3-wire handshake
(3) Counter/timer timing

LH8536 LH8536A
MIN. MAX. MIN. MAX.
1 TcCI Counter input cycle time 500 330 ns
2 TClh Counter input high width 230 150 ns
3 TWCIi Counter input low width 230 150 ns
4 TfCI Counter input fall time 20 15 ns
5 TrCI Counter input rise time 20 15 ns
6 TsTI(PC) Trigger input to PCLK ~ setup time (timer mode) ns 1
7 TsTI(CI) Trigger input to counter input ~ setup time (counter mode) ns 1
8 TwTI Trigger input pu!se width (high or low) ns
9 TsGI(PC) Gate input to PCLK .~ setup time (timer mode) ns 1
10 TsGI(CI) Gate input to counter input ~ setup time (counter mode) ns 1
11 ThGI(PC) Gate input to PCLK ~ hold time (timer mode) ns 1
12 ThGI(CI) Gate input to counter input ~ hold time (counter mode) ns 1
13 TdPC(CO) PCLK to counter output delay (timer mode) ns
14 TdCI(CI) Counter input t to counter output delay (counter mode) ns
Note 1: These parameters must be met to guarantee trigger or gate are valid for the next counter/timer cycle.
----.-----------SHARP.-.-.-----~
481
Z8536/Z8'536A Counter/Timer and Parallel 110 Unit LH8536/LH8536A
PCLK
PCLK/2
(INTERNAL) _ _ _--'
COUNTER
INPUT
TRIGGER
INPUT
GATE INPUT
OUTPUT ----------------------------~.~--
COUNTER ____________________________ J~~--
Counter/timer timing
/
• Functional Description
(1) 1/0 port operations

Of the LH8536 three I/O ports, two (Ports A (2) Bit port operations
and B) are general purpose, and the' third (Port C) . In bit port'operations, the port's Data Direction
is a special purpose 4-bit port. Ports A and B can register specifies the direction of data flow for
be configured as input, output, or bidirectiqnal each bit. Port C has the additional feature of bit-
ports with' handshake. (Four different handshakes addressable writes. When writing to Port C, the
are available.) They can also be linked to form a four most siJnificant' bits are used as write protect
single 16-bit port. If they are not used as ports mask for the least significant bits (0·4, 1-5, 2-6,
with handshake" they provide. 16 input or output and 3-7). If the write protect bit is written with a
bits with the data direction programmable on a bit- 1, the state of the corresponding output bit is not
by-bit ba~is. Port B also provides access for Coun- changed.
ter/Timers 1 and 2. In all configurations, ports A The capability of inverting the data path can be
and B 'can be programmed to recognize specific provided, and output can be specified as open-
datC'l patterns and to generate interrupts 'Yhen the drain.
pattern is encountered. . (3) ,Ports with handshake operation
The four bits of, Port C provide the handshake Ports A and B can be specified as 8-bit input,
lines for Ports A and B when required. A RE- output, or bidirectional ports with handshake. The
QUEST /W AIT line ·can al~o be provided so that LH8536 provides four, different handshakes for its
LH8536 transfers can be synchronized with DMAs ports: Interlocked, Strobed, Pulsed, and 3-Wire.
or CPUs; Any Port C bits not used for handshake or The port can be set as if it is only single-b1:lffered.
REQUEST/WAIT can be used as input or, output This 'is useful if the handshake line must be stopped
bits (individually data-direction programmable)' or on a byte-by-byte basis.
external aCCeSS lines for Counter/Timer 3. Port C Ports A and B can be linked to form a 16-bit
does not contain any pattern'recognition logic. It is, . port.
howe~er, capable of bit-addressable writes. With this In this mode, Post A must be specified for hand-
feature, any combination of bits can beset and/or shake, and Port B must be specified as a bit port.
cleared while the other bits remain undisturbed with- When linked, only Port A has pattern-match capa-.
olit first reading the register. bility. Port B'g. pattern match capabiliy, must be
disabled. '
482
Table 1 Port C bit utilization

Port AlB Configuration PCa PCz PC, PCo
Port A and B: Bit port Bit 110 Bit 110 Bit 110 Bit 110
Port A: Input o,r output port
-- REQUEST IW AIT(O)
(interlocked, strobed, or pulsed RFD or DAV(O) ACKIN(I) Bit 1/0
or Bit 110
handshake)
Port B: Input or output port
REQUEST IW AIT(O) ACKIN
(interlocked, strobed, or pulsed Bit 110 RFD or DAV(O)
or Bit 110 (I)
handshake)
Port A or B: Input porJ (3·wire -- REQUEST /W AIT(O)
RFD(O) DAV(I) DAC(O)
Port A or B: Output port (3·wire REQUEST /W AIT(O)
DAV(O) DAC(I) RFD(I)
Port A or B: Bidirectional port
RFD or DAV(O)
--
ACKIN(I)
REQUEST /WAIT(O) -IN/OUT(I/O)
(interlocked or strobed handshake) or Bit 110
* Both Ports A and B can be specified input or output with Interlokced, Strobed, Pulsed Handshake. at'the same time if RFQUESTlW AlT.
. (4) Interlocked handshake

In the Interlocked handshake mode, the action of INPUT HANDSHAKE
the LH8536 must be acknowledged by the, external
device before the next action can take place. Fi· DATA ~~______________
gure 1 shows timing for Interlocked Handshake.
An output port does not indicate that new data is . ACKIN
(INPUT) STROBED HAND j
available until the external device indicates it is RFD ---t-"o<:::\ SHAKE-Y--- -.,.---
read>:, for the data. Similarly, an input port does not (OUTPUT) DATA MOVEDINTERLOCKED
indicate that it is ready for new data until the data DATA LATCHED TO INPUT HANDSHAKE
IN BUFFER REGISTER
source indicates that the previous byte of the data REGISTER
is no longer available, thereby acknowledging the
. input port's acceptance of the last byte. This allows OUTPUT HANDSHAKE
the LH8536 to interface directly to the port of a Z8
microcomputer, a UPC, an FlO, an FIFO, or to
another CIO port with no external logic.
DA fA
ACKIN
---1 NEXT BYTE
DESKEW TIME Jfr----
i A 4·bit deskew timer can be inserted in the Data (INPUT)
Available (DA V) output for output ports. DAV ,
The deskew timer guan,mtees that the output (OUTPUT) LSTROBED
data is valid for a specified minimum amount of BUFFER NEXT BYTE HANDSHAKE
REGISTER SHIFTED FROM
time. "EMPTIED" OUTPUT REGISTER TO
, Deskew timers are available for output ports in· BUFFER REGISTER
dependent of the type of handshake employed.
Fig.1 Interlocked and strobed handshakes
(5) Strobed handshake.
In the Strobed handshake, mode, data is "strobed~'
into or out of the port by the external logic. Fig. 1
shows timing for the Strobed handshake. IN contrast
to the Interlocked handshake, the signal indicating
the port is ready for another data transfer operates
independently of the ACKIN input. It is up to the ex-
ternal logic to ensure that data oyerflows or under·
flows do not occur.
~.-----....--.-SHARP-.---------
483
Z8536/Z8535ACounter/Timer and Parallel 1/0 Unit . . LH85361LH8q36A
(6) 3-wlre handsha~e . . . counter/timer is linked to /the handshake logic.

The 3-wire handshake is designed for the ~itua- ' The counter/timer maintjlins all of its n:ormal
tion in which one output port' is communicating' capabilities. This handshake is not available for
with many input ports simultaneously. It is essen: bidirectional ports.
tially the' same as the lnterlocked handshake, ex-
cept that two signals are used to indicate if an input. INPUT PORT
port is ready for new data or if it has accepted the
'present data (Fig. 2). With the 3-wire handshake, ACKIN ACKIN
the output lines of many input ports can be bussed
together with open-drain drivers; the output port
OUTPUT PORT
knows when all the ports have accepted the data
and are ready. This is the same handshake as is __ ~TRIGGER COUNTER~ _ ' _
used on the IEEE-488 bus. Because this handshake DA V ' INPUr OUTPUT . D AV
_ C/T3 . .
requires three lines, only one port (either A or B)
Fig. 3 Pulse handshake
can be a 3:wire handshake port at a time. The 3-
wire handshake is not available for the bidirectional
mode. Because the port's direction can be changed (8) Pattern-recognition logic operation
under software control, however, bidirectional IEEE- Both Ports A and B can be programmed to
488·type transfers can be performed. generate interrupts when a specific pattern is rec-
ognized at the port. The pattern:recognition logic
INPUT HANDSHAKE is indePendent of the port application, thereby
allowing the port to recognize patterns in all of its
DATA ~~____________ configurations.. The pattern can be independently
DAV
specified for each bit as 1, 0, rising edge, falling
(INPUT) edge, or any transition. Individual bits may be
RFD ---'-+1""'- masked off.
(OUTPUT) ~ ____+-__.J DATA SHIFTED
TO INPUT (9) Bit port pattern-recognition operations
DAC REGISTER
During bit port 'operations, pattern-recognition
(OUTPUT)
may be performed on all bits, including those used
as 110 for the counter/timers.
The pattern-recognition logic of bit ports oper-
OUTPUT, HANDSHAKE ates in two basic modes: transparent and latched.
In transparent mode, the interrupt indicates that a
DATA ____________~,~N~E~X~T~B_Y~T_E_ specified pattern has occurred~ but a read of the
RFD Data register does not necessarily indicate that
(INPUT) --:--:-:::-=-:::~---J state of the port' at the time the interrupt was
DAC , generated. In the Latched mode, the state of all the
(INPUT)
port inputs at the time the interrupt was generated
DAV is latched in the input register and held until IP is
(OUTPUT) NEXT BYTE cleared.
BUFFER REGISTER SHIFTED FROM (10) Counter/timer operation
"EMPTIED" OUTPUT REGISTER TO
BUFFER REGISTER The three independent 16-bit counter/timers
consist of a presettable Hi-bit down counter, a 16'
Fig.2 3-wire handshake bit Time Constant register, a 16-bitCurrent Coun-
ter register, an 8·bit Mode Specification register,
(7) Pulsed handshake an ,8-bit Command and Status register, and the
The Pulsed handshake (Fig. 3) is designed to in- associated control logic that links these registers.
terface to mechanical-type devices that require The flexibility of the counter/timers is enhanced
data to be held for long periods of time and need by ,the provision of up to four lines per counter/
relatively wjde pulses to gate the data into or out timer (counter input, gate input,. trigger input, and
of the device. The logic is the same as the Inter· counter/timer output) for direct external control
locked handshake mode, except that an internal and status. Counter/Timer l's external I/O lines are
-------I------SHARP,--~.---~--
484
Z8536/Z8536A Couner/Timer and Parallel 1/0 Unit LH8536/LH8536A
provided by the four most significant bits of port B. 2's trigger, gate, or counter input.
Counter/Timer 2's are provided by the four least When linked, the counter/timers have the same
significant bits of Port B. Counter/Timer 3's external capabilities as when used separately. The only res-
110 lines are provided by the four bits of Port C. The triction is that when Counter/Timer 1 drives
utilization of these lines (Table 2) is programmable Counter 2's count input, Counter/Timer 2 must be
on a bit-by·bit basis via the Counter/Timer Mode programmed with its external count input disabled.
Specification registers. There are three duty cycles available for the
timer / counter output: pulse, one-shot, and square-
Table 2 Counter/timer external access wave. Fig. 4 shows the counter/timer waveforms.
CIT! C/T2 C/T3
Counter/timer operations require loading the
Function
PB4 PBo PCo
time constant value in the Time Constant register
Counter ITimer Output
PBI PCI
and initiating the countdown sequence by loading
Counter Input PB5
PBG PB2 PC2
the down-counter with the time constant value.
Trigger Input
PB7 PB3 PC3
The Time Constant register is accessed as two 8-
Gate Input
bit registers. The registers are readable as well as
Lines used for counter/timer 110 have the same writable, and the access order is irrelevant.
characteristics as simple input lines, they can be Once the down-counter is loaded, the countdown
specified as inverting or noninverting; they can be sequence continues toward terminal count as long
read and used with the pattern· recognition logic. as all the counter/timers' hardware and software
They can also include the 1 's catcher input. gate inputs are High. If any of the gate inputs Low
Counter/Timers 1 and 2 can be linked inter· (0), the countdown halts. It resumes when all gate
nally in three different ways. Counter/Timer l's inputs are 1 again.
output (inverted) can be used as Counter/Timer.
PCLK/2aR~~
caUNTERINPUT .
TRIGGER ~
-------, fI
GATE
L-J TC
! TC / TC-l/TC-l!TC-2/ .... I I ! all
PULSE OUTPUT r-l
--------Irr------J '--
ONE SHOT OUTPUT ,I
SQUARE WAVE OUTPUT

(FIRST HALF) - - - - - - - - - - - - - 1 ( 1 1 - 1_ _.....J
SQUARE WAVE OUTPUT - - - - - - - - - - - - - - - f f l f f - - - - - - ,
(SECOND HALF)
Fig.4 Counter/timer waveforms
485
, , , ," , , ". \ ,
Z8636/4853SA C.ount~r/Timer and Parallel 1/0,Unit LH8536/LH8536A'
• Internal Registers
The followings, illustrate the contents of the
registers and, In addition, given to register,
address summary.
• Master Interrupt Control Register (MICR)
AIIdress : 000000
(Read/Write)
I'~I~I~I~I~I~I~I~I
MASTERmTERRUPT~
ENABLE (MfE)
DISABLE LOWER CHAIN (DLC)
I I I LL= ,
ILRESET
LRIGHT JUSTiFIED ADDRESSES
0= Si-lIFT LEFT (Ao from AD!)
NO VECTOR (NV) 1 = RIGHT JUSTIFY(Ao from ADo)
COUNTER/TIMERS VECTOR
PORT A VECTOR INCLUDES
STATUS (PA VIS) INCLUDESSTATUS(CT VIS)
PORT B VECTOR INCLUDES _ _ _ _ _----'
STATUS (PB VIS)
• Master Configuration Control Register (MCCR)
Address: 000001
( Read/Write)
PORT B ENABLE (PBE).J

COUNTER/TfMER 1 ENABLE (CT,IE),
dJj I
I D( I D61 D51 D.I D31 D2ID! I Do COUNTER/TIMER
~ LINK CONTROLS (LC)

LCI LCO
- 0 -0- COUNTER/TIMERS INDEPENDENT
COUNTER/TIMER 2 ENABLE (CT2E) 0 1 CIT l's OUTPUT GATES CIT 2
PORT C AND COUNTER/TIMER 3 ENABLE 1 0 CIT 1> OUTPUT TRIGGE~S CIT 2
(PCE AND CT3E) ,1 CIT 1 s OUTPUT IS CIT 2 s
COUNT INPUT
PORT A ENABLE (PAE)
PORT LINK CONTROL (PLC)
0= PORT,S A AND B OPERATE INDEPENDENTLY
1 = PORTS A AND B ARE LINKED
• Port Mode Specification Register (PMSR)

101000 Port B
(Read/Write)
1
1
PORT TYPE
PTS 1 PTS 0 SELECTS {PT
o 0 BIT PORT
o 1 INPUT PORT
0 OUTPUT PORT
I~I~I~I~I~I~I~I~I
~J
1 BIDIRECTIONA L PORT
INTERRUPT ON TWO BYTES '(ITB)
1L
PMSI
LATCH ON PATTERN MATCH (LPM)
BIT MODE)
DESKEW TIMER ENABLE (DTE)
HANDSHAKE MODES)
PATT:ERN MODE SPECIFICATION BITS (PMS)
P MS'O
SINGLE BUFFERED MODE (S B) 0 --DISABLE
0 PATTERN MATCH
INTERRUPT ON MATCH ,ONL Y IMO) 0 1 "AND"MODE
1 1 "OR" MODE
1 1 " OR PRIORITY ENCODED
~~~~~,~'-~SHARP~~~--'-""""'-----
. ,
VECTOR" MODE
486
• Port Handshake Specflcation Registers (PHSR)
'Addressess : 100001 Port A

101001 Port B
HTSI
HANDSHAKE TYPE ----'-T
SPECIFICATION BITS (HTS)----.J
HTSO
--
(ReadIWrite)
I~I~I~I~I~I~I~I~I
DESKEW TIME SPECIFICATION
I
L---BlTS
SPECIFIES THE MSB's OF
DESKEW TIMER TIME CONSTANT.
o o INTERLOCKED HANDSHAKE LSB IS FORCED 1.
o 1 STROBED HANDSHAKE REQUEST/WAIT SPECIFICATION BIT(RWS)
1 o PULSED HANDSHAKE RWS 2 RWS 1 RWS 0 FUNCTION ..
1 1 THREE-WIRE HANDSHAKE --0- --0- -O-REQUESTIWAIT DISABLED
o 0 1 OUTPUT WAIT
o 1 1 INPUT WAIT
1 0 0 SPECIAL REQUEST
1 0 1 OUTPUT REQUEST
1 1 INPUT REQUEST
• Port Command and Status Registers (PCSR)
Addresses: 001000 Por A

001001 Por B
. ID71 D61 Dsl D.I D31 D21Dl Do II

INTERRUPT UNDER
SERVICE (IUS)--"
INTERRUPT ENABLE (IE)
I
I I III L,NTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
• INTERRUPT PENDING (Ip) (READ ONLY) .
IUS. IE·, AND IP ARE WRITTEN INPUT REGISTER FULL (IRF)
USING THE FOLLOWING CODE: (READ ONLY)
OUTPUT REGISTER EMPTY (ORE)
NULL CODE 0 0 0 (READ ONLY)
'-------INTERRUPT ERROR (ERR)
CLEAR IP & IUS 0 0 1 (READ ONLY)
SETIUS 0 1 0
CLEAR IUS 0 1 1
SET IP 1 0 o·
CLEARIP 1 0 .1
SET IE 1 ~ 0
CLEAR IE 1 1 1
. \ .
~'-~--'-----SHARP'----'-'---""--
487
~
•
........... -
Z8~6iz8536A6dunt~r/Timer and
---.....
Data Path Polarity Registers (DPPR)
...,............-.
Parallel' I/O Unit
•
_
..... ...............
ilH8536/lH8536A
Special 1/0 Contr.ol Registers (SIOCR)

101010 Port B
101100 Port B
000101 Port C (4 LS B s only) 00Q111 Port C (4 LSBs only)
(Read;Write)
(Read/Write)
I~I~I~I~I~I~I~I~I 1~1~1~1~1~1~1~1~1
I. , i
DATA PATH POLARITY (DPP) SPECIAL INPUT/OUTPUT (SIO)
0= NON-INVERTING 0= NORMAL INPUT OR OUT PUr
1 = INVERTING . 1 = OUTPUT WITH OPEN DRAIN -OR
INPUT WITH I's CATCHER
• Port Data Registers (PDR)
Addresses: 001101 Port A"

• Data Direction Registers (DDR) 001110 Port B"
(Read/Write)

101011 Port B
000110 Port C (4 LSBs only)
• Port C Data Registers (PC DR)
( Read/Write)
Address: 001111"
( Read/Write)
I
DATA DIRECTION (DD)
0= OUTPUT BIT
1 = INPUT BIT
"These registers can be addressed directly.
4 MSBs
o= WRITING OF CORRESPONDING LSB ENABLED
1 = WRITING OF CORRSPONDING LSB INHIBITED
(READ RETURNS 1)
• Pattern Polarity Registers (PPR)
Addresses :·100101 Port A
101101 Port B I D71 Dol Dsl D41 D31 D,I 011 Do I
(Read/Write) 1
• Pattern Transition Registers (PTR)
Addresses: 100110 Port A PM PT PP PATTERN SPECIFICATJ4)N

101110 PortB o 0 X BIT MASKED OFF
(Read/Write) o 1 X ANY TRANSITION
o 0 (iERO
o lONE
.1 1 0 ONE TO ZERO TRANSITION(~)
• Pattern Mask Registers (PMR) 1 1 1 ZERO-TO-ONE TRANSITION (l')
Addresses: 100111 Port A.

101111 Port B I~I~I~I~I~I~I~I~I
( R ead/W rite) ·LI____
-------~SHARP-.-------.-. ........... -~
488
• Counter/Timer Command Status Registers (CTCSR)

Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2,
001100 Counter/Timer 3
( ead/Partial Write)
I~I~I~I~I~I~I~I~I
(IUS) ~I ~ COUNT IN
~
INTERRUPT UNDER
SERVICE PROGRESS (CIP)
(READ ONLY)
INTERRUPT ENABLE (IE)-- TRIGGER COMMAND BIT (TCB)
. . (WRITE ONLY READ RETURNS 0)
INTERRUPT PENDING (IP) GATE COMMAND BIT (GCB)
IUS, IE, AND IP ARE WRITTEN
USING THE FOLLOWING CODE: ' - - - - - - READ COUNTER CONTROL (RCC)
(READ/SET ONLY -
NULL CODE 0 0 0 CLEARED BY READING CCR LSB)
CLEAR IP & IUS 0 0 1 ' - - - - - - - - - INTERRUPT ERROR (ERR)
SET IUS 0 1 0 (READ ONLY)
CLEAR IUS 0 1 1
SET IP 1 0 0
CLEARIP 1 0 1
SET IE 1 1 0
CLEAR IE 1 1 1
• CounterlTimer Mode Specifications Registers (CTMSR)
Addresses: 011100 Counter/Timer 1

011101 Counter/Timer 2
Counter/Timer 3
(Read/Write)
. I~I~I~I~I~I~I~I~I
CONTINUOUS SIN-
GLE CYCLE (C/SC)
J JI 1\ ---,-OUTPUT DUTY CYCLE
L....SELECTS (DCS)
EXTERNAL OUTPUT ENABLE (EOE) DCS 1 DCSO
EXTERNAL COUNT ENABLE (ECE) 0 0 PULSE OUTPUT
EXTERNAL TRIGGER ENABLE (ETE) 0 lONE-SHOT 0lJ TPUT
EXTERNAL GATE ENABLE (EGE) 1 0 SQUARE-WAVE OUTPUT
l I D O NOT SPECIFY
RETRIGGER ENABLE BIT (REB)
• CounterlTimer Current Count Registers (CTCCR)
Addresses: 010000 Counter/Timer l's MSB

010001 Counter/Timer l's LSB
010010 Counter/Timer 2' s MSB
010011 Counter/Timer 2' s LSB
010100 Counter/Timer 3' s MSB
(Read Only)
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I
MOST SIGNIFICANT BYTE-------'I IL-----LEAST SIGNIFICANT BYTE
489
Z85361Z8536A
, Counter1Timer and Parallel 110 Unit LH8536/LH85.36A
• C6unterITimer Time Constant Registers (CiTCR)
Addresses: 010110 Counter/Timer l's MSB

010111 Counter/Timer l's LSB
011000 Co~nt~r/Timel' 2' s MSB
. 011010 Counter/Timer 3' s MSB
(Read/Write)
I D71 D61 D51 D.I D31 D21 DII Do I D71 D61 D51 D41 D31 D21 DI I Do I
MOST SIGNIFICANT BYTE I L-,--LEAST SH;NIFICAi-n BYT~
• Interrupt Vector Register (lVR) • Counter/Timer Status
Addresses: 000010 Port A 01

• D2 ..
000011 Port B 0 0 C/T3

000100 Counter/Timers 0 1 C/T2
(Read/Write) 1 0 CITI
1 1 Error
I~I~I~I~I~I~I~I~I
I
INTERRUPT VECTOR
• Port Vector Status • Current yector Register (CVR)
(1) Priority Encoded Vector Mode

.Address : 011111
(Read only)
x X X Number of highest priority bit with a match
10 71 0 61 D51 D41 031 021 DilDo I
(2) All Other Mode I
INTERRUPT VECTOR BASED
ON HIGTEST PRIORITY
ORE IRF PMF Normal UNMASKED IP.
IF .NO INTERRUPT PENDING.
o 0 0 Error ALL 1's OUTPUT.
490

The LH8571 (SPCC71) is a peripheral interface
device for general purpose microcomputer systems -+5V RxD
with two main control functions for an RS232C in- PCLK 2
o TxD
terface and Centronics interface, all within a single
DTR
LSI chip.
The LH8571 provides a serial port for transfer- CTS
ring data in asynchronous mode-and an 8-bit para- DCD
llel port with handshaking function as a Centronics INTACK 6 RTS
interface. RD 7 SLCT
The LH8571 has 24 commands for controlling INPUT PRIME
these ports. The commands not oI?ly control the op- BUSY
eration of RS23.2C teminal units and printers, but FAULT
CS
handle various utilities (e.g.,code conversion) neces-
GND ACKNLG
sary for these units. Accordingly, the CPU needs
WAIT DATA STROBE
merely to specity an operation through the com-
mands, thus significantly reducing the CPU's load _ DB7 DATAs
in handling 110 units through the program, and DB6 DATA7
eventually reducing the amount of memory needed DB5 DATA6
for storing the program. DB. DATAs
The LH8571 controls the peripheral unit control DATA.
DBa
lines (e.g.,RTS and CTS of RS232C interface)
DB2 DATAa
according to the status oj the units, instead of by
software control from the CPU. Consequently, the DBI DATA2
system designer can configure the interface merely DBo DATAl
by connecting buffer devices and connectors. Top View
• Features
1. Asynchronous data transfer serial port
• RS232C interface can easily be realized.
2. Printer control parallel port
• Centronics interface can easily be realized.
3. Data transfer and conversion functions by com-
mand.
• 24 commands.
4. Data conversion function .
• Serial parallel conversion.
• Binary-ASCII conversion.
• Intel hex, format acceptable for data input/
output. ,
5. 128-byte data transfer bufter.
• Useful for the serial port and parallel port.
6. Non-multiplexed bus interface.
7. 40-pin dual-in-line package.
8. Single + 5V power s~pply.
491
Serial Parallel Combination Controller , LH8571
• Block Diagram
Data Bus Data Bus
Internal
Control Logic
Chip
Interrupt Request 5 Buffer

Interrupt Acknowledge 6 128
Interrupt Enable In 4 Bytes
492
• Pin Description
Bidirectional
DBo-DB7 Data bus System data bus
3-state
AID Address/ data select I Address/ data select signal
RD Read I Active low. Indicate the system in read operation.
WR write I Active low. Indicate the system in write operation
WAIT Wait 0 Active low, open-drain. Used to synchronize with CPU.
-- Active low, open-drain. Indicate interrupt request to
INT , Interrupt request 0
input.
IEI Interrupt enable input I
DATA1-DATA g Output data 0 Output data
DATA STROBE Data strobe 0 Active low. Indicate settlement of data.
SLCT Select I Active low. Printer selection signal.
RxD Received data I Receiving data line.
RTS Transmission request 0 Active low. Indicate readiness for dflta transmission.
DTR Data'terminal ready 0 Active low. Data transmission request signal.
PCLK Clock I Single-phase clock. Need not be same as CPU clock.

Input voltage * VIN -0.3-+7 V
Output voltage * VOUT -0.3-+7 V
Storage temperature Tstg -65-+150 "C
* The maximum applicable voltage on any pin with respect to GND.
+5V
From output
under test
Standard test load
---------~--.---SHARP ---.------.-,
493
Parameter Symbol Test Conditions MIN. MAX. Unit

Clock input low voltage VCL -0.3 '0.8 V
Input high voltage VlH 2 Vee V
Output high voltage VOH IOH=-250,..A 2.4 V
Output low voltage VOL IOL=2mA 0.4 V
Input leakage curreot I IIL I 0;;;; VIN;;;;5.25V 10 ,..A
Output leakage current IloL I 0;;;; VIN;;;;5.25V 10 ,..A
Current consumption Ice 250 mA
(1) CPU interface timing (Vee=5V±5%, Ta=0-+70t)
No. Symbol Parameter MIN. MAX. Uoit Note

4 TwCI Clock pulse width, low 105 os
6 TsAlD(WR) AID setup time to WR ~ 80 ns
7 TsAlD(RD) AID setup time to RD ~ 80 os
8 ThAlD(WR) AID hold time from WR t 30 ns
9 ThAlD(RD) AID hold time from RD t 30 os
10 TsCSf(WR) CS low setup time to WR ~ 0 os
11 TsCSf(RD) CS low setup time to RD ~ 0 os
12 TsCSr(WR) CS high setup time to WR ~ 60 ns
13 TsCSr(RD) CS high setup time to RD ~ 60 ns
14 ThCS(WR) CS low hold time from WR t 0 ns
15 ThCS(RD) CS low hold time from RD t 0 ns
16 TsDI(WR) Written data setup time to WR ~ 0 ns
17 Tw(WR) WR pulse width 390 ns
18 Tw(RD) RD pulse width 390 ns
19 ThWR(DI) W ritteo data hold time from WR t 0 ns
20 TdRD(DI) Delay time from RD ~ to valid data os 1
21 ThRD(DI) Written data hold time from RD t 0 ns
22 TdRD(DIz) Delay time from RD t to data bus floating 70 ns
23 TdRD(DBA) Delay time from RD ~ to readout data settlement 0 os
24 TdWR(W) Delay time from WR ~ to W AIT ~ 150 ns
25 TdRD(W) Delay time from RD ~ to W AIT ~ 150 ns
26 TdDI(W) Delay time from valid data to WAIT t 0 ns
Note : All AC output characteristics are based on the stated load conditions.
Note 1: The delay time depends on the device status at the time of access by CPU.
494
PCLK
AID
DB o -DB 7
Write
DB o-DB 7 ----------+-----~~-I~
Read ~~--_+--""fI1

27 TsACK(RD) INT ACK low setup time to RD ! 90 ns 2
28 TdRD(DI) Delay time from RD ! to valid vector 255 ns
29 ThRD(ACK) lNT ACK low hold time from RD t 0 ns
30 ThIEI(RD) IEI hold time from RD t 100 ns
31 TwRDI RD (Acknowledge) low pulse width 255 ns
32 TdIEI(IEO) Delay time from IEI to lEO 120 ns
33 TslEl(RD) IEl setup time to RD ! 150 ns
34 TdACK(IEO) Delay time from INT ACK ! to lEO ! 250 ns
35 TdADKr(IEO) Delay time from lNT ACK hoIEO t 250 ns
Note 2: Interrupt arbitration loop circuit (daisy chain) is not used.
Vector )
\
I--@ @i- f- -
INTACK I
~@-
~
-®j @--..
f--- @-
lEI -K
rE-@~ I---@l----oo
~.
lEO 1( \ 7
---.-.----~--SHARP --.----------------
495
Serial Parallel Combination Controller , LH8Sn
(3) Reset timing
No. Symbol , .Parameter MIN. MAX. Unit Note

36 TdRDQ(WR) Delay time from,RD t (for suppressing reset) to WR l 40 ns
37 TdWRQ(RD) Delay time from WR t (for suppressing reset) to, RD l ' 50 ns
38 TwRES Minimum low width of WR and RD(for resetting) 250 ns 3
Note 3: The internal reset signal lags by 1/2 to 2 clocks behind external reset conditions.
Reset timing

No. Symbol Parameter Note,
39 TdTxC(T"xD) Delay time from sending clock transition to output data transition 4
Note 4: Applies to all baud raets (110·9800 B)
TxC /
k I
TxD
===========@=~------------ Serial port timing

No. Symbol Parameter MIN. 'MAX. Unit Note
40 TdACK (D) Delay from ACKNLG l to data output 13000 18000 ns
41 TdD(DSTR) Delay from data output to DATA STROBE l 6000 ns
42 TwDSTR DATA STROBE pulse width 6000 ns
ACKNLG
DATAl
\
DATA. K
DATA STROBE
"'"
"-"
,
~
f-@- f--@...
496
• Register Table 1 Register address

The LH8571 has the following registers which Register Register address
can be accessed externally (from CPU). DSCO X X XOOOOO
• Master interrupt control register (MIC) DSCI X X XOOOOI
• Data indirect register (DIND) DSC2 X X XOOOI0
• Data status command registers (DSCO, DSC3 X X X 00011
DSCl, DSC2, DSC3, DSC4, DSC5 and DSC4 X X XOOI00
DSC8) DSC5. X X XOOI0l
DSC8 X X XOI000
DIND X X X 10101
MIC XXXI1110
Note: A7-A, is decoded and applied to CS, so that the loca-
tion in the input/output address space is determined.
Bits marked by 'x' are undefined.
DSC31 D71 D61 Ds I D.I D3 I D21 DJ I Do I

-,-,-,---,- L
01 Buffer overflow
1 0 Input characters are other than 0 - F .
(Intel format only)
11 Check -sum error (Intel format only)
o 1 Printer unselect
1 0 Printer paper out Cexternal" circuit required)
11 Printer fault
T ransf er error
Limit error
Parity error
I llegal command
Fig. 1 Error flag (DSC3)
Table 2 MIC register write code

The master interrupt control register (MIC) is
Group 2 . G~oup 1
used to control the interrupt operation (see Fig. Function
D7 D6 Ds D2 Do
2). Writing into the MIC register falls into two
0 0 0 X X Writing to Do and D2
groups. Group 2 uses the write code shown in
0 0 1 0 0 Reset IP CDs) and IUS CD 6 )
Table 2.
0 1 0 0 0 Set IUS CD 6)
0 1 1 0 0 Reset IUS CD 6 )
1 0 0 0 0 Set IP CDs)
1 0 1 0 0 Reset IP CDs)
1 1 0 0 0 Set IE (D7)
1 1 1 0 0 Reset IE CD 7)
497
Serial Parallel Combination Controller· LH8571
1TT.
MIC L::::II=E:-,-II=U=sl~I=P:-LI_J.-...-"§==L=CJ...1~IC=S-:TI
-
T ~Command execution start
Lower chaining prohibited
L - - - - - - - - - - I n t e r r u p t holding
Interrupt under service
Interrupt enabled
Fig.2 Master interrupt control register
• Programming
Use the registers, DSCO, DSCl, DSC2, DSC3, format using DSC2 (Fig. 3).
DSC4, DSC5, and DSC8, to specify operation mode. The result of command execution is indicated on
The 24 types of commands are made valid by first DSCO and DSC3. DSC3 indicates error status as
writing a value corresponding to the desired com- shown in Fig. 1. DSC8 is used as a buffer register
mand number into DSCO, then setting the CST bit after command 22 or 23 is executed.
on MIC. The registers DSCl, DSC2, DSC4, and Tables 3 and 4 show command functions versus
DSC5 are used to specify parameters f()r each com- registers.
°
mand. Command is used inspecifying serial data
ooc21~1~1~1~1~1~1~1~1
- - -:,-r-
T T. Parity mode
o :Even parity
1 : Odd parity
Number of data bits

o : 7 bits
1 : 8 bits
'-----~--- Baud rate (see Note)
000 : 1l0B
001 : 150B
010 : 300B
011 : 600B
100 : 1200B
101 : 2400B
110 : 4800B
111:9600B
' - - - - - - - - - - - - N u m b e r of stop bits of transmission

o : 1 bit
1 : 2 bits
' - - - - - - - - - - - - - I n t e r r u p t mode
o : Interrupt enabled
1 : Interrupt disabled
' - - - - - - - - - - - - - - - E c h o back
o : Echo back mode
1 : Echo back disabled
Note: The baud rate described above is for PCLK=4.0MHz
Fig. 3 Serial data format (DSC2)
498
Table 3 Command function and writing register contents
~
Code Parameter
Function Remarks
Command DSCO DSCI DSC2 DSC4 DSC5
Transfer for·
Specify transfer format
0 OOH mat and oper·
and operating mode.
ating mode
Output serial·input data to
Stop character is spe·
1 01H Stop character Centronics printer until
cified by DSC2.
the stop character arrives.
Operaion stops upon de·
Number of Output serial·input data to
2 02H tection of Control C (hex
output bytes Centronics printer.
03).
Output buffer area con·
Number of Load address Load address Address information
3 03H tents to serial port in Intel
output bytes (high order byte) (low order byte) of data is appended.
format
Read Intel format data on
4 04H serial port and store in
buffer area.
Number of Initialize block transfer
5 05H bytes of block between master CPU and
transfer buffer area.
Operation stops upon de·
Number of Output starting Output data in buffer area
6 06H tection of Control C (hex
output bytes address via serial port.
03).
Operation stops upon de·
Number of Output starting Output data in buffer
7 07H tectiOD of Control C (hex
output bytes address area to printer
03).
Convert binary data
Number of Output starting in buffer area into
8 08H
output bytes address ASCII and output via
serial port.
Convert binary data
Number of Output starting Display address Display address in buffer area into Address information
9 09H
output bytes address (high order) (low order) ASCII and output via of data is appended.
serial port.
Convert binary data
Number of Output starting in buffer area into
10 OAH
output bytes address ASCII, and output to
printer.
Convert binary data
Number of Output starting Display address Display address in buffer area into Address information
11 OBH
output bytes address (high order) (low order) ASCII, and output to of data is appended.
printer.
Read ASCII data on se·
Number of Nunber of
12 OCH rial port and store in
iutput bytes output bytes
buffer area.
Read Intel format data Used when a reader
13 ODH on serial port and store is connected to serial
in buffer area. port.
.-....-------SHARP-.-~~-----
499
~
Code Parameter
Function Remarks
Command DSCO DSCI DSC2 DSC4 DSC5
Read ASCII data on serial After CR reception, CR
14 OEH Output character port until arrival of CR and LF codes are sent
code. out via serial port.
Convert data in buffer
Number of Load address Load address area into Intel format, Used when a puncher is
15 OFH
output bytes (low order byte) (high order byte) and output via serial connected to serial port.
port.
Read binary data on Used when a reader
Number of
16 10H Output character serial 'port into bufferis connected to serial
input bytes
area for storage. port.
, Output data in buifer area
Used when a puncher is
Number of Output starting via serial ports. connected to serial port.
17 11H
output bytes address Opertion stops upon detec·
tion of hex 03.
Output null codes via 256 null codes out·
IS 12H
serial port. putted.
Output EOF in Intel for·
19 13H mat ( : 00000001 FF) via
serial port.
Used when a puncher
Output null codes via
20 14H is connected to serial
serial port.
port.
Output EOF in Intel for· Used when a puncher
21 15H mat ( : 00000001 FF) via is connected to serial
serial port. port.
Read I-byte data on Data is stored in
22 I6H
serial port. DSCS.
Output data written Data needs to be set
23 17H in DSCS by CPU via in DSCS prior to ex-
serial port. ecution.
--.-.--------SHARP----.-.-.-.---
500
Table 4 Register contents after command execution (readout register)
~
Code Parameter
DSCO
DSCI DSC2 DSC3\ DSC4 DSC5
Cornman 1* 2* 3*
0 00 80 COH Error status flag
1 01 81 Cl~ Error status flag
2 02 82 C2~ Error status flag
3 03 83 C3H Error status flag
Number of bytes Load address Load address
input+20H (high order byte) (low order byte)
7 07 87 C7~ Error status flag
8 08 88 C8.H Error status flag
10 OA 8A CA~ Error status flag
11 OB 8B CB~ Error status flag
12 OC 8C CCH Error status flag
Number of bytes Load address Load address
13 OD 8D CDH Error status flag
input+20H (high order byte) (low order byte)
Number of bytes
14 OE 8E CEH Error status flag·
input+20H
15 OF 8F CFA Error status flag
16 10 90 DOH Error status flag
17 11 91 DIH Error status flag
18 12 92 D2H Error status flag
Note 1: 1 *:Value before command execution (command Note 3: If FAULT input becomes low (printer error) during
code value) command execution, LH8571 suspends operation un·
2 *: Value upon normal completion of command ex· til FAULT returns to high (error recovery). At this
ecution. time, DSCO has bit 6 set and bit 7 reset.
3 *:Value upon abnormal completion (error) of
command execution.
These are common to all commands.
Note 2: For error status flag value, see Fig.I.
501
Serial Parallel Combination Controller
.-..-..-..-..-..-..-.....,.-:...,. ... _.... __ .....,.-.
LH8572·
.-..

The LH8572 (SPCC72) is a peripheral device
for general purpose microcomputer systems to per- RxD
form asynchronous serial data tansfers and con- o TxD
trol of Centronics compatible printers.
It supports full duplex asynchronous serial data DTR
transfers. The transfer conditions such as the CTS
baud rate and character length can be set by the OCD
program. Further, it is equipped with a control 1/ RTS
o terminal for simple organization of the various NC
types of modem interfaces. The Receive Buffer INPUT PRIME
has a double buffer structure so that the master BUSY
CPU can easily perform reading and writing of
CS FAULT
data.
A printer control 1/0 terminal is available for GND ACKNLG
easy connection to any printer which is Centronics WAIT DATA STROBE
compatible. A handshake line and control for other DB, DATAs
I/O lines is supported. A 128-byte printer data DB6 DATA,
buffer memory having an· FIFO structure is pro- DB5 DATAs
vided within the LH8572. Efficient use of the DB4 DATA5
printer unit by the master CPU is made possible
DB3 DATA4
with this buffer.
hi this way, the LH8572 peripheral device for DB2 DATA3
general-purpose microcomputers, was developed to DB! DATA2
efficiently perform serial data transfer and printer DBo DATA!
output control within a compact package. It is
Top View
suitable for use in small systems such as personal
computers which use printer units, RS232C ter-
minal units and modem units.
.2. Centronics Compatible Printer Control

• Features . • Furnishes printer interface signals compati-
1. Asynchronous Full Duplex Data Transfer ble with Centronics specifications
• Character length of 5 to 8 bits • Built-in handshake fUnction for data output
• 1 or 2 stop bits • Internal buffer: 128-byte FIFO structure
• No parity bit or oddleven parity • Error detection: Printr fault error/Paper
• False start bit or rejection (rejects spike empty error
noise in the mark line to prevent malfunc- 3. Vector Interrupt'
tion.) • Able to generate an interrupt on various
• Full duplex conditions such as Transmit Buffer empty,
• Transmit buffer has double structure. validity of received character, and Printer
.; Receive buffer has FIFO structure. Output Buffer empty.
• Error detection function, Parity error detec- • Interrupt vectors for Transmit, Receive,
tion, Framing error detection, and Overrun Printer and Error detection can be set indi-
error detection vidually.
• Baud rates: 75, 110, 150, 300, 600, 1200, 4. Non-multiplexed bus interface
2400, 4800 baud selectable 5. 40-pin dual-in-line package
502
• Block Diagram
Internal
Data Bus Control Logic Data Bus
<Il
ERR U
MSR
CTL
'!:"
o
TxS U
"
v
Print RxS
Chip FIFO
128Bytes
PRS
TxB
RxB
PRB
Interrupt Request
------------SHARP---~----
503
Seria Parallel Combination Controller LH8572
• Pin Description
Pin ·Meaning I/O Function
Bidirectional
DBa-DB? Data bus System data bus
3-state
AID Address/ data select I Address/ data select signal
WR Write I Active low; Indicate the system in write operation.
WAIT Wait 0 Active low, open-drain. Used to synchronize with CPU
-- Active low, open· drain. Indicate interrupt request to
CPU.
DATA 1 -DATA 8 Output data 0 Output data
DATA STROBE Data strobe 0 Active low. Indicate s.ettlement of data.
RxD Receiving data line I Receiving data line.
TxD Transmitted data 0 Transmitting data line
RTS Transmission request 0 Active low. Indicate readiness for data transmission.
DTR Data terminal ready 0 Active low. Data transmission request signal.
PCLK Clock I Single· phase clock, need not be same as CPU clock.
+5V
Input voltage * VIN -0.3-+7 v
Output voltage* VOUT -0.3-+7 V From output
Operating tern perature, ·C under test
Topr 0-+70
* The maximum applicable voltage on any pin with respect
to GND.
Standard test load
.-.-.-.-----SHARP----------~
504
• DC Characteristics (Vee=5V±5%, Ta=0-+70·C)
Parameter Symbol Conditions MIN. MAX. Unit Note

Input high voltage VIH 2 Vee V
Output high voltage VOH IOH = - 250 f1A 2.4 V
Input leakage current t hL t 0;;;;; VIN;;;;; 5.25V 10 f1A
Output leakage current t IOL t 0;;;;; VIN;;;;; 5.25V 10 f1A
(1) CPU interface timing

4 TwCl Clock pulse width, low 105 ns
6 TsAlD(WR) AID setup time to WR t 80 ns
7 TsAlD(RD) AID setup time to RD ~ 80 ns
8 ThA/D(WR) AID hold time from WR t 30 ns
9 ThA/D(RD) AID hold time from RD t 30 ns
10 TsCSf(WR) CS low setup time to WR ~ 0 ns
11 TsCSf(RD) CS low setup time to RD ~ 0 ns
12 TsCSr(WR) CS high setup time to WR ~ 60 ns
13 TsCSr(RD) CS high setup time to RD ~ 60 ns
15 ThCS(RD) CS low hold time from RD t 0 ns
16 TsDI(WR) Data setup time to WR ~ 0 ns
17 Tw(WR) WR pulse width 390 ns
19 ThWR(DI) Data input from WR t 0 ns
20 TdRD(DI) Delay time from RD ~ to valid data ns 1
21 ThRD(DI) Data hold time from RD t 0 ns
22 TdRD(Dlz) Delay time from RD t to data bus floating 70 ns
23 TdRD(DBA) Delay time from RD ! to readout data settlement 0 ns
24 TdWR(W) Delay time from WR ! to WAIT ! 150 ns
25 TdRD(W) Delay time from RD ! to WAIT ! 150 ns
All AC output characteristics are based on the stated load conditions.
Note 1: The delay time depends on the device status at the time of access by CPU.
-------......-.----SHARP ----.-,--...------
505
PCLK
AID
____ ~_r~~~----------~
DBo-DB7 --------~-4.~+-~------~~J_--~------------
write
DB o-DB 7 --------4-~--~~~Fv~~~~--~-------------
read
RD ---~-"iJ..~-l

27 TsACK(RD) INT ACK low setup time to RD 90 ns 2
28 TdRD(DI) Delay time from RD ~ to valid vector 255 ns
29 ThRD(ACK) INT ACK low hold time from RD t 0 ns
30 ThIEI(RD) lEI hold time from RD t 100 ns
31 TwRDI RD(acknowledge) low pulse width 255 ns
32 TdIEI(IEO) Delay time from lEI to lEO 120 ns
33 TsIEI(RD) IEI setup time to RD ~ 150 ns
34 TdACK(IEO) Delay time from INT ACK ~ to lEO ~ 250 ns
35 TdADKr(IEO) Delay time from INT ACK t to lEO t 250 ns
Note 2: Interrupt arbitration loop circuit (daisy chain) is not used.
D~o-DB7 --------------------
INTACK
IEI ____~~~~--~----~----_+~~~-----------
lEO
______ ~~~------~~------J
500
(3) Reset timing

36 TdRDQ(WR) Delay time from RD t (for suppressing reset) to WR + 40 ns
37 TdWRQ(RD) Delay time from WR t (for suppressing reset) to RD + 50 ns
38 TwRES Minimum low width of WR and RD (for resetting) 250 ns 3
Reset timing

No. Parameter Note
39 Delay time from sending clock transition to output data transition 4
Note 4: Applies to all baud rates (75 ·4800 B)
TxC I 1: I
TxD
~~~~~-------------~=-=*=------------
Serial port timing

40 TdACK(D) Time from ACKNLG + to data output 24000 ns
41 TdD(DSTR) Time from data output to OAT A STROBE + 6500 ns
42 TwDSTR OAT A STROBE pulse width 6500 ns
AKCNLG ~
DATAl
\
DATA8
I--®-
I--@~/
DATA STROBE
---~-~-·--~SHARP-'-'-----------
507
Serjal· Parallel Combination Controller '1, •
LH8572
• Registers
The LH8572 has 14 registers which can be for character. format, baud rate, stop bit and
accessed externally (from CPU), and their address- parity' mode. Subsequently data required. by'
es are listed in Table 1. To make access to these .controlregister·, master interrupt control reg-
registers, the. high order 7 bits of 110 address ister' and interrupt .vector registers' (trans-
(AT AI) are decoded and fed to SS and the lowest mission, reception and printer error interrupt
order bit (Ao) is connected to A/D. This connec· vector registers) is programmed.
tion permits the assignment of 2-byte port address- (2) Clear the error status register.
es (even address and odd address) to the LH8572. (3) Wait until the data transfer enable bit in the
master interrupt control register is set to "1",
making the LH8572 operable.
Table 1 Register address In case interrupt is used, the above polling op-
eration is unnecessary_ When transmission, recep-
Address Register
tion and printer output become enabled, interrupt
x X X 00000 Error status register (ERR)
request is forwarded to the master CPU, indicating
X X XOOOOI Mode setting register (MSR)
that the LH8572 has become operable.
X X XOOOIO Control register (CTL)
Note: Registers marked by'" can be set or revised even dur-
X X XOOOll Transmission status register (TxS) ing the operation of LH8572.
X X XOOIOO Reception status register (RxS) (2) Data inpuUoutput
X X XOO.lOl Printer status register (PRS) Date transfer between LH8572 and master CPU
X X XOOll0 Transmission buffer (TxB) is carried out in accordance with the following
X X XOOll1 Reception buffer (RxB) procedure.
X X XOIOOO Printer buffer (PRB) (1) Poll the status registers (transmission, recep-
X X XOIOOI Transmission interrupt vector register (TxV) tion and printer status registers) and wait un-
X X XOIOIO Reception interrupt vector register (RxV) til they become "1". In case interrupt (trans-
X X XOIOll Printer interrupt vector register (PRV) mission, receptio'n and printer interrupt) is
X X XOll00 Error interrupt vector register (ERV) used, interrupt occurs as soon as the value of
X X X 11110 Master interrupt control register (MIC) each status register becomes "1", and polling
Note: A7-A, is decoded and applied to CS. so that the location is not necessary.
in the input/output address space is determined. Bits
(2) After the status register has been set to "1"
marked by 'x' are undefined.
(or after interrupt has occurred), begin data
transfer via the buffers (transmission, recep-
• Programming
tion and printer buffers).
The LH8572 has 14 read/write registers which
(3) Clear the status register. If the above opera.
can be accessed directly by the master CPU.
tion is implemented using an interrupt routinej
(1) Initialization
the interrupt-under-service (IUS) bit must be
The device is initialized in accordance with the
reset immediately before the end of each inter-
following procedure.
(1) Following power-on reset, or master reset by
rupt routine.
software, set the mode register is programmed
I 0 I 0 I Os I o. I 0 I 02 I 0, I 00 I
7 6 3
i
I I
Unused
Parity error
'.
Framing error
Overrun error
Printer fault
Paper out
Unused
Master reset
Fig_ 1 Error status register (ERR)
508
I D7 I D6 I Ds D. D3 D2 D, Do
I I
0 0 5 bits / character
0 0 0 75 B
0 0 1 nOB
0 1 0 150B
0 1 1 300B
1 0 0 600B
1 0 1 1200B
1 1 0 2400B
1 1 1 4800 B
S top -bit -2/Stop -bit -1
Odd -parity /Even -parity
With -parity /Without -parity
Fig. 2 Mode setting register (MSR)
I D7J D6 I Ds I D. I D3 I D, I D, I Do I
L RTS
I
I DTR
Transmission enabled
Reception enabled
Printer output enabled
Transmission interrupt enabled
Reception interrupt enabled
Printer interrupt enabled
Fig. 3 Control register (CTL)
I D7 I D6 I Ds I D. I D31 D2 I D, I D L
I
' - - 0
Transmission buffer empty'
* For data transmission, data is written into transmission

buffer upon confirmation that transmission buffer
"vacancy" bit is "1", and thereafter that bit is set to "0"
Fig. 4 Transmission status register (TxS)
• F or data reception, data is readout from reception buffer

upon confirmation that the reception character "validity"
bit is "1", and thereafter that bit is set to "0"
Fig. 5 Reception status register (RxS)
~~------SHARP-----'------
509
I 071 0 1Os I D4 103 1O 1od 0;1 .

6 2 _
I. . L:.m", Wi" -¢,'
• For data print out, data is written .into printer buffer
upon confirmation tbat tbe ·printer buffer "vacancy" bit.
is "1", and thereafter that bit is set to "0"
Fig. 6 Printer status register (PAS)
I~I~I~I~I~I~I~I~I I 071 06 1Os 10 103 1O 10, 1Do I

4 2
,L-------Transmission data I<-----Reception interrupt vector
Fig. 7 Transmission buffer (TxB) Fig. 11 Reception interrupt vector register (RxV)
I~I~I~I~I~I~I~I~I I~I~I~I~I~I~I~I~I
I
II-------Reception data IL------printer interrupt yector
Fig. 8 Reception buffer(RxB) Fig. 12 Printer interrupt vector register (PRV)
I~I~I~I~I~I~I~I~I I~I~I~I~I~I~I~I~I
,L--------printer output data IL------Error interrupt vector
Fig. 9 Printer buffer (PRB) Fig. 13 Error interrupt vector register (ERV)
I~I~I~I~I~I~I~I~I
I<-_ _ _ _ _ _ Transmission interrupt vector
Fig. 10 Transmission interrupt vector register (TxV)
At reading
Master interrupt. enable (MIE)
Interrupt under service (IUS) . TUndefined at reading/"O" at writing
Interrupt pending (IP) ---!.---7----! '-----Disabled lower chaining (OLe)
' - - - - - - - D a t a transfer enable (reading only)
'--------Undefined at reading/"O" at writing
At writing I
:
I
0 0 0 Writing to 00,0,,02,03 and O.

0 1 {) Set IUS
0 1 1 Reset IUS
1 0 0 Set IP
1 () 1 Reset IP
1 1 0 Set MIE
1 1 1 Reset MIE
Fig. 14 Master interrupt control register(MIC)
-------·.--~--~-SHARP - . - . ......... -------~

510
LH8573 General Purpose Interface Bus Controller

The LH 8573 (GPIB73) is a microcomputer peripheral
device used to control interface buses conforming
SRQ/REN IN
to IEEE Std. 488-1978 * (will be termed simply
40
"GPIB"). The GPIB is extensively used as a linkage PCLK 2 39 REN/SRQ OT

bus between data gathering instrumentation de-
vices and a microcomputer system.
The LH8573 incorporates three functions of talk- INT 5
er, listener and controller, all integrated in one INTACK 6
chip. Using this device, the GPIB interface can be

provided for various instrumentation equipment,
personal computers and office computers.
'Note : The standard disclosed in IEEE Std. 488-1978 "IEEE

Standard Digital Interface for Programmable Instru-
mentation "issued by IEEE, U.S.A.
• Features
1. Built-in talker, listener al1:d controller. Talker
function, listener function and Fontroller func-
Top View
tion are integrated in one chip.
2. Built-in buffer memory. Talker or listener
can use 160-byte on-chip buffer.
3. EO! automatic transmission. Upon detection
of the last byte of or EOS in talker mode, EO!
signal is transmitted automatically.
4. EOS automatic detection. Upon reception of
EOS in listener mode, the CPU is informed.
5. Built-in timer. The bus time-out period for
handshaking can be set by the on-chip timer in
the range of 200 I'-s to 12ms at 50 I'-s in-
terval.
6. Interrupt function. Interrupt arbitration facil-
ity of daisy-chain type is provided, allowing
vectored interrupt to CPU.
8. Single+5V power supply
.-----.-,--SHARP-....-.~-~---
511
• . Block Diagram
GPffi
'Data Bus
Data Bus
IFC IN
IFC OT
SRQ/RENIN
9 REN/SRQOT
CONTI
TE
ATN
DAV
NDAC
NRFD
Interrupt Enable Out 3, EO!
Interrupt Enable In 4. CONn
Interrupt Request 5 Internal
Interrupt Acknowledge 6 Control L'!gic
--------SHARP------l----
, -----
512
Multitask Support Processor LH8575
LH8575 Multitask Support Processor

The LH8575 is the stand alone type multitask
support processor providing the multitask capabili-
P30
ties for any simple microcomputer system. 0 P33
The concept of this multitask processing is simi-
lar to a conventional real time OS (operating P27
system). The devices perform task management P26
(creating, deleting, etc.) independently of the master P25
CPU, and carry out muItitask processing for systems P2.
bus with arbitrary CPU architectures merely by con- P23
necting to the system bus. P22
User's programs are scheduled on a priority or
P2,
time sliced basis. Tasks are switched by an inter-
rupt caused by the LH8575, and cummands are CS P20
given to the LH8575 by writing parameters and GND P3,
command numbers in the specified register in the WAIT P32
LH8575. DB7 P17
DB. Pl.
DB5 Pl5
DB. Pl.
DB3 Pb
• Features
~
DB2 Pb
1. Matching with any CPU
DB, Pb
• The LH8575 operates only in response to
DBo Plo
commands which are issued by the main
CPU. The system may have any type of CPU Top View
provided it is responsive to interrupt access
by the LH8575.
2. Task management
• Up to eight tasks can be controlled concur-
rently. By using the task creating and delet- 6. 20-bit general-purpose 110 port
ing technique, a maximum of 255 tasks can • Two 8-bit ports operable in bit input/
be handled. output
• Tasks can be controlled on a priority basis • 2-bit input ports and 2-bit output ports
by the assignment of 255 priority levels. • Tasks can be resumed using the 2-bit input
3. Inter-task communication ports.
• Inter-task communication is possible using 7. Memory assignment.
the "mail box' provided within the LH8575. • Working memory areas can be assigned to
• Inter-task synchronization is possible using each task.
the "mail box."
4. Built-in timer
• Timers with ranges from 10 ms to 255
hours can be used for time-sliced processes
and checking 110 wait time.
• These timers can be set independently for
each task.
5. Built-in clock.
• Time (hours, minutes and seconds) can be
set and read out.
513
Multltask Support Processor LH8575
• Block Diagram
Port 1
Data Bus
Data Bus
TCBl
MBXl Internal
Control Logic Port 2
Data Bus
Interrupt Request 5
514
Maltitask Support Processor LH8575
• Pin Description
Bidirectional
DBo-DB 7 Data bus System data bus
3-sate
AID Addressl data select I Addressldata select signal
WR Write I Active low. Indicate the system in write operation.
WAIT Wait 0 Active low, open-drain. Used to synchronize with CPU.
- Active low, open-drain. Indicate interrupt request to
CPU.
loop circuit (daisy-chain).
Pl o -P1 7 I/O port lines I/O Parallel 1/0
P2 o-P2 7 I/O port lines 110 Parallel 110
P3 0 -P3 3 I/O port lines I/O Parallel I/O
PCLK Clock I Single-phase clock, need not be same as-CPU clock.
• Absolute Maximum Ratings +5V

Input voltage VIN -0_3-+7_0 V
From output
Output voltage VOUT -0_3-+7.0 V under test
Storage temperatuer Tstg -65-+150 °C
Standard test load

Clock input low voltage VeL -0.3 0_8 V
Input high voltage VIH 2_0 Vee V
Input low voltage VIL -0.3 0_8 V
Output high voltage VOH IOH = -250pA 2.4 V
Output low voltage VOL IOL = 2mA 0.4 V
Input leakage current I IlL I 0;;;;; VIN ;;;;; +5_25V 10 pA
Output leakage current IIoL I o ; ; ; VIN ;;;;; +5_25V 10 pA
--.....-.-----SHARP .-----------------
515
• AC Characteristics ,
(1) Master CPU Interface timing
4 TwCI Clock pulse width, low lao,-- . ns
5 TpC Clock period 250 " .,
,
ns
6, TsAlD{WR) AID setup time to WR ~ 80 ns
7 TsAlD{RD) AID setup time to RD ~ 80 ns
8 ThAlD{WR) AID hold time from WR t 30 ns
9 ThA/D(RD) AID :hold time fromRD t 30 ns
10 TsCSf(WR) CS low setup time to WR l 0 ns
11 TsCSf(RD) CS low setup time to RD ~ 0 ns
12 TaCSr(WR) CS high setup time to WR l I 60 ns
13 TsCSr(RD) CS high setup time to RD l 60 ns
15 ThCS(RD) CS 19W hold time from RD t ~
0 ns
16 TsDI(WR) Data setup time to WR l 0 ns
17 Tw(WR) WR purse width 390 ns
19 ThWR(DI) Written data hold time from WR t 0 ns
20 TdRD(DI) Delay time from RD l to valid data ns 1
21 ThRD(DI) Readout data hold time from RD t 0 ns
22 TdRD(DIz) Delay time from RD t to data bus floating 70 ns
23 TdRD(DB A ) Delay time from RD l to r:eadout data valid 0 ns
24 TdWR(W) Delay time from WR J to WAIT l 150 ns
25 TdRD(W) Delay time from RD l to WAIT l 150 ns
Note 1: The delay time depends on device status at the time of access by master CPU.
PCLK
AID
----~1~~--------~-----------
DBo-DB7------~-+~~~--~~~n_--~----------
(write)
....-.~-~----SHARP-.---.-.-.-~
516

1 TsACK(RD) INT ACK low setup time to RD l 90 ns 1
2 TdRD(DI) Delay time from RD l to valid vector 255 ns
3 ThRD(ACK) INT ACK low hold time from RD t 0 ns
4 ThIEI(RD) IEI hold time from RD t 100 ns
5 IwRDl RD (acknowledge) pulse width 255 ns
6 TdIEI(IEO) Delay time from lEI to lEO 120 ns
7 TsIEI(RD) IEI setup time to RD l 150 ns
8 TdACKf(IEO) Delay time from INT ACK l to IEO l 250 ns
Note 1: Interrupt arbitration loop circuit (daisy-chain) is not used.
DB o -DB 7 - - - - - - - - - - - - - - - - - -
INTACK
IEI __~~~__~____________~__~~___________
IEO ______~~------+_------

(3) Reset timing
1 TdRDQ(WR) Delay time from RD t (for suppressing reset) to WR l 40 ns
2 TdWRQ(RD) Delay time from WR t (for sppressing reset) to RD l 50 ns
3 TwRES Minimum low width of WR and RD (for resetting) 250 ns 1
Reset timing
-------~---SHARP --~----.--.--.---
517
-(
Multitask Support Proc~ssor LH8575
(4) Handshaking timing

No Symbol Parameter MIN. MAX. Unit Note
1 TsDI(DA) Data setup time ( -0 ns
2 ThDA(DI) Data hold time 230 ns
3 TwDA DAV width 175 ns 1
,
4 TdDAL(RY) Delay time from DAV low to RDY " 20 175

ns
1
0 2
150 1
5 TdDAH(RY) Delay time from DA V high to RDY ns
0 2
6 TdDO(DA) Delay time from data output to DA V 50 ns
7 TdRY(DA) Delay time from RDY to DA V 0 205 ns
Note 1: Input handshaking
Note 2: Output handshaking
Data input
______ -J.~~~~~~.~--------------
DAV input
RDYoutput
Port read
Input handshaking timing
Data output y- Valid output data

-----~~@~.~----------------------------
DAVoutput.
RDY input
Output handshaking timing

• Registers
(1) Task control under-service (IUS) bits are set or reset in tqis
CPIO (Command parameter register) register.
This register writes the writing perameter pre- Table 1 Register address
vinus to command writing. The readout parameter Register Address
is placed in CPIO upon completion of command ex- PlO X X XOOOOI
ecution. P2D X X XOOOIO
CNST (Command/status register) P3D X X XOOOll
This register is used to write a command. Exe- CNST X X XOOllO
cution information of executed command is placed
SPNI X X XOOlll
in CNST upon completion of commal\d execution. SPN2 X X XOIOOO
SPN 1, SPN2 (New task stack pointer registers) SPBl X X XOIOOI
At occurrence of interrupt for task switching, SPB2 X X XOIOI0
execution starting address information for the new
CPIO X X X,lOlOl
task is placed in this register. , MIC XXXllll0
SPB1, SPB2 (Old task stack pOinter registers)
At occurrence of interrupt for task switching, Note 1: Bits marked by 'x' may be either '0' or '1'.
Note 2: LH8575 uses 2 input/output address locations.
execution for the executed task is written register.
MIC (Master CPU interrupt control register)
Interrpt J:elated parameters including interrupt
enable (IE), interrupt pending (IP) and interrupt-
518
(2) 1/0 Ports (Executio~

P1D, P2D, P3D (Port 1, 2, 3 data registers)
These registers are used to transact data via
port I, port 2 and port 3.
TSPD
Table 1 lists the register addresses.·
( Ready )~TSPD
~__~ ~~~~T
. ~M TRSM
~____
( Wait ) TSPD (Absence)
~CRT TDE~
( Halt)
(1) Task in execution releases CPU.

(2) • Higher ranking task becomes ready.
Time-up by time division
• TNXT
Fig. 1 Task status
MIC I~I~I~I~I~I~I~I~I
L
I Undefined at reading/" 0" at writing
Disabled lower chaining (DLC)
o (unused)
Non-vector (NV)
I Interrupt pending (IP)
I
I I Interrupt under service (IUS)
I I
I I I nterrupt enable (IE)
I
At writing .:,
0 0 0 Writing to D. and D2
0 1 0 Set IUS
0 1 1 Reset IUS
1 0 0 Set IP
1 0 1 Reset IP
1 1 0 Set IE
1 1 1 Reset IE
Note: IP, IUS and IE bits ate set or reset by writing in these
codes,
Fig. 2 MIC bit configuration
• Programming
(1 ) Initialization ters are written at the top of each stack area.
The following describes the task control proce· (3) LH8575 is initialized. Table 2 lists the in-
dure using LH8575. itialization information to written in LH8575.
(1) The LH8575 causes interrupt for task switch- (4) When necessary, the clock is set and the port
ing. However, in order to process, a separate in- mode is specified.
terrupt processing routine must be prepared. (5) Initialization completed. To transfer control
(2) Each task is provided with a stack area. Task from the initialization routine to a task, the task
starting address and initial values for all regis- execution command (TSTR) must be executed.
519
Table 2 System information registered at initialization

Order: Item Contents
1 Vector LH8575 Interrupt vector for task switching
2 User RAM start address (high order byte)
RAM table
3 User RAM end address (high order byte)
4 Task number (hex 01-FF)
\ 5 Priority level (hex 01-FF)
Task table Task 1
6 Task stack pointer (high order or low order byte)
7 Task stack pointer (low order or high order byte)
4n Task number (hex 01-FF)

4n+l Priority leave (hex 01-FF)
Task n
4n+2 Task stack pointer (high order or low order byte)
4n+3 Task stack pointer (low order or high order byte)
(2) Command execution

Table 3 lists the commands of LH8575, and tion). For commands without readout parameter,
Table 4 lists the command execution information. procedure is completed and the following proce-
In writing command into LH8575 the following dures are unnecessary. Commands with readout
data entry procedure applies. parameter (CGET, MALC and PEND) further re-
(1) Write parameters needed in writing command quire the following procedures.
into CPIO in the order shown in Table 3. Com- (4) When Ds = 1 in CNST (indicating the read-
mands with blank parameter field in Table 3 do out parameter is prepared in CPIO). parameter
not require .writing. is read out from CPIO.
(2) Write the command number in CNST. (5) The PRME command must be executed to
(3) It is necessary to confirm the completion of notify parameter readout completion.
command execution by polling D7 in CNST (D7 (6) Wait until CNST D7 becomes "1" to confirm
becomes "I" upon completion of command execu- the· completion of command execution.
---------~-------~ARP~--·--.-.--
' I .
520
Table 3 Command table

Code Command name Function Writing parameter Readout parameter Remarks
OOH INIT LH8575 initialization 1. Total number of tasks
01 H TSTR Termination of LH8575 initialization
and start of task execution
02 H TCRT Task creation 1. Task number
2. Priority level
3. SP (high order or low
order byte)
4. SP (low order or high
l order byte)
03 H TDEL Task deletion Task number
04 H TRSM Task resumption Task number
05 H TSPD Task suspension 1. Task number (1)
2. Control switch
06 H TPRI Task priority change 1. Task number
2. New priority
07 H TSLl Task time·slicing process 1. Priority (2)
2. Time base
3. Count
08H TNXT Transfer execution right to the next
task in time·sliced process.
09 H TIMR Timer setting 1. Control code (3)
2. Count
CSET Clock setting 1. Hour
OAH
2. Minute
*
3. Second
OB H CGET Clock read out 1. Hour
2. Minute
3. Second
OC H MALC Memory allocation 1. Number of memory 1. Allocated memory
blocks required address
*
ODH MREL Memory release
OE H POST Message transmission 1. Mail box number (4)
2. Message data 1
3. Message data 2
4. Message data 3
5. Message data 4
OFH PEND Message reception 1. Mail box number 1. Message data 1
2. Message data 2
*
3. Message data 3
4. Message data 4
10H PMOD Port mode setting 1. Port·1 made (5)
2. Port·2 mode
3. port·3 mode
llH PRME End of parameter readout
Note 1: Commands marked by·" require PRME command execution at parameter readout completion.
Note 2: Numerals give in 'writing parameter' and 'readout parameter' indicate the order of writing and reading.
Note 3: Numerals in 'remarks' indicate the reference number of supplementary explanation.
"'-''-~--'---SHARP'''-''-----''''''''--
521
.-.- .........- .......
Multitask Support Processor
Table 4
-,..-~-~-- .....- ..........................
Command execution information
LH8575
.-
Code Command name Execution information

OOH INIT 0 Normal termination
1 Task number or priority setting error
2 Double specification of same task number
3 Total number of tasks equal to 0 or larger than 8; error in the number of system con-
figuration information; RAM table error
01 H TSTR 0 Nomal termination
3 Initial information not yet set
02 H TCRT 0 Normal termination
1 Task number or priority setting error ,
2 Already created
3 Control tasks more than 8
03 H TDEL 0 Normal termination I
1 Task number error

2 Specified task not yet created
4 Specify self
04 H TRSM 0 Normal termination
1 Task number error
4 Specify self
5 Specification of task in ready status
05 H TSPD 0 Normal termination
1 Task number or control switch number error
[ ,
3 Control switch setting error

5 Specification of task i'n halt status
06 H TPRI 0 Normal termination
1 Task number or priority setting error ,

07 H TSLI 0 Normal termination
1 Priority error or data error
5 Cancellation without setting
08 H TNXT 0 Normal termination
09 H TIMR 0 Normal termination
1 Data error
5 Cancellation without setting
8 Resuming by TRSM
OA H CSET 0 Normal termination
1 Data error
OB H CGET 0 Normal termination
OCH MALC 0 Normal termination
6 Allocation disabled
OD H MREL 0 Normal termination
5 Memory not yet allocated
OE H POST 0 Normal termination
1 Mail box number error or massage data error
7 Mail box busy
OF H PEND 0 Normal termination \
I
\
1 Mail box number error
\
8 TRSM command issued by other task or time out
10 H PMOD 0 Normal termination
11H PRME 0 Normal termination
522
MiJltitask Support Processor LH8575
• Supplement for Writing Parameter
(1)
2. Control switch
I~'~'~'~'~'~'~'~I
L...I----Control switch
o : Bring to complete stop
1 : Halt until external event 1 (fall of P3il
2 : Halt until external event 2 (fall of P30)
(2)
2. Time base
ID7 , D6 , Ds ID, ID3 ID2 IDl IDo I

''------Time base
0: Hour
1 : Minute
2 : Second
3 : 1/100 second
(3)
1. Control code
I D7 I D6 I Ds , D, , D3 'D2 ! D, I Do I
LTimellase
0: Hour
1 : Minute
2 : Second
3 : 11100 second
'---------Unused
L -_ _ _ _ _ _ _ _ _ _ _ Wait switch
0: Wait
1 : Time out period setting only
2. ·Count
1D7 I· D6 , Ds , D, , D3 I D2 I D, , Do I
C=Count (Count multiplied by time base becomes setup time.)
(4)
2. Only in message data 1. ·0" is not allowed.
523
fy1ultitask Support Processor L..H857&
(5)
1. Port-l mode
I D7! D6 ! Ds ! D.! D3 ! D2 ! Dl ! Do I I
L!---Port-l llit I/O definition (l for input; 0 for output) ..
2. Port-2 mode
I~!~!~!~!~!~!~!~I
I Port -2 bit I/O definition (1 for input; 0 for output)
3. Port-3 mode
I~I~I~I~I~!~I~I~I
- - -r-. T1 T Lpoc. 2 , _",.n/_''''
Port 1 : push -ps\l/opnn -drain
P31: External event 1 input
P30: External event 2 inpllt
L--------...:·Port -1 handshaking
( P3 l = DAVlIRDYI)
P32 = RDYI/DA VI
' - - - - - - - - - P o r t -2 handshaking
'(P3o =DAV2/RDY2)
P33 = RDY2/DA V2
L-_ _ _ _ _ _ _ _ _ _ Unused
524
Z85901Z8590A Universal
LH8590/LH8590A Peripheral Controller
The LH8590 Z8590 Universal Peripheral Con·
troller (UPC) is an intelligent peripheral controller
P3!
for distributed processing applications (Fig. 3).
The LH8590 unburdens the host processor by
o P36
assuming tasks traditionally done by the host (or lEO or P37 3 P27
by added hardware), such as performing arithmet· lEI or P30 4 P26
ie, translating or formatting data, and controlling lNT or P35 5 P25
I/O devices. Based on the Z8 microcomputer lNT ACK or P32 6 P2.
architecture and instruction set, the LH8590 con·
P23
tains 2K bytes of internal program ROM, a 256·
P22
byte register file, three 8-bit I/O ports, and two
P2!
counter/timers.
The LH8590 offers fast execution time, an effec· P20
tive use of memory, and sophisticated interrupt, I/ P33
0, and bit manipulation. Using a powerful and ex· P3.
tensive instruction set combined with an efficient DB7 Ph
internal addressing scheme, the LH8590 speeds DB6 Pl6
program execution and efficiently packs program
DB5 Ph
code into the on-cbip ROM.
An important feature of the LH8590 is an inter· DB. Pl.
nal register file containing I/O port and control DB3 PIs
registers accessed both by the LH8590 program
[!I
DB2. Ph
and indirectly by its associated master CPU. This DB! Ph
architecture results in both byte and programming Plo
efficiency, because LH8590 instructions can oper·
Top View
ate directly on I/O data without moving it to and
from an accumulator. Such a structure allows the
user to allocate as many general purpose registers
as the application requires for data buffers be·
tween the CPU and peripheral devices. All gener·
ai-purpose registers can be used as address point·
ers, index registers, data buffers, or stack space.
• Features with a 6-bit prescaler. Counter/Timer TO is

1. Complete slave microcomputer, for distributed driven by an internal source, and Counter/
processing use. Timer Tl can be driven by internal or external
2. Unmatched power of Z8 architecture and in· sources. Both counter/timers are independent
struction set. of program execution.
3. Three programmable I/O Ports, two with 6. 256-byte register file, accessible by both the
optional 2-Wire Handshake. master CPU and LH8590, as allocated in the
4. Six levels of priority interrupts from eight LH8590 program.
sources: six from external sources and two 7. 2K bytes of on-chip ROM for efficiency and
from internal sources. versatility.
5. Two programmable 8-bit counter/timers each
525
• Block Diagram'
UPC Micro,\omputer
Address/Data I 0
Bus
1,0
526
Z8590lZ8590A Universal Peripheral Controller LH8590/LH8590A
• Pin Description
Bidirectional
DBo-DB7 Data Bus System data bus
3-state
A/D Address/Data Select I Address/ data select signal
- Active low. Indicates that reading operation is in prog·
RD Read I
ress.
- Active low. Indicates that writing operation is in prog-
WR Write I
ress.
CS Chip Select I Active low. Chip select signal
-- Active low. Open-drain. Used for synchronization with
WAIT Wait 0
the CPU.
Pl o-P1 7 lIO Port Lines I/o Parallel lIO
P2 o-P2 7 lIO Port Lines I/O Parallel lIO
P3 o-P3 7 lIO Port Lines I/O Parallel lIO
Single-phase clock. This clock does not need to be re-
PCLK Clock I
lated to the CPU clock.

Storage tern perature Tstg -55-+150 °C
• Standard Test Conditions

All voltages are referenced to GND. Positive 5V 5V
current flows into the reference pin.
2.2kfl 18kfl
From output under test
50 PF
r
Standard test load 1
50 PF
r
Standerd test load 2
• DC Characteristics (Vce=5V±5%, Ta=O-+70°C)

Colck input high voltage VCH 2.4 Vee V
Input high voltage Vm 2.0 Vee V
Output high voltage VOH IOH= -250 p.A 2.4 V 1
Output low voltage VOL IOL=2mA 0.4 V 1
Input leakage current hL 0;;:; VIN ;;:; +5.25V -10 10 p.A
Output leakage current 10L 0;;:; VIN;;:; +5.25V -10 10 p.A
Note 1: For Ao-A1 j, Do-D7. MDS. SYNC. MAS. and MRfW flACK of the device for 64-pin development IOH= -100 f1 A and IOL= 1.0mA.
~'-------SHARP---------
527
\ ' ,
Z8590lZ8590A Universal Peripheral Controller LH8590/LH8590A
(1) Master CPU int~rface timing (Vcc=5V±5%. Ta=0-+70t:)
LH8090 LH8090A
Np. Symbol Parameter Unit Note
MIN. MAX. MIN. MAX.
'2 TwCH I Clock high width 105 1855 70 1855 ns
4 TwCl Clock low width 105 1855 70 1855 ns
5 TpC , Clock period 250 2000 165 2000 ns
6 TsA/D(WR) AID to WR ~ setup time 80 80 ns
7 TsA/D(RD) AID to RD ~ setup time 80 80 ns
8 ThA/D(WR) WR to: AID t hold time 30 25 ns
9 ThA/D(RD) RD to AID t hold time 30 25 ns
10 TsCSf(WR) CS ~ to WR ~ setup time 0 0 ns
11 TsCSf(RD) CS ~ to RD ~ setup time 0 0 ns
12 TsCSr(WR) CS t to WR ~ setup time 60 60 ns
13 TsCSr(RD) CS t to RD ~ setup time 60 60 ns
14 ThCS(WR) WR to CS ~ hold time 0 0 ns
15 ThCS(RD) RD to CS ~ hold time 0 0 ns
16 TsDI(WR) Data in to WR ~ setup time 0 0 ns
17 Tw(WR) WR low width 390 250 ns
18 Tw(RD) RD low width 390 250 ns
19 ThWR(DI) Data in to WR t hold time 0 0 ns
20 TdRD(DI) Data valid from RD ~ delay ns 1
21 ThRD(DI) Data valid to RD t hold time 0 0 ns
22 TdRD(DIz) Data bus float from RD t delay 70 45 ns
23 TdRD(DBA) RD ~ to read data active delay 0 0 ns
24 TdWR(W) WR *
to W AIT ~ delay 150 150 ns
25 TdRD(W) RD ~ to W AIT ~ delay ",
150 150 ns
,26 TdDI(W) Data valid to WAIT t delay 0 0 ns
Note: The timing characteristics given reference 2,OV as High and O.8V as Low. All output ac parameters use test load l.
Note 1: This parameter is dependent on the state of LH8590 at the time of master CPU access.
528
Z8590/8590A Universal Peripheral Controller LH8590/LH8590A
PCLK
AID
------Jl~--------------~
DBo- DB7 ----+--1. Jt-f.......;;..-.----..;;;;..--I-\I ,/--+1-------

WRITE CASE ------~f___rl~----.:.....--.....,-'f",+::_--++.....,_:_-------
DBo-DB7
READ CASE--------t-~_jit-1~~~~~--~1J~---------

(2) Interrupt acknowlegge timing
.LH8590 LH8590A
MIN. MAX. MIN. MAX.
27 TsACK(RD) INT ACK J. to RD J. setup Hme 90 80 ns 1
28 TdRD(DI) RD J. to vector valid delary 255 180 ns
29 ThRD(ACK) RD t to INT ACK t hold time 0 0 ns
30 ThlEI(RD) RD to lEI t hold time 100 100 ns
31· TwRDl RD (acknowledge) low width 255 250 ns
32 TdlEI(IEO) lEI to lEO delay 120 100 ns
33 TsIEI(RD) lEI to RD J. setup time 150 120 ns
34 TdACK(IEO) INT ACK J. to lEO J. delay 250 250 ns
35 TdADKr(IEO) INT ACK t to lEO t delay 250 250 ns
Note: The timing charcteristics given reference 2.0V as High and O.8V as Low. All output ac parameters use test load L
Note 1: In case where daisy chain is not used.
529

LH8590 LH8590A
MIN. MAX. MIN. MAX.
1 TsDI(DA) Data in setup time 0 0 ns
2 ThDA(DI) Data in hold time 230 230 ns
3 TwDA Data available width 175 175 ns 1.2
Data available low to ready 20 175 20 175 ns 1.2
4 TdDAL(RY)
delay time 0 0 ns 2.3
Data available high to ready 150 150 ns 1.2
.5 TdDAH(RY)
\ delay time 0 0 ns 2.3
6 TdDO(DA) Data out to available delay time 50 50 ns 2
7 TdRY(DA) Ready to data available delay time 0 205 0 205 ns 2
Note 1: Input handshake
Note 2: Test Load 1
Note 3: Output Handshake
DATA IN ---------'.~~~~~~~r~------------------
DAV INPUT
RDY OUTPUT
Port read
Input handshake timing
DA T A OUT _______ 1 Data output valid

~~~®~--------~----------------
----..!..-.....;;;..-.L-
DAV OUTPUT
RDY INPUT
Output handshake timing

(4) Reset timing
LH8590 LH8590A
MIN. MAX. MIN. MAX.
1 TdRDQ(WR) Delay from RD t to WR t for no reset 40 35 ns
2 TdWRQ(RD) Delay from WR t to RD t for no reset 50 35 ns
3 TwRES Minimum width of WR and RD both low for reset 250 250 ns 1
..
Note 1: Internal reset signal is l/z to 2 clock delays from external reset condItion .
Reset timing
-----..-.---------SHARP -----------.-....-
530
(5) RAM version program memory timing

LH8590 . LH8590A
MIN. MAX. MIN. MAX.
1 TwMAS Memory address strobe width 60 55 ns 1
2 TdA(MAS) Address valid to memory address strobe t delay 30 30 ns 1
3 TdMR/W(MAS) Memory read/write to memory address strobe t delay 30 30 ns 1
4 TdMDS(A) Memory data strobe t to address change delay 60 60 ns
5 TdMDS(MR/W) Memory data strobe t to memory read/write not valid delay 80 75 ns
6 Tw(MDS) Memory data strobe width (write case) 160 110 ns 2
7 TdDO(MDS) Data out valid to memory data strobe ~ delay 30 30 ns 1
8 TdMDS(DO) Memory data strobe t to data change delay 30 30 ns 1
9 Tw(MDS) Memory data strobe width (read case) 230 230 ns 2
10 TdMDS(Dl) Memory data strobe ~ to data in valid delay 160 130 ns 3
11 TdMAS(Dl) Memory address strobe t to data in valid delay 280 220 ns 3
12 ThMDS(Dl) Memory data strobe t to data in hold time 0 0 ns
13 TwSY Instruction sync out width 160 100 ns
14 TdSY(MDS) Instruction sync out t to memory data strobe ~ delay 200 160 ns
15 TwI Interrupt request via port 3 input width 100 100 ns
Note: All timing references assume 2.0 V for a logic "1" and 0.8 quency of 4 MHz. When operating at a lower frequency,
V for a logic ·0·. All output ac parameters use test load the increase in three input clock periods must be added
2. Timings are preliminary and subject to change. to the specified width.Data strobe width varies accord·
Note 1: Delay time are specified for an input clock frequency of ing to instruction being executed.
4 MHz. When operating at a lower frequency, the in· Note 3: Address strobe and data strobe to data in valid delay
crease in input clock period must be added to the speci· times represent memory system access times and are
fied delay time. given for a 4 MHz input frequency.
Note 2: Data strobe width is specified for an input clock fre·
~ --
@---
I
~@-1
X Valid address J(
®- ----
MR/W
(RAM VERSION ~ l(
ONLY )
MDS
WRITE CASE
Do-D7 r--
:j=@'
CV ®
r-@~
WRITE CASE K Data output valid _X

--@
MDS
READ CASE J
Do-D7
~@--- @.... H-
~
READ CASE /
~@1t
@ Data input valid
-@ I~@-
.RAM version program memory timing
531
Z8590/Z8590AUniversai Peripheral Controller LH8590/LH8590A
• Functional Description
(1) Address space. register address locations are shown in Fig. 2. Of
On the 40-pin UPC, all
address space is commit· the 256 UPC registers, 19 can be directly accessed
ted to on-chip memory. There are 2048 bytes of by the master CPU; the others' are accessed in·
maskprogrammed ROM and ,256 bytes of register direcly via the block transfer mechanism.
file. 110 is memory-mapped to three registers in' UPC instructi~ns may access registers directly
the register file. or indirectly using an 8-bit address mode or a
Program Memory Fig. 1 is a map of the 2K 4-bit address mode and a Register Pointer. For the
on-chip program ROM.The first 12 bytes of prog· 4-bit addressing mhde, the file is divided into 16
ram memory are reserved for the LH8590 inter· working register groups, each occupying 16 con·
rupt vectors. tiguous locations (Fig.3).
Register File This 256-byte file includes Stacks An 8-bit Stack Pointer (SP), register
three 1/0 port registers (l H-3 H), 234 general-pur· R255, is used for addressing the stack, residing
pose reginters (6 H- EF H), and 19 control, status ~nd within the 234 general-purpose registers, address
specical 110 registers (OH, 4 H, 5H, and FOH-FFH). location 6H through EFH.
The functions and mnemonics assigned to these
IDENTIFIER
LOCATION (UPC Side)
FFH STACK POINTER, SP
FEH MASTER CPU INTERRUPT CONTROL MIC
FDH REGISTER POINTER RP
FCH PROGRAM CONTROL, FLAGS FLAGS
FBH UPC IlI/TEBRUPT MASK REGISTER I MR
FAH UPC INTERRUPT REQUEST REGISTER I RQ
F9H UPC INTERRUPT PRIORITY REGISTER I PR
F8H PORT 1 MODE PIM
F7H PORT 3 MODE P3M
F6H PORT 2 MODE P2M
F5H ToPRESCALER PREO
F4H TIMER/COUNTER 0 TO
2047 F3H Tl PRES CALER PREI
F2H TIMER/COUNTER 1 T1
USER
FlH TIMER MODE TMR
ROM
, FOH MASTER CPU INTERRUPT VECTOR REG,
, - MIV
EFH
LOCATION OF FIRST BYTE OF INSTRUCTION
12 EXECUTED AFTER RESET
11 IRQ 5 LOWER BYTE '
10 IRQ 5 UPPER BYTE GENE~~L-PURPOSE
,9 IRQ 4 LOWER BYTE REGISTERS

8 IRQ 4 UPPER BYTE
7 IRQ 3 LOWER BYTE
6 IRQ 3 UPPER BYTE
5 IRQ 2 LOWER BYTE DATA INDIRECTION REGISTER DIND
4 IRQ 2 UPPER BYTE LIMIT COUNT REGISTER LC
3 IRQ 1 LOWER BYTE PORT 3 P3
2 IRQ 1 UPPER BYTE PORT 2 P2
1 IRQ 0 LOWER BYTE PORT 1 PI
0 IRQ 0 UPPER BYTE DATA TRANSFER CONTROL REGISTER DTC
Fig.l Program memory map Fig.2 Register file orgranization,
532
FF H
FDH
.-- oI I I I o0 0 0 FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
9FH
90H
The 4 -bit register 8FH
pointer provides the The lower nibble .of
80H
upper nibble of the 7FH the register file
75H(01110101)
register file addres s 70H address (0101) is
6FH provided by the instruction.
for the 4 - bit addres S
60H
mode. 5FH
50H
4FH
40H
3FH
30H
2FH
20H
IFH
IOH
OFH
0
Fig. 3 Register pointer mechanism
(2) Ports control lines by programming the Port 3 Mode reg-

The LH8590 has 24 lines dedicated to input ister. Port 3 is accessed as get:J.eral register 3H.
and output. These are grouped into three ports of The directions of the eight data lines are fixed.
eight lines each and can be configured under soft- Four lines, P3 0 through P3 3 , are inputs, and the
ware control as inputs, outputs, or special control other four, P3 4 through P3 7 , are outputs. The con-
signals. They can be programmed to provide Para- trol functions performed by' Port 3 are listed in
llel liD with or without handshake and timing sig- Table 1.
nals. All outputs can have active pullups and pull- Table 1 Port 3 control functions
downs, compatible with TTL loads_ In addition, Function Line I/O Signal
Port 1 and 2 may be configured as open-drain out- P3 1 I DAV 2 /RDY 2
puts. P3 3 I DAV1/RDY 1
Port 1 Individual bits of Port 1 can be confi- Handshake
P3 4 0 RDY!/DAV 1
gured as input or output by programming Port 1 --
P3 6 0 RDY 2 /DAV 2
r
Mode register (PIM) F8H. This port is accessed by I IRQ 3
the UPC program as general register IH. LH8590
P3!
30 I IRQ 2
Port 1 may be placed under handshake control Iterrupt Request'
P3 3 I IRQ!
by programming Port 3 Mode register (P3M) F7H.
Port 2 Individual bits of Port 2 can be con- Counter ITimer j P3! , 0
I TIN
P3 6 TOUT
figured as inputs or outputs by programming Port ' INT
P3 5 0
2 Mode register (P2M) F6H. This port is accessed P3 2 I IN TACK
by the UPC program as general register 2H, and Master CPU
P3 0 I lEI
its functions and methods of programming are the P3 7 0 lEO
same as those of Port 1. * P3 0 • P3\. and P3 3 can always be used as upe interrupt, reo
Port 3 This port can be configured as I/O or quest inputs. regardless of the configuration programmed .
.-----~-.---SHARP.-.--------~-
533
Z8590/Z8590A Universal Pe-ripheral Controller LH8590/LH8590A
(3) Counter/Timers abled or disabled using Interrupt Mask Register

The LH8590contains two 8-bit programmable (IMR) FBH. Interrupt Priority Register (IPR) F9H
counter/timers, each driven by an internal 6-bit specifies the order of their priority. All UPC inter-
programmable prescaler. rupts are. vectored.
The T1 prescaler can be driven by internal or Table 2 lists the UPC's interrupt sourcers, their
external clock sources. _The TO prescaler is driven types, and their vector locations in program ROM.
by· an intenial clock source.' Both counter/timers The LH8590 also supports polled systems. To
operate indpendently of· the processor instruction accommodate a polled structure. any or all of the
sequence to relieve the program from time-critical interrupt inputs can be masked and the Interrupt
operations like event counting or elapsed-time cal- .Request register polled to determine which of the
culation. TO Prescaler register (PREO) F5H and interrupt requests needs service.
T1 Pre-scaler register (PRE1) F3H can be pro- (5) Master CPU Register File Access
grammed to divide the input frequency of th.e source There are\ two ways in which the master CPU
being counted by any number from 1 to 64. A· can acess the LH8590 register file: direct access
Counter register (F2H or F4 H) is loaded with a and block access.
number from 1 to 256. The corresponding counter Direct access Three LH8590 registers -
is decremented from this number each time the the Data Transfer Control. the Master Interrupt
prescaler reaches end-of-count. When the count is Vector. and the Master Interrupt Control - are
complete, the counter issues a timer interrupt re- mapped directly into the master CPU address
quest; IRQ4 for TO or IRQ 5 for Tl. space.
(4) Interrupts Block Access The master CPU maY-· transmit
The LH8590 allows six interrupts from eight or receive blocks of data via address xxx 101Ol.
different sources as follows: When the master CPU accesses this address, the
• Port 3 lines P3 0, P3 2, and P3 3• LH8590 register pointed to by the Data Indirection
• The master CPU(3). register is read or written. The Data Indirection
• The two counter/tiniers .. register is incremented, and the Limit Count register
These interrupts can be masked and globallY'en- is decremented.
Table 2 Interrupt types, Sources, and Vector locations

Name Source Vector location Comments
IRQO EOM, XESS, LERR 0, 1 Internal (RO bits 0, I, 2)
IRQl DAVI. LRQl 2. 3 External (P3 3 ) ! edge triggere~
IRQ2 DA V2, IRQ2. TIN 4. 5 Ext.ernal (P3 I ) ! edge triggered
IRQ3 IRQ3. lEI 6, 7 External (P3 0 ) ! edge triggered
IRQ4 TO 8, 9 Internal
IRQ5 T1 10,11 Internal
...-.----~-~--SHARP'~--.----.-.~-
.{
534
• Instructions
(1) Addressing modes Assignment of a value is indicated by the sym-
The following notation is used to describe the bol ".... ". For example,
addressing modes and instruction operations. dst +- dst + src
IRR Indirect register pair or indirect work- indicates that the source data is added to the des-
ing-register pair address tination data and the result is stored in the des-
Irr Indirect working-register pair only tination location. The notation "addr(n)" is used to
x Indexed address refer to bit "n" of a given location. For example to
DA Direct address refer to bit"n" of a given location. For example,
RA Relative address dst (7)
1M Immediate refers to bit 7 of the destination operand.
R Register or working-register address (3) Flags
r Working-register address only Control Register 252 contains the following six
IR Indirect-register or indirect working- flags:
register address C Carry flag
Ir Indirect working~register address only Z Zero flag
RR Register pair or working-register pair S Sign flag
address V Overflow flag
(2) Additional symbols D Decimal-adjust flag
dst Destination location or contents H Half-carry flag
src Source location or contents Affected flags are indicated by:
cc Condition code (see list) o Cleared to zero
@ Indirect address prefix 1 Set to one
PC Program Counter * Set or cleared according to operation
SP Stack Pointer (control register 255) Unaffected
FLAGS Flag register (control register 252) X .Undefined
RP Register Pointer (control register 253) (4) Condition codes
IMR Interrupt Mask register (control register Table 3 shows condition code.
251)
1000 Always true .........
0111 C Carry C=l
0110 Z Zero Z=l
1110 NZ Not zero Z=O
1101 PL Plus S=O
0101 MI Minus S=l
0110 EQ Equal Z=l
1110 NE Not equal Z=O
1001 GE Greater than or equal (S XOR V)=O
0001 LT Less than (S XOR V)=l
1010 GT Greater than (Z OR (S XOR V)) =0
0010 LE Less than or equal (Z OR (S XOR V)) = 1
0111 ULT Unsigned less than C.=l
1011 UGT Unsighed greater than (C=O AND Z=O)=l
0011 ULE Unsigned less than or equal (C OR Z)=l
0000 Never true .........
535
Z~90/Z8590A Uni~ersal Peripheral Controller. " LH 8590/LH8590A
(5) 'Opcode map
Lower Nibble (Hex)

o 1 2 3 4 5 6 789 A B c o E F
6.5 6,5 6:5 ' 6,5 10,5 10,5 10,5 10,5 6,5 6,5 12/fo, 5 12/10,0 6,5 12/10,0' 6,5
0 DEC DEC ,ADD ADD ADD ADD ADD ADD LD LD DJNZ JR LD JP INC
'R, JR, rIll', rl.Ira R.. R, IR.. R, R.. IM IR"IM fllRa r,. R. rl,RA cc,RA r"IM cc,DA r,
-
6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5
1 RLC RLC .ADC ADC ADC ADC ADC ADC
R, IR, rllrt r. ,Ira R" R, IR"R, R.. IM IR"IM
-
6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5
R, nt, rl,r, r •. ,Ira R.. R, IR"R, R"IM IR"IM
-
8,0 6,1 6,5 6,5 10,5 10,5 10,5 10,5
3 JP SRP SSC SSC SSC SSC SSC SSC
IRR, 1M r"ra r. ,Ira R" R, IR" It. R"IM IR"IM
-
8,5 8,5 6,5 6,5 10,5 10,5 10,5 10,5
R, IR, r •• fa rl,Ir. R"R, IR" R, R"IM IR"IM
-
10,5 10,5 6,5 6,5 10,5 10,5 10,5 10,5
5 POP POP AND AND AND AND AND AND
R, IR, rl. fa TI.IT, R"R, IR" R, R"IM IR"IM
6,5 6,5 6,5 6,5 . 10,5 10,5 10,5 10,5
-
COM COM TCM TCM TCM TCM TCM TCM
i:::c 6
~ 7
R, IR,
PUSH PUSH TM
r •• T.
10/12,1 12/14,1 6,5
r •. Ir,
6,5
TM
R"R,
10.5
TM
IR" R,
10,5
TM
R"IM IR"IM
10,5
TM
10,5
TM
, -
.0 It. IR, rlt T, r •• Ira R"R, IR"R, R"IM IR"IM \

.0
Z 10,5 10,5 12,0 18,0 6T
...
CI)
8 DECW I!>ECW LDE LOEI
RR, IR, r.,Irf, Ir•• lrra
01
0.
0. 6,5 6,5 12,0 18,0 6T
::l 9 RL RL LOE LDEI EI
R, IR, Ta.Irr. I r 2.I rf t
10,5 10,5 6,5 6,5 10,5 ro,5 10,5 10,5 14.0
RR, IR, rl. Ta r •• Irz R"R, IR" R, R"IM IR"IM
6,5 6,5 6,5 6,5 10,5 10,5 10,5 10,5 ----w:o
R, IR, rl. r, rt. Ira R"R, IR"R, R"IM IR"IM
6,5 6,5 12,0 18,0 10,5 ~
C RRC RRC LOC LOCI LO RCF
R, IR, Tl tIrra Jr. , IrTI R
f •• X,
6,5 ~
d~'~L"
6,5 12,0 18,0 20,0 10,5
0 SRA SRA LDC LDCI CALL LD SCF
R, IR, ra.Irf. Ira ,ITT! IRR, DA ra.x, R
-
6,5 6,5 6,5 10,5 10,5 10,5 10,5 6,5
E RR RR LO LD LD LD LD CCF
R, IR, f •• lrll R"R, IR"R, R"IM IR.. IM
8,5 8,5 6,5 10,5 ----a.o
F SWAP SWAP LO LO NOP
R; . IR, Irll Ta R"IR,
~------------------~~------------------~~----~----~------------'~'~--------
Bytes per 2 3 2 3
Instruction
Lower opcode nibble Legend:
R = 8-Bit Address
Execution cycles 1 Pipeline cycles
r = 4-Bit Address,
R1 or r 1 = Dst address
R2 or r2 = Src Address
Upper opcode _ _ A Sequence:

. nibble Opcode, First Operand, Second Operand .
Note: The blank areas are, not defined.
First operand Second operand

"2·byte instrliction; fatch cycle appears as a 3·byte instruction,
--~-~-----,'--SHAAP - - - - .......... -.--..-..r-~

536
(6) Instruction summary

Instruction
I Addr. mode Opcode Flags Affected Inst~~~ron I Addr. mode Opcode Flags Affected
and Byte Byte
Operation I dst src (Hex) CZSVOH Operation I dst src (Hex) CZSVOH
AOC dst, src (Note 1) 10 ****0* LOEI dst, src Ir Irr 83 -----
dst-dst+src+C dst-src Irr Ir 93
ADD dst, src (Note 1) 00 ****0* r-r + l' rr-rr + 1
dst-dst + src NOP FF ------
AND dst, src (Note 1) 50 -**0-- OR dst, src (Note 1) 40 -**0--
dst-dst AND src dst-dst OR src
SP-SP-2 IRR D4 dst-@SP IR 51
@SP-PC; PC-dst SP-SP+l
CCF EF *----- PUSH src R 70
C-NOT C SP-SP-l; @SP-src IR 71
CLR dst R BO RCF CF 0
dst-O IR Bl C-O
COM dst R 60 -**0-- RET AF -
dst-NOT dst IR 61 PC-@SP; SP-SP+2
CP dst, src (Note 1) AO ****-- RL dst R 90
dst-src
OA dst R 40
~ IR 91
****--
* * * X--
dst-DA dst IR 41 RLC dst R 10 ****--
DEC dst R 00 -***-- '~7 o~ IR 11
dst-dst-l IR 01
OECW dst RR RR dst R EO
dst-dst-l IR
80
81
-***--
l.ru ~ 7 ql IR El
****--
01 8F ------
IMR171-0 RRC dst R CO ****--
OJNZ r,dst RA rA ------ 4::D-I7 0~ IR Cl
r+-r-l r=O-F
SBC dst, src (Note 1) 30 ****1*
if r+O PC-PC+dst
dst-dst-src-C
Range' +127--128 DF 1-----
SCF
EI 9F ------ C-l
IMR(7)-1
***0--
INC dst
dst-dst+ 1
r rE
r=O-F
-***-- SRA dst
4:£Jr111 of IRR DO
Dl
R 20 SRP src 1M 31 ------
IR 21 RP-src
INCW dst RR AO -***-- SUB dst, src (Note 1) 20 ****1*
dst-dst+l IR Al dst-dst - src
IRET BF ******
~
FLAGS-@SP;SP-SP+ 1 , SWAP dst R FO X**X--
PC-@SP'SP-SP + 2'IM~(7)-1 IR Fl
JP cc, dst DA cD ------ TCM dst,src (Note 1) 60 -**0--
if cc is true c=O-F NOT dst) AND src
PC-dst IRR 30 TM dst,src (Note 1) 70 -**0--
JR cc, dst RA cB ------ dst AND src
PC-PC+dst dst-dst XOR src
Ranl!e: +127--128
LO dst, src r 1M rC ------ Note 1: These instructions have an identical set of addressing
dst-src r R r8 modes, which are encoded for brevity. The first opcode nibble is
R r r9 found in the instruction set table above. The second nibble is ex-
r X C7 in the following table to the left of the applicable addressing
X r D7 mode pair.
r Ir E3 For example, to determine the opcode of an ADC instruction
Ir r F3 using the addressing modes r (destination) and Ir (source) is 13.
R R E4
R IR E5 Addr Mode Lower
R 1M E6 dst src Opcode Nibble
IR 1M E7
r r [2]
IR R F5
LOC dst, src r Irr C2 ------ r Ir [ill
dst-src Irr r D2 [i]
R R
LOCI dst, src Ir Irr C3 ------
dst-src Irr r D3 R IR lID
r-r+ 1; rr-rr+ 1 R 1M lID
LOE dst, src r Irr 82 ------
dst-src Irr r 92 IR 1M ill
~-------SHARP----------------
537
Z8590/Z8590A Universal Peripheral Controller. '. LH8590/LH8590A
• Register
RO (DTC)
Date Transfer Control Regist~r
UPC register address (Hex): 00
I D7 I Da I Ds I D4 I D3 I D2 I Dl I Do I
(IRP) 1 (EOM) 0
I/O register pointer = 1
1 =:End of message
Disable data transfer =O _ _ _ _~(E=D:::X~):...J
(LERR)
Enable data transfer= 1 o =No limit error
1 =Limit error
No transfer error= O_ _ _ _ _----oc(X""E=R:,.:.R"")c..J
Transfer error= 1
R4 (LC) R5 (DIND)
limit Count Register' Date Indirect Register
UPC register address (Hex): 04 UPC register address (Hex): 05
I~I~I~I~I~I~I~I~I I D7 IDa' I Ds ID4 ID3 ID2 IDl IDo I

,-I- - - - L i m i t count value ,-I-----Indirection address
(range: 0-255 decimal OO-FF Hex) (Do=LSB)
R240 (MIV)
Master CPU Interrupt Vector Register
UPC register address (Hex): FO
I~I~I~I~I~I~I~I~I
LI------Vector data (Do=LSB)
R241 (TMR)
Timer Mode Register
UPC register address (Hex): F 1
T OUT modes
Reserved= 00
:=J L.o =No function
1 =Load To
Toout=OI
Tl out = 10 - 0 =Disable To count
Internal clock out = 11 1 =Enable To count
TIN I!lodes - - - - - ' ' - - - - - 0 =No function

External clock input = 00 1 =Load Tl
Gate input = 01
Trigger input(non-retriggerable) = 10 ' - - - - - - - 0 =Disable Tl count
Trigger input (retriggerable) = 11 1 =Enable Tl count
538
R242 (T1) R245 (PREO)

CounterlTimer 1 Register Prescilier 0 Register
UPC register address (Hex): F2 UPC register address (Hex): F5
I~I~I~I~I~I~I~I~I
COUNT MODE
LTI INITIAL VALUE 0= To SINNGLE-PASS
(RANGE: 1-.258 DECIMAL I=ToMODULO-N
01-00 HEX) RESERVED
'--------PRESCALER MODULO
01-00 HEX)
R243 (PRE1) R246 (P2M)
Prescaler 1 Register Port 2 Mode Register
UPC register address (Hex): F3 UPC register address (Hex): F6
I~I~I~I~I~I~I~I~I
I
COUNT MODE P2o-P27 I/O DEFINITION
0= TI SINGLE PASS o DEFINES BIT AS OUTPUT
1 = Tl MODULO· N 1 DEFINES BIT AS INPUT
CLOCK SOURCE
o = EXTERNAL TIMING INPUT
(TlN)MODE
1 = Tl INTERNAL
' - - - - - - - - PRES CALER MODULO
(RANGE: }-64 DECIMAL
01-00 HEX)
R244 (TO)
Counter/Timer 0 Register
UPC register address (Hex): F 4
I~I~I~I~I~I~I~I~I
L I - - - - - T o INITIAL VALUE
Oi-OO HEX)
R247 (P3M)
UPC register address (Hex): F7
I D71 D61 Ds] Dd DdD 2 ~ DI I Do I

L o PORT 2 PULL-UPS OPEN DRAIN
o PORT 1 PULL-UPS OPEN DRAIN
o P3s= OUTPUT
1 P35= INT
RESERVED
o P33=INPUT P3. = OUTPUT
1 P33= DAVl!RDYI P 3. = RDYI!DA VI
o P31= INPUT (TIN) P 36 = OUTPUT (T OUT)
1 P 31 = DA V2!RDY2 P 36 = RDY2!DAV2
o P30= INPUT P37= OUTPUT
1 P3D = lEI P37= lEO
o P32=INPUT
1 P32=INTACK
-.----------SHARP.....-..------.-.--
539
...........-....-..--------.-w.....---------
Z859O'/Z859O'A Universal Peripheral Controller
R248 (PIM)
I
LH859O'/LH8590A

upe register address (Hex): F8
1~1~1~1~1~1~1~1~1
1'-------P1ocPb I/O DEFINITION
1 DEFINES BIT AS INPUT
, R249 (IPR)
Interrupt Priority Register
upe register address (Hex): F9 (Write Only)
I D7 I D6 I Ds I D. D3 I D2 I Dl I Do I
RESERVED :J I IRQl, IRQ4 PRIORITY (GROUP C)
)
o = IRQl >IRQ4
1 = IRQ4 >IRQl
INTERRUPT GROUP PRIORIT Y
RESERVED = 00 0 IRQO, IRQ2 PRIORITY (GROUP B)
C>A>B=OO 1 o = IRQ2 >IRQO
A>B>C=Ol 0 1 = IRQO > IRQ2
A>C>B=Ol 1
B>C>A=100 IRQ3, IRQ5 PRIORITY (GROUP A)
C >B >A =101 o= IRQ5 > IRQ3
B >A >C =110 1 = IRQ3 > IRQ5
RESERVED = 111
R250 (IRQ) R252 (FLAGS)
Interrupt Request .Register Flag Ftegister
upe register address (Hex): FA upe register address (Hex): Fe
I D7 D6 I Ds I D. I D3 I D2 I D, I Do I
I USER FLAG Fl
IRQO = MASTER CPU
COMMUNICTAIONS USER FLAG F2
'- IRQ1 = P33 INPUT HALF CARRY FLAG
- I R Q 2 = P3, INPUT DE;CIMAL ADJUST FLAG
IRQ3 = P30 INPUT ' - - - - - OVERFLOW FLAG
IRQ4 = To ' - - - - - - SIGN FLAG
IRQ5 =T, ' - - - - - - - ZERO FLAG
RES ERVED '---------CARRYFLAG
R251 (IMR) R253 (RP)

Interrupt Mask Register Register Pointer
upe register address (Hex): FB upe register address (Hex): FD
I D7 I D6 I Ds I D4 I D3 I D2 I D, I Do I I~I~I~I~I~I~I~I~I
~~ ENABLES
ENABLES
1 ENABLES
IRQO
IRQ1
IRQ2
I'-'..- - - - - - - - R E--DONT
,-I
GISTER
CARE
POINTER
1 ENABLES IRQ3 (rrn)
1 ENABLES IRQ4
, 1 ENABLES IRQ5
R ESERVED
1 ENABLES INTERRUPTS
I .
-.--.--.-.-.-----SHARP ------.-.--------
540'
Z8590/Z8590A Universal Peripheral Cotroller LH8590/LH8590A
R254 (MIC)
Master CPU Interrupt Control Register
UPC register address (Hex): FE
o INTERRUPT REQUEST DISABLED 0-

1 INTERRUPT REQUEST ENABLED 1 END OF MESSAGE
o NO INTERRUPTUNDER SERVICE o WAIT ENABLE WHEN WRITE

1 INTERRUPT UNDER SERVICE 1 WAIT DISABLE WHEN WRITE
o NOMASTER CPU INTERRUPT PENDING ' - - - - 0 ENABLE LOWER CHAIN

1 MASTER CPU INTERRUPT PENDING 1 DISABLE LOWER CHAIN
o VECTOR OUTPUT L . . - - - - - O DISABLE DATA TRANSFER

1 NO VECTOR OUTPUT 1 ENABLE DATA TRANSFER
R255 (SP)
Stack Pointer
UPC register address (Hex): FF
I~I~I~I~I~I~I~I~I
C=STACK POINTER (SPO-SP7)
.-.--.-----SHARP-~--~--.-
541
Z8591/Z8591 A Development Device LH8591'1LH8591A
Z8S911Z8S91A
LH8591/LH8591A Development Device

The 64 pinLH8591 (Z8591) is the development
version of LH8590 Z8590 UPC with internal +5V 1
mask-programmed RqM. This device allows user PCLK 2
to prototype the system in hardware with an actual P3,/IEO 3
device and to develop the code that is eventually P3o/IEI 4
mask-programmed into the on-chip ROM of the P35/INT
LH8590. P32/INT ACK 6
The LH8591 is identical to the LH8590 with the RD,

following exceptions. WRs
• The internal ROM has been removed. A/D 9

added.
The LH8591A is the high speed version which Ph
can operate at 6MHz system clock. 4 PI.
MDS 23
IACK,RD 24
Top View
542
Z8591/Z8591 A Development Device LH8591/LH8591 A
• Block Diagram
Data Bus I/O
I/O
Interrupt Request 5
Interrupt Enable In
Interrupt
• Pin Description
LH8591 has the same functions as those of a 40-pin device LH8590, and the functions of the additional
24 pins are as follows:
AD-All Program memory address 0 Used for the access to the external memory of 4 K bytes.
Do-D 7 Program data I Reads the data through these lines from the external memory.
Interrupt acknowledge Active high. This signal becomes high during interrupt or in·
IACK/MR 0
Imemory read struction fetch cycle of LH8591.
-- Active low. This signal is output every memory fetch cycle
for the interface with the external ROM.
-- Active low. This signal becomes low during instruction fetch
-- Active low. This signal becomes low at the clock cycle just
before Op-code fetching.
----~--.-------SHARP--~--------
543
Z8592/Z8592A Development Device LH8592iLH8592A
LH8592/LH8592A Z85921Z8592A
Development Device

The 64 pin LH8592 (Z8592) is the development
version of LH8590 Z8590 UPC with internal +5V 1
mask-programmed ROM. This device allows user PCLK 2
to prototype the system in hardware with an actual P37/IEO 3
device and to develop the code that is eventually P30!IEI 4
mask-programmed into the on-chip ROM of the P35/INT 5
LH8590.
The LH8592 is identical to the LH8590 with the
following exceptions.
• The internal ROM has been removed. (But
there are 36 bytes internal ROM for a boot-
strap program).
ered and brought out to external pins .
• Contorl lines for the new memory have been
added.
MDS 23
MR/W flACK 24
Top View
......... :-.-.--.-.~-SHARP--.-.-.------
544
• Block Diagram
Data Bus I/O
1/0
Chip
Interrupt Request 5
+5V 1}-------------~
PCLK 2}---------------~
GND171}-----------------~~
Interrupt Acknowledge 24)--------------------~
Output
• Pin Description
LH8592 has the same functions as those of a 40-pin device LH8590, and the functions of additional 24
pins are as follows:
Ao-A 11 Program memory address 0 Used for the access to the external memory of 4K bytes.
Do-D 7 Program data I Reads/writes the data through these lines from the external memory.
Active high. This signal is always active during interrupt cycle of
lACK Interrupt acknowledge 0
LH8092.
Active low. This signal is output every memory fetch cycle for inter-
facing with the external RAM.
Active low. This signal becomes low during instruction fetch cycle
or write cycle.
- This signal is high during instruction fetching by LH8592, or low
MR/W Memory re,ad/write 0
while writing into the external memory.
---- Active low. This signal becomes low during clock cycle just before
Op- code fetching.
-----.-.---------SHARP . - . - - - - - - - - - -
545
Z8593/Z8593A Protopack Emulator lH8593iLH8593A
LH8'593/ LH859 3A, ~~~a:!593A Protopack

TheLH8593 (Z8593) is a ROM less version of
the standard LH8590 (Z8590) housed in a pin
compatible 40 pin package. o
interface to program memory. 2716 type EPROM P37/IEO 3
can be used- for program memory. P30/lEI 4
The -LH8593 allows the user to build the pro- I;'3;/lNT 5

totype and pilot production units. When the final P32/INTACK 6
program is established, the user can then switch
over the LH8590.
DBo
Top View
546
• Block Diagram

*1*2*3r ' " '
Data Bus I/O
I/O
Chip
Interrupt Request 5
Interrupt Enable In
Int errupl Enable OUI

~ : This is equipped witch ROM.
• Pin Description
LH8593 pins are compatible with those of LH8590 . For pin description, refer to those of LH8590.
.-..-.-.--.---SHARP------~-~--
547
~8594/Z8594A Protopack Emul;:ltor LH8594/LH8594A
LH8594/LH8594A ~:=5S:A Protopack

• De.scription • . Pin Connections
The. LH8594(Z8594)is a RAM version (16K bits
RAM) of the standard LH8590, housed in a pin
compatible 40 pin package. 0 P36
interface to program memory, and has 36 bytes of P37/IEO 3 P27
internal ROM for a bootstrap program. P30/lEI 4 P26
This device allows the user to build the pro- P35! INT 5 P25
totype, and when the final program is established, P32/INTACK 6 P2.
the user can then switch over the LH8590. P23
The LH8594A is the high speed version which P22
P2,
P33
P3.
Ph
PIs
Top View
548
• Block Diagram

*1*2*3' • If •
Data Bus
Interrupt Request 5
Interrupt Enable In

e : This is equipped with RAM.
• Pin Description
LH8594 pins are compatible with those of LH8590. For pin description, refer to those of LH8590.
------------------SHARP - - - - - - - - - - - - - - - -
549
Key"'encoder and Data Transmitter/Receiver LH8661
LH8661 Key-encoder and Data TransmitterlReceiver
• Description
The LH8.661 is a high performance and multi-
• Pin Connections
purpose interface LSI which has functions such as RTS

signal encoding from key matrix circuit, serial data 0 CTS
XTAL2 2
transmission/receiving and parallel data input/
XTALI 3 SLCT
output.
The LH8661 can be operated on one of the fol- INPUT' PRIME
lowing five modes: FAULT
• Encodes a key matrix signal, and outputs the RESET 6 BUSY
data to a serial port (Mode 1). NC 7 KSO,
• Encodes a key matrix signal, and outputs the KSO"
data to a parallel port (Mode 2).
NC 9 KS02
• Encodes a key matrix signal, and outputs the
DS/RQ KSO,
data to both serial and parallel ports (Mode 3).
• Encodes a key matrix signal, and outputs the DCD
data to serial port, concurrently, serial input ACK/RD 12 DTR
data is converted to parallel and output to a par- DATAl KSIs -
allel port (Mode 4). DATA2 KSI7
• Parallel input data is converted to serial and out- KSI6
put to a serial port (key scanning function is KSI5
DATA.
sleep)(Mode 5).
DATA5 I KSI.
DATA6 KS13
DATA7 KSI2
DATAs
• Features Top View-
1. Key encoding
• 102 keys compatible with JIS ASCII array can
be encoded. ers.
• Selectable encoding (compatible with ]IS 4. Serial/parallel data conversion
6220-1976 information exchange-code) or • This device can be used as a serial/parallel
no·encoding (native code). data converter with/without a matrix key
• Encoded data can be transferred in serial or board.
output in parallel (mono/bi-modes available) 5. Data buffers 80 bytes X 1 or 40 bytes X 2.
2. Serial data communication 6. On-chip crystal oscillator circuit.
• Encoded· key data can be transferred in asyn- 7. Single+5V power supply
chronous serial mode. 8. 40-pln dual-in-line package
• Serial port can be used as an RS232C inter-
face by attaching buffers.
• Selectable data format (data 7/8, parity, stop
bit 112).
• Selectable baud rate (110, 150, 300, 600,
1200, 2400, 4800, 9600, 19200).
3. Parallel data input/output
• Encoded key data can be output to a parallel
port in parallel.
• Parallel port can be used as a printer interface
compatible with Centronics by attaching buff-
-----------..--..-.--SHARP .....--.-.-----....-.--
550
Key-encoder and Data Trahsmitter/Receiver LH8661
• Block Diagram
Key Scan Data

In -
Parallel
Data
I/O
Logic
and
Control
Mode
Registers
Buffer
80
Byte
Encoder Buffer
Pointer
Vee 1
GND
In~ernal Control
Logic
~-------'-'--SHARP _ _ _ _ _ _ _ _ _ _ _--.r
551
Key-encoder and Date Transmitter/Receiver LH8661
• . Pin Description
KSI 1 -KSI 8 Key scan input I Active low. Key scan data signal input
KS0 1 -KS0 4 Key scan output 0 Key matrix scanning signal output
Bidirectional
DATA 1 -DATA 8 Data bus System data bus
3-State
-- Active low. Data strobe signal when mode 1 to 4 is
DS/RQ Data strobel request 0
selected; request signal when mode 5 is selected.
--- Falling edge active. Acknowledge signal when mode 1 to
ACKIRD Acknowledge/read I
4 is selected; read signal when mode 5 is selected.
Active high. Indicate printer busy (input) when mode 1
BUSY Busy Bidirectional to 4 is selected; indicate data buffer full (output) when
mode 5 is selected.
Active low. Indicate printer disable (input) when mode
---
FAULT Fault Bidirectional 1 to 4 is selected; indicate data buffer full when mode 5
is selected.
Active low. Output printer initialization signal when in
INPUT PRIME Prime input Bidirectional mode 1 to 4; input data buffer pointer initialization sig-
nal when in mode 5.
Active high. Input printer select signal when in mode 1
SLCT Select Bidirectional to 4; indicate that parallel data output is available to de-
vice when in mode 5.
RxD Received data I Receiving data line.
RTS Transmission request 0 Active Low. Indicate readiness of data transmission.
CTS Transmission enable I Active Low. Indicate data transmission enabled.
DTR Data terminal ready 0 Active Low. Data transmission request signal.
DCD Reception enable I Active Low. Indicate data reception enabled.
RESET Reset input I Active Low initialization input.
XTAL 1
Crystal Bidirectional 7.3728 MHz crystal oscillator connected.
XTAL 2

Input voltage VIN -0.3-+7·0 V
Output voltage VOUT -0.3-+7.0 V
Operating temperature Topr 0-+70 'C
Storage temperature Tstg -65-+150 'C

Clock input high voltage VCH Driven by external clock. 3.8 Vee V
Clock input low voltage' VeL Driven by external clock. -0.3 0.8 V
Input high voltage VIH / 2.0 Vee V
Reset input low voltage VRL -0.3 0.8 V
Output high voltage VOH IOH= :-250,uA 2.4 V
Output low voltage VOL .IoL=2mA 0.4 V
Input leakage current IIL 0;£ VIN;£ +5.25V -10 10 ,uA
Output leakage current IOL 0;£ VIN;£ +5.25V' -10 10 ,uA
Reset input current IIR Vee=5.25V, VRI,=OV -50 ,uA
Supply current lee 180 mA
----~------SHARP.-----.--.-;...-
552
Key-encoder and Data Transmitter/Receiver LH8661
Vee Vee
Vee Vee
From output 2.1kO From output 18kO

1.5kO
under test under test
:>O~.......-J .Xl~>:--O
Crystal 2
74LS04 15pF MAX.
L----o--o Crystal 1
;;; 15pF MAX.
Test load 1 Test load 2 External C. G. circuit
( i ) Reception (Vee = 5 V ±5%. OSC freq. = 7.3728 MHz. Ta = 0 to +70°C)
No. Parameter Symbol Note

Time from DCD to DTR signal output Tb DCD(DIR)
DCD \
DTR
RxD
f-e---CD- ~
(ii) Transmission (Vee = 5 V ±5%. OSC freq. = 7.3728 MHz. Ta = 0 to +70°C)
No. Parameter Symbol MIN. Unit Note

® Time from RTS ! to CTS signal acknowledge Td RTS(CTS) 2.7 p.s
® Time from RTS ! to data (TxD) output Td RTS(TxD) 25 p.s
--®...;
,
®
----'--.-----------SHARP - . - - - - - - . - - . - . - -
553

(i)' Input (Vcc=5 V ±5%, OSC freq.=7.3728 MHz,Ta=O to+70°C)

CD INPUT PRIME pulse width Tw IP 7.0 ps
@ Time from INPUT PRIME t to RQ signal output Td IP (RQ) 13.8 ps
® RQ pulse width . TwRQ 4.3 ps
@ Data settlement time from RD ~ Tr RD (D) 16 ps
INPUT PRIME
RQ -~
: ~ ~
' @ ' - - - -
DATA1-DATA s
RD
- ------Jx{S@-j I
~---------------------
------------------
(ii) Output (Vcc=5 V±5%, OSC freq. =7.3728 MHz, Ta=O to+70°C)

® Time from INPUT PRIME t to ACK ~ TdIP(ACK) 5.0 ps
® Time from ACK ~ to data output TdACK(D) 23 ps
(j) Time from data to DS ~ TdD(DS) 5.4 ps
® DS pulse width TwDS 2.6 ps
,
INPUT PRIME
DATAl -DATAs ________-+____- J
• Operation Mode Setting types of keyboard switches.

The LH8661 is available in five operation mod- The status control circuit should consist of op-
es which are obtained by combining the key data' eration mode selector, transmit data format selec-
encode, parallel data transfer, and serial data tor, and baud rate selector. The LH8661's opera-
transfer functions (Fig_I). An Operation mode is tion mode is selected by these settings.
selected with mode switches (MODEI-MODE4) The compatible keyboard types, their configura-
which control the scan signal, SCANl, and key tion and status control switches on the key matrix
scan input signals, KSI 5 -KSI8 . and shown in Fig. 3. Conformity of key data to the
• Key Matrix Configuration 1IS code requires the key arrangement shown in
The key matrix consists of key scan input sig- Fig. 2. The status control circuit should consist of
nals (KSIl-KSI s) and scan signals (SCAN l -SCAN l6 ). the SCAN 1 -SCAN 2 and key scan input signals
The matrix requires status control circuit (switch- (KSIl-KSI s). (Note. Shaded sections in the fig. are
es plus diodes) in addition to the maximum 102 not usable.)
554
m===lfi]] RS232C RS232C Parallel 'output
~:
IlOI~I~ ]o!;/~~
LH8661
lIII11 1Il\
• i .Q. ']} LH8661
serialoutputd : ..--,.Q. {} 1-=
\~ .Serial outpu/4t • ~ Printer with
Keyboard ':1! ;" II " ~ Centronics interface
(i) Operation mode 1 Keyboard
(iv) Operation mode 4
-~:===;;;;=~--I~~ Serial output

~
D rn 0:=<)\ LH8661 I~
Parallel output
Centronics interface (v) Operation mode 5
(ii) Operation mode 2
m===lfi]] RS232C
~O=<)CiLH8~~1 iJD=O~~
Serial !tputI..(J. is I P arall~1 L::-----:---'
j_II\~utPut
@. ~ ~ Centronics interface
Keyboard
(iii) Oyeration mode 3
Fig. 1 Description of device operation modes
9 SK 2
SP SK 3
SK 4
+ SK 5
5 SK 6
6 SK 7
*
EXT 7 / SKs
Control
key
r-- A + c -I
Notel: A, B and C are local scan blocks Alphanumeric sectioni2j-KANA .
(S I) sectIon
Note 2 : Shaded sections in the diagram are not usable (SO)
Fig. 2 Key types and key arrangement
-~------SHARP-~-----'-
555
J
Key'-encoder Data Transmitter/Receiver LH8661
• Keyboard Matrix
(1) Key types and arrangement (2) Transmit character codes
The LH8661 is capable of encoding data from The LH8661 can encode key data into]IS or na-
up to 102 types of keys arranged on a key matrix tive codes. Fig. 4 shows the transmit character
which consists of key scan input signals. KSI1-KSIs• codes that conform to the ]IS C 6220-1976 In-
and scan signals. SCAN 3 -SCAN 16 . The 102 types of formation Exchanging Codes. Fig. 5 shows the na-
keys are divided into the following two blocks: tive transmit character codes. The following figure
CD Data key block: Consists of 96 keys shows typical combinations of keyface symbols in
arranged on the matrix composed of scan signals the alphanumeric and Kana sections of a key.
SCAN 5 -SCAN 16 and key scan input signals /
KSI1-KSI s . When the ]IS code system is selected Alphanumeric section E )/ ~ KANA section
(code select switch at OFF). key data is encoded r-----:-, /
I /
into the transmit character codes shown in Fig. 5. . ;/
In this case the key arrangement shown in Fig. 3 /@
/
is required. When the native code system is / :;I
selected (code select switch at ON). key data is en·

coded into the transmit character codes as shown
in Fig. 6. Fig. 3 Keyface symbols
® Control key block: Consists of six keys on (3) Key entry operations
the matrix which is composed of scan lines The LH8661 supports the following key entry
RCAN 3 -SCAN 4 and key scan input signals features:
KSI1-KSI s . These keys are used to control data • Key contact bounce time of approx. 5 ms.
key encoding and key scanning. The shaded por- • Two-key rollover an(l N-key lockout.
tion of the control key block shown in Fig. 2 is not • Typamatic capability
usable. If any data key other than those listed below is
(51) (50)
b7 0 0 0 0- 0 0 0 0 1 1 1 1 1 1 1 1
b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
b. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b 3 _b 2 b 1 b o Coil
Row 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 0 0 0 0 5P 0 IB P
,
P SK16 SK1 5P - 9 ,. CD @
1 Q a q SK 2 , ® @
0 0 0 1 1
..! A 7' -T .b.
0 0 1 0 2 2 B R b r SK3 r -1 .:/ ;t @ @
0 0 1 1 3 ETX :11= 3 C 5 c 5 SK4 J ? T -t ® ® i E5C(1BH)+A(41H)
0 1 0 0 4 $ 4 D T d t SK 5 , ;r: ~ -\" @ @ t E5C+B(42 H)
0 1 0 1 5 % 5 E U e u SK 6 >t T ~
® (~)' E5C+C(43H)
0 1 1 0 6 & 6 F V f SK 7 '7 7J = :I (j) @ E5C+D(44H)
0 1 1 1 7 . 7 G W g W
V
SK 8 7 :f- :;I '7 ® @ HOME E5C+H(48H)
1 0 0 0 8 B5 ( 8 H X h X SK 9 -{ 7 .:t- I) ® @ 5K 17 E5C+E(45H)
1 0 0 1 9 HTAB ) 9 I Y i y SKIO .,
Ir / JL- ® @ 5K18 E5C+J (4AH)
: J Z SK11 /, @ 5K19 E5C+K(4BH)
1 0 1 0 A LF
* j Z
'" ::J l; ®
1 0 1 1 B ESC + ; K [ k I ;I- ~ ~ I'l @ @
1 1 0 0 C < L ¥ I I SK12 -\' Y 7 '7 @ @
1 1 0 1 D CR - = M 1 m } SKI3 :J. A_ ...... :-- @ @
1 1 1 0 E 50 > N 1\ n SK 14 -I! >I< . @®
-
"
1 1 1 1 F 51 / ? 0 0 DEL SK15 .~ ') '? '@ @
Fig. 4 Transmit character codes (1) •.• J IS codes
---~--------~-SHARP-'-"'-'-------""-'---
556
b3 '0 0 0 0 1 1 1 1 .1 1 1 1
b2 1 1 1 1 0 0 0 0 1 1 1 1
b1 0 0 1 1 0 0 1 1 0 0 1 1
bo 0 1 0 1 0 1 0 1 0 1 0 1
CoIl
b, b6 b 5 b4 Row
4 5 6 7 8 9 A B C D E F
0 8( ~ > z ':/
1
0 0 0 0 EXT -> 7 / SKa SK 16 p @ WJJ) J v@
iv
0 .~
.:::L -iz T
., ?
0
1 0 0 1 1 ENTER 6 SK 7 SKIs 7'-\", @ E -1 H ® / ;t.. X @.
<-
* -t' -( 11 it
0
0 -
& [ j r -
1
1 0 2 RETURN ~ 5 SK6 SK I4 6 -t R @ G ® (j]) C @
;t 0
A =l' J:l '/
0 %
1 0
1 1 3 HTAB i 4 + SKs SKI3 5 '"
¥ I@ T (j) F ® ] .b.IJ V I:::@
.J: - 11
"
0 -
1
1 0 0 4 LF HOME 3 SK4 SK I2 4$? A ® y
? "'- /
® D @
Y
*
:@
'r
B (j])
::::I
0
1
1 0 1 5 BS SKI9 2 SP SK3 SK 11 3:j:1: 7 --® u -j-® S ® ;+@ N @
7 ~ v ~
0 "
*
1
1 1 0 6 ESC SKIs 1 9 SK2 SK 10 2 @ 0
7 '7
• I
--
@ A 7® L IJ@ M@
'£:
0
1 1 1 7 DEL SKI7 0 SKg
I
1 '@ 9 ) 3
o '7® Q;$ICD K @ ,
<
1 8 SKI
;;r :I / ,*'
Note: b 7 =1 when KANA key is ON, b7 =O when off.
Fig. 5 Transmit character codes (2)... Native codes
pressed and held for more than 1 second when the The serial data format can be selected from 7
lIS code sytem is selected, the corresponding bits with parity, 7 bits with no parity (b 7 fixed at
transmit character code is repeatedly entered at a '0'), and 8 bits with no parity. Selection is ex-
frequency of approx. 20 Hz. When the native code ecuted with bit 7 or 8 and with parity switch (see
system is selected, all the 96 data keys are effec- description of transfer data format setting).
tive for the auto repeat function. Fig. 6 shows the serial data format.
(1) Transmit mode
IJ2EkJ [ESk] I BS I ILF I IHTABI I RETURN I The LH8661 automatically adds one start bit
I ENTER II ETXI and two stop bits to transmit data. It holds TxD at
The above control keys are not effective for the high to maintain mark status between characters.
auto repeat function. (2) Receive mode
Receive data must have one start bit, eight data
• Serial Data Transfer bits, and at least one stop bit. While the receiver
The LH8661 transmits serial data via RS232C has a two-stage buffer, data will not be protected
interface when in modes 1, 3, or 5. It can transmit in the event of an overrun.
and receive serial data when in mode 4_
~-'-'-'-----SHARP-'-'------
557
~~ .......... ~~ ......................... .........................
Key':'encoder and bata Transmitter/Receiver
Transmitted data (No parity)

~
LH8661
~
T
.
1-
Start bitT·
' - - - - 8 data bits
' - - - - - - - - - - - - 2 stop bits
Transmitted data (With parity)

ISP ISP I P I b6 I bs I b. I b3 I b2 I bl I bo IST I
TT .
L start bitT
' 7 data bIts
L - - - - - - - - - - O d d parity
' - - - - - - , - - - - , - - - - - 2 stop bits
Reception data (No parity)

I bs I b. I b3 I b2 I bl I bo IST I
-r
I
T Start bit
L _ _ _ _ _ 8 data bits
1 stop bit
Reception data (With parity)

I SP I P I b6 I bs I b. I b3 I b2 I b, I bo IST I
TT _
I
L.
StaJ;:t
- - - - 7 data bits
' - - - - - - - - - - - - O d d parity
' - - - - - - - - - - - - 1 stop bit
Fig. 6 Serial data format
• Parallel Data Transfer
When in modes 2, 3, and 4, the LH8661 can ) nal to low and sets the ACKNLG signal at high.
transfer parallel data to a printer having Centro- Seeing that the ACK signal (inverse of ACKLNG)
nics interface. When in mode 5, it can receive pa- is set to active low, the LH8661 transmits print
rallel data through Centronics interface. data. It then sets the DS signal to low a given time
(1) Centronics interface (parallel data trans- period after completing data transmission. The
mission) printer uses the DS signal to read the data on the
The LH8661 maintains INPUT PRIME at low data bus (DATA1-DATAs),and prints it.
for a given time period after being reset. The The data transmission timing is shown in Fig. 7.
attached printer usually uses this ~ignal to initial- (2) Parallel data reception
ize its internal circuitry. The LH8661 then tests When the LH8661 is placed in mode 5, the {la-
the SLCT and FA UL T inputs to see whether or rallel data port becomes a Centronics input port.
not the printer is ready for operation. When trans- Input data received through this port can be \,lUt·
mitting data, the device also tests for BUSY sig- put in serial form after being subject to parallel-.
nals from the printer. When signal is at high, the to-serial conversion. The control signal SLCT is
printer is busy printing and the device waits for set to high when the LH8661 settles in mode 5.
the printer to become ready. When the printer re- In receiving parallel data, the INPUT PRIME
turns to the ready status, it resets the BUSY sig- signal must be set to low for a given time period.
~'-'------SHARP---'----'-"---'-
558
INPUT PRIME (output)-V
BUSY (input)
\~----------------------------------------------
ACK (input)
DA TAl -DAT As (output) _ _ _ _ _ _ _ _ _ -'X. .___ D_a_ta_se_tt_led

_ _ __
DS (output)
Fig. 7 Parallel port output timing
INPUT PRIME (input) ~
BUSY (output)
\'-----------------------
RQ (output)
DAT Al -DAT As (input) _ _ _ _ _ _ _ _ _ _ -'X'-___ D_at_a_s_et_tl_ed_ _ _ __
RD (input)
Fig. 8 Parallel port input timing
Receiving this low transition signal, the LHB661 BO-byte length of the buffer is used to hold key
responds by initializing the data buffer pointer entry data. When the device is in mode 4, the buf-
and setting both the BUSY and RQ signals to low. fer is divided into a 40-byte segment to hold key
Seeing that the ACKLNG signal is set to high, entu data and another 40-byte segment to hold
the data output device outputs data, then sets the serial input data. When in mode 5, the full
DAT A STROBE signal to low after a given time BO-byte length of the buffer is used to hold para-
period. The LHB661 uses this signal to read data llel input data.
off the data bus (DAT AI-DAT A8). The LHB661 When the buffer becomes full, the LHB661 be-
then sets the RQ signal to low to repeat data read haves as follows:
operation until the data buffer becomes full. • No longer writes key entry data into the buffer.
When the data buffer becomes full, the LHB661 • During serial data input, sets the DTR signal to
activates the BUSY and F AUL T signals to inform high to indicate buffer-full status to the data:
the output device. The parallel port input timing is output device (having RS-232C interface). The
shown in Fig. B. LHB661 accepts no serial data transferred
while the DTR is at high.
• Data Buffer • During parallel data input, activates the BUSY
---
The LHB661 has a built-in BO-byte RAM for and F AUL T signals to indicate buffer-full sta-
data buffer, which is used to hold key entry data, tus to the parallel data output device. The
serial input data or parallel input data. LHB661 outputs no RQ signal while the BUSY
When the device is in mode 1, 2, or 3, the full and F AUL T signals are active.
- - - - - - - - - - - - - - - - S H A R P -.-..-.....-.--~-
559
Support Tools for Micrcomputers
Development Support System SM-D-8000 IT LH8DH110
LH8 DH 11 0 Development Support System SM-D-8000 II

• Description
This system operates under control of the floppy
disk operating system (FDOS), and incorporates
software for developing Z80 application programs.
The software includes a relocatable macro assem-
bler, a text editor, and a debugger. The system
facilitates Z80 software development ap.d mini-
mizes developing time. In addition, program de-
veloping software for Z8, Z8000 and SM series
can also be used in this system. The system can
also be an aid for developing Z80A and Z8 sys-
tems by connecting the In-circuit Emulator (Z80A
or Z8) to the system. In conjunction with a PROM
writer, the system writers EPROMs directly furth-
er reducing developing time.
• Features
1. Z80A CPU (clock frequency>: 4MHz)
2. RAM: 64K bytes
3. Two double-sided double-density floppy disk Baud rate 110-19200B
drives in standard (capacity: 2M bytes) (9 levels selective)
4. -RS232C 2ports 5. Optional hardware
20mA curren loop 1port PROM writer
(shared with RS232C port) Z81Z80B In-circuit Emulator etc.
• Block Diagram
Protect SW .
F'DO
PRO SW
RS232C RS232C
l.
SUB CPU board MAIN CPU borad
system bus
FDJ'
POWER SW
562
Development Support System SM-D-8000 IT LH8DH110
• Software Organization
Control ----i[ Resident monitor
-l
processor Command line interpreter
-r
Text editor
Relocatable macro assembler
Resident software Linker
ZOO (standard) Librarian
Symbolic debugger
--i
Language System generator
SM-D-8000II processor SM series software package
Operating
system Cross software for I-chip microcomputer
(option) Z8 cross-assemhler development
Z-UPC cross-assembler
Z8000 software package
Utilities
(option)
-E PROM programmer
Z80B in-circuit emulator debugger
Z8in-circuit emulator de1:iugger
~
~ASCAL
High-level FORTH
language (option) FORTRAN
COBOL
BASIC
CP/M is a registered trade mark of Digital Research Inc.
--.---.---SHARP....-..---~---
563
...............,.....,..........
Development Support System SM-D-a100
,
.......
......,.~.....,.....,.....,....,.....,
LH8DH136
,
.....,.....,.....,~
LH8-DH130 Development $upport Syste~ SM-D-8100

• Description
This system in based on the Z8001 CPU and
operates under control of the floppy disk operating
system (SM-DOS8100). The system provides a
standard set of software for developing Z8000
programs. There include C compiler, relocatable
macro assembler, text editor and linker for cost
effective software development. The SM-D-8100
consists of main unit and a floppy disk'drive
unit. The main unit is provided with four RS232C
ports so that the system can be connected to other,
devices. The system has 256K-byte of RAM for
flexible upgrading in the future.
• Features
1. Z8001 CPU (clock frequency: 4MHz)
2. RAM: 256K bytes (1 parity bit per 8-bit)
3. Two double-sided double-density floppy disk
drives in standard (separate unit), (Capacity:
2M bytes)
4. Four RS232C ports Baud rate: 110-19200B
, (9 levels selective for each port)
5. Centronics parallel output port
6. High-grade language, C compiler in standard
7. Optional hardware:
SM-E-8100 In-circuit Emulator
------------SHARP---------.-...... -----
564
Development Support System SM-D-8100 LH8DH130
• Block Diagram
Z8001
CPU 1-_-:---' ~::--------I ZBI Bus
MH Buffer. 1-'----11',
L-_~=====L_ _~4~M~H~z~------_4BCLK
ZBi Bus
Buffer
,+12V
-12V
'+ 5V
___ ___ ___ ..J, GND--...----r-;--.....
'-T-r-...,-,r--r-r-"T""T'......
Disk Drive Disk Drive

L...-._--I (FD 0 ) (FDI)
AC 100 V
.---Control processor (standard)

I-
Resident monitor
Lcommand line interpreter (CLI)
t--- Language processor
Resident software (Z8000) (Standard)
C compiler
Text editor
Relocatable macro assembler
SM-D-8100
Linker
Operating system t-- librarian
(SM - DOS 8100) Debugger
Translator (Z80-+Z8000) (Standard)
PASCAL (under development) ,
Floating point arithmetic routines (under development)
E
Cross software (Option) ,
Z80 cross assembler (Development planned)
Z8 cross assembler (Development planned)
Z - UPC cross assembler (Development planned)
"--Utility (Option)
LGeneral-purpose OS (Pianned)
.-.....----------SHARP---~-~.-.-----
565
De,v.elopment Support System SM-D-820.O LH8DH140
LH8DH140 Development Support System SM-D-8200

• Description
LH8DH140 is a microcomputer system using the
28001CPU. It is used as the microcomputer de-
velopment support device or as the general-purpose
microcomputer system, with the SM- UX8000 gener
ai-purpose operating system mounted; which is based
on the system of Bell Laboratories.
• Features
1. Main memory function
• 768K byte RAM
• 1 parity bit for each 8 bits
• Memory management function
2. Supplementary memory function
• Hard disc drive: 1
Winchester type, 8 inch, 20M bytes
• Floppy disc drive: 1
for back up of hard disc equipment
double-side double-density, 8-inch, 1M
bytes
3. I/O interface
• Serial I/O interface: 4 ports
RS232C compatible
Baud rate: 110-9600 for each port
• Parallel I/O interface: I-port
Centro nice compatible
4. Optional hardware
·28000 in-circuit emulator (SM-E-8100)
• 28000 evaluation board
• 28 in-circuit emulator
566
.....................................................................................
• Block Diagram
,,r - - - - ,,
- - -- Main Board Slot 0- - - ----,
AC100V ::[)=I ~ , RAM Internal Bus ZBI ,

Power Supply
I 512K Bytes I I Bus 1--1,--'
: with Parity Buffer ~
I I J ' Memory-Bus 1
~ ~ ~ ~ 1 Buffer_ ,
'+ "I
"" "" ""
+ '" Z ,
L ____________ --------'
I
r - - - - - - - - - - - - --Main Board Slot 1 - --- -- ---l

1 I
: ~Oo~ ' - - Z8010 Memory RAM - :
nr
, r--- ROMmn MMU -Bus 256K Bytes 1
:, Clock ~8;~1 32K Bytes with Parity !
~ I ~
,
OSC_
'Hz Internal Bus
ZBI Bus
r-t--
1
III
~
, ~ 4MHz BCLK f--r--- N
, &~ I 'I
16MHz MCLK
L_'--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_...::..;.._'--_-_-_-_--_--_-_L--.....l J
r--------------- Main Board Slot 2 - - - - - - - - - ,
1 1
Control Buffer r- I
.-_ _ _...,J ~1l-----1 Hard ROM RAM DMA .-.!-
, Disk 8K Bytes 2K Bytes r- I I
: Drive
.--,------J---l ~I----; Control
W I I
'-----I-nt-'ernal Bus
~ ~~~e~us 1
:
1 1 1
1 1
, Z80A CPU 1
1
L_____________ _ _________ , J
r - - - - - - - - - - - - - Main Board Slot 3- - - - - - - - - - - ,

--t r;----l Floppy r----1 DMA '
r-ttr--i ~
,
I
Disk Drive Control
I Internal Bus ZBI Bus

1
:
t----t-- 7
1
I
,
Z 8036 CIO
Centronix
II Z 8030 X 2
Buffer _I
1--;--1----'
, ZBI is the
, Interface RS232C Interface 1 Trademark
L- - - - - - -.i.j - - - - -.u -J:±. -.ll----,.t..±. - - - - - - - -1 of Zilog_ Inc_
Centronix Parallel Output RS232C Ports HD-10F
Floppy
Hard Disk Drive
Disk Drive
I Power Supply
u
q
AClOOV
567
Kernel
Shell
System utilities
SM-UX8000 User access control

Operating system File managment
Status display
System maintenance
Program run control
Software development tools
Languages
Assembler (For Z800l)

C compiler (For Z800l)
C source beautifying program: cb
C program checker:lint
Spreadsheet interpreter
, FORTRAN 77 compiler (option)
:
Text processing
1__ Text editor:ed

Fstream editor:sed
Programming support
~
Debugger:
adb
Loader
SCCS (Source code control system)
: Program maintenance program
,
Cross software
L Z8 cross software
r=..= Z80 cross software
!
.-.-.----~--SHARP-------------
568
Z80B In-Circuit Emulator LH8DH312
LH8DH312 Z80B In-Circuit Emulator
• Description
This is an SM-D-8000 II option, which provides
emulation functions for Z80B systems. The emu-
lator operates under the control of FDOS. It
facilitates debugging and reduces development time
and costs.
• Features
1. Support Z80B (6MHz) system
2. Real-time emulation
3. User system memory: 64K bytes
4. User 110 port: 256 ports
5. Memory address mapping function (unit:4K
bytes)
6. Hardware break point: 2
(with 16-bit counter)
7. User system RAM: 64K-byte static RAM
8. In-circuit emulator debugger
9. Execution modes of user program
(i) Real-time
(ii) 1 step (number of steps can be set)
(iii) Trace
(iv) Snapshot
10. Program can be change at mnemonic.
11. I/O device if the user system can read the
RETI instruction in the user RAM.
12. All the interrupts (NMI,mode 0,1,2) can be
used by the user.
---~------SHARP--~~---~
569
Z80B>ln-Circuit Emulator LH.8DH312.
• Block Diagram
~------------------------------I
Adress Bus Address Bus I Head Board
I===~>t~ :
:==:::;~====~ Z80B Data Bus ~SI/l.~I--"140Pin
CPU - Control '" Plug
Bus c6
I
9 Clock Selectabl,e
I Clock Circuit I._S_W_J CPU Unit
Fla - _ Main Board
Cable~ --------------------------------, I
I
I
I I
I
I
I I
I I
I
I .,
I "
'--'-'--1'-1-t
I !
I .=i
I
I
I·
I
I ROM I
I I
~--------------------------------~---------~
570
Z8 In-Circuit Emulator n LH8DH321
LH8DH321 Z8 In-Circuit Emulator II

• Description
Z8 in-circuit emulator II (LH8DH321) is a de-
vice which has the function to support the develop-
ment of the Z8 MCU 8-bit single-chip microcomput-
er (4Kbytes internal ROM: LH0811/LH0813, 2K
bytes internal ROM: LH0801/LH0803)_ Software
developed by the host computer can be downloaded
via RS232C into this emulator for program debug
purposes.
Prototype Z8 application systems under develop-
ment and developed systems can be emulated on
the real time basis.
By debugging the user system while emulating,
the development term of the user system or mainte-
nance period becomes shorter.
• Features
1. Usable for 4K and 2K bytes internal ROM 6. Break point possessing 8-bit break counter can
2. Stand-alone type: load the program from the be set: up to 4096 in the internal ROM (up to
host computer, and save the program to the 2048 in the 2K internal ROM) 1 in the exter-
host computer after debugging. nal ROM/RAM.
3. Mapping RAM can be designated for memory 7. Step and trace of user program can be ex-
area both of program and data. ecuted.
4. User program in the external ROM can be 8. Contents of user program and register can be
~
5.
transferred to the mapping RAM.
Possess line assembler and reverse assembler,
making debugging effective.
displayed and changed.
9. 110 ports and register files can all be executed
by the user.
7 ~=
• Block Diagram
Z8
Data r-....L.--,
Bus
Z80A
CPU
J1 J2
Terminal Host
571
Z8000 Evaluation Board LH8DH330
LH8DH330 Z8000 .Evaluation Board.
• Description
This board is designed for evaluating application
systems .using the Z8000 I6-bit microprocessor.
It is also available for a development system due
to the emulation function.
• Features
1. User RAM: 32K bytes
2. Monitor ROM : 8K bytes
3. Break point :- I point
4. Support for debugging Z800I CPU Z8002
, CPU programs
5. In-circuit emulation functions
6. Object program execution : Real time, single
step, and trace
7. Connection with SM-D-BOOO IT /SM-D-8100
via RS232C interface
• Block· Diagram
Segment 7
Address/Data 16
Z8001
Z8002 User's Connecter
CPU Control 7
Status 12
16
Console
SM-D-8000 II
572
ZSOOOln-circuit Emulator SM-E-S100 LHSDH340
LH8DH340 ZSOOO In-circuit Emulator SM-E-SIOO

• Description
The SM-E-8100 supports the development of
28000 systems based on either the 28001 or
28002. A developed program loaded in the user's
system memory or, the emulator memory (user RAM
area) can be executed in real time. The SM-E-
8100 can emulate not only programs supplied from
a host equipped with RS232C ports such as the
SM-D-8000 II or SM-D-8100 but can also oper-
ate as a stand alone system.
• Features
1. Emulation for both 28001 and 28002
2. All I/O ports opened for the user
3. User-opened RAM: 32K bytes (e~pandable)
4. Hardware,break points (status, N/S, R/W, B/W
available)
5. Break point counter (16-bit) available
6. Program execution : Real time, single step,
trace, and snap shot
7. Down load and up load from a host computer
8. Built-in debugger (with 32 commands)
573
Z8000 In ...Circuit Emulator SM-E-8100 LH8DH340
• Block Diagram
Option
r:-----::;]
I Changeable I
: I
I I
I
Z8000 1--:-:---:---11
CPU 1
"""7-<3"7'~1
_J
Break
Register
Control ... ...
Circuit 2 2
'j3 ,·e Mem,ory
~
0
::;; by User's
Break
Counter 32 K Bytes
574
PROM Writer LH8DH403
LH8DH403 PROM Writer

• Description
This equipment operates under control of
SM-D-8000 II, FDOS. The control program is sup-
plied on the floppy disk. The equipment writes
programs that have been developed by using
SM-D-8000 II into EPROMs directly, thereby re-
ducing developing time.
• Features
1. Applicable EPROM 2732A, 2764, 27128, and
equivalents
2. Either mnemonic or spelled-out commands
acceptable
3. Data management in file from
4. LED indication during command execution
• Block Diagram
SM-D-8000 II PROM Writer Unit
1------- I---------------~~----I
I
I I " I
I Add~!sI
Address
I Bus I
Address Bus
Bus
Buffer
h====~ IC
Socket
II
Buffer II
'L- __ JI
1..:: __
--....,I
Data Data Bus I
PROM
Bus I
Console Buffer Data
Drive I
Bus
Signal I
I
1,--------, I
I I
I
I
Control
Bus
Control Bus PIO ,------L.L..--, I
Drive Circuit I
I Buffer
I~ _ _~ I I
Cable I I
IL _____ _ IL _____________________ I ~
Buffer Board
+21 V DC
Power
+sv Supply
AC 100 V
575
8M Series Emulator 8ME-20 LU4DH200
LU4DH200 SM Series Emulator SME;:;20

• Description
The LU4DH200 is an emulator designed to sup-
port the development of programs for the SM series
of 4-bit single-chip microcomputers. It consists
of a data input and control key board, LED for dis-
play data, PROM writer and interface enabling·
programs can also be dev~loped in ,RAM by using
the RS232Cto connect it to SM-D-8000 II which
supports a cross-assembler and other software to
facilitate program debugging.
• Features
1. PROM writer (2716, 2732) in standard
2. RS232C 1 port
Baud rate 150-19200B
(8 levels selective)
·3. Paper tape reader interface;Paper tape punch-
er interface in standard
4. Support all functions of SM series by altering
PROM for PLA
5. Function of the emulator
• Execute/halt program
• Display/change data
• One step operation
• Execute start point of CPU
• Repair address
576
SM Series Emulator SME-20 LU4DH200
The SME-20 can be connected through the RS
232C to the SM-D-8000 II to allow efficient prog· Emulator
ram debugging.
Host computer ¢==> (SME-20)
L......_ _ _- - I RS232C L!======::!J
It can also be connected to other support tools
which run under the CP1M operating system and URS232C
equipped with an RS-232C interface.
SM evaluation
board
r----------------------------,
,-----------------,
SM-D-8000II
SME-20
Working
RAM
Floppy Disk
(containing the editor,

cross assembler, etc.)
ROM (1 K)
RAM (64 K)
________________________ -1
RS232C
SIO
PTP/PTR
L ________________
~
Terminal Unit
(Sharp Writer, etc.)
SM Series
Evaluation
Board
.-~------SHARP----.-----
577
SM Series Evaluation Board LUXXXH2
LUXXXH2 SM Series Evaluation Board

• Description
There are designed for evaluating the SM series
of 4-bit 1-chip microcomputers. The boards are
functionally and electrically equivalent to the mask
ROM version.
Programs can be developed either at the EPROM
level, or when used with any of the SM series sup-
port tools (SM-D-80, SM-D-8000 IT ) programs
can be developed at the RAM level.
• Features
l. System debug with EPROM
2. Debug at RAM base in conjunction with sup-
port tool(SM- 0-80, SM- 0-8000 IT)
3. Function of the evaluation board
• Hold function
• One- step function
• Auto-stop function
• Display of the program counter
• Display of accumlator and carry F IF
• Display of RAM address, the register and
memory
• Display of instruction code
• PLA set function
---.-.......------SHARP-.-.--------
578
SM Series Evaluation Board LUXXXH2
• Block Diagram
-~
-11-.===;;;::;- I * Crystal Memory
asc Display
Circuit Circuit
Vc (-5V)
GND (OV)
Break
Address
Setting
Circuit
l!:
I
Programming ~ Instruction
(2716,2732 or Display
equivalent) Circuit
'---~~
Evaluation Card Control Board
• SM Series Evaluation Board

Control board
The evaluation board consists of two printed cir-
cuit boards: the control board and the evaluation
card (on which the evaluation chip and EPROM
socket installed).
Evaluation chip Evaluation card
(LUXXXH4)
-~-----'------SHARP-'---'-'---
579
Memories
NMOS 32768-Bit Mask Programmable Read Only. Memory LH2331 ILH2331 A
lH2331/LH2331A
NMOS 32768-Bit Mask Programmable Read Only Memory
The LH2331/LH23-31A are fully static mask
programmable ROMs organized as 4,096-word-
by-8-bit by using silicon~gate NMOS process tech-
nology. o
• Features
1. 4,096-word-by-8-bit organization
3. Fully static operation (no cloS;k required)
4. All inputs and outputs TTL compatible
5. Three-state outputs
6. Access time (MAX.)
LH2331 : 450ns, LH233iA : 350ns
7. Power-down function Top View
8. 24-pin dual-in-line package (pin compatible
with i 2732 type EPROM)
• Block Diagram
Data Output
~
Output Enable
Al\dress Input
32.768
Cell Matrix
---~'-------"--SHARP-~-----""--'
582
NMOS 32768-Bit Mask Programmable Read Only Memory LH2331 ILH2331 A

Pin voltage * VIN -.0.3-+7 ..0 V
Operating temperature Topr 0-+7.0 "C
Storage temperature T st " -55-+15.0 "C
*Application voltage on any input pin with respect to ground.
• DC Characteristics (Vcc=5V±l.o%, Ta=.o-+7.o"C)

Output low voltage VOL IOI.=2 ..omA .0.4 V
Output high voltage V OH IoH = 2.0.0 p.A 2.4 V
Input low voltage VII. .0.8 V
Input high voltage V IH 2..0 V
Input leakage current I ILl I D";:VIN";:V CC 1.0 p.A
Output leakage current I lLO I CE:;;;; 2V, D::£VouT::£V cc 1.0 f'A
Chip enabled power
IccI 11.0 rnA
supply current
Chip disabled power -
Icc2 CE:;;;;2V 5.0 rnA
supply current
• AC Characteristics (Vcc=5V±l.o%, Ta=D-+7.o"C)
LH2331 LH2331A
MIN. TYP. MAX. MIN. TYP. MAX.
Access time t ACC 45.0 35.0 ns
Chip enable setup time teE 45.0 35.0 ns
Output enable time toE 12.0 12.0 ns
Output hold time tOH .0 .0 ns
Chip turn-off time tDF .0 1.0.0 .0 1.0.0 ns
Test conditions o(AC characteristics

• Input voltage amplitude········································ .. · + 0.4 - + 2.8V
• Input rising/falling time ··········································10ns
• Input threshold level ·······························,··············1.5V
• Output threshold level .. ··········································· 0.8V and 2.0V
• Output load condition .. ············································ 1TTL + 100pF
• Capacitance (f=IMHz, Ta=25"C)

Input capacitance CIN VIN=.oV 15 pF
Output capacitance COUT VouT=DV 15 pF
'-'-~--"--'--SHARP ----------~--------
583
. NMOS 327.68-Bit Mask Programmable.Read Only Memory LH2331 ILH2331 A
• Timing Diagram
CE
(High impedance)
584
NMOS 3276e-Bit Mask Programmable Read Only Memory LH2331/LH2331A
• Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)
Access time vs. supply voltage Access time vs. ambient temperature
].
1.4,..---,----,----,-----,
Ta=700e .,..: 1.4
.. Vcc=4.5 \r
.. .
.,..
.~ 1 . 2 1 - - - - + - - - - + - - - - f - - - - I .:: 1.2
1;; ~
;;
P:::
~r--.
].,
P:::
~
V
u 1.0 I-----+-==~_+---I_-__I u 1.0
~
u
.,
.j
., ~
:3 0.8 '5 0.8
., to
III
., to
to
<:"
" "
<:"
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75
Supply voltage Vcc (V) Ambient temperature Ta (Oe)
Average supply current vs. supply voltage Average supply current vs. ambient
temperature
-- ---
<:
-5 80 ~ 80
<:
N
U
f.----
I-- ICCI -5 r--- I----
.::i
G 60
....u
N
U
~ 60 r---- IcC!
.. ....9
~
e:::
..::-
~
~
"8-
40
20
Icc2
..
j
~ 40
e'"
III
.,'"
20
-- r---,-
- Icc2
~
~ 0
.,8-"
<:
.. 4.0 4.5 5.0 5.5 6.0
.,~ 0 25 50 75 100
Supply voltage Vcc (V) > Ambient temperature Ta (T)
<:
CE to output delay vs. ambient temperature

CE to output delay vs. supply voltage
.,..: 1.4
.,..: 1.4
...,. Ta=700e os
.,
>
Vcc=4.5 V
.:: .~
os
1;;
;; 1.2 ;; 1.2
P::: P:::
"'u
V
'"
u
.j
1.0
.j
1.0 ./
...
..:., ~
j V
""
i 0.8 ~ 0.8
S
s=
0
Itl 0.6 I ~u 0.6

4.0 4.5 5.0 5:5 6.0 o 25 50 75 100
Supply voltage Vcc (V) Ambient temperature Ta ee)
585
NMOS 32768-Bit Mask Programmable Read Only Memory LH2332/LH2332A
LH2332/LH2332A
NMOS 32768-Bit Mask Programmable Read Only Memory
The LH23321LH2332A are fully static mask
programmable. ROMs organized as 4,096 -word-
by-S-bit by using silicon-gate NMOS process tech-
nology. o
• Features
1. 4,096-word-by-S-bit organization
3. Fully static operation (no clock required)
LH2332 : 450ns, LH2332A : 350ns
Top View
7. Programmable chip selects (CS1/CS lo CSz/CS z)
S. 24-pin dual-in-line package (JEDEC standard
pin configuration)
• Block Diagram
Data Output
~
Address Input
32.768
Cell Matrix
----------SHARP--------------
586
NMOS 32768-Bit Mask Programmable Read Only MemOry LH2332/LH2332A

Supply voltage * Vee -0.3-+7.0 V
Operating temperature Top, 0-+70 ·C
Storage temperature T stg -55-+150 ·C
• Recommended Operating Conditions (Ta=0-+70·C)

Supply voltage Vee 4.75 5 5.25 V
V IL 0.8 V
Input voltage
VIH 2.0 V
• DC Characteristics (Vee=5V±5%, Ta=0-+70·C)

Input low voltage VIL 0.8 V
Input high voltage VIH 2.0 V
Output high voltage VOH IoH = 200 p.A 2.4 V
Input leakage current I ILl I O~VIN~Vce 10 p.A
Output leakage current I ILO I CS~2V, O~VouT~Vee 10 p.A
• AC Characteristics (Vee=5V±5%, Ta=0-+70·C)
-
Access time tAce 450 ns
Output hold time tClH 0 ns
Chip enable setup time teE 350 ns
Chi p turn -off time tDF 0 150 ns
Test conditions of AC characteristics

• Input voltage amplitude··········································· + 0.4 - + 2.8V
• Input rising/failing time···········································l0ns
• Input threshold level·· ......................................... ····1.5V
• Output threshold level·································· ........... 0.8V and 2.0V
• Output load condition·············································· 1TTL + 100pF
• Capacitance (f=IMHz, Ta=25·C)

- Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIN VIN=OV 15 pF
Output capacitance COUT VOUT=OV 15 pF
587
~NlOS 32768-Bit Mask Programmable Read Only Memory .LH.2332/LH2332A
• Timing Diagram·
cs
Valid data
(High impedance)
588
NMOS 32768-Bit Mask Programmable Read Only Memory LH2332/LH2332A
• Electrical Characteristics Curves (Vcc=5V, Ta=25t unless otherwise specified)
1.4r---..,.....--...,----,---__, 1.4
Ta=70'C Vee=4.75 V
.a.
>
.~ 1 . 2 1 - - - + - - - - + - - - + - - - \
//
~
10
Q;
V
Il:::
tl 1.01-.=......+---+--~==:::::J
:;
.§
V
:; 0 . 8 1 - - - + - - - - + - - - + - - - \ .~"
(Il
O.s
:l (Il
~
..:"" ..:"
0.6"::-_~~-~-!-::----=-=--~ 0.6
4.0 4.5 5.0 5.5 6.0 0 25 50. 75 100
Supply voltage Vee (V) Ambient temperature Ta (OC)
Average supply current vs. Average supply current vs.

supply voltage ambient temperature
SOr---~--~--_,_--__, so
-- ..:
~
I--- I---
60~--+_--~--_+--~ u 60 r---
~ .....u
.,...
0;
. 40
"
b"
'"
§'
(Il
...~.,
201---+---~--_+--_;
.
~ 20
"
..:>
..:>
O~-~~-~~-~_!_::_-~
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ('C)
Input voltage vs. supply voltage Input voltage vs. ambient temperature
2.0 2.0r---.,...---..,.....--...,-----,
2:: 2::
,., 1.7 1.7
:> ~
:x: :x:
:> :>
."..
.::0
1.4 VIH(MIN.)
VIL(MAX.)
i
.g:,
1.4 ~VlH(MIN.J
VILCMAX.)
=
>.
.=;'"
1.1 -..
>
....."'"
1.1
O.S O.S !-_~:!=---=-=----=---~

4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
589
NMOS 65536-Bit Mask Programmable Read'Oniy Memory LH2362B
NMOS 6SS36-Bit Mask ProQrammable Read

LH2362B Only Memory

The LH2362B is a fully static mask programm-
able ROM organized as 8,192-word-by-8-bit by
using silicon-gate NMOS process technology.
o
• Features
2. Single +5V power supply
6. Access time (MAX.) : 250ns
7. 24-pin dual-in-line package UEDEC standard
pin configuration)
Top View
• Block Diagram
Data Output
,A
Control
Signal
Generator
1!32X8
Column Address Decoder
Address
Input
.,.,
....,
65,536(256 X 32 X 8)
." Cell Matrix
."
<:
~
o
!X:.
590
NMOS 65536-Bit Mask Programmable Read Only Memory LH2362B

Supply voltage * Vcc -0.3-+7.0 V
Operating temperature Toor 0-+70 'C
Storage temperature T st• -55-+150 'C
* The maximum applicable voltage,on any pin with respect to GND.

Supply voltage Vcc 4.75 5 5.25 V
V1L 0.8 V
Input voltage
VIH 2.0 V
• DC Characteristics (Vcc=5V±5%, Ta=0-+70'C)

Input low voltage V1L 0.8 V
0fltput high voltage VOH IOH=200pA 2.4 ,V
Input leakage current I ILl I VIN=OV-Vcc 10 pA
Output leakage current I ILO I CS~2V, VOUT=OV-Vcc 10 p.A
• AC Characteristics (Vcc=5V±5%, Ta=0-+70"C)

Access time t ACC 250 ns
Chip enable setup time tCE 100 ns
Chip turn-off time tDF 100 ns
Output hold time tOH 0 ns

• Input voltage amplitude ........................................... + 0.4 - + 2.BV
• Input threshold level································· ............. 1.5V
• Output threshold level· .. ··························· .. ············· O.BV and 2.0V
• Output load condition ·············································1 TTL+ 100pF
• Capacitance (f=lMHz, Ta=25'C)

Input capacitance CIN V1N=OV 16 pF
591
• Timing Diagram
Ao-A12
~--tACC--~
Valid data
(High impedance)
• Chip Select
L DouT (Data output)

H High impedance
592
• Electrical Characteristics Curves (Ta = 25 "C unless otherwise specified)
1.4 1.4
0;-
.
.,..
oS Ta=70·C
0;-
.
.,..
oS Vcc=4.5V
.::: 1.2 .::: 1.2

.;., .;., V
V
Il::
]
u
u
;;
.,
1.0
0.8
.-- ~ --- f-- Il::
]
;;
u
u
.,
1.0
0.8
",-
~
.,..,''"" .,..,'"'"
.., ..,
...:: ...::
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ("C)
Supply current during operation vs. Supply current during operation vs.
< 100 .----,.-----.-----,------, ...:: 100
-5 -5
Vee=5.0V
90~--+---1----~----~
.~
...
rv
~
~ 80~--1------+----~------;
- "'-f'....
.S
.g "-
-il
~
ii
70r-----4------+----~----~
-ii
il
~ 70 ~
f'.
1
~ 60L---~--~--~~-~ 1
~ 60 0
4.0 4.5 5.0 5.5 6.0 25 50 75 100
Chip enable time vs. supply voltage Chip enable time vs. ambient temperature
1.4 1.4
0;-
0;-
...,.
oS Ta=70·C ~
.,..
Vee=4.5V
L
1.2 .~ 1.2
.
.~ os
0;
Il::
0;
Il:: /
~ 1.0
./
~ 1.0 /
., ., /""
oE .~
., 0.8 ~ 0.8
:g
il il
.9- .9-
""
U 0.6 ""
U
0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supplyvoltage Vee (V) Ambient temperature Ta ("C)
- - - - - - - - - . . - S H A R P - - - - - - ............ - -
593
NMOS 65536-Bit Mask Programmable Read Only Memory 'LH2367
. NMOS 65536-Bit Mask Prograinmable Read Only

LH2367 Memory

The LH2367 is a fully static mask programmable
ROM organized as 8,192-word-by-8-bit by using
silicon-gate NMOS process technology.
o
• Features
5. Three-state output
7. Programmable chip select (CS h CS 2)
8. 28-pin dua:I-in-line package
Top View
• Block Diagram
.
Data Output
Address Input
65,536(256X32X8)
Cell Matrix
594
NMOS 65536-Bit Mask Programmable Read Only Memory LH2367

Applied voltage * V -0.3-+7.0 V
Operating temperature Toor 0-+70 t
Storage temperature T stu -55-+150 t
V1L -0.5 0.8 V
Input voltage
VlH 2.0 Vcc V

In put high voltage VlH 2.0 Vcc V
Output low voltage VOL IoL =2mA 0.4 V
Output high voltage VOH IOH = 200,uA 2.4 V
Input leakage current I ILl I VIN=OV-Vcc 0.01 10 ,uA
VOUT=OV-Vcc
Output leakage current I ILO I (In non· selection mode)
0.01 10 ,uA
Chip enabled power supply

ICCI 50 80 rnA
current
Chip disabled power supply
IcC2 Note 20 40 rnA
current
Note: CE;;;:; 2.0V (Non·active) or CSt or CS. is non-active (CE type chip select)

Access time tAcc 250 ns
Chip enable time (from CE) tCE! 250 ns
Chip enable time (from CS) tCE2 250 ns
Output enable time (from OE) tOE! 100 ns
Output enable time (from CS) tOE2 100 ns
Output turn-off time (from CE) tOFl 100 ns
Output turn-off time (from CS) tOF2 100 ns
Output turn-off time (from OE) t OF3 100 ns
Output hold time toH 0 ns

• Input voltage amplitude ................................. +OAV and +2.8V
• Input rising/falling time ·······················;··················10ns
• Input threshold level··········· .................................. ·1.5V
• Output threshold level··········· ................................. O.8V and 2.0V
• Output load condition ............................................. lTTL + 100pF
595
NMOS.65536-Bit Mask Programmable Read Only Memory LH2367
• Timing Diagram
(1) Type1 (CS1/CS2 is CE function type)
Ao-AI2
tCEI
CE
cs· 1
tCE2
OE
(High impedance)
* 1 CS is the logical product of CS 1 and CS 2
(2) Type2 (CS1/CS2 is OE function type)
t----tCE----'"'i
cs· 1
Valid data
(High impedance)
* 1 CS is the logical product of CS 1 and CS 2
596
NMOS .65536-Bit Mask Programmable Read Only Memory LH2367
• Chip Select
OE cr CS*l Do-D7 Mode
X H X High impedance Non-select, power down
X X L High impedance *2
H X X High impedance Output non-select
L L H DouT Read
*1 CS is high only when the CSl pin and the CSz pin are active at the same time and is low at
all other times. (Non·connection pins are continuously active.)
*2 Chip select input CSl and CSz can be programmed into 2 types depending on the ROM pat·
tern (see timing chart).
Type Function of CSl pin and CSz pin

(1) CE function type Functions at same time as CE pin; when CS = low, non-select power-down mode
(2) OE function type Functions at same time as OE pin; when CS = low, output non· select mode

1.4 1.4
".a. >
Ta=70°C
".a
co
>
1.2
Vcc=4.5V
./"
1.2 '"
.!=
....'"
.!= ....
V
--
..!!
~ '"
1.0
I'--- "*
~
'-' 1.0 /
j
'-'
'-' j
'-'
V
.~'" 0.8 .~'" 0.8
III
III III
III
"..,'" <
"'"
OJ
< 0.6 0.6

4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
120 < 120
~
'-'
::i 110 ~ ~
'-'
110 ~
~
.§
10...
~ 100
/ .§
10...
~ 100 ~
/ ""
OIl
.9
.g
i... 90
~
8
j
00
80
4.0 4.5 5.0 5.5 6.0 25 50 75 100
Supply. voltage Vee (V) Ambient temperature Ta (OC)
597
Chip enable time vs. supply voltage Chip enable time vs. ambient temperature
.,..= 1.4 .,..= 1.4
. Ta=70·C .
.,:- Vee=4.5V
.,:-
.i::
'OJ
1.2
.i::
E., 1.2 /
.Ql
e '/
-
p:;
.;
... ~
~ 1.0
-
u 1.0
.,
:3 V
.s 0.8 ~.,c 0.8
1
.S<
.... .....S<
U
U
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta (·C)
598
CMOS 65536-Bit Mask Programmable Read Only Memory LH5366A
CMOS 65536-Bit Mask Programmable Read

LH5366A Only Memory

The LH5336A is a mask programmable ROM u
organized as 8,192-word-by-8-bit by using CMOS z
process technology.
• Features
4. Edge enabled operation (CEl, CE,)
6. Access time (MAX.) : 2.5 ps
7. Programmable chip select
8. Selectable byte or digit output
9. 44-piJ;l quad-flat package Top View
• Block Diagram
65,536 (256X32X8)
Address Input Cell Matrix
~----------~v~-----------J
Data Output
599

Operating temperature T oDc 0-+60 'c
Storage temperature Ts'o -55-+150 ·C

Parameter Ratings Unit
Supply voltage 4.5-5.5 V
• DC Characteristics (V cc =5V±10%. Ta=0-+60·C)

Input high voltage VIH -0.3 0.8 V
Input low voltage V1L Vcc -1.0 Vcc V
Output high voltage VOH IOH = 100 pA 2.4 V
Input leakage current I ILl I VIN=OV-Vcc 1.0 pA
Output leakage current I lLO I In non·selection mode 1.0 pA
Chip enabled power
IcC! 5 rnA 1
supply current
Chip disabled power
Icc2 C3 • VIN=0.2V or Vcc-0.2V 5 pA
supply current
Note 1: Average current at cycle time of 4,u s with output open and input set to OV or V cc.
Address setup time tAs 1 ps
Chip enable setup time tCE 2.5 ps
Chip enable precharge time tD 1.5 f.1s
Chip turn·off time (CE) tDFI 1.5 f.1s
Chip turn·off time (CS) tDF2 1.5 f.1s
Cycle time [CYC 4.0 f.1s
Test conditions of AC Characteristics

• Input voltage amplitude·· ......................................... + 0.8V --- Vcc-1.0V
• Input rising/falling time· ......................................... 20ns
• Input threshold level··· ......................................... ··1.5V
• Output threshold level············································ 0.4 V and 2.4 V
• Output load condition ·········· .... ·······························10pF
--~--.----SHARP-.-.------
600
• Timing Diagram
CE
CS
(High impedance)
1.4 1.4
Ta=60'C Vee =4.5 V
".
..E!
>
Q) 1.2
".
..E!
>
Q)
1.2
.~
.~
-:0
~ -:0 /'
Ql
p::
u 1.0 ~
Ql
p::
1.0 V
V
u
~
u u
j j
Q)
.~ 0.8 ~ Q)
.~ 0.8
rn rn
rn
Q) Ul
Q)
..::"" "
0.6 ..::" 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Average supply current vs. supply Average supply current vs. ambient
~
voltage temperature
2.5 2.5
..:: ..::
-.S -.S I
u 2.0 tl 2.01-----+---+---+----1
.;:;
V ......
/
~
..=
cQ)
~
1.5 ~ 1.5 ~==:j::==t:::::::i:~=-~
"
bCo V
~
=Ul
Co
.....'on"
1.0 1 1.01-----+---+----+----;
~
~
..::'"
> >
0.5 ..:: 0.5 '--_ _..L-_ _- ' -_ _~---'-
4.0 5.0 4.5 5.5 6.0 o 25 50 75 100
Supplyvoltage Vee (V) Ambient temperature Ta ('C)
~'-'-------SHARP'-'-"-----~
601
CMOS 65536-Bit Mask Programmable Read Only Memory LH5366S

LH5366S Only Memory
The LH5366S is a mask programmable .ROM
organized as 8,192-word-by-8-bit by using CMOS
process technology.
• Features
4. Edge enabled operation (CEl> CE 2 )
5. Three -state outputs
6. Access time (MAX.) : 6 ps
8. Selectable byte or digit output
9. 44-pin quad-flat package Top View
• Block Diagram
65,536 (256X32X8)
Cell Matrix
Address Input
~----------~vr----------~I.
Data Output
'--'-~--'-'--SHARP -.--.-.~-------
602

Operating temperature T oDr 0-+60 "C
* The maximum appl\cable voltage on any pin with respect to GND.
• DC Characteristics (V cc=3.0V, Ta=O- +60"C)

Input high voltage VIH Vcc- 0.6 V
Output high voltage VOH IOH =50 p.A Vcc- 0.5 V
Output low voltage VOL IOL=50p.A 0.5 V
Input leakage current I ILl I VIN=OV-Vcc 1.0 p.A
Output leakage current I Iw I In non· selection mode 1.0 p.A
Chip enabled power
IcCl 1.0 rnA 1
supply current
Chip disabled power
Icc2 Cs, VIN=0.2V or Vcc-0.2V 5.0 p.A
supply current
Note 1: Average current at cycle time of 12,us with output open and input set to OV or Vce.
• AC Characteristics (Vcc =2.5-3.5V, Ta=0-+60"C)

Address setup time tAS 1 p.s
Chip enable setup time teE 6 p.s
Chip enable precharge time to 6 p.s
Chip turn-off time (CE) tDFl 1.5 p.s
Chip turn-off time (CS) tDF2 1.5 p.s
Cycle time tCYC 12 p.s

• Input voltage amplitude···········································+O.5V-Vcc-O.5V
• Input- rising/falling time········· ................................. 20ns
• Input threshold level .. ············· ....................•........... O.3V
• Output threshold level .. ···· ....................................... Vcc- O.3V
• Output load condition .. ············································ 10pF
603
• Timing Diagram
Ao-A12
CE
CS
(High impedance)

1.4 1.4
Ta=60°C Vee=2.5 V
".a.,..
co
~ "...,
.aco
.i: 1.2 .i:
1.2
~.,
p::
u 1.0
\ ~
.~
u
1.0
~
~
V
\
u u
.;; , .;;
., .,
] 0.8 ] 0.8
.,
Ul '\
Ul
.,Ul
Ul
" "
<" 0.6 <" 0.6
2.0 2.5 3.0 3.5 4.0 o 25 50 75 100

0.8 0.8.-----.-----;----,.--.---,
< <
-5 -5
u
0.6 u 0.61----+---+---+-----1
u
.....u
...,"...
......
~
t: 0.4 ...- ...
.,"
.
0.4
B ~
-----
.l:>
1 ...- ~
~.,
0.2
..,.,...
Ul
co
0.2
.. <
.
< 0
2.0 2.5 3.0 3.5 4.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta eC)
604
CMOS 65536-Bit Mask Programmable Read Only Memory LH5367
CMOS SSS3S-Bit Mask Programmable Read

LH5367 Only Memory
The LH5367 is a mask programmable ROM
organized as 8,192-word-by-8-bit by using sili· 00 cE
u u
con-gate CMOS process technology.
• Features
4. Edge enabled operation (CEl. CE 2 )
Top View
• Block Diagram
65,536 (256X32X8)
Address Input Cell Matrix
y
Data Output
---~-------SHA.RP------"""""-
605
CMOS 65536-8it Mask Programmable Read Only Memory LH5367

Storage temperature TSIJl -55-+150 t
Parameter Symbol Conditions MIN. . TYP. MAX. Unit Note

Input high voltage VIH Vcc -1.0 Vcc V
Output high voltage VOH IOH=100pA 2.4 V
Output leakage current I lLO I In non-selection mode 1.0 pA
Chip enabled power
Icc! 14 mA 1
supply current
Chip disabled power
Icc2 Cs , VIN=0.2V or Vcc-0.2V 5.0 pA
supply current
Note 1: Average current at cycle time of 750ns with output open and input set to OV or Vcc_
Address setup time tAs 50 ns
Chip enable setup time teE 450 ns
Chip enable precharge time tp 300 ns
Chip turn-off time (CE) tDFl ·300 ns
Chip turn-off time (CS) tDF2 300 ns
Cycle time teyC 750 ns
• Input voltage amplitude .......................................... +0.8V-Vcc -1.0V
• Input rising/falling time · ............................ · ............ 10ns
• Input threshold level" ............................................ 1.5V
• Output threshold level· .......................... · .... ·: .......... ·OAV and 2AV
• Output load condition ........ · ...... · .............. · .............. ·10pF
• Timing Diagram
Ao-A12
CE
CS
(High impedance)
606
., Ta=60'e ].
1.4
Vee =4.75 V
.
~ 1.2
.,
.
.:: .~
1;j 1.2
~~ Ol
~
~
~
!
u
u
.,
oS
1.0 i".......
........... , !
tl 1.0
.,
:atil 0.8
~
~
.,"'"' 0.8
.,
til
..:"" ..:""
0.6
4.0 5.0 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ee)

6.0 5.5.-----r----r---~-----,
/ ..:
5
V u
...
5.01----+---+---+----1
-. ./ u
&l
e
5.0
./
/ -&l
t: 4.51----+---+---+----1
.g: / e
~ 4.0 / b
,V ~ 4.01---+---+---+-----1
~
.,.. .~
..: ~
3.0 ..: 3.S'-_ _..i-_ _..I.-_ _-:!::-_ _:-!
4.0 5.0 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ('e)
2.0 2.0,.---'T"""--....- - - , - - - - - ,
2:-
2:- 1.7
d 1.7
d :>
:> 23
23 :>
:> 1.4 ., 1.4
VIH(MIN.)
.
OIl :;::::--V1H(MIN.)
1.
o
VIL<MAX.) .:::
..
0 V1L(MAX.)
=1.1 i
oS
1.1
!
0.8 0.8~ _ _1.-_ _L -_ _J....-_----I.
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
~'-----------SHARP -------------.-..-.
607
CMOS 98304-Bit Mask Programmable Read Only Memory LH5396/LH5396A
LH'5396/LH5396A
CMOS 98304-Bit Mask Programmable Read Only Memory
The LH5396/LH5396A are mask programmable
ROMs organized as 12,288-word-by-8-bit by us-
ing silicon-gate CMOS process technology.
• Features
1. 12,288-word- by-8- bit organization
2. Single +4.5V power supply
4. Edge enabled operation (CE I , CE 2 )
LH5396 : 6.0 ps, LH5396A : 3.0 ps
8. Byte/digit outpilt select
• Block Diagram
Data Output
,.----"---,
12 10 9 8 7 4 3
GND
30 L/U
29 BID
L/U.B/D
Control
Circuit
Address Input
--~'-'------SHARP -----"-------.-
608

Operating temperature T oDr 0-+60 ·C
Storage temperature T s '" -55-+150 t
Supply voltage Vee 4.0 4.5 5.0 V
V 1L -0.3 0.8 V
Input voltage
V IH Vee -1.0 Vcc V
Operating temperature T oDr 0 60 t
• DC Characteristics (V ce =4.5V±10%, Ta=0-+60t)
LH5396 LH5396A
Input low voltage V1L -0.3 0.8 -0.3 0.8 V
In put high voltage VIH Vee -1.0 Vee Vee -1.0 Vee V
Output low voltage VOL IOL =1.6mA 0.4 0.4 V
Output high voltage VOH IOH = 100pA 2.4 2.4 V
VIN=OVor
Input leakage current I ILl I VIN=Vec
1.0 1.0 pA
In non·selec-
tion mode:
Output leakage current I Iw I VOUT=OVor
1.0 1.0 pA
VouT=Vee
Chip enabled power
Iecl 3.0 7.0 5.0 12.0 mA 1
supply current
Chip disabled power
Iec2 5.0 5.0 pA 2
supply current
Note 1: Average current at cycle time of 4.5 fL s (LH5396 is 7.5 fL s) with output open and input set to OV or Vee.
Note 2: In chip selection mode: VIN=O.2V or VIN=Vce-O.2V
• AC Characteristics (V ee =4.5V±10%, Ta=0-+60t)
LH5396 LH5396A
Address setup time t AS 1.0 1.0 ps
Chip enable setup time teE 6.0 3.0 f-LS
Chip enable precharge time tp 1.5 1.5 f-Ls
Chip turn-off time (CE) tDFl 1.5 1.0 f-LS
Chip turn-off time (CS) tDF2 1.5 1.0 f-Ls
Cycle time teYe 10,000 10,000 f-LS

• Input voltage amplitude ........................................... +0.8V -Vcc-1.0V
• Input rising/falling time·········································· 20ns
• Input threshold level···············································1.5V
• Output threshold level .. ···········································OAV and 2AV
• Output load condition .. ···················:························10pF
609
• Capacitance (f=1MHz, Ta=25"C)

• Timing Diagram
)(
--tAS tcye
tl' J
'\
CE )
-tCE--
fi:
tDF2
CS lL'
~
f--tDFI-
;'
Valid data
(High impedance) '\.'\.'\.'"
• Chip Select
CSO/CSO -CS 3 /CS 3 CE 1 CE 2 0 0 -0 7 Mode
L H °OUT Read
L L
In selection mode
H L
High impedance Non-selection
H H
In non-selection mode X X
• Byte/Digit Output Select

Oata output pins
LlU BIO
07 06 Os 04 03 O2 01 00
L L 07 06 Os 04 03 O2 01 00
L H 07 06 Os 04 03 O2 01 00
H L 07 06 Os 04 03 O2 01 00
H H 07 06 Os 04 07 06 Os. 04
610
• Electrical Characteristics Curves (Ta=25°C unless otherwise specified)
1.4 1.4
Ta=60"e Vcc=4.0V
v.: v.:
. .
>
Q)
1.2 '\. >
1.2
.,..
.~
Q)
.,o£j. V
~
u
u
1.0 ~ ~
u 1.0 /
~ /
j u
j
Q)
of
''""
0.8 --- oE'" 0.8
''""
Q)
<:"
" "'"
<:"
0.6 0.6
3.5 4.0 4.5 5.0 5.5 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ("e)
4 4
Vcc=5.0 V
tl'= 1.5,us
tl'= 1.5,us
3 3
LH5396A(tcYc ~4.0 11-~

~J\. o~
- ~I
2 2
. . ",,7.5I1- S )
LH5396(tc\C _ _
-I...i
...
LJ396(tcY cJ7 .5 ,uS ) -
=
"
o
3.5 4.0 4.5 5.0 5.5
j
U) o 25 50 75 100
Output high voltage vs. supply voltage Output low voltage vs. supply voltage
6:0 0.4
= -lOO,uA I oL =1.6mA
...--...--
IOH
C C
:z: 4.5 .-1
0.3
o
:>
'~"
.---V-- :>
0
.,
.±::
~
"§,
:.a
"[ 1.5
o-=
3.0
~'"
"0 0.2
>
-"=
..s
'"
0-=
0.1
-- :---
----
o o
3.5 4.0 4.5 5.0 5.5 3.5 4.0 4.5 5.0 5.5
Supply voltage Vee (V) Supply voltage Vee (V)
----------SHARP--------
611
CMOS 98304-Bit Mas~ Programmable Read Only Memory LH5396S
LH5396S CMOS 98304-Bit Mask Programmable Read

Only Memory
The LH5396S is a ma~k programmable ROM
organized as 12,288-word-by-8-bit by using sili-
• Features
1. 12,288-word-by-8- bit organization
4. Edge enabled operation (CEl. CEz)
5. Three-state ,outputs
8. Byte/digit output select
• Block Diagram
Control
Circuit
Address Input
.-----.-.--SHARP--------,,---
612
CMOS 98304-Bit Mask Programmable Read Only Memory lH5396S

Operating temperature Top, 0-+60 "C
\

VIL -0.3 0.5
Input voltage V
VIH Vee -0.5 Vee
Operating temperature Top, 0 60 "C
• DC Characteristics (V ee =+2.6-+3.4V, Ta=0-+60"C)

Input high voltage VIH Vee- 0.5 Vee V
Output low voltage VOL IOL=300pA 0.3 V
Output high voltage VOH IOH=30pA Vee- 0.3 V
Input leakage current I ILl I VIN=OV or Vee 1.0 pA
In non· selection mode:
Output leakage current I ILO I VOUT=OV or Vee
1.0 pA
Chip enabled power

IcC! 0.8 2.0 mA 1
supply current
Chip disabled power
Iee2 2.0 pA 2
supply current
Note 1: Average current at cycle time of 18 p. s with output open and input set to OV or Vee.
Note 2: In chip selection mode: VIN=O.2V or VIN=Vcc-O.2V
(Vee=+2.6V-+3.4V,
, Ta=0-+60"C)

Address setup time t AS 2.0 p.s
Chip enable setup time teE 15 p.s
Chip enable precharge time tp 3.0 p.s
Chip turn·off time (CE) tDFl 3.0 p.s
Chip turn·off time (CS) tDF2 3.0 p.s
Cycle time teYe 10,000 p.s

• Input voltage amplitude .......................................... +0.5V-V cc -0.5V
• Input rising/falling time ·········································20ns
• Input threshold level········································ .. · .. Vcc /2
• Output threshold level··········································· 0.3V and Vcc-0.3V
• Output load condition·· ............................................ Non loading
613
• Capacitance (f=IMHz, Ta=25t)

• Timing Diagram
)K
f-<-tAS tcvc
tp I
CE ~
J
I---tCE- tDF2
CS ,I ~
f-;;--t D F l -
///h Valid data

(High impedance) ",~
• Chip Select
CS O/CSO-CS 3 /CS 3 CE I CE 2 Do-D7 Mode
L H DOUT Read
In selection mode L L
H L
H H

Data output pins
LlU BID
D7 D6 D5 D4 D3 D2 Dl Do
L L D7 D6 D5 D4 D3 D2 DI Do
L H D7 Ds D5 D4 D3 D2 DI Do
H L D7 D6 D5 D4 D3 D2 DI Do
H H D7 D6 D5 D4 D7 D6 D5 D4
614
NMOS 131072-Bit Mask Programmable Read

LH23126 Only Memory

The LH23126 is a fully static mask programm-
using NMOS process technology. o 27 CSI/CSI/NC
Al3
As
A9
All
• Features OE/OE
1. 16,384-word- by-8-bit organization
2. Single + 5V power supply CSo/CSo
7. Programmab.1e chip select
8. Programmable output enable
9. 28- pin dual-in-line package Top View
• Block Diagram
Data Output
J.
-e
C ~ Q)~
o ._
C; ~-.
0
Output Buffers
Utllc.:l
.,.''""
"0
"0
..: Column Address Decoder
~
c '"
E ..
..::t::
o
Uo:l
=
Address Input
.,''"" '.,'""
'"
"0 '" .,
:g" 131,072(256X64X 8)
:;:
~ <0
u),.o
..: "0 Cell Matrix
~~ ~ ~
o
O::o:l
= 0
...... 0::0
615
NMO.S 131072-Bit Mask Programmable Read Only Memory LH~.3126
• Ab~olute Maximum t:latings

Storage temperature TsUr -55-+150 t
* The maximum applicable vol,tage on any pin with respect to GND.

V1L O.S V
Input voltage
V lH 2.2 V
• DC Characteristics (Vcc=5V±1O%, Ta=0-+70t)

Input low voltage V1L -0.3 O.S V
Output high voltage VOH IoH =-400 f'A 2.4 V
Input leakage current I ILl I VIN=OV-Vcc 10 pA
Output leakage current I ILO I VOUT=O-VCC during standby 10 pA
Current IDuring operation Icc I SO rnA
consumption I During standby Icc2 CSsO.SV, CS~2.2V 40 rnA

Read cycle time t RC 250 ns
Chip enable time tCE 250 ns
Output enable time tOE 100 ns
Chip select time tcs 10 ns
Output select time tos 10 ns
Output turn·off time (from CS) tDFl 70 ns
Output turn·off time (from OE) tDF2 70 ns
Output hold time toiI 10 ns
Conditions for measurement of AC characteristics
• Input voltage amplitude ................................... +OA-+2AV
• Input rising/falling time ................................... 20ns
• Input decision level ·········································1.5V
• Output dicision level················,······················· O.BV and 2.0V
• Output load condition··········· <........................... 1TTL + 100pF
---~~~-~--SHARP---------------.-
616
NMOS 131 072-Bit Mask Programmable Read Only Memory LH23126
• Timing Diagram
tRC
Ao-A!3
{ tACC
tCE
~I
CS*!
tcs
OE*2
Do-D7
(High impedance)
*1 CS is the reverse polarity of CS

CS/CS is the logical product of CS/CSo and CS/CS/NC
*2 OE is the reverse polarity of OE
• Chip Select
CS/CS" OE/OE 00-07 Mode
H/L DouT Operating
H/L
LlH Operating
High impedance
LlH Standby
----.--~---SHARP--.-.-.--.--
617
CMOS 131072-Bit Mask Programmable 'Rea~ Only Memory. LH53127
CMOS l3l072-Bit Mask Programmable Read

LH53127 Only Memory
• Description
• Pin Connections
organized as 16,384-word-by-8-bit by using CS!/CSI I Vee

poly-crystal silicon-gate CMOS process technology. 0 CSo/CSo
A; AI3
As As
As A.
A. All
• Features A3 )E
1. 16,384-word-by-8-bit organization A2
Al CE
3. Low power consumption.
Ao D7
4. Edge enabled operation
5. All inputs and outputs TTL compatible D6
. 6. Three-state outputs DI
7. Access time (MAX.) : 250ns D.
8. Programmable .chip select GND
9. 28-pin dual-in-fine package Top View
• Block Diagram
Data Output
"
Control
Signal
Generator
1!32XB
Col'1mn Address Decoder
Address
Input
.,
.,.,... 65,536(256X32XB)
:g Cell Matrix
..:
,.
Q
e<::
-----------------SHARP .------.-.~----
618
CMOS 131 072-Bit Mask Programmable Read Only Memory LH53127

Input voltage * VIN -0.3-V ee +0.3 V
Output voltage * VOUT -0.3-Vee +0.3 V

V1L 0.8
Input voltage V
VIH 2.2
• DC Characteristics (Vee=5V±10%, Ta=0-+70'C)

Output high voltage VOH IoH =-1.0mA 2.4 V
Input leakage current I ILl I VJN=OV-Vee 1.0 pA
Output leakage current I lLO I 1.0 pA 1
IcC! 8 mA 2
Current consumption
Iee2 1 mA 3
Current consumption -
ISB CE=Vee, V1N=OV or Vee 30 pA
during standby
Notel: During high impedance output, CE=2.2V or OE=2.2V, VOUT=OV-Vee
Note 2: During operation, input amplitude is OV or Vee, teYe=350 ns and output pin is open.
Note 3: During chip non-select, input amplitude is OV or Vee, teye=350 ns, and output pin is open.
• AC Characteristics (Vee =5V±10%, Ta=0-+70'C)

Cycle time teye 350 ns
Access time from CE teE 250 ns
Access time from CS/CS tes 250 ns
Access time from OE tOE 100 ns
Address setup time (from CE) t ASE 0 ns
Address setup time (from CS) tASS 0 ns
CE precharge time t pE 100 ns
CS/CS precharge time t ps 100 ns
Data off delay time from CE toFl 0 100 ns
Data off delay time from CS/CS toF2 0 100 ns
Data off delay time from OE toF3 0 100 ns
619
.................................................,......................
CMOS 131072-Bit Mask Programmable Read Only'Memory ,
~....,---..,
LH53121

• Input voltage frequency··················,············:···· OAV -2AV
• Input rise/falI' time .......................................... IOns
• Input decision level ............ · ............................ 1.5V
• Output decisipn level ............................... ; ....... O.8V and 2.0V
• Output load condition ............ · .................. · .... · .. 1 TTL+ 100pF
Address input requires that it should be defined' during an active period.
• Capacitance
Ratings
Parameter Symbol Conditions Unit
MIN. TYP. MAX.
Input capacitance CrN VrN=OV 10 pF
• Timing Diagram
(1) When the CE input is used as the clock
(The chip is selected by the input of CSo/CSo• CS 1 ICS,.)
t---------tCYC-------~
Ao-At3
OE
Do-D, ----------------------~~K
(2) When the CS input is used as the clock (9E~VIL(MAX.))
~------tCYC------__I
CSo/CSo
Chip select
CSt/CSt
Ao-At3
OE
--------SHARP.......,~-----....--,
620
CMOS 131072-Bit Mask Programmable. Read Only Memory LH53127
• Chip Select
IT cSo/CSQ, CS,/CSI- DE Do-D7 Mode
L Valid data output Read
Select
L H Output non -select
High impedance
Non-select X Non-select
H X Standby
~---'---'---SHARP---'-'-"'-------
621

LH53129 Only Memory .

organized as 16,384-word-by-8-bitby using sili-
I~I~ I~I~
uu ::Je.8ooci).ci)r.i)u
con-gate CMOS process technology_ zz.;z;)CQ>uuuuz
• Features
L 16,384-word-by-8-bit organization
2. Single +4.5V power supply
4. Edge enabled operation (CE l. CE z)
8. Byte/digit output select
9. 44-pin quad -flat package Top View
• Block Diagram
Chip Enable { l~
Cbi, S.I~; { ,
Circuit
Address Input
622

Storage temperature T s '" -55-+150 "C
VIL -0.3 0.8
Input voltage V
VIH Vee -1.0 Vee
Operating temperature T oDr 0 60 "C
• DC Characteristics (Vee=4.5V±10%, Ta=0-+60"C)

Input high voltage VIH Vee -1.0 Vee V
Output high voltage VOH IOH=100fLA 2.4 V
Input leakage current I ILl I VIN=OV-Vee 1.0 fLA
In non -selection,
Output leakage current I ILO I 1.0 fLA
VOUT=OV-Vee
Chip enabled power
leCl 3 7 rnA 1
supply current
Chip disabled power
lee2 CS, VIN=0.2V or Vee-0.2V 5.0 fLA
supply current
Note 1: Average current at cycle time of 7.5,.,s with output open and input set to OV or Vee.
• AC Characteristics (Vee=4.5V±10%, Ta=0-+60"C)

Address setup time t AS 1 fLS
Chip enable setup time teE 6 fLS
Chip enable precharge time to 1.5 fLs
Chip turn-off time (CE) tDFl 1.5 fLS
Chip turn-off time (CS) tDF2 1.5 fLs
Cycle time tcYe 7.5 10,000 fLs

• Input voltage amplitude·· .. ······································· +0.8V-Vcc -1.0V
• Input rising/falling time···· ...................................... 20ns
• Input threshold level··· ........................................... 1.5V
• Output threshold level············································ 0.4 V and 2.4 V
• Output load condition ............................................. 10pF

-----------SHARP---------
623
CMOS 131072-Bit Mask Programmable Read Only Memory' lH53129
• Timing Diagram
CE
CS
(High impedance)
• Chip Select
CS O/CS O-CS 3/CS 3 CE 1 . CE 2 Do D7 Mode
L H DOUT Read
H L
H II

Data output pins
LlU BID
D7 D6 D5 D4 D3 D2 D1 Do
L L D7 D6 D5 D4 D3 D2 D1 Do
L H D7 D6 D5 D4 D3 D2 D1 Do
H L D7 D6 D5 D4 D3 D2 D1 Do
H H D7 D6 D5 D4 D7 D6 D5 D4
624
• Electrical Characteristics Curves (Ta=25"C unless otherwise specified)

Normalized chip-enable delay time VS. Normalized chip-enable delay time vs . .
supply voltage ambient temperatur~
1.4 1.4
,
Ta=60'C Vee =4.0 V
;; 1.2 1.2 /
.,.,
" /'
~
~ u
II 1n
?:
u
u
1.0
0.0
.II
t:. 1.0 /
'"
u
.:t:: ~ r--- .:t::'"
u V ,
'"
.;; 0.8 .;;'" 0.8
0.6 0.6
3.5 4.0 4.5 5.0 5.5 o 25 50 75 100
<: 4 <: 4
~ tcye =7.5 /JS ~ Vee=5.0V
tl'=1.5/Js tcye =7.5 /JS
g
....
G
....
u tl'=1.5/Js
3 3
.~
......
/ "go
--
2
~ ...'"
.S:
~ .....
.g
~
...
..,"
~
""
§'
4.0 4.5 5.0 5.5 <Il 0 25 50 75 100
Supply voltage Vee (V) Am!>ient temperature Ta ('e)
Output high voltage VS. supply voltage Output low voltage vs. supply voltage
6.0 0.4
IOH=0.4mA IOL=1.6 rnA
~
V· ?: 0.3
4.5
r-
~
i
.. 3.0
---
~
:i
..c:
~
i 1.5 1
o=
0 0
3.5 4.0 4.5 5.0 5.5 3.5 4.0 4.5 5.0 5.5
Supply voltage Vee (V) Supply voltage Vee (V)
.-----.-------SHARP·~.-.----~-.-.
625
CMOS 131072-Bit Mask Progiammable

LH53129A Read Only Memory .

. The LH53129A is a mask programmable ROM
lorganized as 16,384-word-by-8-bit by using sili-
• Features
4. Edge enabled operation (CEl> CE z)
8. Byte/digit output select u u
9. 44-pin quad-flat package z Z Top View
• Block Diagram
Data Output
~
Chip Enable { 18
8JVCC
Chip Select { 24 5 GND
30 LlU
9 B/D
L/U.B/D
Control
Circuit
Address Input
626
CMOS 131 072-Bit Mask Programmable Read Only Memory LH53129A

Operating temperature Topr -5-+55 ·C
Storage temperature T st " -55-+150 ·C

VIL -0.3 0.8
In put voltage V
V IH Vcc -1.0 Vcc
Operating temperature T oDr -5 55 ·C
• DC Characteristics (V cc =4.5V+5V±10%, Ta=-5-+55·C)

Input high voltage VIH Vcc -1.0 Vcc V
Output high voltage VOH IOH= 100 flA 2.4 V
Input leakage current I ILl I VIN=OV-Vcc 1.0 f'A
In non-selection mode,
Output leakage current I lLO I 1.0 flA
VOUT=OV-Vcc
Chip enabled power
IccI 7 14 rnA 1
supply current
Chip disabled power
Icc2 CS, VIN=0.2V or Vcc-O.2V 5.0 flA
supply current
Note 1: Average current at cycle time of 4.0 p's with output open and input set to OV or Vee.
• AC Characteristics(Vcc=5V±10%, Ta=-'-5-+55·C)
Address setup time tAS 1 f'S
Chip enable setup time tCE 2.5 f'S
Chip enable precharge time tD 1.5 f'S
Chip turn-off time (CE) tDFI 1.5 f's
Chip turn-off time (CS) tDF2 1.5 f's
Cycle time tcYC 10,000 fls

• Input voltage amplitude ........................................... +O.8V - Vcc-1.0V
• Input rising/falling time··· ...... ·· .... · .... ··· ............ ······· 20ns
• Input threshold level ............................................. ·1.5V
• Output threshold level ............................................ OAV and 2AV
• Output load condition'" .......................................... lOpF
---------------$HARP--------
627
CMOS 131072-Bit Mask Programmable' Read Only Memory LH53129A
• Capacitance - (f ko lMHz, Ta=25"C)

Parameter Symbol Conditions MIN. TYP. . MAX. Unit
Input capacitance CIN V[N=OV 15 pF
Output capacitance COUT Va T=OV 15 pF
• Timing Diagram
I--tAS tCYC
~r---t
J
CE '%"
CS
J---tCE-----I
I---tOF1-
r
(Highim pedance) .
,,',/,
/.
Valid data
• Chip Select
CS O/CS O -CS 3 /CS 3 CE 1 CE 2 Do 0 7 Mode
L H DOUT Read
H L
H H

Data output pins
LlU BID 06
07 .
Os 04 03 O2 01 Do
L L 07 06 Os 04 03 O2 01 Do
L H 07 06 Os 04 03 O2 01 Do
H L 07 06 Os 04 03 O2 01 Do
H H 07 06 Os 04 07 06 Os 04
628
• Electrical Characteristics Curves (Ta=25"C unless otherwise specified)

Normalized chip-enable delay time vs. Normalized chip-enable delay time vs.
1.4 1.4
Ta=60'C Vee=4.5 V
1.2 1.2
:>
0
.n "- U
1n
~
~
N
II
u
u
.
!:
II
1.0 ~
:> 1.0
~
<
'"
u
.;:'" 0.8
------r- .;:"'
"-
.;:"' 0.8
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
<" 6.0 t eye =4.0.us
-<
-5
6.0 r-------,-----.----,
Vee=5.5V
-5
tl' =1.5.us G teyc=4.0.us
G ..:i tp=1.5.us
..:i 4.5 ./
4.51===~===*==_t_----1
.§ ~ .§
-:0
-:0...
., ~ ~
go 3.0 ./
""o
.~
30r---+----r---+--~
.
.~ .g
.g
~ 1.5 ~ 1.51----+----r---+--~
... ...
1i 1i
..e;. ..e;.
~ 0
IS:
r/l 4.0 4.5 5.0 5.5 6.0 ~ 0~--2~5~-~5~0---7=5~-~100
I
Output high voltage vs. supply voltage Output .low voltage vs. supply voltage
6.0 0.4
10H=0.4 mA
V IOL=1.6 rnA
4.5 ........ ~ C
0.3
~'"
..,........ V" :>
..J
0
.,
:'if
,;:: 3.0
..,.
. ,;:: 0.2
..
-
o 0
:;
..c
~
..s ,.,..
~ 1.5 ~ 0.1
:; :;
o 0
o O~_~~_~~ _ _~____~
4.0 4.5 5.0 5.5 6.0 4.0 4.5 5.0 5.5 6.0
Supply voltage Vee (V) Supply voltage . Vec (V)
.-.----------SHARP----.----
629
NMOS 262144-Bit Mask Programmable Read

LH23257 ·Only Memory
• Description
• Pin Connections
Vee
using silicon-gate CMOS process technology. 0 A"
A7 AI3
A6 AM
A5 A9
A. All
• Features A3 OE OE
1. 32,768-word-by-8-bit organization A2
2. Single + 5V power supply AI cs CS
3. Fully static operation (No clock required)
4. All input and output TTL compatible
5. Three-state outputs. Do
6. Access time (MAX.) : 250ns 01 0;
7. ~rogrammable chip select 02
9. 28-pin dual-in-line package Top View
• Block Diagram
Data Output
"
Output Buffers
Address Input
262,144 Cell Matrix
630
NMOS 262144-BitMask Programmable Read Only Memory LH23257

Storage temperature Tst~ -55-+150 'C

Parametet: Symbol MIN. TYP. MAX. Unit
V IL -0.3 O.S V
Input voltage
VlH 2.2 Vcc V
• DC Characteristics (Vcc=5V±10%, Ta=0-+70·C)

Input low voltage VIL -0.3 O.S V
Output high voltage VOH IoH = -400,u A 2.4 V
Input leakage current I ILl I VlN =0-5.5V 10 ,uA
Output leakage current I ILO I VouT =0-5.5V during standby 10 p.A
Current I
during operation ICCl IouT=OmA SO rnA
consumption I during standby Icc2 CS~O.SV, CS;;;;2.2V 45 rnA
• AC Characteristics (Vcc=5V±1O%, Ta=0-+70'C)

Output turn-off time (from CS) tDF! 70 ns
Output turn-off time (from OE) tDF2 70 ns

• Input voltage frequency .................................... + 0.4 - + 2.4 V
• Input rise/fall time .......................................... 20ns
• Input decision level ....................................... "1.5V
• Output decision level ....................................... O.BV, 2.0V
• Output load .................................................. ·1 TTL+ 100pF
631
NMOS 262144-Bit Mask Programmable Rea~ Only Memory LH232.57
• Pin Capacitance (f=1MHz, Ta=25'C)

• Timing Diagram
tRC
~ ~t\
I - - tOH
tACC
\ tCE
tcs tDFl
"(- tOE-
ro- tDF2
~ VII
(High impedance) ~\\
Valid data -I) ) )
• Chip Select
CS/CS OE/OE Output Current consumption
LlH Standby
High impedance
LlH
H/L Operating
H/L DOUT
632

., 1.4
.,.a 1.4
~ .. ... Vee=4.5V
.::'" 1.2 .::'" 1.2

1;j ]
'" ~
---
Ql
P::: ~
~
u
u
~
1.0
v--- u
u
~
1.0
~
.~'" 0.8
V "
.~
0.8
''"" '"
'" ""'"
"
..::" ..::"
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta COC)
80 ..:: 80
~ ~ teYe=250ns
tcYc=250ns
u u Vee=5.5V
~ 60 ~ 60
c
.§
.Ii;
.~
1;j
~ t:.........
go 40 .-- V ....
"go 40
.ff r--
.g 1
4.5 5.0 5.5 6.0 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta ("C)
Output enable time vs. supply voltage Input voltage vs. supply voltage
.,.a 1.4 2.0
...
.::'" E::
1;j
Ql
1.2 :: 1.7
:>
~ VlH
"'
;;'"
B
1.0
~1.4
"
~
'B
.±::
.
o
VIL
.0
'"c
"
0.8 ILl
i-;;
0 0.6 0.8
4.0 4.5 5.0 5.5 6.0 4.0 4.5 5.0 5.5 6.0
Supply voltage Vee CV) Supply voltage Vee CV)
- . . - . - - - - - - S H A R P - - - - - . - . - - .......
633
CMOS 2~2144-Bit Mask Programmable Read Only.Memory LH53256

LH5325·6 Only Memory
.• Description • Pin Connections

organized as 32,768-word-by-8-bit by using sili-
• Features
3. Low power consumption_
4. Edge enable operation (CEl> CE 2)
8. Bytel digit output select
9. 44-pin quad-flat package Top View
• Block Diagram
262,144 (512X64X8)_
Cell Matrix
Address Input
~----------~y~----------~
Data Output
----------SHARP----------
634

Pin voltage * VIN -0.3-+7.0 V
Operating temperature ,Topr 0-+60 "C
* The maximum application voltage on any pin with respect to GND.
• DC Characteristics (Vcc=5.0V±10%, Ta=0-+60"C)
Input low voltage V;L -0.3 0.6 V
Input high voltage VIH Vcc -O.4 Vcc V
Output leakage current I Iw I 1.0 pA 1
Chip enabled power
Icc! 10 mA 2
supply current
Chip disabled power
Icc2 50 pA 3
supply current
Input capacitance CIN 5 pF 4
Output capacitance COUT 10 pF 4
Note 1: CE I =Vcc-O.2V or CE2=O.2V or OE=Vcc-O.2V, VOUT=OV-Vcc
Note 2: ~t amplitude: O.4V-Vcc-O.4V, tcYc=900ns, output open
Note 3: CE1=VCC-O.2V, CE2=O.2V
Note 4: Ta=25t:, f= IMHz
• AC Characteristics (Vcc=5.0V± 10%, Ta=0-+60"C)

Chip enable setup time tCE 800 ns
Address setup time t AS 30 ns
Address hold time tAH 100 ns
Chip turn·off time (CE) tDFl 100 ns
Chip turn-off time (OE) tDF2 100 ns
Chip enable precharge time to 100 ns
Cycle ,time tcYC 900 ns

• Input voltage amplitude .........................•................ +O.4V-V cc -O.4V
• Input rising/falling time ......................................... 20ns
• Input threshold level ··············································1.5V
• Output threshold level ..•......................................... 0.4 V and 2.4 V
• Output load condition ............................................. 10pF
635
............,...............--...-:...-.........................
CMOS 262144-Bit Mask Programmable Read Only Memory
.............
~
LH53256
• . Timing Diagram
A o -A 14
CSo/CSo-CS 3 /CS 3 Input transition
L/U, BID
(High impedance)
1-------tCYC----~~
• Chip Select
CE 1 CE 2 OE CS2/CSO -CS 3/CS 3 Mode Do-D 7
0 DOUT
In selection mode Read
L H 1
X In non-seleCtion mode Non-selection
L L X High impedance
H L X Standby
H H X

Data output pins
L/U BID
07 06 05 04 03 D2 01 Do
L L D7 D6 05 D4 03 D2 D1 Do
L H D7 D6 D5 D4 D3 O2 D1 Do
H L D7 06 D5 D4 D3 D2 . D1 Do
H H 07 D6 05 04 07 06 05 04
636
• Electrical Characteristics Curves (Ta=25t unless otherwise specified)
Normalized chip-enable delay time vs. Normalized chip-enable delay time vs.
1.4 1.4
Ta=60'C V cc=4.5V
~ 1.2 .... 1.2

>
<=
"- U
'tn
/
~
u; C'O
II
tl .
II
/
e 1.0
--
!: 1.0
'"
<.)
~
~
'"
<.) ~
~
~ 0.8 ~'" 0.8
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta' ('C)
8 8
tcyc =900 DS
tl'=100DS .,/
6 ~ 6
4
--- ~.
2 2
Vcc=5.5 V
tcyc=900 DS
tp =100 ns
o
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage V cc (V) Ambient temperature Ta ("C)
Output voltage vs. supply voltage Input voltage vs. supply voltage
6.0 2.4 r--------,------r---,
IOH=-1.0mA Ta=O'C(VlH)
~VOH
IOL=4mA Ta=60'C(VILl
.--' ~
e Ta=75'C e 1.8
4.5
0:
.",..,.. I-"" :=
>
0
>
.; ::l
>
0
>
..'"
;!:O
3.0
'~"
;!:O
0
1.2
0
'"
:;'" 1.5 i 0.6
.fr .....c
0=
VOL
o 0
5.0 5.5 6.0
4.0 4.5 5.0 5.5 6.0 4.0 4.5
Supply voltage Vee (V) Supply voltage Vce (V)
-----·-~.-----SHARP-.----------
637
CMOS 262144-Bit Mask Programmable Read Only Memory - LH53257
CMOS 262144-Bit Mask Programmable Read·

LH53257 Only Memory
• Description
• Pin Connections
able ROM organized as 32,768-word-by-8-bit by Vee

using polycrystal silicon-gate CMOS process tech-
0
AI,
nology. A7 AI3
A6 As
A, Ao
A, All
A3 OE OE
• Features
A2
Al CS CS
An
Do
4. Fully static operation (No clock required)
5. All input and output TTL compatible DI
6. Three-state outputs Dz
8. Programmable chip select Top View
• Block Diagram
Data Output
r - - -________~A~_ _~_ _~--~
Cell Matrix
Address Input (32,76SXS)
638
• Absolute MaXimum Ratings

Output voltage * VOUT -0.3":'+7.0 V
*The maximum applicable voltage on any pin with respect to GND.
VIL -0.3 0.8 V
Input voltage
VlH 2.2 Vee V
• DC Characteristics (V ee =5V±10%, Ta=0-+70"C)

Input low v~ltage VIL -0.3 0.8 V
Input high voltage VlH 2.2 Vee V
Output low voltage VOL 10L =1.6mA 0.4 V
Output high voltage VOH IOH=-200 pA 2.4 V
Input leakage current I ILl I V IN =0-5.5V 10 pA
CS=0.8V, CS=2.2V,
Output leakage current I lLO I VoUT =0-5.5V
10 pA
Current IDuring operation Icc 10uT=OmA 30 rnA

consumption I During standby ISB CS";:0.2V, CS~Vee-0.2V 30 pA
'. AC Characteristics (Vcc =5V±10%, Ta=0-+70"C)

Access time tAce 250 ns
Output enable time toE 100 ns
Output turn·off time (from CS) tDFl 100 ns
Output turn·off time (from OE) tDF2 100 ns

• Input voltage frequency width····························· ······0.8 - 2.2V
• Input rise/fall time ................................................. 20ms
• Input decision level··· ............................................• ·1.5V
• Output decision level····················· .......................... 0.8V and 2.2V
• Output load .. ·························································1 TTL+ 100pF
---------SHARP-----.-.-.---
639
CMOS 262144-:Bit Mask Programmabl~ Read Only Memory LH53257
• Pin Capacitance (f=IMHz,Ta=25'C)

Parameter Symbol Conditions MIN. rip. MAX. Unit
Input capacitance CIN VIN-OV 10 pF
Output capacitance CIN VOUT=OV 10 pF
• Timfng Diagram
Ao-Au =x1-:_~-_-_-_-_~-_-_~t_RC~~~~~~~~~~
. .-_. . . I-.01----tACC----''"I
I-o,""-----tcE-----""I
~-.,;..-+.;;:.:...--_
,e tcs
OE
(High impedance)
• Chip Select
CS/CS OE/OE Output Power consumption
L/H X' During standby
High impedance
LlH
H/L During operation
H/L Output
640
CMOS 262144-8it Mask Programmable Read Only Memorx LH53257
• Electrical Characteristics Curves (Vcc=5V, Ta=25"C unless otherwise specified)·

1.4 1.4
~ ~
~
.
.,..
~
...,. Vee=4.5V
.~ 1.2 "- .~
1.2
...
'"
].,
;;
~
~
p:: p::
1.0 1.0 ~
-----
u u
~
u
-
u
.;; .;;
., .,
'Srn 0.8 .! O.I!
.,rn .,rnrn
...:"" ...:""
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta C·C)
12 12.-----------.-----~----~
tcye=250ns
tnc=250ns
u
..::; 9 / Vee=5.5V
9~~~,-----+-----~----~
-T'----I--_..J
,/
/ .S...
go
.,.
61----+-----+-----/----1
./' .rr.
V .g
~. 31----+-----+-----/----1
8
~
4.5 5.0 5.5 6.0

~
{fl
°0~--~25~-~5~0----~75~--~100
Output enable time vs. Input voltage vs. supply voltage
supply voltage
~ 1.4 2.0
.,.
~
.~
... 2:
;; 1.2 r-...
e ;;'"
~
2'"
.,
·s.,
...,
1.0
""'" ~
~
:>
~
::
.,
.;::
.
0
'=
0.8
J 1.1
~
0 0.8'--____-'-____--'-____--'____- - J
0.6
4.0 4.5 5.0 5.5 6.0 4.0 4.5 5.0 5.5 6.0
Supply voltage Vee (V) Supply voltage Vee CV)
~.-~-----SHARP-.------------
641
. CMOS 524288-Bit Mask Prograf!1mable Read Only Memory LH53512
CMOS 524288-Bit Mask Progrartunable Read

Only Memory

organized as 65,536-word-by-B-bit by using sili-
• Features
1. 65,536-word-by-B-bit organization
4. Edge enabled operation
B. 24-pin small-outline package
Top View
• Block Diagram
10
9
8
Address Input / Data Output 7
6
5
'4'
Low
Address I--r- X
Latch Decoder - 65,536 X8
Cell Matrix
3
8 8
~ ~. High
Address
Y Y Selecter
Latch Decoder
.1 Output Output Latch /

l Buffer Output Mode Select
Chip Select {~.~

T
Chip
Select
PLA ~
16
1
~
4
~
U
Output
I
Control I 1 GND
18 Vee
Low Address High Address Byte/Digit Output

Read Signal Read Signal S elect Enable
,------...-. ....... . - - - - - S H A R P . - . - . - - - - - - -
642

• Recommended Operating Conditions (Ta=25"C)

Supply voltage Vcc 4.0 5.0 6.0 V
V1L -0.3 0.8 V
Input voltage
VIH Vcc -1.0 Vcc V
• DC Characteristics (V ee =5.0V±20%, Ta=-5-+55"C)

Input high voltage VIH Vec -1.0 Vcc V
Output high voltage VOH IOH =-0.5mA Vcc -0.8 V
Input leakage current I ILl I 1.0 pA 1
Output leakage current I ILO I 1.0 pA 1
Chip enable power supply ICCI 1,500 pA ·2
current Icc2 500 pA a
Chip disabled power supply
current
ICC3 3.0 pA .
Note 1: Input leakage current (except A/Do_7): VIN=OV-Vcc
110 leakage current (A/Do-7): VIN/OUT=OV-Vcc
CSI=0.2V, CSI=Vcc-0.2V or OE=0.2V, OE=Vcc-0.2V
Note 2: tcyc=4.4 ,.,s, Vcc=5.5V, output open, VIN= +0.4-+5.1 V
Note 3: tCyc= 15 ,.,S, Vcc=5.5V, output open, VIN=+0.4-+5.1 V
Note 4: CS1=0.2V, CS1=Vcc-0.2V
643
CMOS 524288-Bit Mask·Programmable Read Only Memory LH53512
• AC Characteristics (V cc =5:0V±20%, Ta=-5-+55'C)

Low.er ·address setup time- tSLA 0 ns
Lower address hold time tHLA 200 ns
Higher address setup time tSHA 0 ns
Higher address hold time tHHA 200 ns
CS hold time (non· selection) tHC 0 ns
CS setup time tsc 200 ns
BID setup time tSB 0 ns
BID hold time tHB 200 ns
LAS pulse width tWL 500 ns
HAS pulse width tWH 500 ns
HAS access time tHAS 3,000 ns
OE access time tOE 1,000 ns
AID open setup time tFO 0 ns
OE to data out delay taD 0 ns
OE to pulse width two 0 ns
CSI data off delay tcF 0 200 ns
OE to data Qff delay tOF 0 200 ns
OE LAS delay taL 200 ns
BID OE setup time tSBO 200 ns
BID OE hold time tHBO 200 ns
Cycle time (8-bit output mode) tcYCl 4,400 ns
Cycle time (4-bit output mode) t CYC2 580 ns

• Input voltage amplitude ........................................... +OAV -Vcc-OAV
• Input risingifalling time························ ................... 20ns
• Input threshold level .. ·· .. ············ .. ····· .. · .......... ··· ...... 1.5V
• Output threshold level .. ······ .. ···· .. ····· .. ·· .... ·· .... ···· .... ··OAV and Vee -O.8V
• Output load condition .......................... ·· ...... · ...... · .... l00pF
• Capacitance (f=IMHz, Ta=25'C)

644
• Timing Diagram
a-bit output mode
4-bit output mode
* DOUT=Do::-3 at B/D=O Arbitrary order of output and number of output

repetition.
D4 - 7 at B/D= 1
645
CMOS 1048576-Bit Mask Programmable Read Only Memory ,LH531 000
CMOS I048576-Bit Mask Programmable

LH531000 Read Only Memory

/ The LH531000 is a mask programmable ROM
organized as 131,072-wOl:d-by-B-bit by using
silicon-gate CMOS process technology.
• Features
1.
131,072-word-by-B-bit organization
2.
Single+5V power supply 20 CS/CS/CE/CE
Low power consumption
3.
4.
Fully static operation
5.
Automatic power down mode
6.
All input and output TTL compatible
7.
Three-state outputs
B.
Access time (MAX.) : 250ns (normal mode)
BOns (nibble mode) Top View
CS type 20pin = CS/~
OE type 20pin = OE/OE
10. 2B-pin dual-in-line package
• Block Diagram
Data Output
~~----~~~--------~
D7 Ds Ds D4 Da D2 DI Do'
CS/CS/OE/OE 20
Address
Input
1,048,576(131,072 X 8)
Cell Matrix
646
................ -........... -...... - . - . -...... - . -....................
Only Memory for "kanji" Characters Generation
LH53012 Series
I NEW I
LH53012 Series CMOS 12441S0-Bit Mask
Programmable Read Only Memory for "kanji" Characters Generation
.---------------------------------~
LH530101 - 4 are mask ROMs for "kanji"
characters generation which memorize a total of Vee
6834 characters of non-"kanji" and "kanji". It is 0 NC
able to input the first and second bytes of JIS ~kan·
ji" code and a character is composed of 24 X 24 NC
dots prescribed in lIS C 6226-1983 Y7
Y6
Y5
y,
Y3
• Features y,
1. 4 chips in a set
Non-"kanji"(524 characters) + First standard CSI
"kanji"(2965 characters) : LH530101 +
OE
LH530102 Second standard "kanji"(3388 char·
NC
acters) : LH530103 + LH530104
2. Row scanning method NC
3. 103,680-word-by-12-bit organization D11
4. Single + 5V power supply D",
5. Low power consumption D9
6. Fully static operation (no clock required) DB
7. Three-state outputs D7
D5
9. Involved the error correcting. circuit GND
10. 40-pin dual-in-line packge Top View
647
CMQS,124416-:-Bit Mask Programmable Read
OnJy Memory for "kanji" Characters Generation
.-........,....,... -.-.-.-..-.-.-.- ...........
LH53012 Series
• Block Diagram
30
Chip Chip
Select { Select
Input Buffer Output
Enable Enable
Buffer
,...---'..........., Ao
Row
Decoder
Address
Buffers
Character Sense
Address Amp.
Input Column Memory Output . Output
Decoder Arrey ECC Buffers
-----..--.-~.---SHARP,.- ........... -~.-.~--
648
Ordering Procedure of Mask ROM
~~~.-~~.-~ ......-.-~.-~~~~~
Mask ROM Ordering Procedure

The ordering procedure for mask ROMs is de· ROM.
scribed below along the mask ROM development After the ROM data is received, we use a CAD
flow chart. system to create a magnetic tape to prepare the
ROM data from the user should be submitted in ROM mask, and create a new EPROM or paper tape
the form of an EPROM or on paper tape. At the and their print-outs for comparison to make sure
same time, the fo\1owing information should be pro- that the CAD-processed ROM data is correct.
vided. After the user verifies that there are no prob-
(1) Type of media on which ROM data is pro- lems with the results, we start preparing the mask
vided and the TS (technical sample) and submit these to
(2) Specified items (chip select, markings) the user for evaluation.
(3) Corporate name, person in charge, signature If there are no problems with the TS, the user
(4) Date of order submits the "Mask ROM TS Certification" to us.
When submitting the ROM, two sets of ROM data We can begin mass production immediately or
media and ROM print-outs must be submitted to shortly thereafter according to instructions given
make sure that correct data can be read from the by the user.
Mask ROM Development Flow Chart
Client SHARP
EPROM or
paper tape
Mask ROM delivery /+----+-------------1 Mass production start
---------.-.....-SHARP-.-.-,--------
649
CMOS 65536-Bit Electrically Programmable ROM LH5764J
CMOS 65536-Bit Electrically Programmable

LH5764J ROM
The LH5764] is a CMOS UV ERASABLE and
electrically programmable read only memory organ-
ized as 8,192-word-by-8-bit. It is especially well
suited for application where rapid turn-around
and/or bit pattern experimentation, and low-power
consumption and fast access time are important.
• Features
1. 8,192-word-by-8- bit organization
2. Access Time (MAX.)
LH5764]-20 : 200ns
LH5764]-25 : 250ns
LH5764]-30 : 300ns
LH5764]-45 : 450ns
4. Programming power supply: + 12.5V ± 40% 6. Fully static operation
Programming pulse width : 1 ms/byte 7. Input and output TTL compatible
5. Power consumption (MAX.) : 150m W (operation) 8. Pin compatible with i2764
0.55mW (standby) 9. 28-pin dual-in-line package (Ceramic)
• Block Diagram
65,536
Row Cell Array
Address Input
'" ...
ec .'". '"0
=
_'"0"
'Ii '"0
u<o
0'"0 '"
...o
c_~
... "c ...'"
~
"0
UUl0"""
..... (0)
Data Output
------------SHARP----------
650
CMOS 131072-Bit Electrically Programmable ROM LH57128J
CMOS 131072-Bit Electrically

LH57128J ProgTammable ROM
The LH57128J is a CMOS UV ERASABLE and
electrically programmable read only memory organ-
ized as 16,384-word-by-8-bit It is especially well
suited for application where rapid turn-around
• Features
2. Access Time (MAX.)
LH57128J-20: 200ns
LH57128J-25 : 250ns
LH57128J-30: 300ns
LH57128J-45 : 450ns
4. Programming power supply: + 12.5V ± 40% 6. Fully static operation
Programming pulse width: 1ms/byte 7. Input and output TTL compatible
5. Power consumption (MAX.) : 150mW (operation) 8. Pin compatible with i27128
0.55mW (standby) 9. 28-pin dual-in-line package (Ceramic)
• Block Diagram
A7 .,''....""
"'"'""
..:
"0
0
Il::
.,....
"'.,""
0
131,072
Cell Matrix
00
~ ~ ~ 1------+----.1'\ r------""""'------,
~:g ~ 1------+----1/
U":O
.... 1----'
'0 - ~
.......... I-------~'"I
§ .~ ~ L--r---r--r-..,...---r-~_r-r__'
UUl0
---.-.--------~SHARP-----~--
651
, (
............. - . - . -....... - . - _ . -...........................

CMOS 262144-Bit Electrically Programmable ROM' LH57256J
CMOS 262144-Bit Electrically

LH57256J 'Programmable ROM ',' NEW I
The LH57256J is a CMOS UV ERASABLE and
electrically programmable read only 'memory organ-
ized as 32,76S-word-by-S-bit. It is especially well
suited for application where rapid hlrn-around
• Features
1. 32,768-word-by-S-bit organization 20 CE/PGM
2. Access Time (MAX.) ,
LH57256J-20 : 200ns
LH57256J-25 : 250ns
LH572p6J-30 : 300ns
LH5725'6J-45: 450ns
4. Programming power supply: + 12.5V ± 40% Top View
Programming pulse width: 1ms/byte
5. Power consumption (MAX.) : 150mW (operation) 7. Inputs and Outputs TTL compatible
0.55mW (standby) S. Pin compatible with i27256
6. Fully static operation 9. 2S-pin dual-in-line package (Ce:amic)
• Block Diagram"
'"
..."'"
"""" "...
<
262,144
it "" Cell Matrix
0
0
~
" 0"
=~'"'" "...8- 1----+----0/

..=Ei"""
0"" "
u<o
...
"0- ~
........
.., c "
CE/PGM 20}---~'" = "" =
0 · ....
UClJtj
QJ
652
CMOS 1024-Bit Static Random Access Memory LH51 01-30/LH51 01-45
LH5101-30/LH5101-45
CMOS l024-Bit Static Random Access Memory
The LH5101-30/LH5101-45 are fully static RAMs
organized as 256-word-by-4-bit by using sili-
• Features
1. 256-word-by-4-bit organization
3. Fully static operation
LH5101-30 : 300ns, LH5101-45 : 450ns
7. Data can be held on +2V supply voltage
8. Low power current consumption at standby Top View
mode 10 pA (MAX.)
• Block Diagram
Chip Enable Input { ~99\----L-/

Data Output
Read/Write Input
Do<. l.,.'{ :
Output Disable 8
Address Input
"--~------SHARP'-'-------'-'
653
CMO$ 1024,..Bit Static Random Access Memory LH5101-30lLH51 01-45

Supply voltage· Vcc . -0.3-+7.0 V
Input voltage· VIN . -0.3-V;cc+0~3 V
Output voltage· VOUT -0.3-Vcc +0.3 V

Input low voltage V1L 0.65 V
Input current I III I 0;;;;;;V1N;;;;;;V CC 1.0 pA
Output leakage current I ILO I O~VIN~VCC, CE1=2.2V 1.0 pA
Output open
Current consumption 1 Iccl 20 mA
VIN=Vcc , CE 1;;;;;;0.65V
Output open
Current consumption 2 Icc2 25 rnA
VIN=2.2V, CE 1;;;;;;0.65V
Chip disabled current -
ICCL O;;;;;;VIN;;;;;;VCC , CE2 ;;;;;;0.2V 10 pA
consumption
(1) Read cycle (Vcc =5V±10%, Ta=0-+70t)
LH5101-30 LH5101-45
Cycle time tRC 300 450 ns
Access time t ACC 300 450 ns
Chip enable time 1 teal 250 400 ns
Chip enable time 2 te02 350 500 ns
Output enable time taD 180 250 ns
Chip turn-off time tDF 0 100 0 130 ns
Data hold time from a.ddress tOHl 0 0 ns
Data hold time from CE I tOH2 0 0 ns
(2) Write cycle (Vcc~5V±10%, Ta=0-+70t)
LH5101-30 LH5101-45
MIN. TYP. MAX. MIN. TYP_ MAX.
Cycle time twc 300 450 ns
Access time tAW 60 130 ns
Chip enable time 1 teWl 250 350 ns
Chip enable time 2 teW2 250 350 ns
Data setup time tDW 150 250 ns
Data hold time tDH 40 50 ns
Pulse width twp 180 250 ns
Recovery time tWR 40 50 ns
Input enable time tDs 100 130 ns
.-.-.-.-----SHARP~.----....-,-~--
654

• Input voltage amplitude···· .. ····· .. ·· ............................ + 0.65 - + 2.2V
• Input rising/falling time ......................... ·················lOns
• Timing reference level································ ....... ·····1.5V
• Output load condition·· .. ··········································1 TTL+ 100pF
• Capacitance (f=IMHz, Ta=25"C)

Input capacitance CIN VIN=OV 3.5 6 pF
Output capacitance COUT VOUT=OV 9 12 pF
• Low-Voltage Data Hold Characteristics (Ta=0-+70"C)

Supply voltage for
V OR VCE2~0.2V 2.0 V
data hold
Supply current for
IccoR VCE2~0.2V, VOR=2.0V 5 pA
data hold
Chip turn·off time teOR 0 ns
Operation recovery time tR t RC ns 1
Note 1: ' In data hold mode, all input/output pins are put below VD•. tRe : Read cycle time
• Timing Diagram
(1) Read cycle
1--------tRc------~
~+__--·tC02--__i
OD
(in I/O common mode)
j E - - - - I t ACC
For data input/output separation, OD is made low. In read cycle, R/W is made high.
655
CMOS 1024-Bit Static Ran<;:Jom Access Memory LH51 01-301LH51 01-45
(2) Write cycle
~-------------tw~------------~
.tcw,---~
CE,
~------~-tcw,,--~----~
DI,- Dr,
-tDI'!---------;~
------~~~~------twp------~r_------r_---
R/W
In I/O common mode, OD is made high during the write period. For data input/output separation, OD may be either high or low.
(3) Low-voltage data hold
-.-..---.----SHARP--.--~--.-.
656
• Electrical Characteristics Curves (Vcc=5V, TA=25t unless otherwise specified)

1.4 1.4
Ta=70"e 0;- Vcc=4.5 V
.aco V
r---. .~
>
'" /
1.2
v
'" ~
co
1/
Qi
~
l:3 1.0 l:3 1.0
~
:;
:;
.!'"
OJ
OJ
0.8
~ .!'"
~ 0.8
/
'" ...:""
...:""
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100

40 40
...: ...:
5 5
G 30 N
<.) 30
~ <.)
>-<
C
..'" c
..'::s"
----
::s 20 20
b" ~ b"
is: ~ r--
----
Q.
..'"
::s
OJ
co
10
~
,
§-
OJ
g:,
.
co
10 ...
...:'" ...:'"
> >
o
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
SupplyvoItage Vee (V) Ambient temperature Ta ("e)
Input voltage vs. sup·ply voltage Input voltage vs. ambient temperature
2.0 2.0 ..-----..-----,----,---~
~
.... 1.5
;; V IH
;;'" - VIL :>

i5
'" 1.0
! ~
.:::
g ~
'[ 0.5 '[ 0.51---+----+----+----1
..s .a
o
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
657
CMOS 1024-Bit Sta~'ic Random Access Memory LH51 01 iLH51 01 L3
LH510'1/LH5101L3
CMOS I024-Bit Static Random Access Memory
• Description .• Pin Connections
The LH5101/LH5101L3 are fully static RAMs
organized as 256-word-by-4-bitby using sili-
o
• Features
LH5101 : 800ns, LH5101L3 : 650ns
8. Low power supply current at standby mode Top View
• Block Diagram
Chip Enable Input { 1

191)---L~
Data Output
Read/Write Input
Do<, r.,.. { :
Output Disable 18
'--.r---I
Address Input
.-..-...-.....~----SHARP ----------------
658
. CMOS 1024-Bit Static Random Access Memory LH51 01 ILH51 01 L3

Input voltage * VIN -0.3-V cc +0.3 V
Output voltage * VOUT -0.3-V cc +0.3 V
Storage temperature T= -55-+150 "C

Input low voltage V1l 0.3 0.65 V
Output low voltage Val Iol =2.0mA 0.4 V
Output high voltage VOH IOH =-1.0mA 2.4 V
Input current' I ILl I 0;&V1N;&V CC 1.0 pA
Output leakage current I lLO I 0;&V1N;&V CC, CEI=2.2V 1.0 pA
Output open, VIN=Vcc
Current consumption 1 IcC! 9 22 mA
CE 1 ;&0.65V
Output open, VIN=2.2V
Current consumption 2 Iccz 13 27 mA
CE I :S:0.65V
Chip disabled current I LH5101 100
Iccl CE z ;&0.2V pA
consumption I LH5101L3 200
(1) Read cycle (V cc=5V± 10%, Ta=O- +70"C)
LH5101 LH5101L3
Cycle time tRc 800 650 ns
Chip enable time 1 teal 800 600 ns
Chip enable time 2 te02 850 700 ns
Output enable time too 350 350 ns
Chip turn-off time tOF 0 200 0 150 ns
Data hold time from address tOHI 0 0 ns
Data hold time from CE I tOHZ 0 0 ns
(2) Write cycle (V cc=5V± 10%, Ta=O- +70"C)
LH5101 LH5101L3
Chip enable time 1 tcwI 600 550 ns
Chip enable time 2 tew2 600 550 ns
Data setup time tow 400 400 ns
Data hold time tOH 100 100 ns
Input enable time tos 200 150 ns
659
. CMOS 1024.:Bif Static Random Access Memory· LH51 01 ILH5101 L3 .

• Input voltage amplitude .. ·· ....................................... + 0.65 - + 2.2V
• Input ri~ing/falling time········ .................................. 20ns
• Timing reference level··· .. ········································ L5V
• Output load condition .. ·················;··························1 TTL+ 100pF
• Capacitance' (f=1MHz, Ta=25t)

Input capacitance CIN VIN=OV 6 10 pF
Output capacitance C~UT VOUT=OV 15 20 pF
• Low-Voltage Data Hold Characteristics (Ta=0-+70t)

Supply voltage for data
VDR VeE2~0.2V 2.0 V
hold
Supply current for data hold lee DR VeE2~0.2V, VDR=2.0V 20 pA
Chip turn:off time teDR 0 ns
Operation recovery time ** tR tRe ns
** In data hold mode, all input/output pins are put below VD •.
tRC : Read cycle time
---------- ........ ~--~-SHARP -------...~---~

660 I
CMOS 1024-Bit Static Random Access Memory LH5101/LH5101 L3
• Timing Diagram
(1 ) Read cycle
t-'--------tRC--------I
t---+--tC02:----I
OD
For'data input/output separation, OD is made low. In read cycle, R/~ is made high.
(2) Write cycle

~-----~tWC:--------~
_ _ _1-_--. J----·tCWl--.......j
eE,
I--+---t-tCW2:-------;~
Oh-DI.
f----tDW'-----!~
___-+~,~---:tw~--~~~~~----
R/W
In 110 common mode, OD is high during the write period. For data input/output separation, OD may be either high or low.
i.~-- ~~~~~~:~----
Supply voltage
V,,--------
VIH::£:t:'~
O.2V--- --
________________ __
- ------------
'b~
---
OV---- ---
. - - - - - - . - . - - S H A R P .-......-,--_.-.....-._---
661
CMOS 1024-Bit Static Random Access Memory LH5101S
LH5101S CMOS l024-Bit Static Random Access Memory

The LH5101S is a fully static RAM organized as
256-word-by-4-bit by using silicon-gate CMOS
process technology.
• Features
8. Low power supply current at standby mode
10 pA (MAX.) Top View
9. 22- pin dual-in-line package
• _Block Diagram
Chip' Enable Input { 19!>t==L~X~--'

Read/Write Input 0 Data Output
Do<, I"., { ':
Output Disable 18
'-v--'
Address Input
662

Output voltage * VOUT -0.3-Vee +0.3 V
Storage temperature T.t .. -55-+150 'C
• DC Characteristics (V ee =2.6-3.4V, Ta=-10-+60'C)
Parameter Symbol Conditions, MIN. TYP. MAX. Unit

Input high voltage VIH Vee- 0.6 Vee V
Output low voltage VOL IOL =500 pA 0.3 V
Output high voltage VOH IOH=-30pA Vee- 0.6 V
Input current I III I OS::VIN~Vee 1.0 pA
Output leakage current I lLO I OS::VINS::V ee, CE I =Vee- 0.6 1.0 p.A
Output open, VIH = Vee,
Current consumption 1 IcC! 5 11 rnA
CE I S::0.6V
Output open, VIN=2.2V
Current consumption 2 lee2 8 13 rnA
CEI~0.6V
Chip disabled current
leeL O~VIN~Vee, CE2~0.2V 10 pA
consumption
(1) Read cycle (V ee =2.6-3.4V, Ta=-10-+60'C)

Cycle time t Re 3.5 ps
Access time t Aee 3.0 ps
Chip enable time teo 3.0 ps
Address enable time t AEO 2.9 ps
Output enable time too 1.3 ps
Chip turn-off time tOF 0 750 ns
Data hold time from address tOHl 0 ns
Data hold time from CE I toH2

0 ns
toH3
tAEI 0.1 ps
Adress enable delay time
tAE2 0.5 p.s
(2) Write cycle (V ee =2.6-3.4V, Ta=-10-+60'C)

Cycle time twe 3.5 p.s
Access time tAW 750 ns
Chip enable time 1 tewl 2.2 p.s
Chip enable time 2 tAEW 2.1 p.s
Data setup time tow 1.5 p.s
Data hold time tDH 370 ns
Pulse width twp 1.5 ps
Recove'ry time tWR 180 ns
Input enable time tDs 750 ns
tAE3 0.1
Address enable delay time p.s
tAE4 0.5
-'-'-~--'--SHARP'-~~~----'--
663

• Input voltage amplitude· .. ··· .. ····················· .. ········ .... + 0.65 - + 2.2V
• Input risinglfaliing time .......................................... 10ns
• Timing reference level .......................................... "1.5V
• Output load condition ............................................ ·1 TTL+ 100pF
• Capacitance (fc=lMHz, Ta=25"C)

• Low-Voltage Data Hold Characteristics (Ta= -10- +60·C)

Supply voltage for data hold V OR VCE2 S:O.2V 2.0 V
Supply current for data hold IccoR VCE2 S:O.2V, VOR-2.0V 5 pA
Chip turn-off time tCOR 0 ns
Operation recovery time ** tR t RC ns
**In data hold mode, all input/output pins are put below VDR_ tRe: Read cycle time
• Timing Diagram
(1) Read cycle
~--------------tRC--~--------~
AE
OD
For data input/ output separation, OD is made low_
664
(2) Write cycle
twe
Ao-A7
tew!
eE!
AE
tAt..W
tDH
DI!-DI.
tDW
tw
R/W
In 110 common mode, OD is made high during the write period. For data input/output separation, OD may be either high or low.
-------}=:.=~'~~":~------
-------- '"b
Supply voltage ,Vee
2.60V
VD.
AE
V 1H
O.2V
~~~------------------~
--- ------ - ---
---
OV -----------------------------
Address enable (AE) may be high normally, but in this case, the address input level must strictly be below VIL and above VIH in.
clusive of noise spikes. Use of AE in such a timing relationship that the AE input is included inside the address input as shown
in the timing chart is fairly recommended.
665
CMOS 1024-Bit Static Random Access Memory LH5101W
CMOS I024-Bit Static Random Access

LH5101W Memory
The LH5101W is a fully static RAM organized
as 256-word-by-4-bit by using silicon-gate CMOS
process technology.
o
• Features
2. Single ,+ 5\1 power supply
5. Three-.state outputs
8. Low power supply current at standby mode
100 pA (MAX.) Top View
• Block Diagram
Chip Enable Input{ 19iH-_ _L";Y->--"---'
Data Output
Output Disable 8
----~--.--,------SHARP ....-..-.~.-.------
666

Supply voltage· Vcc -0.3-+7.0 V
Input voltage• VIN -0.3-Vcc +0.3 V
Output voltage· VOUT -0.3-Vcc +0.3 V
Operating temperature T= 0-+70 'C
Storage temperature T","- -55-+150 'C
• DC Characteristics (V cc =5V±10%, Ta=0-+70'C)

Input low voltage V1L 0.3 0.65 V
Input current I ILl I 0:5:V1N :5:Vcc 1.0 p.A
Output leakage current IILO I 0:5:V1N :5:VCC , CE I -2.2V 1.0 p.A
Output open, VIN=Vcc,
Current consumption 1 IcC! 9 22 mA
CE 1;;;;0.65V
Output open, VIN=2.2V,
Current consumption 2 Icc2 13 27 mA
CE I :5:0.65V
ICCL 0;;;;V1N;;;;VCC, CE 2 ;;;;0.2V 100 p.A
consumption
(1) Read cycle (V cc =5V±10%, Ta=0-+70'C)

Cycle time t RC 800 ns
Access time tAcc 800 ns
Chip enable tillie 1 teOI 800 ns
Chip enable time 2 tC02 850 ns
Output enable time toD 350 ns
Chip turn-off time tDF 200 ns
Data hold time from address toHl 0 ns
Data hold time from CE I tOH2 0 ns
(2) Write cycle
Cycle time
Parameter Symbol
(Vcc=5V±10%, Ta=0-+70'C)
MIN. TYP. MAX. Unit B

twc 800 ns
Chip enable time 1 tcwi 600 ns
Chip enable time 2 tCW2 600 ns
Data setup time tow 400 ns
Data hold time tOH 100 ns
Pulse width twp 400 ns
Recovery time tWR 50 ns
Input enable time tos 200 ns

• Input voltage amplitude .......................... ·· .............. · +O.65-+2.2V
• Input risingifalling time ................................ · ........ ·10ns
• Timing reference level ............................................ 1.5V
• Output load condition .................. · .......................... 1TTL + 100pF
667
CMOS t024-Bit Static Random Access Memory LH5101W
............... - ............ - ......_ _ _ _ _ _ _ _r.._..:_ _ _,.._.
• Capacitance (f=IMH~, Ta=25'C)

Input capacitance CIN VIN=OV 3.5 6 pF
• Low-Voltage Data Hold Characteristics (Ta=0-+70'C)

Supply voltage for data hold VDR VCE2~0.2V 2.0 V
Supply current for data hold IccDR VCE2~O.2V, VDR=2.0V 5 pA
Chip turn-off time tCDR 0 ns
Operation recovery time ** til t RC ns
**In data hold mode, all input/output pins are put below VOR.
me : Read cycle time
668
• Timing Diagram
(1) Read cycle
i-------tRC----------l
tCOI
t---+---tcoz-----I
too
00
tOF
i---tACC
DOl-DO.
For data input/output separation, OD is mode low, In read cycle, R/W is mode high.
(2) Write cycle
I-------twc----------.~
___+-__... ro<-----tcwl----t
CE z
I-+----tcwz---------;~
00
(in I/O common mode) tOH
011-01.
I----tow----<*;;-.-
R/W ---~--,~-----twp r-----~----
In 110 common mode, OD is made high during the write period. For data input/output separation, OD may be either high or low.
Supply voltage Vee

4.5V === __ ~~r~:·~~"-·:~~;;-u-
~~~-----------------~
VD.
VIH
CEz O.2V --- - -------------- ---
OV
.-.-----------SHARP .-.-.-----------
669
CMOS 2048-Bit Static Random Access Memory LH51 02/LH.51 02-8-
LH5102/LH5102-8
CMOS 2048-Bit Static Random Access Memory

The LH5102lLH5102-B are fully static RAMs
organized as 512-word-by-4-bit by using metal-
gate CMOS process technology.
Vee
AI
R/W
• Features
1. 512-word- by-4-bit organization
Single + 5V power supply
2.
3.
Data can be held on + 2V supply voltage
4.
5.
All inputs and outputs TTL compatible
6.
Three-state outputs
7.
B.
Pin compatible with SHARP LH5101 or Intel
5101 (except Pin 19) Top View
LH5102-B: BOOns, LH5102 : 1,200ns
• Block Diagram
Chip Select Input Qll:J+------,
Read/Write Input
u
Data Input { ;
Output Disable '!'8=~;:::=~~:2~=j2f~~~

f(: 5i}-(:6)-o{7)----'
~
Address Input.
670
CMOS 2048-Bit Static Random Access Memory LH51 02/LH51 02-8

Input voltage * VIN -0.3-V cc +0.3 V
Output voltage * VOUT -0.3-V cc +0.3 V
Storage temperature Tst2 -55-+150 t
• Recommended Operating Conditions (Ta=0-+70t)
VIL -0.3 0.65 V
Input voltage
VIH 2.2 Vcc V

Output high voltage VOH IoH --1.0mA 2.4 V
Input current I ILl I VIN=O or Vcc 7.0 pA
Output leakage current I ILO I CS~0.2V, VOUT=OV or Vcc 1.0 pA
IcC! Output open, VIN - VCC 3 22 rnA
Current consumption
Icc2 Output open, VIN = 2.2V 13 27 rnA
Chip disable current
IccL CS~0.2V 200 pA
consumption
Parameter Unit
Read cycle
Cycle time t RC 900 1,200 ns
Access time t ACC 800 1,200 ns
Chip enable time teo 800 1,200 ns
Output enable time taD 400 500 ns
Chip turn·off time tDF 0 200 0 250 ns
Data hold time toH 0 0 ns
Write cycle
Cycle time twc 900 1,200 ns
Data setup time tDW -200 0 ns
Input enable time t DS 150 250 ns

• Input vqltage amplitude··········· ................................ + 0.65 - + 2.2V
• Input rising/falling time .......................................... 20ns
• Timing reference level······ ...................................... 1.5V
• Output load condition ········································ .. · .. 1TTL+ 100pF
671
CMOS 2048-Bit Static Random Access Memory LH51021LH5102-8
• Low-Voltage Data Hold Characteristics (Ta=O-+70'C)
Parameter Symbol Condition-s MIN. TYP. MAX. Unit

Supply voltage for data hold VDR Vcs~0.2V 2.0 V
Supply current for data hold IccDR Vcs";::0.2V. VDR=2.0V 40 pA
Chip turn·off time tCDR 0 ns
Operation recovery time ** tR t RC ns
**In data hold mode, all input/output pins are put below VD•. tRe: Read cycle time. -

672
CMOS 2048-Bit Static Random Access Memory LH5102/LH51'02-8
• Timing Diagram
(1) Read cycle
tRe
Ao- As 'V
JI\
'V
JI\
..... tOHr---
cs
teo ~
I
OD ( Note 1) tOD-
I
(in I/O common mode) J
----- -----tAee
----'V
I--tDF-
--
_________ JI\ Valid data
----- ---
Notel: For data input/output separation, OD is made low.
(2) Write cycle
twe
Ao-As W V--
JI\ .JIL-
cs l/
,
~
1"--
OD ( Note 2) V
(in I/O common mode) )
tDH
I---tos- i--=+
------ ----'V
Valid data
,V- ----
------ ____ .11\tow ~~- ----
~
'\ twp U
R/W
1\
I------tAW_ i--twR-
Note 2 : tn I/O common mode, OD is made high during the write period. For data input! output separation, OD may be either high
or low.
Supply voltage ,~~n-----J ~~~~~ ~"~---1

.
Vo.--------- -
--- 'r
~~~:::::::~~=====~======;
teoR
. CS OV--- - - - ---
---'----.-..---SHARP . - . - . - - - - - - - -
673
CMOS 2048-81t Static Random Access Memory LH51 02/LH51 02-8

1.4 1.4
Ta=700e Vee=4.75 V
"...,.
..=
\ /
V
.:: 1.2
]., V
V
"'"
Il::
u 1.0 u 1.0
u
~ ....--'
.j j
., .,
.~
0.8
~ .~
'" 0.8
'.,'"" ~
<:"
" <:"
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta coe)
Current consumption vs. supply voltage Current consumption vs. ambient

temperature
5.0 5.0
<:
6
~ 4.0 4.0
- tl
-u
u
13.0
~ ~
- .§
~
~§
3.0
--- --- r--

....-- ~
§
" r--
i" 2.0 ~ 2.0
l3" "l3
u u
1.0 1.0
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta re)
2 . 5 . - - - . , - - - . . . , - - -....- - , 2.5
2: 2:
..I 2.0r---+--- :: 2.0
>;:; > V1H(MIN.)
-
> >.," 1.5
., 1.5 i-----+----+---+----I
~ ~
.:!::
1
J 1.0 ......."----+----+---+----1
:;
11.0
V1L(MAX.)
-
0.5!";:-_ _:'-:-_ _:::-::-_ _-="="_ _-:' 0.5
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
-~-~----SHARP--------~-~-~
674
CMOS 2048-Bit Static Random· Access

LH5102W Memory

The LH5102W is a fully static RAM organized
as 512-word-by-4-bit by using metal-gate CMOS
process technology.
Vee
o A.
R!W
As
• Features
1.
512-word-by-4-bit organization
Single + 5V power supply
2.
3.
Data can be held on + 2V supply voltage
4.
5.
All inputs and outputs TTL compatible
6.
Three-state outputs
7.
Pin compatible with SHARP LH5101 or Intel
8.
5101 (except Pin-19) Top View
9. Access time (MAX.) : 1,200ns
10. 22-pin dual-in-line.package
• Block Diagram
:J-----iRow Row
l--_-;of.Address.t==~Address
!r-_-.....Buffers Decoders
Chip Select Input 1 7 ' ) - + - - - - - - - ,
00----1 Input
l}----..... Data
.3}----..;o-j Control
Output Disable 181}----C>O-------L..J

~--------------------------~5~6 7~------~
'-----r---"
Address Input
--------------SHARP-----------
675
CMOS 2048-Bit Static Random Access Memory lH51{)2W

Supply voltage *
- Vee -0..3-+7.0. V
Input voltage * VIN -D.3- Vee+ D.3 V
Output voltage * ,VOUT -0.3 Vec +0.3 V
Operating temperature Toor -20.-+70 .'C
Storage temperature T st• -55 +150. 'C
Supply voltage Vee 4.0. 5 5.5 V
V1L -0..3 0..65 V
Input voltage
V IH 2.2 Vee V
• D'C Characteristics (V ee =5V±10%, Ta=-2D-+70'C)

Input low voltage V1L 0..3 0..65 V
Input high voltage ViH 2.2 Vee V
Output low voltage VOL IOL -2.DmA 0..4 V
Output high voltage VOH IoH =-1.DmA 2.4 V
Input current I ILl I V1N-DV or Vee 7.0. ,pA
Output leakage current I Iw I CS~0.2V, VOUT-OV or Vee ' 1.0 pA
IcCl Output open, V IN - Vee 3 22 rnA
Current consumption
Iec2 Output open, VIN=2.2V 13 27 rnA
Chip disabled current
rCeL CS;a;0.2V 20.0. pA
consumption
• AC Characteristics (Vee=5V± 10%, Ta=-2D-+7D'C)
Parameter I Symbol I MIN. I TYP. I MAX. I Unit

Read cycle
Cycle time t Re 1.2 ps
Access time t Aee 1.2 j.lS
Chip enable time teo 1.2 ps
Output enable time taD 50.0. ns
Chip turn·off time tDF 0. 250. ns
Data hold time tOH 0. ns
Write cycle
Cycle time twe 1.2 j.lS
Access time tAW 30.0. ns
Data setup time tDW 6 ns
Data hold time tDH 10.0. ns
Pulse width twp 40.0. ns
Recovery time tWR 20.0. ns
Input enable time t DS 250 ns

• Input voltage aIp.plitude···················· .. ····················· +0.65-+2.2V
• Input rising/falling time' ......................................... 20ns
• Timing reference lE\vel ............................................ 1.5V
• Output load condition ......................'....................... 1TTL + 100pF
676
• Low-Voltage Data Hold Characteristics . (Ta=-20-+70'C)

Supply voltage for data hold VOR Vcs";;0.2V 2.0 V
Supply current for data hold IccoR Vcs~0.2V, VOR=2.0V 40 pA
Chip turn-off time tCOR 0 ns
Operation recovery time ** tR tRc ns
** In data hold mode, all input/output pins are put below VDR. tRC : Read cycle time

677
CMOS 2048-Bit Static Random Access Memory LH51.02W
• Timing Diagram
(1). Read cycle
Ao-As
cs
J---1I----tco---..-i
OD (Note 1)
DO,-DO. Valid d!lta
Notel: For data input/output separation, OD is made low.
(2) Write cycle
J---------twc------------~~
cs
OD (Note 2)
tDH
_ _~f_--!::::::j""----twp------lr_-.......,r_--
R/W
Note 2 : In 110 common mode, OD is made high during the write period. For data input/output separation, OD may
be either high or low.
8"",1, ........¥l'l'--· _1m~:-_h:"_'~~=-l

VOR--------
V[H~~~-----------------~~
cs O.2V---
ov--- -
-- -
- -
-
-
--
--
---
- -
---
---
678
• Electrical Characteristics Curves (Vcc=5V, Ta=25°C unless otherwise specified)

1.4
Ta=70'C ., 1.4
Vee=4.5V
...,
\
..El
>
.~
1.2 /
~ V
~.,
~
u 1.0 V
'""
u
."! ,,/'
., ., ,../
.~ 0.8 .~ 0.8
:J..,'" .,..,''""
.., ..,
«: «: 0.6
0.6
4.0 4.5 5.0 5.5 6.0 -20 0 20 40 60 80 100
Current consumption vs. supply voltage Current consumption vs. ambient

temperature
5.0 5.0
«:
~
8 4.0 G
4.0
..... ..:;
.§
~ 3.0
~
- .§
<t 3.0
--------
"'"
~
i... 2.0
- ........ ~ i
I 2.0
r-- I"-
~
...
u ~
U
1.0 1.0
4.0 4.5 5.0 5.5 6.0 -20 o 20 40 60 80 100
2.5.-----,---,---,.------, 2.5
2: 2:
== 2.0 1------1f------ 2.0
-
VIH(MIN.)
:> >==
:5 :5
:> >
., 1.5
:.:: VIL(MAX.)
0
>
:; 1.0
....."""
0.5 ~----:-"=--~7--~-=----:! 0.5

4.0 4.5 5.0 5.5 6.0 -20 0204060 80 100
------------$HARP----------
679
NMOS· 4096-Bit Static Random Access Memory LH2114L-20
NMOS 4096-Bit Static Random

LH2114L-20 Access Memory

The LH2114L-20 is a fully static RAM organ-
ized as 1024-word-by-4-bit by using silicon-gate
NMOS process technology_
• Features
3. Fully static oper~tion (no refresh or clockre-
quired)
5. Three-state outputs.
6. Access time (MAX.) : ,200ns
• Block Diagram
'"
"...'" M emory Array
Address Input )-----------~~==~ ~ ...~ 64 Rows
c " 64 Columns
)-----------c~=====1 ]o 8"
)--_ _ _--{:(~==~ U I=l
Row I/O Circuits '
Row Address
Decoders
T
Address Input
680
NMOS 4096-Bit Static Random Access Memory LH2114L-20

Storage temperature T.tK -55-+150 t

Output low voltage VOL IoL =2mA 0.4 V
Output high voltage VOH IoH =-lmA 2.4 V
Input leakage current I ILl I VIN=OV or Vcc 10 ~A
Output leakage current I ILO I CS=V IH, VI/0 =0.4V or Vcc 10 pA
Current consumption Icc VIN =5.5V,IlIo=OmA 70 mA
(1) Read cycle (Vcc=5V± 10%, Ta=0-+70t)

i Cycle time tRc 200 ns
Output turn·off time tOF 70 ns
Output hold time toH 20 ns
(2) Write cycle (Vcc=5V±1O%, Ta=0-+70t)

Cycle time twc 200 ns
Output turn·off time tOF 70 ns
Conditions for measurment of AC characteristics

• Input signal level .. ·········································· +OA-+2AV
• Input signal rise/fall time ·································10ns
• Time measurement level .................................. ·1.5V
• Output load condition····································· .. 1TTL + 100pF
681
NMOS 4096-Bit Static Random Access Memory LH211.4L-20
• Pin Capacitance (f=lMHz, Ta=25'C)

Input/output capacitance CliO VI/O=OV 4.5 10 pF
• Timing Diagram
(1) Read cycle
i--------tRC-------'"'i
i-----tACC--_
(Note) WE is "High"
(2) Write cycle
tire
Ao-Ag
CS
1 tAIr ,. 3
682
NMOS 4096-Bit Static Random Access Memory LH2114L-20

1.2 1.2
~
..eco
.. \
~
~ ..
.:::'"
V
./
.:::'" 1.1 1.1
~ ~ /'
~
/
"'"
~
j
<.>
<.>
1.0
"""'-
-- j
<.>
<.>
]'"
1.0
/'
]'" .....
.,.,
0.9 0.9
..,..,'" ..,..,'"
...: ...:
0.8 0.8
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta ('G)

60 60
...:
...: ~
~
50
V <.l
50
~
-.
<.>
~
-..'"
c
40 ./
V '"
..,"
c
40
..........
~
il
.E:> ,/
V .E:>
Co
.," Co ~
~
..
..'..'""
:f
...:
30
.'..'co""
...:
OIl 30
"
20
4.0 4.5 5.0 5.5 6.0 20 0 25 50 75 100
Supply voltage Vee (V) Ambient.temperature Ta (,C)
2.5 2.5
?::
2.0 2.0
..J
> :c
:5
;;.-
1.5 VII!:-- > 1.5
.'"
OIl
~ VlH
VIL
.±:
.
0 VIL
~
:; 1.0
Co
i 1.0
.E .E
0.5
4.0 4.5 5.0 5.5 6.0 25 50 75 100
683
--------_....... .. ....- ..................- -
CMOS 4096""Bit Static Random Access Memory:'
.- .-
- LH5114-4
CMOS 4096. . Bit Static Random Access

LH5114-4 Memory .'
. \

The LH5114-4 is a fully static RAM organized
as 1024-word-by-4-bit by using silicon-gate
CMOS process technology.
o
• Features
7. Data can be held on + 2V supply voltage
8. Supply current at standby mode 10 ~A
(MAX.) on + 2V supply voltage Top View
• Block Diagram
Memory Array
32 Rows
128 Columns
Chip Select Input ~ ....--..

'fY=)
Write Input lO~-+~_~f---------rHH-t-----'
~----------------~~~~~~--------~
'----v--'
Address Input
684
CMOS 4096-Bit Static Random Access Memory LH5114-4

Output voltage * VOUT -0.3-V ee +0.3 V
V1L -0.3 0.65 V
Input voltage
VIH 2.2 Vee V
Operating temperature Toor 0 70 "C
• DC Characteristics (V ee =5V±10%, Ta=0-+70"C)

Output high voltage VOH IoH =-lmA 2.4 V
Input leakage current I ILl I V1N=OV or Vee 1.0 pA
Output leakage current I lLO I CSS;:V IH • VIIO =O.4V or Vee 1.0 pA
Current consumption Icc CS;;;;;0.65V. VIN=Vee=5.5V 6 15 rnA
IeeL CS;;;;;Vee,O;;;;;VIN;;;;;Vee 100 pA
consumption
• AC Characteristics (V ee =5V±10%, Ta=0-+70"C)
Parameter t Symbol t MIN. t TYP. t MAX. t Unit

Read cycle
Cycle time t Re 450 ns
Access time tAee 450 ns
Chip enable time teo 500 ns
Chip turn·off time tOF 150 ns
Write cycle
Cycle time twe 450 ns
Chip select time lew 400 ns
Chip select hold time teH 20 ns

• Input voltage amplitude ........................................... +0.65- +2.2V
• Input rising/falling time .......................................... IOns
• Timing reference level .......... · ................................. 1.5V
• Output load condition· ............................................ 1TTL + 100pF
.---.-~.---SHARP.-----.---
685
• Low-Voltage Data Hold Characteristics

Supply voltage for data hold VCC(PD) 2.0 V
- 2.2V~VCC(PD ~Vcc 2.2 V
CS voltage for data hold VCC(CS)
2.0V~VcgpQt~2.2V VCCPD V
Supply current for data hold Icc PD VIN=Vcc=2.0V 0.5 10 pA
Chip turn-off time ts,PD) tRC ns
Operation recovery time tRPD tRc ns
• Capacitance
Output capacitance CliO VIIO=OV 35 pF
• Timing Diagram
(1) Read cycle
CS
1/01-1/0.
(Data output)
(2) Write cycle
twc
tcw tCH
cs \ \ \ '\ -J- / / / / / /
tAW tWR_
twp
WE tAS ~ \ 'k.
«E
tDW "I .. tDH~
1/01-1/0. I
(D ata input)
Fixed data »
5V
VCC(PD)
OV
• Electrical Characteristics Curves (Vcc=5V. Ta=25"C unless otherwise specified)

1.4 1.4
Ta=70'C Vee =4.5 V
~
.
..3
>
.,/'
.~ 1.2
-............
]
~
III ./
tl 1.0 r---........ ~ 1.0
./
~
-............ V
.§
III
.,
:; 0.8 "- .5
III
:; 0.8
.,.,
~
..:" ..:""
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Average supply' current vs. Average supply current vs. ambient

supply voltage temperature
20 20
..:
.5
tl 15 u 15
...... ~
~...
e 10
".,...... 10
""
~
1
-- --- ..,. r----- r--
~
---
8:
.,
;, 5 .," 5
...
III ... r--
> >
..: ..:
o
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambi~nt temperature Ta eC)
2.0.----,-----r---...,----, 2.0
G
G r---
=
:>
1.5
= 1.5 ....
:>
Vw
VIL -
::
:>
::
:>
., -
...
III
1.0
~
.:::0
1.0
1> >
"S
I 0.5 .s"'" 0.5
o~--~-~~--~--~
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
---.-----SHARP-...-.------~
687
................ -.....
CMOS'4096-Bit Static Random Access Memory
~.-~...., ........... ................-....,.....
.-'
" "'LH5104-4
LH5104-4 CMOS 4096-Bit Static Random Access

Memory "
,• Description • Pin Connections

The LH5104-4 is a fully static ~AM organized
as 4,096-word-by-l-bit by using silicon-gate
CMOS process technology.
o
• Features
1. 4,096-word-by-l-bit organization
3. Fully static operation (no refresh or clock reo
quired)
4. All inputs and outpu~s TTL compatible
7. Data can be held on + 2V supply voltage
8. Supply current at standby mode 10 pA on Top View
+ 2V supply voltage (MAX.)
9. l8-pin duai-in-line package
• Block Diagram
Row
Address
Decoders
Data Input 1ll}--i-----1----:~-11>-------1 l---i>-----i.7 Data Output
Chip Select Input 10!}--;~---==:;J:J_ _ _.J
Write Input 8)....;~:±~J---------++-H-+++--...J
688
CMOS.4096-Bit Static Random Access Memory LH51 04-4

Input voltage * V IN 0.3 Vee+ 0.3 V
Output voltage * V OUT -0.3 Vee+ 0.3 V
Operating temperature TQI>r 0-+70 "C
Storage temperature T~ -55 +150 "C
• DC Characteristics (Vee =5V±10%, Ta=0-+70"C)

Output low voltage VOL IOL -3.2mA 004 V
Output high voltage VOH IOH - ImA 204 V
Input leakage current I ILl I VIN OV or Vee open 1.0 pA
Output leakage current I Iw I CS- VIH, VOUT OAV or Vee open 1.0 pA
CS- VIN , Output open
Current consumption Icc 7 15 rnA
VIN =V ee =5.5V
IeeL CS~Vee, VIN=OV or Vee 50 pA
consumption
(1) Read cycle (V ee =5V±10%, Ta=0-+70·C)

Cycle time t Re 450 ns
Acc·ess time t Aee 450 ns
Chip enable time 1 teo 450 ns
Data hold time from address taH 30 ns·
Chip turn-off time tOF 120 ns
Output enable time ta~ 20 ns
(2) Write cycle (V ee =5V±10%, Ta=0-+70"C)

Cycle time twe 450 ns
Chip select time tew 320 ns
Output disable setup time twz 110 ns
Output enable setup time tow 0 ns

• Input voltage amplitude··················· ........................ + 0.65 - + 2.2V
• Timing reference level· .......................................... ·1.5V
• Output load condition ................. ····························1 TTL+ 100pF
.-.-----~--.....-.--SHARP .-.~--.--.-.--
689
CMOS 4096.;.Bit Static Random Access Memory LH51 04-4
Parameter Symbol. Conditions MIN. TYP. MAX. Unit

Input capacitance CIN YIN=OY 6 pF
Output capacita~ce COUT YOUT=OY 15 pF
• Low-Voltage Data Hold Characteristics (Ta=0-+70·C)

Supply voltage for data holding YCCPD 2.0 Y
- 2.2Y';;:YccPD ';;:Ycc 2.2
CS v:oltage for data hold YI Y
2.0Y~YCC(PD)~2.2Y YCC(PD)
Supply current for data hold Icc PD YIN =Y cc =2.0Y 0.2 10 flA
Chip turn·off time tS(pD t RC ns
Operation recovery time tR PD) tRc ns
'-~-------SHARP~-----'----
690
CMOS 4096-Bit Static Random Access Memory LH51 04-4
• Timing Diagram
(1) Read cycle
tRC
\V "V
11\ 1\
tACC tOH
~
tc
cs \\\\ ~ ,'/////1///
tou tDF
DOUT
-
V L II
1\-"'.1'--
Valid data \ \"
/J
(2) Write cycle
fE-------twc:--------t
WE
DOUT
4.5V
VCC(PD)
OV _~C:.:::S:",-......J
691

.,.a 1.4
Ta=700e 1.4
Vee=4.5 V
... ~
... V
.=:'" /
1.2
~ 1.2
~
10
;;
Il:::
.!!l
'"
/'
/
Il:::
;;
($ 1.0
.~'"
Ul
Ul
'"
<""
0.8
"" -............
~
;;
u
u
.~'"
Ul
Ul
"'"
<"
1.0
0.8
/ ,
0.6 0.6
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta (Oe)
Average supply current vs. supply Average supply current vs. ambient
voltage temperature
20 20
< <
3 3
u 15 u 15
......u ......u
C .,
C
...
..'"
1
""
.'."
Ul
10
5 .- ------ ----
,
~ i
""
.'".."
Ul
10
5
r--
---- ~~
..
<'" <
..'"
o
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta (Oe)
Input voltage vs. supply voltage Input voltage .vs. ambient temperature
2.0
---
2.0
---
--- --- -
G G
~
--
-
1.5 ... 1.5
... VIH
> 'ill.
>
>
.. ~
~
>
.. ~L
...'" 1.0
!
..'" 1.0
..
~ ..
'0
i 0.5
1 0.5
..s
o
4.0 4.5 5.0 5.5 0.0 0 25 50 75 100
-----~--~----SHARP.-.-.--.-----
692
CMOS 16384-Bit Static Random Access Memory LH5116-15/LH5116-20
LH5116-15/LH5116-20

The LH5116-15/LH5116-20 are fully static
RAMs organized as 2,04S-word-by-S-bit by using
silicon-gate CMOS process technology_
o
• Features
L 2,04S-word-by-S-bit organization
2_ Single +5V power supply
3_ Fully static operation
LH5116-15: 150ns, LH5116-20 : 200ns
7. Supply current at standby mode 10 pA
(MAX.) on + 2V supply voltage Top View
S. 24-pin- dual-in-line package
• Block Diagram
~VCC
Memory- Array
128 Rows
~GND
128 Columns
Column
Address Buffers
Write In put,$l }-
Chip Select 18~-t--tL:::8:=:::::
Output Enable 20 1 )}-----+-11-+--+--------'
L---~====~~--------~~r-----------------------~
Address Input
693

Input voltage * VIN -0.3-Vcc +0.3 V
Operating temperature T OPT 0-+70 'C
Storage temperature T stg -55-+150 'C
*The maximum applicahle voltage on any pin with respect to GND.
• DC Characteristics (Vcc=5V±10%. Ta=0-+70'C)

Input high voltage VlH 2.2 Vcc+ 0.3 V
Input leakage current I ILl I VIN=OV. Vcc 1.0 pA
Output leakage current I ILO I CS=V lH• Vl/o=OV-Vcc 1.0 pA
ICCI Il/o=OmA (OE=Vccl 15 30 rnA 1
Current consumption
Icc2 Il/o=OmA (OE=V lH ) 25 40 rnA 2
Current consumption CS=V cc. all other input pins=
ICCL 10 pA
during standby OV-Vcc
Notel: CS=OV; all other input pins=Vcc
Note 2: CS=VIL; all other input pins=VIH
(1) Read cycle . (Vcc=5V±10%. Ta=0-+70'C)
LH5116-15 LH5116-20
Chip enable time teE 150 200 ns
Chip select time tcs 15 20 ns
Output enable time tOE 75 100 ns
Output select time tos 15 20 ns
Output turn-off time (from CE 2) tOFl 0 40 0 60 ns
Output turn-off time (from CEll tOF2 0 40 0 60 ns
(2) Write cycle (Vcc =5V±10%. Ta=0-70'C)
LH5117-15 LH5117-20
Chip select time tcw 110 135 ns
Access time ' tAw 110 135 ns
Address setup time tAs 0 5 as
Output turn-off time (from OE) tOFl 40 60 ns
Data setup time tow 70 80 . ns
Output turn-off hold time
tow 15 20 ns
(from WE)
Output turn-off time (from OE) tOF2 40 60 ns
--~-'---~--SHARP ---.-.-----------
694
CMOS 16384-Bit Static Random Access Memory LHS116-1S/LHS116-20

• Input voltage amplitude ........................................... +0.8- + 2.2V
• Input signal rise/fall time ................ ························10ns
• Time measurement level ····································· .... ·1.5V
• Output load condition ............................................. 1TTL + 100pF
• Low Supply Voltage Data Hold Characteristics: (Vee =5V±10%, Ta=0-70'C)

Data hold supply
VeeDR VCs"=Vee, VIN=OV or Vee 2.0 V
voltage
Data hold supply Vee=Ves=2.0V,
IecDR 10 pA
current VIN=OV or Vee
CS setup time tSDR t Re ns
CS hold time tRDR tRe ns
• Capacitance (f=lMHz, Ta=25'C)
Parameter Symbol ~
Conditions MIN. TYP. MAX. Unit
Input! output capacitance CliO VlIO=OV 8 pF
• Timing Diagram
(1) Read cycle
----tRc-----ti--...j
~:::::::-t-Ac-C~~--~--~---~.-,~~-tO-H-----------
1------tCE----~"'"
cs
I/O}-I/Os
~--.------SHARP.-----~.-.-~.---
695
(2)
.....
CMOS.16384-Bit Static Random Access Memory
~ ~.-~~.-~
Write cycle (Note 3)

.-~ .... LH5116-15/LH5116-20
---.-~
~-----------twc----------~
Ao-AIO
1--------tAW -------+-~;o.j
cs
Note 3:· WE must be high when there is a change in Ao-Alo.

Note 4: When CS and WE are alLlow at the same time, write occurs during the. period twP.
Note 5: tWR is the time from the rise of CS or WE, whichever is first, to the end of the write cycle.
Note 6: During this period the input/output pin is in an output condition, so input with a phase reversed from
that of the output is not permitted.
Note 7: If CS should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8: OE is maintained at "L" level.
Note 9: DOUT outputs data with the same phase as the input data of this write cycle.
Note 10 : If CS is low during this period, the input/output pin is in the output condition. During this condition, a
data input signal with a phase opposite that of the output is not permitted.
(3) Low supply voltage data hold
~-----;;+<------- Data hold time -----~ofE_=:.::...~
5.0V
4.5V
VIH
VCCDR
VIL
GND --------------------------------
696
• Electrical Characteristics .Curves (Vcc=5V, Ta=25"C unless otherwise specified)

.,.e 1.2
.,.e 1.2
...,. ..
.,..
~
.~
1;;
Ql
u
1.1
1.0
""~ .~
~
Il::
u
u 1.0
1.1
/
V
./
~ ........... ~
u .j
.j
., .,
.! .!
0.9 0.9
.,
C/l
C/l .,
C/l
C/l
..:"" ..:""
0.8 0.8
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Average supply current 1 vs. Average supply current 1 vs.

25 25
..: ..:
-! -!
~
20 u 20
.;:;
-- ---
u
......u /'
-.,"" / .,
C
"
"" 15
"" 15
i
"
/ b"
is:
r-- t---
".,
...,.
C/l
10
,/
.'..""
"
C/l
10
.." ..
..:'"
..:
5
4.0 4.5' 5.0 5.5 6.0 25 50 75 100
Input voltage vs. supply voltage Input voltage vs. ambien! temperature
2.5 2.5
2: 2:
2.0 2.0
>" >".,
>= ~ >
.,OIl
.
.::
0
..
$-=
1.5
1.0
--- ~
~
-
VIL
'"~
.::0
..
$-=
1.5
1.0
VlH
VIL
0.5 0.5
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta (·C)
--------SHARP-~-.-----
697
. .-..-......,.....,.-.~ .........,.........,.....,.....,-
CMOS 16384-Bit Static Random Access Memory LH5117 .:.15/LH5117-20
-.....,,.....,
LH5117-15/LH5117-20
CMOS 16384-Bit Static Random Access rtlemory
• Description , • Pin Connections

The LH5117-15/LH5117-20 are f.ully static
RAMs organized as 2,048-word-by-8-bit by us-
o
• Features
LH5117-15: 150ns, LH5117-20: 200ns
7. Supply current at standby mode 10 pA (MAX.)
on + 2V supply voltage Top View
• Block Diagram
--lvcc
Memory Array
128 Rows
~GND
128 Columns
.~~______~~~r-~---------~,~
:ro r---, ~
¥s -ui L---->. Sense Amp. . L-k
.5il~~
~
Data I/O ~ I ~ hIII ~I>-+-+-f-h
~ ! Column Decoders
'is O r : :::::---->-+-I+t+h
f t
'-r-t ~
Column
Address Buffers
::::---
Write Input~ 'y-

Chip Enable {~r-jH~=8;:::::~)}-____-+--+--l_+-______--'
L--=====::::.-_.....:..__ --{4
~
5 6 .7~}----------------l
Address Input
698

Supply voltage Vcc -0.3-+7.0 V
Input voltage VIN -0.3-V cc +0.3 V
Operating temperature ToDr 0-+70 "C
• DC Characteristics (V cc =5V±10%. Ta=0-+70"C)

Output low voltage VOL ICL=2.1mA 0.4 V
Output leakage current I Iw I CS2=V IH • VIIO=OV-Vcc 1.0 pA
Iccl IIIo=OmA (CEl=Vcd 15 30' rnA 1
Current consumption
Icc2 IIIo=OmA (CE I =V IH ) 25 40 rnA 2
Current consumption CE 2=V cc. all other input
ICCL 10 pA
during standby pins=OV-Vcc
Notel: CE2=QV; all other input pins=Vcc
Note 2: CE2=VIL; all other input pins=VIH
(1) Read cycle (Vcc=5V±10%. Ta=0-+70"C)
LH5117-15 LH5117-20
Cycle time tRC 150 200 ns
Chip enable time tCE 150 200 ns
Chip select time tcs 15 20 ns
Output turn·off time (from CE 2) tDFl 0 40 0 60 ns
Output turn·off time (from CEll tDF2 0 40 0 60 ns
Data hold time toH 15 20 ns
(2) Write cycle (Vcc =5V±10%. Ta=0-70"C)
LH5117-15 LH5117-20
Chip select time tcw 110 135 ' ns
Address setup time tAS 0 5 ns
Output turn-off time (from WE) tDF 40 60 ns
Data setup time tDW 70 80 ns
Output turn-off hold time
tow 15 20 ns
(from WE)
---~"""-'--'-'--SHARP ------.-.----.-.
699
CMOS 16384-Bit Static Random Acce~s Memory LH5H7-15/LH5117;.20

• Input voltage frequency width .: ............................... + 0.8 - + 2.2V
• . Input signal rise/fall time .··············,··················10ns
• Time measurement level ·························:·······1.5V
• Output load conditions ······· .. ·····················:··1 TTL+ 100pF
• . Low Supply Voltage Da~a Hold Characteristics (Vcc =5V±10%. Ta=0-70"C)
Parameter" Symbol Conditions MIN. TYP. MAX. Unit

Data hold' supply voltage VCCDR V~E2=VCC. VIN=OV or Vcc 2.0 V
VCC=VCE2=2.0V. pA
Data hold supply voltage IccDR 10
VIN=OV or Vcc
CS setup time tSDR t RC ns
CS hold time tRDR t RC ns
• Capacitance (f=1MHz. Ta=25"C)

Input capacitan<;e CIN VIN=OV 5 pF
Input! output capacitance CliO VlIO=OV 8 pF
• Timing Diagram
(l) Readicycle
1-------tRC-----~~
~:= =-=-=-=- t-AC-C-=-=- =- =- =- =- . . .;-~;!-ci-tO-H-----

~----tCE----_3>oj
CE2
-.----------,-SHARP----.---~~.---
700
(2) Write cycle (Note 3)/
~----------twc----------~~
~---------tAW--------~~~
14--+--- tcw (Note 7) --------;~
Note 3 : WE must be high when there is a change in Ao-AlO.

Note 4 : When CE2, CEI, and WE are all low at the same time, write occurs during the period twP.
Note 5 : tWR is the time from the rise of CE2 and CEI or WE, whichever is first, to the end of the write cycle.
Note 6 : During this period the input/output pin is in an output condition, so input with a phase reversed from that of
the output is not permitted.
Note 7 : If CE2 or CEI should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8 : Dour outputs data with the same phase as the input data of this write cycle.
Note 9 : If both CEI and CE2 are low during this period, the input/output pin is in the output condition.
5.0V
4.5V
VIH
VCCDR
VIL
GND --------------------------------
-----------SHARP----.-.-.-----
701
OMOS 16384-Bit Static Random Access Memory LH5117-15/LH5117-20
• Electrical Characteristics Curves (Vcc=5V, Ta=25°C unless otherwise sp~ified)

Access time vs. supply voltage Access time vs ..ambient temperature
., 1.2
., 1.2
.,.
..e
,...
..e
V
.:=
III
1.1 ... III
.:= 1.1 ./
]
III
"~ ~ V
~ ~
/
..<.l
<.l
<
1.0 <.l
<.l
:!
1.0
/'
]
III
.,.,
III
0.9
I'" ~
.,
.!j
.,.,
III
0.9
<"" <""
0.8 0.8
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta C'C)

25 25
< <
-.§. -.§.
<.l 20 <.l 20
....<.l ....
...'"
<.l
- --
/
i..
.... ~ ...
III
--
15 15
b" ~ b"
...,g; ~ .,~
r----
"...,
..,.g:,
III
10
...'",.
III
III
10
< <
5
4.0 4.5 5.0 5.5 6.0 25 50 75 100
Supply voltage Vee CV) Ambient temperature Ta C'C)
2.5,-----r----.,---,----...., 2.5
~ ~
:::l 2 . 0 1 - - - - t - - - + - - - + - - _ j :::l 2.0
:> :>
:> = VIH
III 1.51----t---+--==;;;;;;o-+~=-_j
.:::
~
~
11.01---+---+----+-----j
- -VIH
r-VIL
0.5 L-_ _I-_--:-I-_--:-I.:-_~

4.0 4.5 5.0 5.5 6.0 25 50 75 100
Supply voltage V cc (V) Ambient temperature Ta C'C)
702
LH5118-15/LH5118-20
CMOS 16384-Bit Static Random Access Memory .
The LH5118-15/LH5118-20 are fully static
RAMs organized as 2,048-word-by-8-bit by us-
o
• Features
1. 2,048-word -by- 8- bit organization
LH5118-15: 150ns, LH5118-20: 200ns
7. Supply current at standby mode 10 pA (MAX.)
on + 2V supply voltage Top View
• Block Diagram
Memory Array
128 Rows
128 Columns
"0
!::c
Data I/O o
U
L~===~::!.:"'::"'::::'::'-_-<4 5 6 7 } - - - - - - - -_ _ _ _....I
\ Addresvs Input J
~.-.-------SHARP--.------
703
CMOS:16384..;Bit Static Random Access Memory lH5H8-15/LH5118-20
• Abs.olute Maximum Ratings

Parameter Symbol Ratil).gs Unit
Supply voltage Vcc -0.3-:-+7.0 V
Input voltage VIN -0.3-Vcc +0.3 V
• DC Characteristics (Vcc=5V± 10%. Ta=O- +70"C)

Input low voltage V1L -0.3 O.B V
Output low voltage VOL ICL=2.1mA 0.4 V
Input leakage current I ILl 1 VJN=OV-Vcc 1.0 pA
CE 2=V IH or CE I =V IH •
Output leakage current I Iw I Vl/O=OV-Vcc
1.0 pA
ICCI Il/o=OmA (WE=Vccl 15 30 rnA 1

Current consumption
Icc2 Il/o=OmA (WE=V1Ll 25 40 rnA 2
Current consumption CE 2 and CE I = Vcc. all other
IccL 10 pA
during standby input pins=OV-Vcc
Note 1: CE2=CEl=OV; all other pins=Vcc
Note 2: CE2=CEl=VIL; all other pins=VIH
(1) Read cycle (Vcc =5V±10%. Ta=0-+70"C)
LH511B-15 LH511B-20
Access time tACC 150 200 ns
Chip enable time tCE 150 200 ns
Chip select time tcs 15 20 'ns
Output turn-off time (from CE 2) tOFl 0 40 0 60 ns
Output turn-off time (from CEll tOF2 6 40 . 0 60 ns
Data hold time(from address) tOH 15 20 ns
(2) Write cycle (V cc= 5V± 10%. Ta=0-70"C)
LH511B-15 LH511B-20
MIN. TYP. MAX. MIN. TYP. ,MAX.
Chip select time tcw 110 135 ns
Address setup time tAS 0 5 ns
Output turn-off time (from WE) t 40 60 ns
. Data setup time tow 70 BO ns
Output turn-off hold
tow 15 20 ns
time (froni WE)
704

• Input voltage amplitude········ .. ································· +O.8-+2.2V
• Input signal rise/fall time .. ········· ·····························10ns
• Time measurement level· .. ·······································1.5V
• Output load condition············································· 1TTL + 100pF
• Low Supply Voltage Data Hold Characteristics (V ee =5V±10%. Ta=0-70"C)
Data hold supply voltage VeeDR Vcrz=Vee• VIN=OV or Vee Z.O V
Vec=VeE2=Z.OV.
Data hold supply current IeeDR 10 p.A
VIN=OV or Vee
CS setup time tSDR tRe ns
CS hold time tRDR t Re ns
• Capacitance (f=lMHz. Ta=Z5"C)
Parameter Symbol Conditions MIN. . TYP. MAX. Unit

Input capacitance C IN VIN=OV 5 pF
Input/output capacitance CliO VIIO=OV 8 pF
• Timing Diagram
(1) Read cycle
t-----tRc----\k--l
~=-=- =- =- =- :. .-t-A-C - - - - - - - -l>.-I.......;{f-tO-H-----

o!
A.-AI.
iE------tCE----~
iE----tcs-----i ~_r±_----r_~~
1/01-1/0.
705
/
CMOS 16384-Btt Static Random Access Memory LH5118-15/LH5118-20'
(2) Write cycle (Note 3)
~------------twe----------~~
Note 3 : WE must be high when there is a change in AD-AID.

Note 4 : When CE2, CEI, and WE are all low at the same time, write occurs during the period twP.
Note 5 : tWR is the time from the rise of CE2 and CEI or WE, whichever is first, to the end of the write cycle.
Note 6 : During this period, the input/output pin is in an output condition, so input with a phase reversed from that of
the output is not permitted.
Note 7 : If CE2 or CEI should drop at the same time as WE or later, the output buffer is maintained at high impedance.
Note 8 : DOUT outputs data with the same phase as the input data of this write cycle.
Note 9 : If both CEI and CE2 are low during this period, the input/output pin is in the output condition. During
this condition, a data input signal with a phase opposite that of the output is not permitted.
5.0V
4.5V
VlH
Vee DR
VIL
GND
'--~-~'-----SHARP"-""--'-'--~---
706
• Electrical Characteristics Curves (Vcc=5V, Ta=,25°C unless otherwise specified)
.,..e 1.2
.,..e 1.2
V
...,. ..
.,..
.
.~ 1.1 "- .~ 1.1 L
.,
..!S /'
V
Ql
""
P::: P:::
u 1.0 u 1.0
u u
~ ,/
j j
., .,
]
.,.,
.,
..:""
0.9
"" ]
.,.,
.,
..:""
0.9
0.8 0.8
4.0 4.5 5.0 5.5 6.0 o 25 5Q 75 100

25 25
..: ..:
5 5
G 20 G 20
V
-- --
..:i ..:i
.,
C
.. 15
v C.,.
. 15 '""'"
r--- r--
"
.Q
os
/'
V os
"
.Q
.,""os""
§:
.,os
.,
.,..""
10
..".. 10
..:
.
..:"
5 5
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
2.5 2.0
C
C 2.0 1.5
... ;;-
'" VlH
:>
==
-
--- -
VlH ;;-== VIL
-- ----
;;- 1.5 1.0
"~
"~ .::co
~ ..
VIL
..
:; 0.5
1.0
ic
""
......c
......
0.5
4.0 4.5 5.0 5.5 6.0 0 25 50 75 100
Supply voltage Vee (V) Ambient temperature Ta (·e)
707
NMOS6.5536-Bit Dynamic Random Access Memory LH21.64-15/LH2164-20
LH2164-15/LH2164-20
NMOS 65536-Bit Dynamic Random Access Memory
The LH2164 is a dynamic RAM organized as
65,536-word-by-1-bit by using high-performance
depletion load, n-channel double-poly silicon-gate
MOS technology.
o
• Features
LH2164-15: 150ns, LH2164-20 : 200ns
3. Cycle time (MIN.)
LH2164-15: 270ns, LH2164-20 : 330ns
4. Power supply: +5V±10%
5. Power dissipation (MAX.) : 248mW(operation)
: 28mW(standby)
6. All inputs and outputs TTL compatible Top View
7. Address and input date latch capability. __
8. Three-state outputs date controlled by CAS
and not latched at the end of cycle
9. Common 110 capability using the early-write
mode
10. Read/modify/write, page-mode, RAS-only re-
fresh, and hidden ~efresh capabilities
11. Built-in gated CAS function
12. Built-in biasing-voltage generator circuit for
high-output board
13. 2 ms refresh period, 128 cycle refresh
------.-~-~---SHA~P-.-- ....... - . . . . - . . - -
708
NMOS 65536-Bit Dynamic Random Access Memory LH2164-15/LH2164-20
• Block Diagram
;;., ;;., ;;.,

......os ......os os
;;.,
......os .,
" .,... ......
''""
''""
<I)
'9""0 ''""
<I) <I) ...
" .,
<I)
..: ..: ..:

'" '" '" 9""0 ..:
''""
Cflc.
I 9
;:g..:
W
u
-o" 0""
uo
W
u
Cflc. Cflc.
I 9 I 9
;:g..: ;:g..: W
u
-"
"
uo"
o
0
W
u
Cflo.
I 9
;:g..:
Row Row
Address Input
Decoder
;;., ;;., ;;., ;;.,
os os
'"
<I)
......'" ... ...... '"
<I)
'"
<I) ......os ... ...... ''""
<I)
..:
"'"
Cflo.
..: '" "
9""0 ..:
"'"
[flo. [flo."'" ..: '"
9""0 '" '"
[flo.
I 9
;:g..: W -"
" 0
o '"
uo
W
u
I 9 I 9
;:g..:
W -"
" 0
0''''
uo
W
u
I 9
;:g..:
u ;:g..: u
Data Bus Selecter
Write Clock
Data In Buffers
Data Out
Column Address 15,}--------~ Buffers 14 Data Output
Strobe
Biasing-voltage Generator
Circuit For High-output
Board

Output voltage VOUT -1.0-+7.0 V 1
Supply voltage Vee -1.0-+7.0 V 1
Output short·circuit current los 50 rnA
Current consumption PD 1.0 W
Operating temperature Tooe 0-+70 °C
Notel: Referenced to Vss.
• Recommended Operating Conditions (Ta=0-+70°C)

Vee 4.5 5.0 5.5
Supply voltage V 2
Vss 0 0 0
VIH 2.4 6.5
Input voltage V 2
V ,L -2.0 0.8
Note 2: Referenced to Vss.
---------SHARP---------
709
NMOS 65536-Bit Dynamic Random . Access Memory \
LH2164,.15ILH2164-20
......,......,......,......,......,......,~ -......,......,......,......,.....,......,.....,......,

Average supply current RAS, CAS=cyciing
ICCI 46 rnA 3,4
during normal operation tRc=MIN.
Average supp!y current in ----
Icc2 RAS, CAS=VIH 5 rnA 3
standby mode
Average'supply current RAS=cycling, CAS.=V IH
IcC3 35 rnA 3,4
during RAS only refresh tRc=MIN.
Average supply current RAS=V IH, CAS = cycling
lcc4 35 rnA 3,4
in page mode tpc=MIN.
OV~VIN~6.5V
Input leakage current I IlL I Pins other than that 10 pA 3,4
being measured are OV
Output leakage current I IOL I OV~VouT~6.5V 10 pA 3
Output high voltage VOH IouT =-5mA 2.4 V
Output low voltage VOL IouT =4.2mA 0.4 V
Note 3: Output pin in high impedance state
Note 4: iccJ, icc3, and icC4 depend on cycle time.
• AC Characteristics (Note 5, 6, 7) (V cc =5.0V±10%, Ta=0-+70"C)
LH2164-15 LH2164-20
Parameter Symbol Unit Note
MIN. MAX. MIN. MAX.
RAS cycle time tRc 270 330 ns
Read/write cycle time t RwC 300 375 ns
Page mode cycle time tpc 170 225 ns
Access time from RAS t RAC 150 200 ns 8,10
Access time from CAS teAC 100 135 ns 9,10
Output turn off delay tOFF 0 40 0 50 ns
Rise/ fall time tT 3 35 3 50 ' ns 7
RAS precharge time t RP 100 120 ns
RAS pulse width t RAS 150 10,000 200 10,000 ns
RAS hold time t RSH 100 135 ns
CAS precharge time tep 60 80 ns
CAS pulse width (page mode) teAS 100 10,000 135 10,000 ns
CAS hold time teSH 150 200 ns
RAS/CAS delay t RCD 25 50 30 65 ns 11,12
CAS/RAS precharge time t CRP 0 0 ns
Row address setup time tASR 0 0 ns
Row address hold time tRAH 20 25 ns
Column address setup time tASC 0 0 ns
Column address hold time tCAH 45 55 ns
Column address
tAR 95 120 ns
hold time from RAS
Read command setup time t RCS 0 0 ns
Read command hold time, tRCH 0 0 ns 15
Write cOmmand setup time twcs -10 -10 ns 14
W rite command hold time t WCH 45 55 ns
Write command hold
t WCR 95 120 ns
time from RAS
Write command pulse width twp 45 55 ns
Write command/RAS read time t RWL 60 80 ns
Write command/CAS read time teWL 60 80 ns
Data input setup time tDS 0 0 ns 13
Data input hold time tDH 45 55 ns 13
710
LH2164-15 LH2164-20
MIN. MAX. MIN. MAX.
Data input hold time from RAS tDHR 95 120 ns
CAS/write command delay tCWD 70 95 ns 14
RAS/write command delay t RWD 120 160 ns 14
Read command hold
-- tRRH 20 25 ns 15
time from RAS
CAS precharge time tcPN 25 30 ns
Refresh time tREF 2 2 ms
Note 5: For the memory to operate normally, a minimum pause of 500 p s after the power is turned on and then
several dummy cycles are necessary. Generally, eight normal refresh cycles should be performed.
Note 6: Measure AC characteristics when tT= 5 ns.
Note 7: The prescribed input reference levels for timing are VIHI"m) and VILlro,,). Transition time (tT) is the time
between VIH and VIL.
Note 8: When tRCD ;:;;; tRCD(m,,). When tRCD < tRCDlm"i, tRAC becomes large by (tRCD - tRCDlm,,)).
Note 9: When tRCD = tRCD(ro,,).
Note 10: Load condition for 2TTL+ 100pF.
Note 11: tRCDlm,,) is the largest value of tRCD that protects tRAqm,,) and is not an operation limit. If tRCD(ro..) ;:;;; tRCD,
the access time is controlled by tCAC.
Note 12: tRCDlm;.) = tRAHlmmi+2tT+tASClmm)
Note 13: The fall of CAS becomes the reference of tDS and tDH in the early write cycle and WE becomes the
reference in the read/write cycle and in the read/modify/write cycle.
Note 14: twcs, tCWD, and tRWD are not operation limits at the point the operation mode is prescribed. When twcs
;;;; tWCSlmm), the early write cycle begins and the DOUT pin becomes high impedance.
If tRWD ;;;; tRWDlmm) when tCWD ;;;; tCWD(mm), the read/write cycle begins and the output data becomes
information of the selector cell.
In the case of timing other than that above, output becomes indeterminate.
Note 15: Operation is guaranteed when either tRCH or tRRH is satisfied.
• Capacitance (V cc =5V±10%, f=IMHz, Ta=0-70"C)

Input capacitance CIN ! Ao-A 7 , DIN, WE
. 5 pF
Input capacitance C1N2 RAS, CAS 6 pF
Output capacitance COUT DOUT 8 pF
• Timing Diagram
(1) Read cycle
~---------------------tRC--------------------~
--------~~---------------tRAs--------------~~--------~
----~~-------tRsH--------~
---------++-------+""""\ 1E----tCAs----+j ~f-Ir---------""
~------------tRAC------------....,.,
High impedance
DoUT Valid data
------------------------SHARP·.-.-.------------
711
NMOS 65536-Bit Dynamic Random Acce.ss Memory . LH2164-H?ILH2164-20
(2) Write cycle (Early write)
tRC
tRAS
tCSH
tRSH rLtRP~ \
r--"tCRP-OO
-
f---tRCD-"------Oo
tCAS
\ \
f--tAR V / f-o--tCPN-I-
~ ~--.-t~SC~
=:::>{Row addres~.I.mn addrs. ~
-tWCR
tCWL
I !WC~ ~
\l-- twp /
tRWL
~-- -t'DH-
X Valid data
K
tDHR
High impedance
DOUT
(3) Read write and read modify write cycles
tRWC
~
tRAS
tAR
tCSH
1 tRP i'-
f-o---- t RCD---;---'" tRSH
tCAS
~
~tCPN~
\. \. /
tA~ ~ tASC teAH
J
.-1"4- t---
-~ow -t~X
addres!x' Column address K
~tCWL-
tCWD -tRWL-
;- -I
tRWD --twp-j
. k---tCAC-----<OO ~~'
. High impedance f",
DOUT Valid data ll\'\'\
'\W
tRAC
~~
XYalid data}(
712
(4) RAS only refresh cycle
~----------------tRC----------------~
IE-------t RP------~
High impedance
DOUT
Note: CAS=VlH
(5) Hidden refresh cycle
713
NMOS 65536-Bit Dyn~mic Random Access Memory LH2164,.1.p/LH2164-20
(6) Page mode read cycle
(7) Page mode write cycle
~------------------------tRAS------------------------~
714

1.3 ., 1.3
i Q)
.e:
] 1.2
Q)
~
u 1.1 r--....
!
Q)
.~
1.0
"~ !
Q)
~
..,..,
1.0
~
~
/
""
''""
Q)
Q)
g
-<
0.9
r-- -<
0.9
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Average supply current during page mode! Average supply current during page mode
vs. supply voltage vs. am~ient temperature
..e
50 ..
E
50r-----------~----~----~
.
"
e
=
.S 40
Ta=O'C
.
g
.S
Vcc=5.5V
40 1---,...----+---+-----1
.a" .g
~ ~
~ ~ ~ 30 t==t==:t===i===i
V-- ..E:>-<
~~
------ '~" .§
t~
20~--+----r--~----;
~ ~
10 100L-----2~5----~50~--~7~5----~100
4.0 4.5 5.0 5.5 6.0
Average supply current during standby Average supply current during standby
vs. supply voltage vs. ambient temperature
5 5r-----------~----~----~
.S
.. Ta=O'C Vcc=5.5V
.a..." 4 4r---..,.----r--~--~
---
""..,
"
....
;;.-<
~~
~~
~
3
2
r---
-
gj,$
---I---
3r-----+-----+-----~----~
2r---+----r--~--~
~-t-_-l
f 1 ~ "'g
~ .!! ~ .!!
-< '" -< '"
1 1~----~----~----~----~
4.0 4.5 5.0 5.5 6.0 .0 25 50 75 100
.--------SHARP------------
715
NMOS 65536-Bit Dynamic Random Access Memory LH2164;"15/LH2164~20 .
Average supply current during RAS only refresh Average supply current during RAS only
vs. supply voltage \ refresh vs. ambient temperature
40 40~----------~----~----~
Ta=O'e
I :::~ Vee=5.5V
.!f 30 ~--,--.-----+---/-----t
---- .g
-- ---- ~ i
'a
~
..."
~1
.t
~ ~
...
< b6
<"
Ei
~
201---+----+---/-----t
101---+----+---/-----t
o O~----~----~----~----~
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Supply voltage Vee (V) Ambient temp·erature Ta ('e)
Average supply current during page mode Average supply current during page mode
40 40
OIl
.e...
..g
Ta=O'e
.e
.
...g...
Vee=5.5V
30 301---.---+---~----~
i...
...
B<"
~,,~
b
~-.,
co
E! 20
...,... "".., 10
~ E!
:>
..:
0
.
~
~
---- ~
b" ..:E! 20 1 - - - + - - - - + - - - ; - - - ;
""~
~i
...~ E! 1 0 1 - - - + - - - - + - - - / - - - - - t
~ ~
""
o °O~----2~5----~50-,----~75~--~100
4.0 4.5 5.0 5.5 6.0
Supplyvoltage Vee (V) Ambient temperature Ta ('e)
716
NMOS 65536-Bit Dynamic Random Access Memory LH2164A-15/LH2164A-20
LH2164A-15/LH2164A-20

The LH2164A is a dynamic RAM organized as
65,536-word-by-1-bit by using high-performance
depletion load, n-channel double-poly silicon-gate
MOS technology.
• Features
LH2164A-15: 150ns, LH2164A-20 : 200ns
, LH2164A-15: 260ns, LH2164A-20 : 330ns
4. Power supply: +5V±10%
5. Power consumption (MAX.) : 248mW(operation)
: 28mW(standby) Top View
7. Address and input data latch capabili~
8. Three-state output data controlled by CAS and
not latched at the end of cycle
- mode
10. Read/modify/write, page-mode, RAS-only re-
fresh, and hidden refresh capabilities
11. Built-in gated CAS function
12. Built-in biasing-voltage generator circuit for
high-output board
13. 2 ms refresh period, 128 cycle refresh,
--------$HARP-.---------
717
- NMOS 65536-:-BitDynamic Random Access Memory LH2164A-15/LH2164A-20
• Block Diagram
<i>
. = fij "'
m
E""
-00
"
o "
"
0 Cfl""
I
~<
E
Ad<lress Input 1=====~Row Row

Decoder
>.
""'"
c
Cflp.
...
c "
E""
"......
< "'"
c
"
Cflp.
<i>
"'
m
Cfl",
I E -"
" 0 I E I E
~< o "
00 ~< ~<
Data Bus Selecter
Write Clock
} - - - + - - - - - - - - - - + - - 7 J Data In Buffers
Data Out
Buffers 14 Data Output
Biasing-voltage Generator'
Circuit For High-output
Board

Output voltage -,--_.,- VOUT -1.0-+7.0 V 1
Supply voltage Vee -1.0-+7.0 V 1
Output short-circuit current los 50 rnA
Current consumption PD 1.0 W
Operating temperature Tope 0-+70 ·C
Storage temperature T stg -55-+150 ·C
Notel: Referenced to Vss.
• Recommended Operating Conditions (Ta=0-+70·C)

Vee 4.5 5.0 5.5
Supply voltage V 2
Vss 0 0 0
VlH 2.4 6.5
Input voltage V 2
VIL -2.0 0.8
Note 2: Referenced to Vss .
.-.-......-.------SHARP.-----.---
718
• DC Characteristics (Vcc=5.0V± 10%, Ta=O- +70'C)

Average supply current RAS, CAS=cyciing
ICCl 45 rnA 3,4
during normal operation tRc=MIN.
Average supply current ----
Icc2 RAS, CAS=V lH 5 rnA 3
in standby mode
Average supply current RAS=cyciing, CAS=V lH
Icc3 35 rnA 3,4
during RAS only refresh tRc=MIN.
Average supply current in pagt RAS=V lH , CAS=cyciing
Icc4 35 rnA 3,4
mode tpc=MIN.
OV;;;;;V IN ;;;;;6.5V
Input leakage current I IlL I Pins other than that 10 pA 3,4
being measured are OV
Output leakage current IloL I OV;;;;;V ouT ;;;;;6.5V 10 pA 3
Output high voltage VOH IouT =-5mA 2.4 V
Output low voltage VOL IouT=4.2mA 0.4 V
Note 3: Output pin in high impedance state
Note 4: IcCl, Icc3, and Icc4 depend on cycle time.
• AC Characteristics (Note 5, 6, 7)
(V cc =5V±10%, Ta=0-+70'C)
LH2164A-15 LH2164A-20
MIN. MAX. MIN. MAX.
RAM cycle tiine tRc 260 330 ns
Read/write cycle time tRwc 285 350 ns
Page mode cycle time tpc 145 190 ns
Access time from RAS tRAC 150 200 ns 8,10
Access time from CAS t CAC 75 100 ns 9,10
Output turn off delay tOFF 0 40 0 50 ns
Risel fall time tT 3 35 3 50 ns 5
RAS precharge time t RP 100 120 n~
RAS pulse width tRAS 150 10,000 200 10,000 ns

RAS hold time t RSH 75 100 ns
CAS precharge time tcp 60 80 ns
CAS pulse width (page mode) teAS 75 10,000 100 10,000 ns
CAS hold time teSH 150 200 ns
RAS/CAS delay time t RCD 25 75 30 100 ns 11,12
CAS/RAS precharge time t CRP 0 0 ns
Row address setup time tASR 0 0 ns
Row address hold time tRAH 20 25 ns
Column address setup time tAsc 0 0 ns
Column address hold time teAH 45 55 ns
Column address hold
-- tAR 120 155 ns
time from RAS
Read command setup time tRcs 0 0 ns
Read command hold time tRCH 0 0 ns 15
Write command setup time twcs -5 -5 ns 14
Write command hold tim~ tWCH 45 55 ns
Write command hold
-- tWCR 120 155 ns
time from RAS
Write command pulse width twp 45 55 ns
Write command/RAS read time t RWL 45 55 ns
-------------SHARP.-.----------
719
NMOS 65536-Bit'Dynamic Random Access ~emory
LH2164A-15 LH2164A-20
Parameter· Symbol Unit Note
MIN. MAX. MlN. MAX.
Write command/CAS read time tcwL 45 55 ns
Data input setup time tos 0 0 ns 13
Data input hold time tOH 45 55 ns 13
Data input hold time from RAS tOHR 120 155 ns
Write command delay time
t ewo 50 60 ns 14
from CAS
Write command delay time
tRwO 125 160 ns 14
from RAS
Read command hold time
tRRH 20 25 ns 15
from RAS
CAS precharge time tePN 25 30 ns
Refresh time tREF 2 2 ms
Note 5: For the memory to operate normally, a minimum pause of 500 p. s after the power is turned on and
then several dummy cycles are necessary. Generally, eight normal refresh cycles should be per·
formed.
Note 6: Measure AC characteristics when tT= 5 ns.
Note 7: The prescribed input reference levels for timing are VlHlmm) and VILlm,,). Transition time (tT) is the time
between VIH and VIL.
Note 8: When tRCD;;>tRCDlm,,). When tRCD< tRCDlm,,), tRAC becomes large by (tRco-tRCDlm,,)).
Note 9: When tRCD=tRCDlm,,).
Note 10: Load condition for 2TTL + 100pF.
Note 11: tRCDlm,,) is the largest value of tRCD that protects tRAqm,,) and is not an operation limit. If tRCD(m,,);;>tRCD,
the access time is controlled by tCAC.
Note 12: tRCD(min)=tRAHlmm)+2tT+tASqmm).
Note 13: The fall of CAS becomes the reference of tDS and tDH in the early write cycle and WE becomes the
reference in the read/write cycle and in the read/modify/write cycle.
Note 14: twcs, tCWD, and tRWD are not operation limits at the point the operation mode is prescribed. When twcs
;:;;;tWCSlmm), the early write cycle begins and the Dour pin becomes high impedance.
If tRwD;:;;;tRWD(mm) when tCWD;:;;;tCWD(mm), the read/write cycle begins and the output data becomes in·
formation of the selector cell.
In the case of timing other than that above, output becomes indeterminate.
Note 15: Operation is guaranteed when either tRCH or tRRH is satisfied.
• Capacitance (Vee=5V± 10%,f= IMHz, Ta=O- +70"C)

Input capacitance CIN ! Ao -A 7 , DIN, WE 5 pF
Input capacitance CIN2 RAS, CAS 6 pF
Output capacitance COUT DOUT 8 pF
~---'--------~~SHARP - - - - - - - - - - - - - - - - -
720
• Timing Diagram
(1 ) Read cycle
tRC
tRAS
RAS
tRSH
tCAS
CAS
Ao-A?
WE
tRAC
DouT
High impedance
(2) Write cycle (Early write)
tRC
tRAS
fE----tRCD~
tCSH
tRSH rLtRP~ ~
I--tCRP--
tCAS
\ \ V
tAR- r- J I---tCPN---1-
--X
~~H tA!f
- ~
K X B
- Row address
-tWCR
Column addres
tCWL
I"twc~
'\14- twp ~/
tRWL
~f- -tDH~
X Valid data
K
tDHR
High impedance
DOUT
'-~---'-"'--SHARP----"---------
721
(3) Read/write and read/modify/write cycl~s
tRWC
tRAS
RAS
- tAR
tCSH t-tRP ....... ' - -

fE--tRCD
- tRSH
tCAS
V-
~
r-.. '
J I--tcPs-l'-
tf.!! ~ t~~ ~
-..
~w Addre~Column address K
t~
I--tqVL-
tCWD ~t'RWL---OO
WE I .i
tRWD --twp-.,.j
-tCAC ~~
DOUT
High impedance nn Valid data ~
~-\.- #U
tRAC
~~
X! J(
Vahd data
(4) RAS only refresh cycle
~--------------tRC--------------~
i------tRp·-----"'"
High impedance
DoUT
722
(5) Hidden refresh cycle
(6) Page mode read cycle
723
NMOS 65536-B.it Dynamic Random Access Memory· LH2164A-15/LH2164A-20
(7) Page mode write cycle
Ao-A7
DIN
• Electrical Characteristics Curves

1.3 1.3
".a...,
>
Ta=25'e ".a.,.
>
Vcc=5V
1.2 .:: 1.2

.:: -:;;
-:;; Qj
Qj
Il:: ~
I'-... u., 1.1
.,
u 1.1
"
!
!
., ., /
'E.,
.,.,
<""
1.0
0.9
4.0
'"
4.5
~
5.0
Supply voltage Vee
r--
5.5
(V)
6.0
:3III
III
"
«""
1.0
~
25
~
50 75
Ambient temperature Ta ('e)
100
Average supply current during normal Average supply current during normal
operation vs. supply voltage operation vs. ambient temperature
50 50
bO
.S
Ta=O'e ..
.S
...
Vcc=5.5V
... 40 ..a 40
..a
i< ffi<
... 8
..... ~ ... 8
8~
~
~
" 30 "
~.~ 30
b ..a" ~
~ ~ ~
..c._
c. ..
III.,...
.,bO-ll.
III .,bO- C.
0
..
.,...> ...8
0
20
.,...> 8...
lO ..
20
,
0
< "
0
< "
10
4.0 4.5 5.0 5.5 6.0 25 50 75 100
724
Average supply current during standby Average supply current during standby
5 5~--------~~----,-----~
Ta=O·C Vee=5.5V
.;...
.g 4
".,....
--- --
~
- - r---
.e>~
3
8:<
r-- '" 8
rn~
~E 2
f:--g
~ ~
< '"
1 1~----L-----~----~ ____~
4.0 4.5 5.0 5.5 6.0 o 25 50 75 100
Average supply current during RAS only Average supply current during RAS only
refresh vs. supply voltage refresh vs. ambient temperature
40 40~----------~----~----~
I~..,
CI)
< Ta=O·C Vec=5.5V
P:::
.~
. .
-------
30 .5 30
.g
.... ~ "''""
..Iii.
"'<
" 8
~
20
~
".'"
B< 20
.e>~ .e>3
""
""..= ""§"~
''"" '""
~~ . 10 .'" . 10
os ... ....
~"i1
<~~0 <
>-
§
o °o~--~L-----~----~----~
4.0 4.5 5.0 5.5 6.0 25 50 75 100
Average supply current during page mode Average supply current during page mode
vs. supply voltage ambient temperature
IVS.
40 40~----------,-----~----~
.., Ta=O·C .., Vee=5.5V

.5
.g
. 30
.
.5
.g 30
".." ".'"
---
'" <
,,~
... 20 '" <

<>~
... 20
-
~
~
-8:~
8 -8:~
8
'"'" "
,,"8
. ..,"
: 8 10
- '"''"" ""'0"
." ..,'"
: 8 10
<"
> os > ..
"" < ""
o 0
4.0 4.5 5.0 5.5 6.0 0 25 50 75 100
---.---------SHARP-~----------
725
NMOS 262144-Bit Dynaniic Random Access Memor:y LH2464/LH2465
I NEW I
LH2464/LH2465 NMOS 262144-Bit Dynamic
Random Access Memory

The LH2464/LH2465 .are dynamic RAMs organ-
ized as 65,536-word-by-4-bit by using high-
performance depletion load n-channel double-poly-
cide silicon-gate MOS technology.
• Features
1. 65,536-word by-4-bit organization
2. LH2464 : page-mode
LH2465 : nibble-mode
LH2464/5-10 : lOOns
LH2464/5-12: 12Dns
LH2464/5-15: 150ns
4. Single +5V power supply Top View
5. Power consumption (MAX.) :
467.5mW (operation)
27.5mW (stand-by)
6. CAS-before-RAS refresh capabilities
7. Built-in refresh counter
8. 4ms refresh period, 256 cycle refresh
9. 18-.pin dual-in-line package
726
NMOS 262144-Bit Dynamic Random Access Memory LH2464/LH2465
• Block Diagram
Clock
} - - - ; Generator
No.1 Clock
Generator 1----_-------3>-1
No.2
Column
A, Address
Buffer
A.
A5 Row
Address 2 I/O,
A6
Buffer 3 1/02
A7
1/03
I/O.
:><
~
.,...
~ "".,"
0
Memory
.,...
<Il
Q
Refresh
" Array
<Il
Address t:::
Counter
;<
~
""...:"" '"
0
p::
1 OE
V BB Generator
-.--------SHARP------------
727
NMOS 262144-Bit Dynamic Random Access Memory LH21256/lH21257/LH21258
LH'21256/LH21257/LH21258

The LH2i256/LH21257/LH21258 are dynamic
RAMs organized as 262,144-word-by-1-bit using
.high-performance depletion load n.-channel dou·
ble- polycide silicon-gate MOS technology.
• Features
2. LH21256 : page-mode
LH21257 : nibble-mode
J.,H21258 : byte-mode
LH21256/7/8-10: lOOns
LH21256/7/8-12: 120ns
Top View
LH21256/7 /8-15 : 150ns
LH21256/7/8-10 : 200ns
LH21256/7/8-12 : 230ns
LH21256/7/8-15 : 260ns
7. Address and input data latch capabili~
8. Three~state output data controlled by CAS and
not latched at the end of cycle
mode
10. Read/modify/write, RAS-only refresh hidden
refresh capabilites and CAS before RAS reo
fresh
1 L Built-in refresh counter
12. 4ms refresh period, 256 cycle refresh
7~8
·NMOS 262144-Bit Dynamic Random Access Memory LH21256/LH21257/LH21258
• Block Diagram
Clock
Generator
No.1 Clock
Generator 1 - - - - - - - - - - ,
No.2
Column
Address 1 - - - - - - - - - - - - - 1 \ ,
Buffer
Address
Input
Row
Address
Buffer
in
Buffer
Refresh
Address
Counter
729
LSls for Telephone
Tone Dialer CMOS LSI LR4087
LR4087 Tone Dialer CMOS LSI

. The LR4087 is a monolithic LSI and uses an in'
expensive crystal reference to provide eight audio
sinusoidal frequencies Dual-Tone MUlti-Frequency
is obtained by mixing these frequencies.
• Features
1. Low standby current
2. Auxiliary switching functions on chip
3. Minimum external parts count
4. Uses inexpensive 3.579545MHz television color-
burst crystal
5. Built-in regulator of dual or single tone ampli-
tudes
6. 16-pin dual-in-line Pilckage Top View
• Block Diagram
Row Input
~
VKB "Xl>-----{JIQ) Mute

Output
VDD
Oscilation ~81)-~--t""--,
Output
Oscilation Tone
Input '-!.F~-~-- Output
XMTR
Switch
GND L-===~_ _ _ _ _ _ --J>--__--(~ Single

Tone
~--~--a~~~H~------~6r-----------------------------~
Inhibit
GND
732
Tone Dialer CMOS LSI- LR4087

Supply voltage VDD 10.5 V 1
Operating temperature Toor 30-+60 t
Maximum power consumption PD 500 mW 2
I
VIN1 -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Note1: Referenced to GND.
Note 2: Ta=25t
Note 4: The maximum applicable voltage on any pin with respect to VDD.

Parameter Raiting Unit
• Electrical Characteristics (Ta=-30-+60t)

- VIH1 0.7VDD V DD V
STI input voltage 5
V1L1 0.0 0.3VDD V
VIH2 0.7VDD V DD V
COL input voltage 6
V1L2 0.0 0.1 VDD V
-- V1H3 0.9VDD V DD V
ROW input voltage 7
V1L3 0.0 0.3VDD V
Output voltage
I ROW TONE VOK
RL =lk.o
317 400 504 mV rms
S
I COL TONE Voc 396 500 630 mV rms
RLl VDD=3.5V 620 .0
TONE output resistance
RL2 V DD =10.0V 330 .0
XMTR output current, IoHx1 V DD =3.5V, VOHx=2.5V -15 -25 rnA
10
no key input IoHx2 V DD =10.0V, VOHX=S.OV -50 -100 rnA
XMTR output current,
IXLEAK VDD =10.0V, VOUT=OV 0.1 10.0 pA 10
in key input
MUTE output current, lOLl VDD =3.5V, VOL =0.5V 0.5 2.0 rnA
11
no key input IOL2 VDD=lO.OV, VOL =0.5V 1.0 4.0 rnA
MUTE output current, lOB! V DD =3.5V, VOH=3.0V 0.5 2.0 rnA
11
in key input IOH2 VDD=lO.OV, VOH=9.5V 1.0 4.0 rnA
ISB1 VDD=3.5V 0.25 100 pA
Standby current 9
ISB2 VDD=lO.OV 0.5 200 pA
IOP1 VDD=3.5V 1.0 2.0 rnA
Operating current 9,13
IOP2 VDD =10.0V 5.0 10.0 rnA
Input resistance RIN 20 100 k.o 5,S
Tone output (no key input) -SO dBm
Output rise time tr 3.0 5.0 ms 12,13
Pre-emphasis 1.0 2.0 3.0 dB 14
Tone output distortion VDD~4.0V -20 dB 15
Note 5: Applies to STI pin. Note 11 : Applies to MUTE output pin.
Note 6: Applies COL input pin Note 12 : Rise time for tone output to reach 90% of maximum amplitude after key input.'
Note 7: Applies ROW input pin Note 13 : Characteristics of crystal resonator used. Rs=100n, Lm=96mH, CM=0.02pF,
Note 8: Ta=25t Ch=5pF, F=3.579545MHz
Note 9: All output pins open -Note 14 : Level ratio of high group tone to low group tone. __
Note 10 : Applies to XMTR output pins Note 15 : Unnecessary frequency components against total power of basic tone signal of ROW
and COL .
.-.-----.--'~---SHARP-.....------ ......... - - -
733
..............-..-...............-,.._..- . - ..................--.-..--.-......
Tone Dialer. CMOS LSI . LR4087
IN40004o
(4X)
H----rrImwi'DD
1!!H_---,1~'RllW§
a+-_....,1;;.t3 ROW3 TONE
l!m~I!lIIii+---,liiiZ RliWi OUT 16
... \1 LR4087
9 COU
L----isi-lCOL3 1200
' - - - - - ' i - l , COLZ
L-----:S;..!COLI
3.579545 7 OSC MgM""IO,-+----+--.
MHz '" osc
8 OUT GND -"
6
0.0051'F
-----------------~
""....,......l-1~r 00
2N6660
network
• Test Circuit
COLI
3
f1
I
7
~ 3.579545MHz
T
8
COLz 4
COLs
5
COL.
9
16 Tone Output
I - -
ROWI
LR4087
1 2 3 A 14
ROWz
4 5 6 B 13 RL
<i
ROWs
7 8 9 C --
12
ROW. .,;,
0 # D 11
*
6
, GNDJ.
----------SHARP--:---------
734 '

The LR4089 is a monolithic LSI and uses an in-
sinusoidal frequencies. Dual- Tone Muiti-Fre-
quency is obtained by mixing these frequencies.
• Features
1. Minimum external parts count
2. Divider, R-2R resistive ladder, CMOS opera-
tional amplifier on chip
3. High-accuracy tone out
burst crystal
5. Single tone output
6. CD inhibits tone generation Top View
• Block Diagram
Row Input
,--A-----, VDD
r-~~~1r-~----------------------------'
Any Key
Q Down
Oscillation Output
Output 8hr---t--,
Oscillation 6 Tone
Input 7 Output
L-----{2 Chip
Disable
'----------------<l~------IJ5J Single
Tone
Inhibit
•
Column Input
------------SHARP-.--.----...-.--~
735
, '. t: ~ ., "
Tone t)ialer CMOS LSI LR4089
.• Absolute Maximum Ratings

Parameter Symbol Ratings. Unit Note
Supply voltage Voo 10.5 V 1
Storage temperature T st• -55--1'150 t
Maximum power consumption Po 500 rriW 2
VINl -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Note 1: Referenced to GND.
Note 2 : Ta=25t
Note 3 : The maximum 'applicable voltage on any pin with respect to GND.
Note 4 : The maximum applicable voltage on any pin with respect to VDD.

Parameter Rating Unit
• Electrical Characteristics (Ta=-30-+60t) .

Input low voltage VINL GND 0.3Voo V 5
Input high voltage VINH 0.7Voo Voo V 5
Input resistance Rl Ta=25t 20 100 kO 6
TONE DISABLE input voltage VINTO GND 0.3Voo V
TONE output level VOUT Voo =3.4-3.6V, RL =100kO -10 -7.0 dBm 7,15
Pre· emphasis 2.4 2.7 3.0 dB 8
TONE output distortion Voo =3.4-10.0V -'-20 dB 9
Output rise time tr 2.8 5.0 ms 10,11
AKD output sink current IAKo ON VouT=0.5V 500 pA 12
AKD output off current IAKo OFF VouT=5.0V 2 pA 12
Supply current
I. In operation lop Voo=3.5V 2.0 rnA 13
1 In standby ISB VoD =10.0V 200 pA 14
Tone input level (no key input) -80 dBm
Note 5: Applies to ROWand COL input pins.
Note 6: Applies to STI and CD input pins.
Note 7: Applies to low group single tone signal.
Note 8: Level radio of high group tone signal to low group tone signal.
Note 9: Unnecessary frequency component against basic tone signal total power (RMS) of ROWand COL.
Note 10: Rise time for tone output to reach 90% of maximum amplitude after key input.
Note 11: Characteristics of crystal resonator used. Rs=lOOO, Lm=96mH, CM=O.02pF, Ch=5pF, F=;=3.579545MHz.
Note 12 : . AKD output means N·channel~n drain output. .
Note 13: In single keyJ!!put, CD="l", STI="O"
Note 14: In stand·by, CO="l", STI="O"
Note 15: OdBm=0.775V
736
• Test Circuit
r
1
DD
COL!
7 ~ 3.579545MHz
--
COL z
3
4
sW
COL 3
5
COL 4 LR4089
I I
ROW!
9
16 Tone Output
1 2 3 A 14
ROW z
4 5 6 B 13
--
ROW 3
7 S 9 C 12'
ROW 4 RL
0 .jj: D 11
*
6 ,
" GNDl
-----~-----SHARP - - - ' - - - - - - - - - ......... -,.-,

737
_..........._.......'._.........................-----_.....................
Tone Dialer CMOS L S I L R 4 0 9 1
'

sinusoidal frequencies. Dual-Tone Multi-Fre-
quency is obtained by mixing these frequencies.
o
,. Features
1. CEPT Compatible
2. High accuracy tone output
3. Divi"der, resistive ladder network, CMOS oper-
ational amplifier, and bipolar transistor on
chip
4. Uses 3.579545MHz crystal
5. Single tone output
6. Uses either 2-of-8 keyboard or single contact Top View
keyboard
7. Low standby current
• Block Diagram
Row Input
Bipolar Output
~ VDD
~----~J~l~~~n~--~~2}---------------------~~~--,
"L-..........J1'71 Bipolar
Input
Oscillation 9>--.__~'-------;::~J..---.cJ
Any Key
Down Output
Output
Oscillation 1 OPamp
Input 8 Output
Chip
Disable
' - - - - - - - - - - - - - - - ' - - - - U 6 Single

Tone
Inhibit
738

Maximum power consumption Po 500 mW 2
VINl -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Notel: Referenced to GND.
Note 2: Ta=20t
Note 4: The maximum applicable voltage on any pin with respect to VDO,


In operating Voo When tone signal is output 3.0 10.0 V
Supply voltage
In stand-by Voo CD=O 2.0 10.0 V 5
VlHl 0.7VDO Voo V
COL input voltage 6
VILl 0.0 0.3 V
VIH2 ' Voo-0.3 Voo V
ROW input voltage 7
VIL2 0.0 O.3Voo V
VIH3 0.7VOD Voo V
Input voltage 8
VIL3 0.0 0.3VDD V
Input resistance Rl Ta=25t 20 100 kO '8
Tone output level VOUT Voo =3.4-3.6V -10.Q -8.5 -7.0 dBm 9,17
Pre-emphasis
No filter 1.0 2.0 3.0 dB 10,17
(high-group tone signal)
Tone output distortion Voo =3.4-10.0V -20 dB 11,17
Output rise time tr 5 ms 12
VDD=3.5V
AKD output source current IAKD ON 500 /LA 13
VAKO=3.0V
VDo =10.0V
AKD output off current IAKD OFF 10 /LA
\ VAKD=OV
In operation lop VOD=3.5V 1.0 2.0 rnA 14
Supply current In operation lop VDD =10.0V 5.0 rnA
In stand-by ISB VoD =10.0V 1.0 200 /LA 15
Tone output (no key input) -80 dBm
OP amplifier output resistance 10 kO 16
OP amplifier output current VDD=3.0V 250 /-LA 16
Note 5: Voltage to whIch AKD output responds by key mput.
Note 6: Applies to COL input pins (COLI-4).
Note 7: Applies to ROW inQ!!!.pins (ROWI-4).
Note 8: Applies to CD and STI input pins.
Note 9: Applies to low-group single tone signal. ,
Note 10: Level ratio of high-group tone signal to low-group tone signal. __
Note 11: Unnecessary frequency component against basic tone signal total power (RMS) of ROWand COL.
Note 12: Rise time for tone output reach 90% of maximum amplitude after key input.
Crystal reasonators used are as follows :
R5=1000, Lm=96mH ,CM=0_02pF, Ch=5pF, F=3.579545MHz
Note 13: AKD output is P-channel open drain output.
Note 14: Crystal resonator is used as indicated in Note 12 when single key is pressed (pin 6).
Note 15: In stand-by, CD="O', STI="I" '
Note 16: OP amplifier output resistance is determined by capacity of pin l. The 10 kO shown in the test circuit is used in a standard
filter circuit. When the capacity of pin 1 is too large, it is necessary to reduce the resistance_
Note 17: RL (Pin 18)=6200 : Voo=3.4-5V
3000 : Voo=7.5V or more
- - - - - - - - - - . - . . - "'-SHARP ~~.-....-.---------..-,
739
Tone Dialer CMOS Lsi LR4091
• Test Circuit
. 18
VDD -,.;-
Power -
17 ~
supply LR4091·
1
~
---
lOkO
7
VBIAS=O.5V: VDD;;>4.0V
VBIAS=OV: VDD>4.0V
740

sinusoidal frequencies. Dual-Tone Multi-Fre-
quency is obtained by mixing these frequencies .
.
• Features
1. Internal regulation of tone amplitudes
2. Internal loop compensation and pre-emphasis
3. Tone frequencies within 0.65% for 12 stand-
ard frequencies
burst crystal
5. Tone-disable capability
6. Mute output for electronic switching Top View
7. Uses either 2-of-8 keyboard or single contact
keyboard
8. Single-tone capability
• Block Diagram
Row Input
,
Mute
~--~.Q) Output
Oscillation 8hr--t--,
Output
9
Oscillation 7 Tone
Input Output
Chip
'---4---(2 Disable
Single
~-~----------------~--------(l~ Tone
Inhibit
.-------.-.---".-~SHARP'--------.-~-
741

Supply voltage Voo '+10.5 V 1
Storage temperature TSJiL -35-+85 "C
VINl -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Note 2: Ta=25't
Note 4: The maximum applicable voltage on any pin with respect to VDO.
• Electrical Characteristics "

(Ta=O- +60"C)
Parameter I Symbol I Conditions MIN. TYP. MAX. Unit

Supply voltage
Tel Loop in Operation Voo. 3.5 10.0 V
Power Supply in Operation VODb 3.8 10.0 V
Stand-by Vs CD=GND 3.0 10.0 V
CD, STI mput voltage
logic"'l " V
logic "0" V
COL input voltage
logic "1" V
logic "0" V
ROW Input voltage
logic "1" V
logic "0" V
Input resistance
ROW RRI Ta=25"C 15 kO
COL ReI Ta=25"C 15 kO
CD, STI Ta=25"C 20 60 125 kO
742
Tone Dialer CMOS LSI LR4092.
3 7
4
c:::::J !3.579545 MHz .
5 18
9
14 LR4092 6
1 2 3 A
4 5 6 B 13
8 9
12
7 C
11
0 # D
* 16 10
1800
RCVR
Type 2500 GNI------'

Speech network
Bl------'
~~~--~----------~RR
1N4004
(X4)
743
Ptdse:Dia/er CMOS LSI LR40981 A
.....~~.......- . .IIIIIIf!.~. . . .~~....,.-.-......- .....~.-
LR40981A Pulse Dialer CMOS LSI

.• Description • Pin Connections
The LR40981A is a monolithic CMOS LSI which
uses a ceramic resonator and provides the features
required for a pulse dialer with redial.
o
• Features
1. Direct telephone· line operation
2. Uses 2-of-7 matrix keyboard
3. CMOS process for low-power operation
4. 2.5 -6.0V power supply
5. Make/Break ratio pin-selectable
6. Ceramic resonator ·used as frequency reference
7. Redial with:lf or *
8. MUTE output for electronic switching
9. 16-pin dual-in-line.package Top View
• Block Diagram
COlumn.{
Input 5
! Memory Pulse
Output
I!';,~ {fi34>----i'" o Mute

Output
r-----~9r----o~------------------~
Oscillation Oscillation Make/Break Hook Switch/Test
Input ,Output Ratio Select .
7~4
Pulse Dialer CMOS LSI LR40981A

Operating temperature Topr -30 +60 t
Storage temperature T s," -55-+150 t
VIN1 -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Notel: Referenced to GNO.
Note 2: Ta=25t:
Note 3: The maximum applicable voltage on any pin with respect to GNO.

Parameter Specified value Unit
Supply voltage 2.5 6.0 V

Key contact resistance RKI 1 kO
Key board capacity CK1 30 pF
KIH 0.8Voo Voo V 5
Input voltage 2-of-7 input mode
KIL GND 0. 2Voo V 5
Key pull-up resistance KIRU 100 kO
Voo=6.0V, VIN=4.8V
Key pull-down resistance KIRO 4 kO
MUTE sink current 1M Voo-2.5V, VouT-0.5V 500 pA 6
Pulse output sink current Ip Voo =2.5V, VouT -0.5V 1.0 mA 7
(V 00- VRFF) value VREF ISUPPLy-150pA 1.5 2.5 3.5 V 8
Memory hold current IMR All outputs in no-load state 0.7 pA
Operating current lop All outputs in no-load state 100 150 pA
MUTE, PULSE
ILKG Voo=6.0V, VouT=6.0V 0.001 1 pA 6,7
Output off current
Note 5 Applies to key input pins (ROW 1-4, COLI-3)
Note 6 Applies to MUTE output pin.
Note 7 Applies to PULSE output pin.
Note 8 Applies to VREF pin.
745
• Timil'lg. Diagram
:t* or *
Key input
COL scan -------------------- ~
ROW scan
ON -HOOK input I--++------------i

MUTE output Digit 2 ~---.., Digit 4
L--";;""'-f-'
PULSE output -i----'
sci ator 0 eratJon

ON-HOOK/I
TEST mode
1---- . ON -HOOK mode "I" "I r-'~---- Redial mode
(Normal dial)
• Test Circuit
Power supply
+
OFF-
1 16 15kO HOOK 3OkO
2 15
3
KeYboard{
6
LR40981A
}K~"ro
7 10
8 9 67% break
61% break
746
R3
TIP
RING
Telephone line
Re
VDD M/B
I
I
C1 15 ON-HOOK I
+-..:::..:__--1>-!6~GND I
2 VRE~ULSE I
I
I
.------'3'-1COL 1 I
I
.------'4'-1COL, I
I
5 COL, I
LR40981A _______________ JI
I 2 3 14 ROW,
4 5 6 13 ROW,
7 8 9 12 ROW, Speech network
... 0 # 11 ROW, MUTE~I~O_ _-I--t
OSC" OSCOL'T
A type keyboard 7 8
C3
QI.Q3 : 2N5550 RI : 2.7kO

Q2.Q. : 2N5401 R2 : 75kO
Q5 : 2N6661 R3: 22MO
DI.D2 : IN914 R.: 390kO
C1 : 20,uF (low leakage product) R5: IMO
C 2 .C 3 : lOOpF±20% Re : 1500
R7 : 100kO
747
Pulse Dialer CMOS LSI LA40982
'-'_'-''-~''_'''_'''_IPi:-''~''_''''_'''-'-'~ _ __
LR40982 Pulse Dialer CMOS LSI

• Description ..• Pin Connections
The LR40982 is a monolithic CMOS LSI which
uses a ceramic resonator and provides the 'features
required for a pulse dialer with redial.
o
• Features
1. Direct telephone-line operation
4. 2.5-6.0V power supply'
6. Ceramic resonator used as frequency reference
7. Redial with :1:1: or*
• Block Diagram
COlumn{
Input 5
! Memory Pulse
Output
I~ {u. 3
_---.
Mute
Output
Oscillation Oscillation Make/Break Hook Switch/Test

Input Output - Ratio Select
748.
Pulse Dialer CMOS LSI LR40982

Supply voltage VDD -0.3-+6.2 V 1
Operating temperature Toor -30-+60 ·C
Storage temperature T st• -SS-+lS0 "C
Maximum power consumption PD SOO mW 2
VIN ) -0.3 V 3
Maximum pin voltage
VlN2 +0.3 V 4
Note 2: Ta=25t:.

• Electrical Characteristics (Ta=-30-+60"C)

Key board capacity CKI 30 pF
KlH 0.8VDD V DD V S
KIL GND 0.2VDD V S
Key pull-up registance KIRU 100 kO
VDD=6.0V, VIN=4.8V
Key pull-down resistance KIRD 4 kO
MUTE sink current 1M VDD=2.SV, VOUT=O.SV 500 pA 6
Pulse output sink cllrrent Ip VDD=2.5V, VOUT=O.SV 1.0 rnA 7
(VDD-VRFF) value VREF IsuPPLY= 150 pA 1.S 2.5 3.S V 8
Operating current lop 100 ISO pA
MUTE, PULSE
ILKG VDD=6.0V, VOUT=6.0V 0.001 1 pA 6,7
Output off current
Note 5 Applies to key input pins (RDW 1-4. COLl-3).
-.-----~---SHARP-.---.-----
749
.........r.-__...____
J
........................,.........................
~ .....,
• Timing Diagram
# or *
Key input
COL scan --------'------------ JUUu-
ROW scan,
ON -HOOK input
MUTE output .-...1-....L.j

L......,;=---~
Digit 4
PULSE output--1I---,
SCI ator ope,ratIon

ON-HOOK/I
TEST mode Redial mode
I----OFF-HOOK mode """ ., j-o.>------
(Normal dial)
• Test Circuit
Power supply
+
OFF-
16 15kll HOOK 30kll
15
.10
9 67% break
61% break
750
TIP
RING
Telephone line
Rs
VDn
15 ON-HOOK
Q 6 GND
I 2 PULSE
~-----l~"":3'-1v REF
, - - - - ' - 1 COL,
,
1
r _ _-=-t 4 COL, 1
1
5 COL, -I
I
LR40982 I
1 2 14 ROW, I
I
4 5 6 13 ROW, I
7 8 9 12 ROW, I
I
* 0 II 11 ROW4MUT"1-<~-+I ____________________ J I
OSC'NOSCOUT
A type keyboard 7 8
Type 500 Speech network
QI.Q3. Q.=2N5550 RI=8kO

Qs,Q6=2N5401 R2=500kO
Q2=2N3822 R3=22MO
D1 =lN914 R •• Rs=390kO
C1 =20,uF(Iow leakage product) R6,R g =100kO
C2.C3=100pF±20% R7. RS=3kO
751
Pulse; Dialer CMOS LSI LR40991

• Description • PinConnec,ions
uses a CR oscillator and provides the features re-
quired for a pulse dialer with redial.
o
• Features
4. 2.5-6.0V power supply
6. 20/10 pps pin-selectable
7. *
Redial with :1:1: or
9. CR oscillator T~p View
10. IS-pin dual-in-line package
• Block Diagram
Pulse
Output
2 Mute
Output
L--r~~~J'<--------~o 20110
pps
Select
Make/Break Hook Switch/Test
Ratio Select
~'-'~--~'---SHARP--'-"--'-'----
752

Storage temperature T stg -55-+150 t
VIN! -0.3 V 3
Maximum pin voltage
V1N2 +0.3 V 4
Note 2: Ta=25"'C.

Supply voltage 2.5-6.0 v

KIH 0.8VDD V DD V
Input voltage 2-of-7 input mode 5
KIL GND 0.2VDD V
MUTE sink current IML VDD =2.5V, VouT =0.5V 0.5 2.0 rnA
6
MUTE source current IMH VDD =2.5V, VouT=2.0V 0.5 2.0 rnA
PULSE sink current Ip V DD =2.5V, VouT =0.5V 1.0 rnA 7
V REF output value VREF ISUPPLY= 150 /L A 1.5 2.5 3.5 V 8
Memory hold current IMR All outputs in no-load state 0.7 /LA
Operating current lop All outputs in no-load state 100 150 /LA
Key pull-up resistance K1RU VDD=6.0V 100 kO
Key pull-down resistance KIRD VIN=4.8V 4 kO
ON-HOOK pull-up resistance ROH 100 kO
MUTE, PULSE
ILKG VDD =6.0V, VouT=6.0V 0.001 1 /LA
output off current
Note 5 Applies to key input pins (ROWI-4, COLI-3).
----------SHARP-----------------
753
• Timing Diagram
Digit 1 Digit 2 # or *
Key input -----.Ur----.L.Jr---------,Ur----------
COL scan ~----~~O!l~--- ~ ----------- m.r-
ROW scan~: ____ ~~0!l~___ lJ1JLJl.Jl----------- ~
I I .
r-
I I ,
ON -HOOK in;;-l ! r),l'

:" ~ I : : . :
MUTE output --'j
~
i i .. L.IU':
t i l I
I!II~ III I
I I i
PULSE output I I I : !!
: :l ' Oscillator stop ,
oscillatorl : : :1l1lrTT1I1n
.. .,.- ' Ii II
I I I I I I
CR2 output -------"1'

------010: ..4kHz
I I I I I I I
I
- - - - - - - - - - - - ____ rnr-
,JU
:
tDB I I tB I I I I I : I :
tpDP :: tlDP ~II I ItMOI : I
/----'-'-"'"----1:11
I" I
!!II.
Normal dial liP,

'E:~I
• .I
i
I
i
:
Redial mode
TEST
ON -HOOK mode OFF -HOOK mode _. OFF -HOOK mode mode
·1· ~~---------------~~~--
• Test Circuit
Power supply
+
OFF
-HOOK
1 1MO
2 17
~: }
3 IMO
4
KeYboard{
5 ~ Keyboard
LR40991
6 1L-
12
60% break
66'% break .
20pps
IOppso--~
--.-------------SHARP - - - - - - - - - - - - -
754
Telephone line
R6
Speech VDD
R2 17 ON- 12
network
t--+---"-:-tHOOK MU TEI--~---+
6 GND
2
~----~~~--~3~VREF
~_ _-,-/4 ~~~l LR4099I

.-____5, COL: PULSE~I~8~-----1-+----~
[t[t[tr--~I6~ROWI
15 ROW 7 R5
1-4~~~-~I4d1 ____2 CRI 8 C2
t*7hlj8rn9tl===:II3~
0 ;l:
~OW
ROW 4
3 C R2 t-9--1t;;RC-B4'
CR3I-'-..JIf'V\r~
I
I M/B 20/10
I
I 11 10
I
I
I
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...1J
Rl=2.7kO Ql=2N5550 C 1 =22,uF

R2 =75kO Q2=2N540I C2=390pF
R3=22MO Q3=2N5550 C 3 =IO,uF
R4=390kO Q4=2N5550 D1 =IN9I4
R5=2MO Q5=2N2222 D2=IN9I4
R6=I500 Q6=2N2303 D3=IN4004
R, =IOOkO
RB=220kO Relay: 1.5V bistable latching
------------------SHARP - - - - - - - - - - - - - -
755
Pulse Dialer CMOS LSI , '\LR40992

o
• Features
5. Make/Break ratio pin -selectable
6.,20/10 pps pin-selectable
7. Redial with :1* or*
9. CR oscillator Top View
• Block Diagram
Column {
Input
!
5 Pulse
Output
Row """ {11'46t--~ Mute
Output
L~=:::.!:....,.....r---------1Qg 20/10 pps

Select

Ratio Select
756

Storage temperature Tst2 -55-+150 'C
VIN1 -0.3 V 3
Maximum pin voltage
V1N2 +0.3 V 4
Note 2: Ta=25t:.
Note 4: The maximum applicable voltage on any pin with respect to VDD'

• Electrical Characteristics (Ta=-30-+60'C)

KJH 0.8Voo Voo V 5
KIL GND 0. 2Voo V 5
Key pull-up resistance K1RU 100 kO
Voo=6.0V, VIN=4.8V
Key pull-down resistance K1RO 4 kO
MUTE sink current 1M Voo=2.5V, VouT =0.5V 500 pA 6
Pulse output sink current Ip 1.0 rnA ,7
V REF output current IREF VOO,VREF=6.0V 1.0 7.0 rnA 8
Operating current lop All outputs in no-load state ' 100 150 pA
MUTE, PULSE
ILKG Voo=6.0V, VouT=6.0V 0.001 1 pA 6,7
Output off current
Note 5 Applies to ~ut pins (RDW'-4, COL'-3)
Note 8 Applies to VOEF pin.
~--""'-'-'--~-SHARP-~------
757
• Timing Diagram
Digit 1 Digit 2 # or *
Key input ~--""LJr-----'LJr--------""'LJ""----------
---uuuuuL___ ~~O~~ JUL...fIJlf ----------- ~

KnJlJ1Jlf ------------
COL scan ____
__ : 500Hz
ROW scan ----------~ ~
ON-HOOKin~ ,)l r-
--
: I:
MUTE output
i
:
I,
:
: I,
:
1
i
;
I
!
r--
I
: : : I I :
--- I I : ~~ r------f I
PULSE output I i I U I I
: :I : : 4kHz oscillato~: i :Oscillator stop :
CR2 output -----+--------'"1~~-
tDB
I I I I I J44
I :
: I U~L-----------------:.ru--
n~II-;-ilnn
t8 I I: I I
I
I lI I I
tpop II tmp ~ I I tMol I I
I---------i,. ·1 , ~:, '
, i Normal dial liP, .1': I Redial mode
ON-HOOKmode .1. OFF-HOOK mode _. OFF-HOOK mode TEST mode
• Test Circuit
Power supply
+
OFF
IMO -HOOK
2 17
3 16 IMO
4 15
KeYboard{
5 14 }KO,OOUd
LR40992
6 13
12
60% break
66% break
20pps
10pps
758
TIP RING
2
V REF
6 12
GND MUTE
3 COL,
- - - - 18
COL, PULSE
COL,
lR40992
ROW,
15 Rs
4 6 ROW,
14
7 9 ROW,
13
jj: ROW,
17 ON- R6
HOOK
20/10
10
RI =560kn QI=2N5401 DI =IN4004

R2 = 1.4kn Q2=2N5550 D2=lN4004
R3 =470kn Q3=2N5550 D3=IN4004
R. =330kn Q.=2N5401 D.=IN4004
Rs = 2Mn Qs=2N5401 Ds=IN914
R6 =220kn D6=lN914
R7 =lOOkn C I =68,uF D7=IN4004
Rs = 3kn C 2=390pF
R9 = 3kn ZI=120voit,
R IO =100kn lwatt Zener
Rll = 10Mn
759
Pulse Dialer.CMOS LSI LR40993

• Features
3. CMOS process for low-power operation 12 MUTE
6.20110 pps pin-selectable
*
7. Redial with :j:j: or
10. Beep-tone output for key input
• Block Diagram
'"0 '" ... Pulse

; ~ I-----~
o~
'" 8 Output
~ ~ I-----~L______~______~~--;_~
'" ~
:.=:..:; "
"o
U Mute
Output
Tone 20/10 pps

Output Select
) - - - - - { l)----{J171}-........,----------.....J
Make/Break Hook SJitch/Test
Ratio Select
I
~-----------SHARP-----.---___:_
760

Operating temperature Topr -30-+60 t
Storage temperature Tst~ , -55-+150 t
VINl -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Note 2: Ta=25'C.


Key board capacity CKI 30 pF
KIH 0.8VDD VDD V 5
KIL GND 0.2VDD V 5
Key pull-up resistance KIRU 100 kO
VDD =6.0V, VIN=4.8V
Key pull-down resistance KIRD 4 kO
MUTE sink current 1M V DD =2.5V, VouT =0.5V 500 pA 6
Pulse output sink current Ip V DD =2.5V, VouT=0.5V 1.0 rnA 7
TONE output sink current ITL V DD =2.5V, V ouT =0.5V 250 pA 8
TONE output source current ITH V DD =2.5V, VOUT=VDD-0.5 250 pA 8
MUTE, PULSE
ILKG VDD =6.0V, VouT=6.0V 0.001 1 pA 6,7
Output off current
Note 5 Applies to key input pins (ROW(-4, COL I - 3)
'Note 6 Applies to MUTE output pin.
Note 8 Applies to TONE pin.
-'-~--'---SHARP~-'--'-'-----~
761
• Timing Diagram
_
..........................._-,._.. ..........................................
Pulse Djaler CMOS LSI LR40993
Digit 1 Digit 2 "* or *

Key inPlJt - - -.... Ur----.Ur--------....U r ---------
- - - -. - ,UnUnUnUnUnl.""----------
COL scan
: .
500Hz
~------------=unu______ .
R-O-W scan ~----52~f!z--- ~ _____________~
ON -HOOK input
'
~",,_-+i!~
---1
I
+1---------------IJJ.l'--------------ir-
~l :! I
MuTE output 1 : I : : i I
-
:I
--';---;I-;I---lJf-----, ~ I.
: I
1
:
PULSE output I I U . 1.
: : I I I I I : Oscillator stop ., I
_ _';-_-1 4kHz 1 1 Oscillator 1 1 I nn;----'-----'nn I .
CR2 output 1 -------:-~--------:-:4-.Jl!U ..
UJ.lL -------.,..--------+.nr--
: tDS ' ii tB : : : :: : i I : I
1 tpDP 1 I tIDP ~ I I tMO. I 1 I :
1
I
1-------'-'-'-t~I.
I.. I I Normal
-I
dial l/Pr
I.~ I
I ':
I
I
r
Redial mode
I
1
I
I
ON -HOOK _m_od_e.-IIf.._ _ _ _O_F_F_-_H_O_O_K_m_Od_e_ _ _ _

_____ MM~ ____ ~~ _________
-_*1.1\. .
MM~
OFF HOOK i.
.od. :1
_____________
TEST .odo
Tone output
• Test Circuit
Power supply
- +
OFF
1MO
~ 18 -HOOK
-----L 17
/
Keyboard
{~
---.!.. :: } ~
.~ LR40993
_1_4__ Keyboard
6 13
2MO 7 J2
I390 p;' 8 11 60% brea~
/220kO 9
- 10 I /
66% break
0---
20pps
-
lOpps
762 '
• System Co~figuratiori
RING Telephone line

TIP
Z2 VDD 11
M/B
2
TONE D7
6 12
GNDMUTE
3
COLI
4 COL2 13
5 ---'pULSE N-,
COL3 I
16 LR40993 I
1 2 ROW 1 I
15 ROW2 R5
4 5 6 I
14 CR 1 I
7 8 9 ROW3
13 ROW. CR2 I
0 #
* 17 ON-
CR 3
1
I
R6 I
HOOK 10/20
I
10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..J
I
Speech network
Rl =560kO R IO =100kO DI =IN4004 C 1 =68.u F

R2 = l.4kCl Rl1 =10MO D2=IN4004 C 2=390pF
R 3=470kO D3=IN4004 ZI. Z2=120V : 1watt
R.=330kO QI =2N5401 D.=1N4004 Zener Diode
R5= 2MO Q2=2N5550 D5=IN914
Rs=220kO Q3=2N5550 Ds=IN914
R 7·=100kO Q.=2N5401 D7=IN4004
Rs= 3kO Q5=2N5401 Ds = Zener Diode
R9= 3kO
'-'---'~------SHARP ~.-.-.-.------
763
Pulse Dialer CMOS LSI 'LR40994

• Description • Pin Connectio'ns
quired for a pulse dialer with rediaL
• Features
L Uses'2-of-7 matrix keyboard )
5. 20110 pps pin-selectable
6. Redial with # or *
10. 18-:pin dual-in-line package
• Block Diagram
Column { !
Input "'5",----. Pulse
8 Output
Row { I; 1 Mute
Input U3}--+j Output
Tone Output 2 20/10pps

L.,.-=:.:.:::::....,......Jt----------~ Select

Ratio Select
~------- ........ --SHARP--.--,-.-.-----~

764

Operating temperature Topr -30-+60 ·C
Maximum power consumption Po 500 mW .-t-----
2
VIN1 -0.3 V 3
Maximum pin voltage
VIN2 +0.3 V 4
Note 2: Ta=25"C
Note 4: The maximum applicable voltage on any pin with respect to V DO,
• Electrical Characteristics (Ta= -30- +60"C)

Supply voltage VDD 2.5 6.0 V
Key contact resistance RKI 1 kD
KIH 0.8VDD V DD V 5
KIL GND 0.2VDD V 5
Key pull-up resistance KIRU 100 kD
V oD =6.0V, VJN=4.8V
Key pull-down resistance KIRD 4 kD
MUTE sink current 1M VDo =2.5V, VouT=0.5V 500 pA 6
PULSE output sink current Ip V Do =2.5V, VouT=0.5V 1.0 mA 7
TONE output sink current ITL V DD =2.5V, VouT=0.5V 250 pA 8
TONE output source current IrH VDD =2.5V, VOUT=VDD-0.5V 250 pA 8
MUTE, PULSE
ILKG VDD =6.0V, VOlrt=6.0V 0.001 1 pA 6,7
Output off current
Note 5: Applies to ~ut pins (ROW I - 4, COL , - 3)
Note 6: Applies to MUTE ou'tput pin.
Note 7: Applies to PULSE output pin.
Note 8: Applies to TONE pin .
.-..-------$HARP---------
765
• Timing Diagram
Digit 1 Digit 3 *" or *

----~~.---~L_J~----------~L_J~-------------
Key input
COL scan --utI1Jl.AA___ ~~<!..l!.z__ _ ~-----------~

ROW scan~: ___5..oE!.I~ __ _ ~-------------~
, r
, r
ON-HOOKmp~L__ r:r-__________________~rl~______________~r----
I
!
II
! I
111
I
rI I
I
MUTE output :
I
:1
! I
:t
I t
11
i
IIJr~ " r
PULSE output Ir r:
I
I
.
I
,
I
,i :urn
i 4kH
z.J
: : Oscillator r::
:Oscillator stop
r ,
nilr--:---t""1nn .
I
r nr--
, ------ "--------j-l-,- JUU : i UUI ----------------tJU
I
: I I tDS : : tB I :: :: i
I : l :
I tpDP, ' hDP ~ I ,tMDI I ,
I:
r :
I I. -, I ............ I I I I :
, , r Normal dial l/Pr. I Redial mode ':
ON -HOOK mode I
• ..
OFF -HOOK mode
..
I OFF -HOOK mode Ir-TEST mode
Tone output n.nnn nnnn ·U'--_________
• Test Ciruit
Power supply
+
OFF-
HOOK
1 18 IMO
2 17 ~
3 16 IMO
}K~
Key- { 4- 15
board 5 LR40994 14
6 13
2MO 7
8
20pps
10pps 0-----+
766
Telephone line
TIP RING
1
VDD 11
M/B.
2
TONE
~_ _ _ _ _-=6-1 GND MUTE 1-1_2_-+--+---1
r".:...·----3-tCOL l
4 18
COL2PULSE
5
COL 3 I
LR40994 I
16
2 3 ROWl I
15 Rs I
4 5 6 ROW2
14 I
7 8 9 ROW3 I
13 CR 2
ROW. I
* 0 :1*
CR 3 I
17 ON- I
HOOK 10/20 I
I
10
C - _ _ _ _ _ _ _ _ _ _ _ _ ---lI
Speech network
Rl =560kO RIO =100kO Dl =IN4004 C,=68pF

R 2 = 1.4kO Rll = 10MO D2=IN4004 C2=390pF
R3=410kO D3=IN4004 Zl = 120V, I-watt Zener Diode
R.=330kO Ql =2N5401 D.=IN4004 Z2 = 120V, I-watt Zener Diode
Rs= 2MO Q2 =2N5550 Ds=IN914
R 6=220kO Q3 =2N5550 D6=IN914
R 7 =100kO Q.=2N5401 D7 =IN4004
Rs= 3kO Qs =2N5401 Ds = Zener Diode
Rg= 3kO
--'.-------SHARP--------
767
Pulse/Tone Dialer CMOS LSI LR4801D
LR4801D PulselTone Dialer CMOS LSI

The LR480ID is a CMOS LSI for the repertory
dialer switchable between tone and pulse dialing
with the beep-tone function and ten I8-digit num-
ber memory storage~ TONE OUT
o PULSE OUT
ROW,
COL2 ROW2
• Features COL3 ROW3
GND ROW4
L Switchable between DTMF tone dialing and
pulse dialing modes TEST HKS
2. Stores ten I8-digit telephone number memory MUTE
including a redial memory MODE ,I

4. PABX pause storage
5. Uses the single contact, the standard 2 of 7 or
2 of 8 matrix keyboard Top View
6. Switchable between 10 pps and 20 pps in
pulse dialing mode
7. A 3.579545 MHz color burst crystal can be
used for the clock oscillator
768
• Block Diagram
Hook Switch
18 Tone Output
Mode Select
Col umn Input 17 Pulse Output
Column Input
Row Input 11 Mute Output
Vnll GND
• Pin Description
Signal Name Symbol I/O Function
V DD Power supply
COL I -COL 4 COL 4-string Key input
Key input I
ROW I -ROW 4 ROW 4-string key input
GND Ground Negative power supply pin
TEST Test input I Pin used for LSI testing
OSC IN Oscillator I
Connect crystal for color burst
OSC OUT connection 0
Pin connection Operating mode
Voo 20-pps pulse dialer
MODE Mode select I Open lO-pps pluse dialer
GND DTMF tone dialer
MUTE Mute output 0 Sending of MUTE signal
Voo on-hook mode
HKS Hook switch input I
Open off-hook mode
GND off-hook mode
PULSE OUT Pulse output 0 Sending of lOOpps or 20pps pulse signal
Sending of DTMF tone signal or output of beep tone signal
TONE OUT Tone output 0

On hook I Off hook I
Tone mode I Beep tone I DTMF signal
I Pulse mode I Beep tone I Beep tone
'-~------SHARP--------
769

Pin voltage Voo 10.5 V 1
Input voltage V IN -0.3-V oo +0.3 V 2
Power consumption Po 500 mW 3
Storage temperature Toor -55-+150 "C
Note 3: Ta=25"t

Parameter Unit
Supply voltage V
• DC Characteristics (Ta=25"C)

V IL GND 0. 2Voo V
Input voltage
V IH 0.8Voo Voo V
Tone output I ROW VOR RL=lkO 290 350 450 mV Rms
voltage I COLUMN Voc RL=lkO 380 450 550 mV Rms
Standby current ISB Voo=3.5V 3 6 pA 4
Operating current lop Voo =3.5V 2 3 mA 5
Mute output current IOL Voo=2V, VoL =0.5V 1 2 mA 6
Pulse sync output current IpL Voo=2V, Vo=0.5V 1 mA
Pulse leakage output current I ILKG I Voo=6V, Vo=6V 1 p.A
Key pull·up input resistance RKP Voo=3.5V 100 kO 7
Key pull·down input r!!sistance RKD Voo=3.5V 5 kO 7
Mode pull·up input resistance RMP Voo=3.5V 100 kO
,
Mode pull-down input
RMO Voo=3.5V 100 kO
resistance
HKS pull·up input resistance RHK Voo=3.5V 60 kO
Tone output distortion Voo~4V, RL=lkO -20 dB 8
Pre-emphasis PEHB Voo~4V, RL =lkO 1 2 3 dB
Note 4: All output pins in no-load condition when clock is stopped and when on hook.
Note 5: All output pins in no-load ·condition during key input and when on hook/off hook.
Note 6: Applied to the MUTE pin. _
Note 7: Resistance when ROW pin or COL pin is 125 Hz and is scanned at high or low level. _ _ __
Note 8: Unwanted frequency component corresponding to the total power of the fundamental tone signal of the ROW pin and COL pin.
770
• AC Characteristics (Ta=25"C)

Oscillation start time tos 8 ms 9
Key debounce time tDB 4 32. ms 10
10 pps 11
Pulse rate PR
20 pps 12
Break time tB 60 ms 13
13
Interdigital pause time t IDP 1000 ms
14
Mute overlap time tMO L 2 4 ms
Predigital pause time tpDP 40 ms 13
Tone output rate TOR 220 ms
Note 9: When crystal oscillation element with characteristics Rs= 1000, Im=96mH,
Cm=0.02pF, C.=5pF, f=3.579545 MHz is used.
Note 10: Key input is accepted after oscillation begins if valid after tOB.
Note 11: Opens the MODE pin.
Note 12: Connects the MODE pin to V~o.
Note 13: During 10-pps pulse mode (112 during 20-pps mode).
Note 14: 100 msec during DTMF mode;
• Timing Diagram
(1) Pulse mode

llil input illinpu;:.t_ _ _ _ _ _ _ _ _~I~R=E:::D~IA=L=I~i...:np~u-t_ _ _ _ _ _ _ _ __
Key input ~ LJ
COL scan
ROW scan ------ ~ -------------

HKS input
MUTE input
PULSE input
OSCIN Oscillator operation
(2) DTMF mode

MUTE output
TONE output
I---- Normal dialing mode 1 - - - - - - Automatic dialing mode
771
Pulse/Tone Dialer CMOS LSI . .LR4801D
• System Configuration (tone mode connection example)
SI
~--------~~--~~------~o------------------
Telephone line
7
VDD TEST
~~~---+--~6rlGND RK B R
---17 Type 2500 GN
12 PUL S E i-'1"""";'--f-<"'-- 0..-1: Speech network
'-'IiMr-=lHKS C
R13
r-------~!~~ TONE~I~8--~~~--4~~~~-C
r--- 5 C2
,C3
2 LR4801Q
C4 MUTE~I~I----+---~--+---~~~~~~
16
1 2 If;
15
4 5 R2
14 10 P
7 8 R3 MODE
13
0 R.
*Keyboard OSCI'
OSC
Ol'T
P T
8 9
3.579545 MHz
Connect to P for pulse mode

Connect to T for tone mode
Z. =10DK820 Q.=2N6660
Rl =2201W Q2=2N5401
R2 =560kO Qj=2N5550
R, =1.5kO Q4=2N5550
R4 =1500 Q5=2N5550
R5 =270kO Qs=2N5550
Rs =510 SI, S2, S,=Hook switch
R7 =5kO Dl-D4=lN4004
Rs =1000 D5=lN270
R9 =2000 Ds=IN752 (5.6V)
RlO=100kO D7=1~914
Rll=IMO Ds=lN914
R12=10kO
R13=4700
*1 R14=390
* 2 Cl =68 I' F (Must be input to smooth the power supply a?d
prevent latch up.)
772
Pulse/Tone Dialer CMOS LSI LR4802
LR4802 Pulse / Tone Dialer CMOS LSI

The LR4802 is a CMOS LSI for the repertory di-
aler switchable between tone and pulse dialing
(make/break ratio: 32%/68%) with ten 18-digit
number memory storage. TONE OUT
o PULSE OUT
ROWl
ROWz
• Features ROW3
1. Switchable between DTMF tone dialing and ROW.

pulse dialing modes HKS
2. Stores ten 18-digit telephone number memory MUTE
including a redial memory MODE
2 of 8 matrix keyboard
5. Make/Break ratio: 32%/68% Top View

pulse dialing mode
7. A 3.579545MHz color burst crystal can be
---~----SHARP-'--'------
773
Pulse/Tone Dialer- CMOS LSI LR4802
• Block Diagram
Hool> Switch
18 Tone Output
Mode Select
17 Pulse Output
Col_ """ { ,
Test
Column Input
11 Mute Output
Oscillation Input 8
Oscillation Output 9
Von GND
• Pin Description
Signal Name Symbol 110 Function
V DD Power supply
COL 1 -COL 4 COL 4-string key input
Key input I
ROW 1 -ROW 4 ROW 4-string key input
GND Ground Negative power supply pin.
OSCIN Oscillator I
OSC OUT connection 0
V DD 20-pps pulse dialer
MODE Mode select I
Open lO-pps dialer
MUTE Mute 'output 0 Sending of MUTE signal

V DD On-hook mode
Open On-hook mode
GND Off-hook mode
PULSE OUT Pulse output 0 Sending lOOpps or 20pps pulse signal.

TONE OUT Tone output 0 Sending of DTMF tone signal.
774
• AC Characteristics (Ta=25"C).

Key debounce time tDB 4 32 ms 10
10
Pulse rate PR
20
pps r-1L
12
13
Interdigital pause time t IDP 1000 ms
14
Mute overlap time t MOL 2 4 ms
Predigital pause time t pDP 40 ms 13
Tone output rate tOR 220 ms
Note 9: When crystal oscillation element with characteristics Rs= 1000, Lm=96mH,
Cm=0.02pF, Ch=5pF, f=3.579545 MHz is used.
Note 10: Key input is accepted after oscillation begins if valid after tOB.'
Note 12: Connect the MODE pin to VDO.
Note 13: During 10·pps pulse mode (112 during 20·pps mode).
Note 14: 100 ms during DTMF mode.
• Timing Diagram
(1) Pulse mode

m
input [IJ inpu;..:.t_ _ _ _ _ _ _ _ _ _~I~R-=E=D_=;I~A=L:.I-in...:p-u-t_ _ _ _ _ _ _ _ _ __
Key input ~ LJ
COL scan
ROW scan ------~ - - - - - - - - - - - - -
HKS input
MUTE input
PULSE input
OSCIN Oscillator operation
(2) DTMF mode

MUTE output
TONE output
~~:RSJ
Normal dialing mode Automatic dialing mode
---......-.-------SHARP-------------
776
7
- VOl) TEST
~~~---+--~6~GND RK B R
----- 17 Type 2500 GN
12 PULSE 1-1'-;'-1-<"'- Speech network
'----"VVIr----l HK S C
R'3 3 _
r - - - - " -5t C2
4~
2 C3 LR4802
C GD
• MUTE~I~I~-+--~-+----~t--r-~ Ql
16 - S
1 2 R,
4 5 15 -
R2
14 - 10 P
7 8 9 ST R3 MODE
13 -
* 0 #RE R.
OSC
OSCn, OUT
Keyboard P T
8 9
3.579545 MHz
Connect to p' for pulse mode

Z, =lODK820 Q,=2N6660
Rl =2201W Q2=2N5401
R2 =560kO Q3=2N5550
R3 =1.5kO Q.=2N5550
R. =1500 Q5=2N5550
R5 =270kO Q6=2N5550
R6 =510 Sl, S2, S3 = Hook switch
R7 =5kO DI-D.=IN4004
Rs = 1000 D5=IN270
R9 =2000 DF IN752 (5.6V)
RlO= 100kO D7=IN914
Rll=IMO Ds=IN914
R12=lOkO
R13=4700
*1 R14=390
* 2C, =68!, F (Must be input to smooth the power supply and
prevent latch up.)
.-----~-----SHARP-.----~--...-
777
LR4803 Pulse / Tone Diqler CMOS LSI

(make/break ratio: 40%/60%) with ten 18-digit
number memory storage.
TONE OUT
o PULSE OUT
ROW!
ROW2
• Features ROW3
1. Switchable between DTMF tone dialing and ROW.
2. Stores ten 18-digit telephone number memory MUTE
including a redial memory
MODE
2 of 8 matrix keyboard
5. Make/Break ratio: 40%/60% Top View
6. Switch able between 10 pps and 20 pps in
pulse dialing mode
778
)
• Block Diagram
Hook Switch
18 Tone Output
Mode Select
Col~o j,... { , 17 Pulse Output
Test
Col umn Input
-.," '..""
til .~
Po.....:I
~. j,~. j 11 Mute Output
Oscillation Input 8
Oscillation Output 9
VDD
• Pin Description
Signal Name Symbol I/O Function
Voo Power supply
COL I -COL 4 COL 4·string key input
Key input I
ROW I -ROW 4 ROW 4-string key input
GND Ground Negative power supply pin.
OSCIN Oscillator I
OSCOUT connection 0
Voo 20·pps pulse dialer
MODE Mode select I
Open lO·pps pulse dialer
Pin connection Operati\lg mode

Voo On·hook mode
HKS Hook switch inJlut I
Open On·hook mode
GND Off· hook mode
PULSE OUT Pulse output 0 Sending of lOOpps or 20pps pulse signal

TONE OUT Tone output 0 Sending of DTMF tone signal.
- - - - - - - - - - S H A R P - - - - - . - ........ _ - - - -
779

Supply voltage VDD 10.5 V 1
Input voltage VIN -0.3-VDD +0.3 V 2
Power consumption ' PD 500 mW 3
Storage temperature Toor' -55-+150 "C
Note 2: The maximum -applicable voltage on any pin with respect to GND.
Note 3: Ta=25t

Parameter Unit
Supply voltage
• DC Characteristics (Ta=25"C)

V1L GND 0.2VDD V
Input voltage
VIH 0.8VDD V DD , V
Tone output lROW VOR RL=lkO 290 350 450 mV RMS
voltage I COLUMN Voc RL=lkO 380 450 550 mV RMS
Standby current ISB VDD=3.5V 3 6 pA 4
Operating current lop VDD=3.5V 2 3 rnA 5
Mute output current Io'L VDD =2V, VoL =0.5V 1 2 rnA 6
Pulse sync output current IpL V DD =2V, Vo=0.5V 1 rnA
Pulse leakage output current I ILKG I V DD =6V, Vo=6V 1 pA
Key pull-up input resistance RKP V Do =3.5V 100 kO 7
Key pull-down input resistance RKD Voo=3.5V 5 kO 7
Mode pull-up input resistance RMP VDo=3.5V 100 kO
Mode pull-down input
RMD VDD=3.5V 100 kO
resistance
HKS pull-up input resistance R~K Voo=3.5V 60 kO
Tone output distortion V Do ;;;;;4V, RL=lkO -20 dB 8
Pre-emphasis PE HB V Do ;;;;;4V, RL=lkO 1 2 3 dB
Note 5: All output pins in no-load condition during key input and when on hook/off hook.
Note 6: Applied to the MUTE pin.
Note 7: Resistance. when ROW pin or COL pin is 125 Hz and is scanned at high or low level.
Note 8: Unwanted frequency component corresponding to the total power of the fundamental tone signal of the ROW pin and COL pin.
/'
- - - - - - - - - - - - - S H A R P ---.-.-.-------~
• AC Characteristics (Ta=Z5"C)

Key debounce time tDB 4 32 ms 10
10 11
Pulse rate PR pps t--------
20 12
13
Interdigital pause time tIDp 1000 ms
14
Mute overlap time t MOL 2 4 ms
Predigital pause time t pDP 40 ms 13
Note 9: When crystal oscillation element with characteristics Rs=1000, Lm=96mH,
Cm=O.02pF, Ch=5pF, f=3.579545 MHz is used.
Note 10: Key input is accepted after oscillation begins if valid after tDB.
Note 12: Connect the MODE pin to VDD.
Note 13: During 10·pps pulse mode (112 during 20·pps mode).
Note 14: 100 ms during DTMF mode .
• ' Timing Diagram
( 1) Pulse mode
rn input IT] inpu~t_ _ _ _ _ _ _~_ _~I~R=E:.::D~I~A=L=-I_in..:.p...:ut_ _ _ _ _ _ _ _ _ __
Key input ~ L...J
COL scan
ROW scan ------~
HKS input
MUTE input
PULSE input
Oscillator operation Osci lator operation
(2) DTMF mode

MUTE output
TONE output
~~~:J
---~-------SHARP-------.-
781
.............
Poise/Tone Dialer CMOS LSI
~- ...... ~...,~..., ..... ......
~
.
...,~~~~ .....
LR4803
.
Rl S1
~~~~~~~--~~~~~~~o~~~~~~~~--
3-
4~
5 C2
2 C3 LR4803
C. 11
MUTE Q1
16
1 2 if;
15
4 5 R2 10 P 20pps
14
7 8 9 ST
0 ;I:
*Keydoard
13
R3
R.
OSCIN
MODE
OSC
OUT
TWO Ru
P T
8 9
3.579545 MHz
Connect to P for pulse mode

ZI =10DK820 . QI=2N6660
RI =220,1W Q2=2N5401
R2 =560kO Q3=2N5550
R3 =1.5kO , Q4=2N5550
R. =1500 Q5=2N5550
Rs =270kO Qs=2N5550
Rs =510 SI, S2, S3=Hook
R7 =5kO DI-D4=lN4004
RB =1000 D5=1N270
R9 =2000 Ds=1N752 (5.6V)
RlO=100kO D7=1N914
Rl1=1MO DB=1N914
R12=10kO
R13=4700
* 1 R14=390
*2 CI=68,uF (Must be input to smooth the power supply and
prevent latch up.)
-----~~--~.-SHARP ~--,I-------------.-
782
LR4804 Pulse / Tone Dialer CMOS LSI

with a 32-digit last number redial and the mode
(pulse or tone) memory storages_ TONE OUT
MOD OUT 2
o PULSE OUT
ROW\
ROW2
• Features ROW3
L Switchable between DTMF tone dialing and ROW.
2. The original mode in OFF HOOK state switch- MUTE
able by a pin and the mode in dialing by a
MOD SELECT
mode key
OSCOUT lO/20PPS
3. Stores a 32 -digit telephone number redial SELECT
memory and the mode memory
4. PABX pause Storage
5. Uses the single contact or 15 keys matrix Top View
keyboard
6. Make/Break ratio: 40%/60%
7. Switch able between 10 pps and 20 pps in
pulse dialing mode
783
• Block Diagram
Mode Select
Hook Switch
Mode Select
19 Pulse Output
Column Input
CI,)~
<II_
-"
" 0
Il.u
RAM
13 Mute Output
Oscillation Input 9
Oscillation Output
L-----------------~Il}-----------------------__{
lO/20PPS Select VDD

r,
Note) Be sure not to apply higher voltage than VDD to the TONE
OUTPUT pin. .
.--.--------SHARP,-----------------
784
• Pin Description
Signal Name Symbol lIO Function
V DD Power supply
COL I -COL 5 COL 4-string key input
Key input I
ROW I -LOW 4 ROW 4-string key input
GND Ground Negative power supply pin
OSC IN I
Oscillator connection Connect crystal for color burst
OSC OUT 0
Mode Level
MOD OUT Mode output 0 Pulse High impedance
Tone Low

10120PPS
10/20PPS select input I GND 10-pps pulse dialer
SELECT
V DD 20-pps pulse dialer

MOD SELECT Mode select I V DD Pulse dialer
Pin cannection Operating mode

V DD On-hook mode
Open On-hook mode
GND Off-hook mode
PULSE OUT Pulse output 0 Sending 10-pps or 20-pps pulse signal

TONE OUT Tone output 0 Sending of DTMF tone signal

Supply voltage V DD 10.5 V 1
VINI -0.3 V 2
Input voltage
VIN2 0.3 V 3
Power consumption PD 500 mW 4
Note 4: Ta=25"C .

Parameter Unit
Supply voltage V
785
Pulse/Tone Diler CMOS LSI LR4804
". DC Characteristics (Ta=25"C)
Input voltage
V 1L GND 0.2VDD Y
VIH 0.8VDD VDD V
Tone output I
ROW VOR RL=lkO, VDD =4V 300 370 500 mV RMS
voltage I
COLUMN Voe RL=lkO, VDD=4V 400 480 600 mV RMS
Standby current ISB VDD=3.5,V 3 6 pA 5
Operating current lop VDD=3.5V 2 3 mA 6
Mute output current IOL VoD =2V, VOL =0.5V 2 mA 7
Pulse sync output current IPL VDD =2V, Vo=0.5V 1 mA
Pulse leakage output current I ILKG I VDo =6V, Vo=6V 1 pA 8
Key pull-up input resistance RKP VOD=3.5V 100 kO 9
Key pull-down input resistance RKD VOD=3.5V 2 kO 9
HKS pull-up input resistance RHK VDD=3.5V 40 kO
Tone output distortion VOD~4V, RL =lkO -23 dB 10
Pre-emphasis PEHB VDD~4V, RL =lkO 1 2 3 dB
Memory retention current IMR 0.7 3 pA
Key input resistance RKS 5 KO
Note 6: All output pins in no-load condition during key input and when off hook.
Note 7: Applied to the MUTE, MOD pins.
Note 8: Applied to the MUTE, MOD, PULSE pins.
Note
Note
9:
10:
Resistance when ROW pin or COL pin is 125 Hz and is scanned at high or low level. _ _ __
.
Unwanted frequency component corresponding to the total power of the fundamental tone signal of the ROW pin and COL pin.
"
• AC Characteristics (Ta=25"C)
Parameter Symbol MIN. TYP. 'MAX. Unit Note

Key debounce time tOB 54 70 ms 11
10 pps 12
Pulse rate PR
20 pps 13
14
Interdigital pause time tlDP ",
1000 ms
15
Mute overlap time t MOL 6 ms 16
Predigital pause time tpop 40 ms 14
Note 11: Key input is accepted after oscillation begins if valid after tDB.
Note 12: 10/20 pps SELECT pin connect to GND
Note 13: 10120 pps SELECT pin connect to VDn
Note 14: During 10 pps pulse mode (1/2 during 20 pps mode)
Note 15: 120 ms during DTMF mode
Note 16: 3.5 ms during DTMF mode
786
• Timing Diagram
rn input IMODlinput IT! input ~ inputr-_ _ _.....:I~R:.:E==D==I~A=L=t-in..:p-u-t_ _ _ _ _ _ _ _ _ _ __

Key input
COL scan
ROW scan
HKS input
MUTE output
PULSE output
TONE output
MOD output
OSCIN sci ator operation Oscillator operation
Normal dialing mode i E - - - - - - Automatic dialing mode - - - - -
(When IOpps pulse mode is selected via pin 11 and 12)
Rll
T -------'VIfIr-------~
Telephone line
R-------+--....
+
Cl
6 VDD
~----+--+----;71GND SEL
11 IO/20PPS
14.!..JHKS
L----..:. TONE 1-2-J°IMr+--6.--+_ _._--£
3 - RIO
.---------4'~
5 ~ LR4804
.------:::-1
7 C3 D
.-----8~C. PULSE~I~9-~.--~-----------+-~~~t. . FI
18 Cs R6 G S
1 2 17 Rl
4 5 6 R2
"7+!8~9~C~lKH>~_~1~6
f- 15 _R3
~*~O~~lD~--~R4
Keyhoard "'9~---;i-:-:" OSCOUT
787
Pulse/Tone Dialer CMOS LSI
.......... --....- ....---...
, I
~ ...................
LR4805
LR4805 Pulse / Tone Dialer CMOS LSI,

The LR4805 is a CMOS LSI for the dialer switch-
able between tone and pulse dialing (make/break
ratio: 32%/68%) with a 32-digit redial number
TONE OUT
memory and the pulse or tone mode memory stor-
ages. MOD OUT 2 0 PULSE OUT
ROWl
ROW2
COL3 5 ROW3
• Features GND ROW.
1. Switch able between DTMF tone dialing and HKS
pulse dialing modes MUTE
2. The original mode in OFF HOOK state switch- MOD SELECT
able by a pin and the mode in dialing by a'
OSCOUT lO/20PPS
mode key SELECT
3. Stores a 32-digit telephone number redial
memory and the mode memory
Top View
4. PABX pause Storage
5. Uses the single contact or 15 keys matrix key-
board
tl. Make/Break ratio: 32%/68%
pulse dialing mode
8.A 3.579545MHz color burst crystal can be
788
• Block Diagram
Modle Select
r--------------;2~----------------------------------,
Hook Switch
Mode Select
19 Pulse Output
Column Input
RAM
13 Mute Output
Oscillation Output
L------------------{ll}------------------------(
IO/20PPS Select Voo
Note) Be sure not to apply higher voltage than Voo to the TONE
OUTPUT pin.
789
Pulse/Tone Dialer CMOS LSI LR4805,
• Pin Description
Pin Name I/O Function
Voo Power supply
COLl-COLs Key input of COL 5th row
Key input I
ROWl-ROW4 Key input of ROW 4th row
GND Ground Negative power supply terminal
OSCIN I
Oscillator connection Collar burst crystal connected
OSCOUT 0
Mode Level
MOD OUT Mode output 0 Pulse High impedance
Tone LOW

10120PPS 10/20PPS
I GND IOpps pulse dialer
SELECT select input Voo 20pps pulse dialer

,Mode select
MOD SELECT I Voo Pulse dialer
input GND DTMF tone dialer
. MUTE Mute output 0 Transmission of Mute signal

Hook switch Voo ON-Hook mode
HKS I
input Open ON-Hook mode
" GND OFF-Hook mode
PULSE OUT Pulse output 0 Transmission of 10pps or 20pps pulse signal

TONE OUT Tone output 0 Transmission DTMF tone signal

VINl -0.3 V 2
Maximum pi!! voltage
VIN2 0.3 V 3
Power dissipation Po 500 mW 4
Note 1: Referenced to GND
Note 2: The Maximum applicable voltage on any pin with respect to GND
Note 3: The Maximum applicable voltage on any pin with respect to GND
Note 4: Ta = 25't
• Recommended Operatir:tg Conditions

Parameter Unit
Supply voltage V
790
• DC Characteristics
Paramater Symbol Conditions MIN. TYP. MAX. Unit Note
VIL GND 0.2Voo V
Input voltage
VIH 0.8Voo Voo V
Tone output I ROW VOR RL= lkO, Voo=4V 300 400 500 mVRMS
voltage I
COLUMN Voc RL= lkO, Voo=4V 400 500 600 mVRMs
Stand·by current ISB Voo=3.5V 1 2 pA 5
Operating current lop Voo=3.5V 1 2 rnA 6
Mute output current IOL Voo=2V, VOL=0.5V 2 rnA 7
Pulse sink output current IpL Voo=2V, Vo=0.5V 1 rnA
Pulse leak output current iLKG Voo=6V, Vo=6V 1 pA 8
Key pullup input resistance RKP Voo=3.5V 60 KO 9
Key pulldown input resistance RKO Voo=3.5V 2 KO 9
HKS pullup input resistance RHK Voo=3.5V 30 KO
Tone output distortion Voo 2': 4V -23 dB 10
Pre-emphasis PEHB Voo 2': 4V, RL=lkO 1 2 3 dB
Memory retention current IMR 0.5 1 pA
Note 5: All output pins in no· load state, clock stationary, on· Note 9: Resistance at which ROW pin or COL pin is scanned to
hook. High/Low level by 125Hz.
Note 6: All output pins in no· load state, key input, off· hook. Note 10: Unnecessary component~ainst basic tone signal
Note 7: Applies to MUTE and MOD pins. total power of ROWand COL pins.
Note 8: Applies to MUTE, MOD, and PULSE pins.
Paramater Symbol MIN. TYP. MAX. Unit Note
Key bounce time tOB 54 70 ms 11
10 12
Pulse rate PR pps r---
20 13
14
Interdigital pause time tIDP 1,000 ms
15
Mute overlap time tMOL 6 ms 16
Pre·digital pause time tpop 40 ms 14
Tone output rate tOR 220 ms
Note 11: Key input is accepted tOB after oscillation starts, if

effective.
Note 12: 1O/20pPs SELECT pin connected to GND.
Note 13: 10120pPs SELECT pin connected to Vo~.
Note 14: 10pPs pulse mode (1/2 in 20pPs pulse mode).
Note 15: 120 ms in DTMF mode.
Note 16: 3.5 ms in DTMF mode.
-.-----..-~-SHARP-.-.-.--.---
791
• Timing Diagram
rn input IMODI inputlIl input~ inputr--_ _ _~IR:.:;E=D=I~A=L=I~in...:p-u-t_ _ _ _....;........_ _ _ _ __

Key input
COL scan
, ,
ROW scan
HKS input
MUTE output
PULSE 'output
TONE output
lOOms
MOD output
OSCIN Oscillator operation OsciI ator operation

(10pps at pins 11 and 12, on pulse mode select)
Rll
T
D?,: Ds
81
Telephone line
R
~D6
~R3
~
.. ,
..:J Rg ckRI
Rs
. Z2
~
Q. R2
D. ~ tf
-~~,
Qs
+ D3
ZI ~~ Z~CI 1
121
6 VDD MOD R8 IRRB R GNI
GND SEL R7
~ 10/20PPS
Si ;:r 83
14 20 RIO
V Q3
: 2500 type speech
IL C __________
network
:
I
HKS TONE
,
~
3- lk.o
4 S D2 DI
5~ LR4805' R.
7 C3 D
19
I
1 2 3 A RED·
IP
8 C.
18 CS
RI
PULSE
I! j:{6
G S
FI
4 5 6 B P
7 8 g C IIIJ
17 R2
16
15 R3
MUTE 13
MODOUT ~
LED i a.
.... Q2
* 0 :j:j:n R4/ 0SC IN.f'-. 2 1 .

Keyboard
91 1m 110 OSCOUT
3.579545MHz
QI = 2N5401 R, = 1'00kO Rs = 220k.o (YoW) Rg = 10M.o Z, = 5.6V: 1N752 Zener Diode

Q2 - Q s = 1N5550 R2 = 3kO R6 = 120kO RIO = 1kO Z2 = 110V : 1N5379
CR I = CR033 R3 = 470kO R7 = 2,5kO Rl1 = 22.0 (W) S, - S3 = Hook Switch
DI - DB = 1N4004 R. = 1000 RB = 3.30 C I = 681'F
FI = 2N6660
~'--'-"-----SHARP----'------·--
792
Pulse/Tone Dialer CMOS LSI LR4806B
LR4806B Pulse / Tone Dialer CMOS LSI

• Description
The LR4806B is a CMOS LSI for the repertory
• Pin Connections
TEST 1
dialer switchable between tone and pulse dialing. MOD OUT
It offers one-touch dialing of up to 21 numbers, 10/20 pps
0 M/B
last number redial and other features. MOD 3 OSCOUT
MUTE 4 OSCIN
COL,
COL2
• Features ROWs 7 COL3

ROW. S COL.
1. Switchable between DTMF tone dialing and
ROW3 COLs
pulse dialing modes
2. The original mode in OFF HOOK state switch- ROW2 COL6
able by a pin and the mode in dialing by a ROW! COL7
mode key KEYTONE COL.
3. Stores twenty 16-digit telephone number mem- PULSE OUT VDD
ory and recalls by one-touch in the same mode GND TONE OUT
as the storing mode Top View
4. Stores a 32 -digit telephone number redial
memory and the mode memory and can clear it
arbitrarily
5. Switchable for pulse ratio (10pps/20pps) and
for make ratio (33%/37%) in pulse dialing
mode
6. Hooking control input applied to on-hook dial-
ing and speakerphone
8. Auto-repeat dialing function/ (In other party's
absence, repeats recalls automatically at con-
stant intervals)
9. Flash signal output
--------SHARP--------
793
MOS ICs/LSls
CMOS Gate Array -LZ92 Series
--~~--.-.-~~~-.-.~~-~-
,
LZ92 Series CMOS Gate. Array \
• Descripition • Feature.
The LZ92 series employs the lastest silicon-gate 1. Short developing time
CMOS technology, and features high speed and low' 2., Low development cost
power consumption. 3_ Suitable for ralatively sin all volume production
The LZ92 series uses a single + 5V power but large variety of special-purpose LSIs
source, allowing a wide operating voltage range, 4. Abundant series (for 300, 450, 600, 800,
and having a TTL-level 110 interface. 1000, 1500,2200, 3000,4000, and 5000
The basic internal gate operates in a time delay gates)
of 2.8ns. Ten series are availa-ble depending on the
number of gates: LZ92300, LZ92450, LZ92600,
LZ92800, LZ921000, LZ921500, LZ922200,
LZ923000,LZ924000 and LZ925000.
As development is supported by CAD system,
reliable development of special purpose LSI is
possible in a short time. In choosing a series, con-
siders that 90 % of the internal gate can be used.
• LZ92 Series Device List
Model
LZ92300 LZ92450 LZ92600 LZ92800 LZ921000 LZ921500 LZ922200 LZ923000 LZ924000 LZ925000
-Parameter
No, of gates (as counted in terms
300 450 600 816 1010 1500 2240 3145 4009 5000
of dual-input NAND gates)
No. of I/O buffers 37 45 51 61 67 83 97 112 128 140
Total No. of pins 40 48 54 64 70 86 100 120 136 150
110 level TTL/CMOS level
Internal gate 2.8 ns per gate (F.0.=3, wire length 2mm)
Delay time Input buffer TTL input 4,5ns/CMOS input 4.0ns (F.O.=3, wire length 2mm)
Output buffer 4.5ns (CL=20pF)
Supply voltage 5V±5% (TTL interface)/5V±10% (CMOS interface)
Internal gate 25,uW/gate (F.0.=3, wire length 2mm, f=lMHz)
Power, consumption Input buffer 32,uW/gate (F,0.=3, wire length 2mm, f=lMHz)
Output buffer 600,uW/gate (f=lMHz, CL=20pF)
16,18,20 16,18,20 18,20,22 18,20.22 22,24,28 24,28,30
22 24 28 24 28 30 24 28 30 24,28,40
DIP ~,~,~ ~:~:~ ~:~:~ ~:~:~ ~,@,~ @,~.~ M 40,64 64 64
~,@ ~ M M ~.M M
44,48,60 60,64.76
Package 36.44.48 36,44,48 44,48,60 64,76,80 76,80,*96 76,80,*96
QFP 36.44,48 36,44.48 64,76,80 80,96
60 60,64 64,76 96.100 100 100
96 100
SOP 24 ' 24 24 24 24
PGA 120 120.144 120,144,180
DIP: dual-in-Iine package SOP: small-out-Iine package * Limited to 18 X 18 mm square type,

QFP : quad-flat package PGA : pin-grid array
-----------SHARP.--.-.--------
796
CMOS Gate Array LZ92 Series

Paramater Symbol Ratings Unit
Supply voltage Vee -0.3-7 V
Input voltage VI -0.3-Vee+0.3 V
Output voltage Vo -0.3-Vee+0.3 V
Operating temperature Topr -10-+70 QC
Storage temperature Tstg -55-+150 QC

TTL level CMOS level
Supply voltage Vee 4.75 5 5.25 4.5 5 5.5 V
Operating temperature Topr -10 +70 -10 +70 QC
• Electrical Characteristics (Vee=5V±5%, Ta=-10-+70"C)
TTL level CMOS level

Paramater Symbol Test conditions Unit
Input low voltage VIL 0.8 1.5 V
Input high voltage VlH 2.0 3.5 V
Output low voltage VOL IOL=4mA ( 0.4 0.4 V
Output high voltage VOH IOH=-2mA 2.4 4.0 V
Input leakage current iIL Vl=OV-Vee -10 10 -10 10 pA
Output leakage current Ioz High impedance status -10 10 -10 10 pA
• Basic Cell Delay Time (1 ) Logic cells

The following figure shows typical propagation Logic cells such as inverters, NAND gates, and
delay times of a three-input NAND gate, two-input NOR gates, and composite gates such as latches
NAND gate, and inverter each configured with and flip-flops are available in 81 cell types.
basic cells. (2) Input/output buffer cells
Buffer cells used in the periphery of a chip are
10r----------------------------, available in 6 types of write-only buffers, 4 types
Vcc=5V, Ta=25"C of read-only buffers, and 4 types of read/write
Wire length = 2mm
.,
-.5
buffers: 14 types in all.
• Development of LSI Devices USing

., Gate Arrays
.~
For gate array development we provide the following:
~
.... 5 CD Design manual
c
.S
® Cell library
® Design form (2mm graph paper in A2 size)
~.
go ® Test pattern coding sheet
...
p.. ® Logic template
After completing logic design in accordance with
the design manual. please submit the following to us:
CD Logic diagram
o 2 3 4 5 6 7 8 9 10 ® Input/output timing diagrams (test data)
Fan out number ® Package specifications
® Pin configuration
797
CMOS Gate Array LZ92 Series
• Development Sequence Flowchart for Gate Array LSI
------
Presentation of
LST
Client
Logic circuit diagram

Timing chart (test data)
..;- -
!
-
Design manual
SHARP
Design manual
Design remarks
Function block
Layout
--
Cell library
specifications Package specification I Method of drawing logic
........ _ , .......
I - circuit diagrams
Method of making timing chart
! Log ic circuit
-
diagram
Tim ing chart input
~ I:
Machine write
Approval
Logical circuit
output
OK
Simulation and
approval
Critical path
assignment diagram
and specifications
1i I
L
oglca Slmu ation
' "
E
Jl
~ Approval
...'"
Q '"
OK Automated «:
positioning U
Automated layout
I -
~
Timing simulation
I
t
Writing design
specification
documents
~
I
Appr./
OK Making master
Mask making
I
- wafer
(Before
dis tribution)
Trial sample test ~
I
Sample
1 LZ92300
LZ92450
Sample making and
mass production
NG
Evaluation I I
LZ92600
LZ92800
OK
! LZ921000
LZ921500
Mass production LZ922200
Master wafer
LZ923000
LZ924000
I
LZ925000
I Delivery I-
798
CCD Image Sensor LZ2020
LZ2020 CCD Image Sensor

The LZ2020 is a CCD linear image sensor with
2,048 PN photodiode elements, two 1,024-bit ana-
log shift registers, an output amplifier and com-
pensation output amplifier on a single chip.
• Features
1. Dynamic range 54dB (TYP.)
2. Enhanced spectral response (particularly in the
blue range) and excellent output uniformity
3. Transfer efficiency 99.996%
4. 2,048 elements on a single chip; picture ele-
ment size: 14 pmX 14 pm
5. On chip output amplifier and compensation
amplifier Top View
6. All operating voltages under 15V
7.8 lines/mm resolution across a 256 mm page
8. 24-pin dual-in-line package (Ceramic)
• Block Diagram
Reset
Shift Registor Transistor Reset
Clock Output Gate Transistor
~ Gate Clock , Drain
r----U~--------~9 8}---------~5
Output
Transistor
Drain
Test
Output
Transfer 1 Transistor
Gate Source
Clock
Dummy
3 Output
Transistor
Source
~
Test Shift Resister Dummy Reset Dummy
Clock Transistor Reset
Gate Clock Transistor
Drain
-~--------SHARP-'------'-'"
799
CeD Image Sensor lZ2020

Pin voltage * VT "-0.3-+18 V
Operating temperature Vonr -25-+55 t;
Operating temperature T.t • -40-+100 t;
* Voltage applied to any pin with respect to Vss.
• Electrical Characteristics
(foil =f0l2=0.2MHz, fRs =O.4MHz, T 1nt =10ms, VoD =15V, V RD =14V, VoG =9V, VPG =l1V, Ta=25t;)

Dynamic range DR (IX2) 54 dB
Saturation exposure SE (1) 0.4 0.7 1.3 1x's
Saturation output voltage V••t (lX2) 400 550 650 mV
Sensitivity R (lX2) 0.5 0.8 1.2 V/lx-s
Photo response non-uniformity PRNU (2X3) ±7.5 ±10 %
Average dark signal ADS (2) 0 0.8 5.0 mV
Dark signal non-uniformity DSNU (2) 0 5.0 mV
Spectrum range SR 0.35 1.1 pm
Power consumption P (2) 150 mW
Output impedance Z (2) 1.0 k.o
Condition (1) : Standard tungsten lamp, 2854°K
Condition (2) : Load resistance, 1k
Condition (3) : Standard tungsten lamp, 2854 OK, with I -75 filter
(1) Photo Response Non- uniformity (PRNU)

Bit voltage non-uniformity
Within ± 3.0% relative to the previous bit
\ m I ,..-_,..- Reference
J. level .1V",= IVi-I-Vi I
U"J:~~-==t
.1V
it .1V
V'_I XI00;;o3.0%
where, i=1-2,048
Effective bits: 0-2,047, Reference level is a voltage at reset.
(2) Signal Rise Time
tl = 120ns
t 2 =100ns
t3=I60ns
The output voltage shall settle within 100ns
after ~ IA has risen above 8 volts.
(Waveform is observed with an oscilloscope.)
800
CCO Image Sensor LZ2020
(3) Output during halt period

f {> 1 =f {> 2=O.5MHz, fRS= lMHz
T 1nt =2.2ms, VoD =12V, VRD =14V, VOG=9V .
VPG =l1V, Ta=25t
The output during the halt period shall be 7mV or lower, while the output level is kept at 125mV.
Note: The test conditions (1), (2) and (3) are applicable to items (1), (2), and (3).
• Pin Capacitance (Ta=25"C)

Parameter Pin number TYP. Unit
Shift register clock 8,9,16,17 550 pF
Transfer gate clock 13 230 pF
Reset transistor gate clock 4,20 10 pF
Output transistor source 1,23 10 pF

Output transistor drain voltage VOD 14.5 15.0 15.5 V
Reset transistor drain voltage VRD 13.5 14.0 14.5 V
Output gate voltage VaG 8.0 9.0 10.0 V
Photo gate voltage VPG VPG =V,sTH+l(V) 10.0 11.0 12.0 V
Test pins 1 and 2 TP io TP 2 14.5 15.0 15.5 V
Test pins 3 and 4 TP 3 , TP 4 0 V
~ LAL> 12AL
Shift register clock, low level 0 0.5 0.8 V
~ JBL> ; 2BL
; LAU, ; 2M
Shift register clock, high level 11.0 12.0 13.0 V
; LBU, ; 2BH
Transfer gate clock, low level V PTL 0 0.5 0.8 V
Transfer gate clock, high level V"TH 9.0 10.0 11.0 V
Reset gate clock, low level VRSL 0 0.5 0.8 V
Reset gate clock, high level VRSH 9.0 10.0 11.0 V
f;LA>f;2A
Shift register clock frequency 0.5 MHz
f;JB,f;2B
Reset gate clock frequency fRs 1.0 MHz
801
CCD Image Sensor LZ2020
• Drive Signal Timing Chart

r-IE;------------T,",
¢T -Il-------------ill-------l
RS
as
Optoelectric transducing period
1 2 3 4
~~ bits
~ 2047 t,>100ns
t5 > lOOns
tl>O
tz>l,us
t3> 1,us
t/JT~
1 tl~tz~ t3r- RS
t/JIA,t/JIB~
os
2 3
>IE 1 </>1, </>z vs. </>T relationships *2 </> I, </>z vs. RS relationships
• Photo-element Structure
AI
Channel stopper
Unit: mm
• Standard Characteristics
Dark current characteristics Spectral sensitivity characteristics
2) 100
<:> 55T I
:::
.. .
.,
x
.,
! '0"
.±:
80
I
I
I
~
>.
."'=
100
v 1\
'0
-" "
> :;
>
.fr 40
60
/
-'
./
40T ./ .~
.;;
.,"
.,
50 / 1\
\
til
~
0
0; .S
.~
0
"
... 20
10
/
/
./
./
./
~t C
.:::
10
"
0::
,,-V ..........
Ul B
Ul '" 1/""""': 0 u
0.5 1.0 1.5 2.0 2.5 3.0 " 400 600 800 1,000
Integration period T S (s) Wavelength (nm)
- - - - - - - - - - - - - - - - - S H A R P - - - - - - ' - - ...........
802
I • I§
(J)
I
H
I»
3
~
+I2V
CD
I
.1~
0
::2.
I IC3A
R,=IkO
C, =500pF
R, I ;J;
+I5V <
CD
0
~r
I
~
I
I
I
lkO c:
500 ;:::;:
ICIC IC3B C,
I CKQ CKQ
IC5A IC5B
500
I
I
J J CKQ
K Q K Q
500
I IC2A IC2B
500
~N
I
LZ2020
2kO
DS0026
L_
J-- 1
X2 2
'0 Voe +15V
3
D Q
I
L
I
2kO 4
Vee 5
I 7
8
I
I
ICI
IC2,5,6
IC3
IC4
IC7,8,9
SN 74132
SN 74107
SN 7404
SN7474
SN74I61
+15V
9
10
11
12
16
15
14
13
+15V
I
I
I I
I
8I
~
h
High VOltage MOS IC LZ1008AD
LZI008AD High Voltage MOS Ie

The LZI008AD is a high voltage (300V) 8-out-
put-port monolithic Ie fabricated using Sharp's
advanced N-channel DMOS process. It can be used
as a matrix driver for electrolumiIlescent panels,
plasma display panels, electrostatic printers and
TTL-high voltage circuit interfaces.
• Features
1. High voltage 300V (MIN.)
2. Output current 35mA (TYP.)
3. Mutual conductance 10m U (TYP.)
4. TTL compatible
5. DMOS process
6. I8-pin dual-in-line package Top View
• Equivalent Circuit
Gate 1 Drain 1 Gate 2 Drain 2 Gate 8 Drain 8
L---+-----4.------4--------4-----<>-----Q Source
* leakage transistor
.-.--------SHARP-~--...-..----
804
High Voltage MOS IC LZ1008AD

Parameter Symbol Conditions Ratings Unit Note
Input high voltage BVIN Applied to input pins. -0.4-+15 V 1,2
Applied to output pins at
On·output high voltage Vo IN -0.4-+300 V 1,2
V;N=5.5V.
Applied to output pins at
Off·output high voltage Vo OFF -0.4-+600 V 1,2
VIN=OV.
Power consumption PD Ta;i25t 0.91 W
Derating ratio Ta>+25t 9.5 mW/t
Storage temperature TstR -55-+155 t
Note 2: Permanent damage will result if a voltage above the rated value is applied.

Output high voltage BV OUT VIN=OV, IOUT=20 pA 600 V
Output voltage VOUT VIN =5.5V, D=O.1 % 300 V 3
Input high voltage BV IN IIN=20pA 15 V
Threshold voltage Vp VouT=10V,louT=lpA 0.8 1.4 V 4
VIN =4.5V, VouT =300V, D=O.l% 30 35
Output current lOUT mA 3,4
VIN =2.5V, VouT =300V, D=O.l% 1.5
VIN =O.4V, VOUT=300V .10 pA 5
Output leakage current lLO
VIN =0.8V, VouT=300V / 10 pA 4,5
Input leakage current ILIN VIN =10V 1.0 5.0 pA 4
On·state resistance RON VIN =4.5V, IouT=5mA 1.0 kO 4
Mutual conductance Gm VIN =2.55V, VouT =100V 3 10 mU 4
Input capacitance CIN VIN=OV, f=IMHz 10 pF
Note 3: D(duty cycle)=O.l%, see following waveform.
ON ----------~
OFF---------~ L-__________~.
n ~.----- tl =101's
t2=10ms
J I
~1·~------;t2--------~.,
Note 4: At Ta=25't
Note 5: The value for one HVMOST output pin.
805
High Voltage MOS IC lZ1008AD
• Electrical\Characteristics Curves (Ta=25t unless otherwise specified)

)
On-state resistance vs. Ambient temperature Threshold voltage vs. Ambient temperature
C 2.5 1.5;.--_,.-----r----,-----.------,
C VOUT=5V
IouT=5mA e VOUT=lOV
~
~ 2
..
:>-
IouT=I.uA
!
~
.2l
1.5
1
~
L
..,
..!!
~
-- -----
~
~ ~
:si 115
...8Ul
., (15 .,
! ~
.......
'f' 0 Eo-< 0
~ -50 o 50 100 150 -50 0 50 100 150
Ambient temperature Ta ('C) Ambient temperature Ta ('C)
Output current vs. Ambient temperature . Input current vs. Ambient temperature
-< 60 VOUT=5V
4
---
V,,=10V
~
- r----
. VIN=5V
50
!
g 40
.. 30
il
~ 20
---r----- - ..:;
z
3
r---- ~
1
1.. 10
o 0
-50 o 50 100 150 o 50 100 150
Ambient, temperature Ta ('C) Ambient temperature Ta ('C)
Output current vs. Output voltage·

50
V,,=6V
-<
~ 40 ...- 5.5
5.0-
~
I--
-
.... :>
4.5
0
30 4.0-
1i...
!i
20 ,~ 3.5
I Ifr
3.0
10 2.5-
0 2.0
1.5
100 200 300
Output voltage VOUT (V)
----~-----SHARP-...-.-.--.---
806
LZI016AD High Voltage MOS IC

• Pin Connections
• Description
The LZI016AD is a high voltage (250V) 16-out-
put-port monolithic IC fabricated using Sharp's
advanced N-channel DMOS process. It can be
used as a matrix driver for electroluminescent
paneis, plasma display panels, electrostatic print·
ers and TTL-high voltage circuit interfaces.
• Features
1. High voltage output 250V (MIN.)
3. Internal 8·bit X 2-shift-register circuit
4. Circuit expansion capability
5. TTL compatible Top View
6. High speed data transfer (clock frequency
4MHz)
7. Single power supply: + 5V
8. DMOS process
• Block Diagram
...o
G
" --.. -
109,
Qo '"
8bits
Shift Register
NC
Truth Table
DI~ CL STB I-iVMOST
X L X OFF
X H L ON
L H H ON
H H H OFF
T '
High Voltage
Output
~'-~-----SHARP-'-'--'----"-
807
• Absolute Maximum Ratings (Ta=25'C)

Supply voltage Vee Applied to the logic supply pin. -0.3-+7 V 1
Input voltage VIN Applied to all input pin. -0.3-+7 V 1
Output voltage VOUT Applied to the data output pin. -0.3-+7 "V 1
Applied to the high voltage
ON·output high voltage ,VHVO(ON) -0.3-+250 V 1,2,4
output pin.
OFF ·output high voltage VHVO(OFF -0.3-+350 V 1,3,4
output pin.
Power consumption PD Ta~25'C 600 mW
Derating ratio Ta>+25'C 5 mW/'C
Operating temperature Toor -20-+70 'C
Note 1: The maximum applicable voltage on any pin with respect 'to GND.
Note 2: Applied when HVMOST is on.
Note 3: Applied when HVMOST is off.
Note 4: Permanent damage will result if a voltage above the started value is applied.
• DC Characteruistics
(1) HVMOST Characteristics (V ee =+5V±10%)

HVMOST "ON"
,ON·state resistance RON 650 0
IHvo=5mA, Ta=25'C
HVMOST ·ON"
Output current IHvo 40 mA 5
VHvo =250V, Ta=25'C
HVMOST ·OFF"
Output leakage current IlL I 10 pA 6
VHvo =300V, Ta=-20-70'C
HVMOST ·OFF"
Total output leakage current I hL I 30 pA 7
VHvo =300V, Ta=-20-70'C
Note 5: D(duty circle)=O.1 %, see following waveform.
ON ---------c:::Ltt
OFF ---- _ _r-L
n
. .....- - -
IE t2 .. I
tt=10ps, t2=10ms
Note 6: Value for each HVMOST output pin.
Note 7: Sum of total output leakage current.
(2) Logic Section Characteristics (Vcc =+5V±10%, Ta=-20-+70'C)

Supply voltage Icc VIN=OV 18 mA
IoH = -0.5mA; applied to
Output high voltage VOH ---- 2.4 V
Doun , DouTz.
IOL = 1.6mA; applied to
Output low voltage VOL ---- 0.4 V
Doun, Doun.
Input leakage current I IlL I VIN=OV-Vcc 10 pA
808
• AC Characteristics (V cc =+5V±10%, Ta=-20-+70t)

Clock frequency f~ 4 MHz
Clock pulse width t,., t~ 100 ns
DIN setup time t DS 60 ns
DIN hold time tDH 60 ns
LS pulse width t LP 150 ns
Clock to LS delay tCL 0 ns
LS to clock delay t LC 0 ns
DouT delay tpD CL=30pF+ 1TTL 190 ns 7
LS to STB delay t LSB 0 fLs
LS to CL delay tLCL 0 fLs
STB pulse width tsp 1 fLs
CL pulse width tcLP 1 #s
HVO fall time tpL CL=2,200pF 50 fLS 8
HVO rise time tpH RL=33kO 340 #s 8
Note 7: Applied to data output pins.
Note 8: Applied to high voltage output pins; test circuit is as follows. RL =33kO
..---+--_-.1\/"'----_ HV (300V)
Input signal conditions:
Input pulse level: + 0.8 to + 2.0V
LZ 1016 A -----4
Input rise/fall time: 20 ns
Time measurement level: 50%
• Pin Capacitance (VCC=OV, f=lMHz, Ta=25t)

Input capacitance CiN VIN=OV 6 10 pF
High voltage output
CHVO VHVO=OV 17 30 pF
pin capacitance
•. AC Timing Chart
CLOCK
L5
5TH
7
_ _ _ _ _...J,r~:---tcLP'------o~------
HV08 ~~------------ 90 %
809
. High Voltage MOS IC LZ1016AD
.......II!I!I• ......,..-....,....... . - . . . . , . . - . . . . , . . . . , . . . . , . . -_ _ _ ,._~....,....,
ON-state resistance vs. ambient Output current vs. ambient temperature.

temperature
1200 80
eL="High" eL=Pulse
~<:
Sa
.,., 1000
STB="Low
,.
/ 70 '\. STB="Low
.
z II
o 0
~!
..
800
V
/
/ <:
~
0 60 "~
"'.., :z:
'"
'" '"
... .....>
! 600
/ d 50
til
'r;; I'
......'"
...'"
'" 400
/ ..,os 40
E
'(' ios
Z 200 0 30
0
o
-100 -50 0 50 100 ISO 200
20
-100 -50 0 50 100 150 200
Ambient temperature Ta ("e) Ambient temperature Ta ('e)
Output current vs. output voltage

70
\'ee- 5.5\'
60 ~
~
5.0\'
4.5V F - -
-
#;
,
<: I--""
~ 50
..:;>
0
40 JV
Ii...
... 30
..,os
0
-=
~ 20
I
10
STB="Low
.
eL=Pulse(Note 1 )
0 200 300
100
Output voltage V HVO (V)
Note 1: The pulse described below is applied to CL.
Vee -------I=t-tl . n
GND----~ L---H---~ L
\E t2 .\
tl=IOjls, h=IOms
(D=O.I%)
-------.....-.-----$HARP . . . . - . - - - - - - - - - - -
810
High Voltage Mas IC LZ1032AM
LZI032AM High Voltage MOS Ie

• Description
The LZ1032AM is a high voltage (250V) 32-out-
put-port monolithic Ie fabricated using Sharp's
advanced N-channel DMOS process. It can be
• Pin Connections

panels, plasma display panels, electrostatic print-
ers and TTL-high voltage circuit interfaces.
• Features
1. High voltage output 250V (MIN.)
3. Internal 32-bit shift register circuit
4. Expandable circuit structure
5. TTL compatible
4MHz) Top View
8. DMOS process
• Block Diagram
Data
Output
High
Voltage
Output
Truth Table
Data
Input 6 DIN CL STB HVMOST
X L X OFF
X H L ON
L H H ON
H H H OFF
Clock Latch Strobe Clear

Strobe
811
.........................................,..............:..,....:-..............-.
HighVortage MOS IC LZ1032AM
•. Absolute Maximum Ratings (Ta=25t) .
Parameter Symbol Conditions Ratings Unit Noie

Supply voltage Vee -0.3-+7 V 1
Input voltage VIN Appliep to input pins. -0.3-+7 V 1
You;. Applied to data output pins. -0.3-+7 V 1
Oiitput voltage VHVO(ON -0.3-+250 V 1,2
~HVQLOFF -0.3-+350 V 1,3
.Power consumption
Derating ratio
" Po Ta~25t
Ta>+25"C
. 600
5 mW/t
mW

Storage temperature T't2 -55-+150 t
Note 2: . The maximum applicable voltage when HVMOST is ON.
Note 3: The maximum applicable voltage when HVMOST is OFF.
(1) . HVMOST Characteristics (V ee =+5V±10%)

HVMOST "ON"
ON·state resistance RON
IHvo =5mA, Ta=25"C
650 n
HVMOST "ON"
Drain current IHvo 40 mA 4
VHvo =250V, Ta=25"C
HVMOST "OFF"
Output leakage current IL 10 pA 5
VHvo =300V, Ta=-20-+70t
ITL HVMOST "OFF"
Output total leakage current 30 pA 6
VHvo =300V, Ta=20-70t
Note 4: Duty circle = 0.1 %. with 10,u s ON·period.
Note 5: The value for one HVO output pin.
Note 6: The total leakage current of HVO.
(2) Logic Characteristics (V ce =+5V±10%,Ta=-20-+70"C)

Supply voltage lee VIN=OV 18 mA
Input high voltage VIR 2.0 Vee V
Output high voltage VOH IoH = -0.5mA, Applied to DouT 2.4 V
Output low voltage VOL IOL = 1.6mA, Applied to DouT 0.4 V
Input leakage current IlL VIN=OV-Vee 10 pA
-----~~---SHARP~-.-..------.-....---
812
High Voltage MOS IC LZ1032AM
• AC Characteristics (Vcc=+5V±10%, Ta=-20-+70t)

Clock frequen~y f~ 4 MHz
Clock pulse width t ~, t-; 100 ns
DIN setup time tos 60 ns
DIN hold time tOH 60 ns
LS to clock delay tLc 0 ns
DouT delay tpo CL (D ouT )=30pF+1TTL 190 ns
LS to STB delay kSB 0 ns
LS to CL delay tLCL 0 ns
STB pulse width tsp 1 fls
CL pulse width t CLP 1 fls
HVO fall time tpL CL (HVO)=2,200pF, RL =33kO 50 fls
HVO rise time tpH CL (HVO)=2,200pF, RL =33kO 340 flS 7
Note 7: The output delay depends on the load condition. HV(300V)
Test conditions:
Input pulse level: + 0.8 to + 2.0V RL =33kO
Input rise/faIl time: 20 ns HVO
HVO output load. condition: See figure. LZI032AM ----i
• Capacitance (VCC=OV, f=lMHz, Ta=25t)

Input capacitance CIN VIH=OV 6 10 pF
Output capacitance CHVO VHVO=OV 17 30 pF
;
All pms except for the pm under measurement are grounded.
-----------SHARP-----------
813
High Voltage MOS IC .LZ1032AM
........... - . . -__...._ ._ _...... - . . - . . - .......-.r.-.r.-.r.-..-......
• ' AC Timing Diagram
CLOCK
DIN
DouT
LS
STB
CL
90%
Hvon
• Example of Application
The following is a thin film EL matrix panel
drive circuit fabricat~d by application of the high
voltage MOS Ie.
Note: The thin film EL matrix panel is a capacitive load.
814
High Voltage MOS Ie LZ1108AD
LZII08AD High Voltage MOS Ie /
• Description • .Pin Connections

The LZl108AD is a monolithic FET array fabri-
cated using Sharp's abvanced P-channel DMOS
process_ It provides voltage as high as 600V in
input-off state, and permits stable operation at
300V drain voltage in input on state_ It can be o
panels, plasma display panels, and electrostatic
printers.
• Features
l. High voltage 300V (MIN_)
2_ High density 8 output/package
3_ Output current 20mA (TYP_ : VHVO = 300V)
4_ High mutual conductance 7.5m U (TYP.)
Top View
5_. DMOS process
6_ I8-pin dual-in-line package
• Equivalent Circuit
Drain 1 Drain 8
Gate 8
Gate 1 o--.JVV'r-----1--I
Source o-----+----'-~~--------------+-------~-'
'Leakage transistor
815
High Voltage MOS IC
.-.~~ ..... -~~.-.~...--.~.....-~ ......... .........--'
~
(Ta=25"C)
.LZ1108AD
• Absolute PI(Iaximum Ratings

Input high voltage BV IN Appiy to input pins. -15-+0.4 .. V 1,2
Applied to the output pin,
, ON-output high voltage BVo ON -300-+0.4 V 1,2,3
/. when ViN=5.5V.
Applied to the output pin,
OFF-output high voltage BVo OFF -600-+0.4 V 1,2
when VIN=OV. I.
Power consumption PD Ta~25"C 600 mW
Derating ratio Ta>+25"C 5 mW I"C
Storage temperature T s,", -55-+150 "C
Note 1: The maximum applicable voltage on any pin with respect to S (Source).
Note 2: Permanent damage will result if a voltage above the stated value is applied.
Note 3: D (duty cycle) = 0.1 %, ON time = 10 f.ls.
• Electrical Characteristics (Ta=-20-+70"C)

Output high voltage BVOUT VIN =OV,louT =-20pA -600 V
Output voltage VOUT VIN =-5.5V,O=0.1% -300 V 4
Input high voltage BV IN IIN =-20pA -15 V
Threshold voltage Vp VOUT= -10V, lOUT = -1 pA -1.1 -1.1 V 5
V1N =-4.5V, VouT =-300V, D=O.1% -15 -20
Output current louT rnA 4,5
V1N =-2.5V, VouT =-300V, D=O.1% -1
V1N =-0.4V, VouT =-600V 10 pA 6
Output leakage current I lLO I VIN =-0.8V, VouT =-'600V 10 pA 5,6
V1N = -O.4V, VOUT= -600V 30 pA 7
Total output leakage current I hLO I VIN =-0.8V, VouT =-600V 30 pA 5,7
Input leakage current I ILIN I VIN =-10V 1 5 pA 5
ON resistance RON VIN = -4.5V, louT= -lmA 2 kn 5
Mutual conductance Gm VIN =-3.0V, VouT =-150V 3 7.5 mU 5
Input capacitance CIN VIN=OV, f=lMHz 10 pF
Note 4: D (duty cycle) = 0.1 %; see following waveform.
OFFn---- r--------, r----
ON _________ -::L:J- U h=10J'S
t2=10ms
Note 5: Ta=25"C ~1>------t2----_"'i~1
..

Note 7: Sum of total HVMOST output current.
---------------SHARP ~.-.-.--.-.--
816
• Electrical Characteristics Curves
Output current vs. Output voltage
6'......2. -60
-:;
II -50
8 VIN=-7V
<: -40
/ 6V -
-5
~
1-<
::> -30 V 5V
~
-20
V
""...... 4V
V
"
;;" -10
3V
;;'" 2V
0
o ---'200 -400 -600 -800 - 1000 -1200
Output voltage V OpT (V)
.--------SHARP--------
817
. High Voltage MOS IC LZ1116AD
LZll16AD High Voltage ·MOS Ie

•• Description • Pin Connections
The L21116AD is a high voltage (- 300V)
16-output-port monolithic Ie fabricated using S'1'1l
Sharp's advanced P-channel DMOS process. It
o CL
can be used as a matrix driver for electrolumines- DOUT2
cent panels, plasma display panels, electrostatic DIN2
printers. GND
HVOIS
HV015
HV014
• Features HV03 HV013
1. High voltage output 300V (MIN.) HVO. HV012
2. Output current 30mA (TYP. : VHVO = 300V) HVOs HVOll
3. Internal 8-bit X2-shift-register circuit HVOs HVOIO
4. Expandable circuit structure HV07 HV09
5. High speed data transfer (clock frequency . HVOg NC
4MHz) Top View
6. Single power supply: - 5V
·7. DMOS process
8. 28"':pin dual-in-line package
• Block Diagram
8bits
::ihift Register
Truth Table
DIN CL STB HVMOST
X L X OFF
X L H ON
H L L ON
L L L OFF
,
High Voltage
Output
I,
~""""'------~--~SHARP~''-'----~--''''''''''''
818
High voltage MOS IC LZ1116AD
• Absolute Maximum Ratings (Ta=25"C)

Supply voltage Vee Applied to the logic supply pin. -7-+0.3 V 1
Input voltage VIN Applied to all input pins. -7-+0.3 V 1
Output voltage VOUT Applied to the data output pin. -7-+0.3 V 1
ON·output high voltage' VHYO(ON) -300-+0.3 V 1,2,4
output pin.
OFF·output high voltage ~HVO(OFF output pin.
-300-+0.3 V 1,3,4
Power consumption Po Ta~25"C 600 mW

Derating ratio Ta>+25"C 5 mW/"C
Note 2: Ap'plied when HVMOST is ON. D (duty cycle) = 0.1 %, ON time = 10 "s
Note 3: Applied when HVMOST is OFF.
Note 4: Permanent damage will result if a voltage above the stated value is applied.
(1) HVMOST Characteristics (Vee=+5V±10%)

HVMOST "ON"
ON ·state resistance- RON 1.3 kn
IHYo =-lmA, Ta=25"C
HVMOST "ON"
Output current IHyo -20 -30 mA 5
VHYo =-300V, Ta=25"C
HVMOST "OFF"
Output leakage cUl'rent I IL I VHVO= -300V, Ta=-20-+70t;
10 p.A 6
HVMOST "OFF"
Total output leakage current I ITL I VHvo =-300V, Ta=-20-HOt;
10 p.A 6
Note 5: D (duty cycle) = 0.1 %; see following waveform.
0:: ~~~~~~ ______t=:fr----------.. . . .U

'JooEE>-------t2-----"'''"i,
tl=10"s
t2=lOms '
(2) Logic Section Characteristics (V ec =+5V±10%, Ta=-20-+70"C)

Supply voltage Icc V1N=OV -6 -12 mA
Input high voltage VIR -0.8 0.3 V
Input low voltage V1L Vee -2.4 V
IoH = -0.5mA; applied to
Output high voltage VOH ---- -0.5 V
DouTl, DOUT2
IOL = 1.6mA; applied to
Output low voltage VOL ---- -2.5 V
DOUTh DOUT2
Input leakage current IlL VJN=OV-Vee 10 p.A
--------.--------SHARP.-~~------
819
• AC Characteristics (V cc =:=+5Y±10%, Ta=-20-+70"C)·

Clock frequency fl' . 4 MHz
Clock pulse width tl', tr 125 ns
DIN hold time ton 60 ns
LS to clock delay t LC 0 ns
, DouT delay tpo CL=30pF 250 ns 7
LS to STB delay t LSB 0 ps
LS to CL delay t LCL 0 ps
STB pulse width tsp 1 ps
CL pulse width t CLP 1 ps
HVO fall time tPL CL=900pF, 15 ps 8
HVO rise time tpn . RL =20kO 60 ps 8
Note 7: Applied to data output pins.
Note 8: Appiled to high voltage output pins; test circuit is as follows. RL=20kO
~r--+--"l-""'''''
.- I
)I HV(-300VI
Input signal conditions: LZll16AD 1 ___
Input pulse level: -2.0 to -0.8V CL=900pF
Input rise/fall time: 20 ns GND
• Capacitance (Vcc=OV, f=IMHz, Ta=25"C)
Parameter Symbol Conditions MIN. T¥P. MAX. Unit

Output capacitance Cnvo Vnvo=OV 17 30 pF
CLOCK
LS
-~l-<-- t LSB
STB ~-------------tsp------------~~
CL - __________-JI1-'--------------tCLP------"'·~·-;.ll I~---- ___________

PL
HV08
~
. ~''7 %
1_0_%_o_.____________________--J~
..
.-....-------~--SHARP--".---------
820
LZl132AM High Voltage MOS Ie

The LZ1132AM is a high voltage (300V) 32-out-
put-port monolithic Ie fabricated using Sharp's adva-
nced P-channel DMOS process. It can be used as a
matrix driver for electroluminescent panels, plasma
display panels, electrostatic printers.
• Features
14 HV03
1. High voltage output 300V (MIN.) 1 HV02
2. Output current 30mA (TYP. : VHVO = 300V)
3. Internal 32-bit shift register circuit
4. Expandable circuit structure
4MHz) Top View
6. Single power supplJ! : - 5V
7. DMOS process
• Block Diagram
Data
Output
High
Voltage
Output
Data
Input Truth Table
DIN CL STB HVMOST
X L X OFF-
X L H ON
H L L ON
8 L L L OFF
Latch Strobe Clear
Strobe
-------------SHARP - - - - - - - - - - - . . -
821

SUpply voltage Vee -7"':"+0.3 V 1
Input voltage VIN Applied to all input pins. -7-+0.3 V 1
VOUT Applied to the data output -7-+0.3 V 1
Output voltage VHVO(ON -300-"""0.3 V 1,2
iVHVo(OFF -350-+0.3 V 1,3
Power consumption Po Ta~25"C 600 mW
Derating ratio Ta>+25"C 5 mW/"C
Operating temperature Top; -;-20-+70 "C
Note 2.: The maximum applicable voltage when HVMOST is ON. D (duty cycle) = 0.1 %, ON time = 10 ps
Ndte 3: The'maximum applicable voltage when HVMOST is OFF. .
(1) HVMOST Characteristics (V ee =-5V±10%)

HVMOST "ON" ,
ON -state resistance RON 1.3 n
IHvo =-lmA, Ta=25"C
HVMOST "ON"
Output current IHvo -20 -30 rnA 4
VHvo =-300V, Ta=25"C
HVMOST "OFF"
Output leakag~ current I IL I VHvo =-300V, Ta=-20-t70'C
10 /LA 5
HVMOST "OFF"
Total output leakage current I ITL I VHvo =-300V, Ta==20-70'C
30 pA 6
Note 4: Duty cycle = 0.1 %, ON time = 10 ps

Note 5: Value for each HVMOST outPllt pin.
(2) Logic Section Characteristics (Vee=+5V±10%, Ta=-20-+70"C)

Supply voltage Icc VIN=OV -8 -16 rnA
Input high. voltage - VIH -0.8 0.3 V
Input low voltage VIL Veee -2.4 V
Output high voltage VOH IOH=-0.2mA; applied to DouT -0.5 V
Output low voltage. VOL IOL = 1.6mA; applied to DouT -2.5 V
Input leakage current IlL VIN=OV-Vee 10 /LA
i j
---------------SHARP . - . - . - - - - - - . - . - .
822
High Voltage MOS Ie LZ1132AM
• AC Characteristics (Vcc=5V±1O%, Ta=-20-+70"C)

Clock frequency f~ 4 MHz
Clock pulse width t", t" 125 ns
DIN hold time tOH 60 ns
LS to clock delay tLc 0 ns
DouT delay tpo CL (DouT)=30pF 250 ns
LS to STB delay kSB 0 ns
LS to CL delay t LCL 0 ns
STB pulse width tsp 1 ps
CL pulse width tcLP 1 ps
HVO fall time tPL CL (HVO)=900pF, RL=20kO 15 ps'
HVO rise time t pH CL (HVO)=900pF, RL =20kO 600 ps 7
Note 7: Output delay time varies depending on load condition. HV (-300Vi
Test conditions: RI =20kO

Input pulse level: -2.0 to +0.8V HVO
Input rise/fall time: 20 ns
LZl132AM -----I
HVO output load conditions (figure at right). Tel =900pF
7Ir
• Capacitance (VCC=OV, f=lMHz, Ta=25"C)

Input capacitance CIN V1N=OV 6 10 pF
Output capacitance CHVO VHVO=OV 17 30 pF
All pins except pin being measurement are counnected to GND.
CLOCK
LS
-<>+--+>- t LS B
STB ~-------------tsp------------~~
CL _ _ _ _ _ _ _ _ _ _ _ _- J~-------------tCLP------------~~I~ _______________
, 1
PL
7tPH90%
HV032
~_O_?~______________________ --J'
--------------SHARP------.---~
823
Electroni'c Melody Generator CMOS LSI LR3461
'LR3461 Electronic Melody Generator CMOS LSI

The LR3461 is a CMOS LSI with melodies and
alarm functions. It can be used in music boxes
and alarm sound generators.
NC
T3 2
o VDl)
OSCIN NC
OSCoUT 4 MH
• Features MA ML
1. Melody with accompaniment SI
2. Mask ROM programmable S02
3. 8 melodies (3-melody select inputs) SOl
4. Loudness volume control function EV2
5. Melody envelope controlled by external CR cir-, EVI
cuit
T2
6. CR controlled oscillation system (with external
resistor)
7. Single power supply: -1.5V Top View
8. CMOS process
9. 22-pin\dual-in line package
• Block Diagram
1 Vss(OV)
c., c ..., ..., '--v---'.

~
0
~
0 8 8'" ""
8 "'~
= ~ ~ ~1j"
OJ Q) OJ "S Q,) .~ 1"S
.,.... """
"0
o
Q)~ "" 0 cu
..........
~
.
-~
"
0-
.£
>
Q)
~~
" 6.
[go
8_
o ., ~;; ~o-< ~o "0
0
.,~
::;;cii
..
.... "i"'ii
~(/J
,:: .. =
-~ ~
" > o ""
,,~
~~ ::;;0 ""
<~ "=
<0
824
Electronic Melody Generator CMOS LSI LR3461
•, Absolute Maximum Ratings

Pin voltage * 1 VTl +0.3--3.0 V
Pin voltage * 2 VT2 +0.3-Voo-0.3 V
• 1: Applied to Voo pin. Referenced to Vss.

• 2: Applied to pins other than Vss and Voo. Refers to the Vss pin.
Parameter Symbol Specifications Unit

Supply voltage VOOa -2.0--1.2 V
Ext. resistor for OSC Rs 390±5% kO
• Electrical Characteristics (VOO= -1.5V, Ta=25"C)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit Note

VIH -0.3
Input voltage V
VIL -1.2 1
IIH! VIH=OV 2 10 pA
Input current
IIH2 VIH=OV 10 200 pA 2
IOHl VOH=-0.5V 250 pA 3
IOH2 VOH=-0.5V 3
pA 4
IOL2 VOL=-lV 3
Output current IOH3 VOH=-0.5V 5
pA 5
IOL3 VOL=-lV 200
, IOH4 VOH=-0.5V 200
pA 6
IOL4 VOL=-lV 5
loos Standby state with no load 3 pA
Supply current
100. Melody ON with no load 1 rnA
Note 1: Applied to ST, SI,S3, and MA pins. Note 4: Applied to SO, and S02 pins.
Note.2: Applied to SI pin when melody is OFF. Note 5: Applied to ML pin; Iou is for melody OFF.
Note 3: Applied to EVI and EV2 pins. Note 6: Applied to MH pin; IOL is for melody OFF.
• Melody Specifications length of notes is controlled with "1" and "0".

<No. of tunes) Max. 8
<R 0 M) 600 steps x 13 bits
<Sound source> 2 channels J= J:i(1)+ J:i(0) ................................. 2 steps
J. =J:i(1)+J:i(0)+J:i(0) ...................... · 3 steps
)! = J:i (1)+ J! (0) ................................ 2 steps
Numbers given in parenthese provide envelope
control.
<No. of repeated plays> 1 to 15 endless
Note: given in parentheses are output only for
(A single play with auto stop can be specified by
attack sounds.
connecting the T3 input to Voo, overriding the num·
<Tempo> Variable at 15 steps each (minimum
ber of repeated plays specified in ROM.)
length of note is selectable between 31
(Command types) Melody command
and 468 ms.)
<Length of notes> 2 types (other types are made
Control commands --c
C
Jump command
Set Repeat Count command
available by controlling step
End command
count.)
If the shortest note in a tune is J!, the two types
of note, J! and J:i, can be specified in a step. The
----~-.-----.---SHARP ----------------
825
,.-_ ......
<Command configuration>
_-_....- ............__
Electronic Melddy.Generator CMOS LSI
<Melody Start / Stop>'

:.-.,. .._....,...., LR3461
CD' One shot type (repeat 1-15 times)

, Main melody tones
Main melody envelope control
Accompaniment tones Start input ST -1'l'--____-.-...n..____
Accompaniment envelope control
Length-of-note control
Mode input MA ------------L.J
<Music &~lection> Melody output ON
One of eight pieces of music is selected by the OFF
status of the music select input S1 to S3. Since Auto stop Forced stop
these inputs are provided with pull-down resis- ® Hold type (repeat -1-15 times)
tors, they may be connected to Vss or be left open.
If the status of the music select input is changed S tart input S T
during play! the newly selected piece of music will
be played from the beginning at that point. Mode input MA _ _ _ _ _ _ _ _ _ _ _ _ __
LR3461(A version of the LR3461 into which
ON
the following pieces of music have been written in Melody output
at Sharp:) OFF
Auto stop Forced stop
S1 S2 S3 Music Remarks ® Hold type (endless)
H H H For Elise Beethoven
L H H Lorelei German song Start input S T --1
H L H The Smith in the Village Japanese children's song
Mode input MA _ _ _ _ _ _ _ _ _ _ _ _ __
L L H Romance of Love Spanish song
H H L Sakura Sakura Japanese old folk song
Melody output ON --1
L H L Annie Rolley Scottish song OFF /L--
H L L Green Sleeves English fork song Forced stop
L L L Cuckoo German song
H: Vss,~: VDD or open (specifies endless for all the

pieces.)
LR34611
o
33pF
+ Tn: 2SC1383
Trz: 2SA683
826
\
Electronic Melody Generator CMOS LSI LR3462
LR3462 Electronic Melody Generator CMOS LSI

The LR3462 is a CMOS LSI with melodies and
alarm function.
S, ST
S2
0
MA
S3 OSCOUT
• Features T, OSCIN
1. Mask ROM programmable Vss T3
2.8 melodies (3-melody select input)
T2 VDD
3. Capable of driving piezo-electric buzzer
NC NC
4. CR controlled oscillation system (with external
resistor) NC so
5. Single power supply: -1.5V NC so
6. I8-pin dual-in-line package
Top View
• Block Diagram
Oscillator Programable
Circuit Counter
Tempo
Control
Circuit
Melody Control
Melody Melody Output
Jump, Repeat
Generator Control Circuit
Start, Stop
. - . - . - - - - - - S H A R P - - - - - - . - .......... ....,..----..
827
Electric Melody Generator CMOS LSI . LR3462

Pin voltage VTl -0.3-+0.3 V 1,3
Pin voltage VT2 VTI -0.3-+0.3 V 2,3
Operating temperature T~Dr -10-+50 "C
Note 1: Applied to VDD pin.
Note 2: Applied to pins except Vss, VDD.

Parameter SYJJ.lbol MIN. TYP. MAX. Unit Note
Supply voltage Voo -2 -1.2 V
Note 4: The variable resistance Rsexternally attached between pins 15 and 16 varies between 0-
,1MO. When variance in the oscillation frequency between pins is permitted, use a fixed
resistance Rs =680kO ± 5%. (Note that when measuring the OSC OUT signal, variations in
the oscillation frequency may be caused by theinput impedance of the measuring device.)
• Electrical Characteristics (V oo =-1.5V, Ta=25"C)

VIH -0.3
Input voltage V 5
VIL -1.2
Input current ITH VIH=OV 2 10 pA
IOH VoH =-0.5V 800
Output current pA 6
IOL VOL=Voo+0.5V 800
I~os Standby, no·load 3 pA
. Current consumption
Ioo. Merody ON, no-load 1 mA
Note 5: Applied to pins ST, g, S2, S3, MA
Note 6: Applied to pins SO, SO
------~----SHARP ---.-.--------.-
828
Electric Melody Generator CMOS LSI LR3462
• Melody Specifications
<Number of melodies> Max. 8 value in parentheses ( ) : envelope control
<ROM> 600 steps <Times played> 1 to 15 or endless (by con-
<Sound source> 1 sequence necting the T 3 input to V DD, the melody can
<Sound range> 2.5 octaves be set to play once and then turn off auto-
<Tempo> 15 steps each (select matically.)
mlllimum note length <Commands> Melody commands
<Note length>
between 31 and 468
ms)
2 types (lengths other
Con t ro I
comman s
d -E Jump command
.
TImes repeat command
End command
than these are realized <Melody selection> One of the eight melodies is
by the number of steps) selected depending on the state of the melody
Example: When the longest note in the melody selection inputs Sl-S3. The melody selection
is p, the two types of notes that can be spe- input pins have a built-in pull-down resist-
cified for one step are ) and P. The length ance, so they can be connected to Vss or used
of notes is controlled using "1" and "0". open. When the state of the melody selection
J = P (1) + P (0) .................... 2 steps inputs changes during play, the melody speci-
J. = P (1) + P (0) + P (0) .......... 3 steps fied is played from the first.
Po = P (1) + }l (0) ..................... 7 steps
<Melody start and stop>
(1 ) One shot type (repeats 1 to 15 times)

Start input ST ~_ _ _ _ _ _ _ _ _ .....In'-_____
Mode input MA
Melody output ON
OFF
I
---.I
/' /'
L
(2) Hold type (repeats 1 to 15 times)
S tart input S T
Mode input MA
ON ,------,
Melody output
OFF -.J
I
/I' /'
L
(3) Hold type (repeats indefinitely)
~
S tart input S T
L
Mode input MA
Melody output
ON
OFF
'~
r-------------~
/
L
Forced stop
---.-----SHARP--------~
829
Electric Melody Generator CMOS L_SI LR3462
!
LR3462
• LR3462! (LSI with melodies written by Sharp)

Sl S2 Ss Melody
H H H When the Saints Go Marching in
L H H Twinkle Twincle Little Star
H L H Bridal March
L L H Silent Night
H H L o Sole Mio
L H L For Elise
H L L Wedding March
L L L Jingle Bells
H: High, L: Low
8~O
Voice Synthesizer CMOS LSI LR3681
LR3681 Voice Synthesizer CMOS, LSI

The LR3681 is a voice synthesizer CMOS LSI. ~
08
gg~~S:g~22
...l
The integration of all the functions required for
generating voice output enables voice synthesizer
'systems to be easily composed.
2 DAI
NC
• Features
1. Voice output period of time: 4 - 5sec
(The voice quality is determined by the length
of voice generated)
2. Available sound sources include male, female
voices and effect sounds
5 6 7
3. Voice synthesis method is based on a wave-
form encoding system ggg888~88
4. 32K bits of data ROM on chip Top View
5. Expandable up to 128K bits of external ROM
6. Internal 8-bit of DI A converter
7. Time base: 4.19MHz crystal
8. Single power supply: - 3V
9. CMOS process
• Block Diagram
y
Address Output for Interface
to External ROM
Data Input Control
Output
.
Output Input
831
Voice Synthesiz9>r CMOS LSI LR3681

Perameter Symbol Ratings Unit Note
Pin voltage 1, Voo -6.0-+0.3 V
Pin voltage 2 VIN Voo-0.3-+0.3 V 1
Operating temperature Top'. -20-+70 °C
The maximum applicable voltage on ~in with respect to Vss.

Note 1: Applied to pins NrN g• CEo POW. DAIo DA 2• OSC'N. OSCOUT• EO,-EO g• AOI-AOs•
, BO I-B06 • and CO I -C06 • '

Parameter Symbol Specifications Unit
Supply voltage Voo -,2.7--3.3 V
Oscillator frequency fose 4.1943 (TYP.) MHz
• Electrical Characteristics (Voo=-3.0V, Ta=25t)

VlH -0.6
Input voltage V 2
VIL Voo+0.6
IlHl VlN=OV 2 30 pA 3
IIlPut current 11H2 VlN=OV 2 30 pA 4
hH3 VlN=OV 3 pA 5
IOHI VouT=-0.5V 100
pA 6
lOLl VOUT=Voo+0.5V ,100
Output current
10HZ VouT=-0.5V 100
VouT=Voo+0.5V
pA 7
IOL2 100
Of A converter bits 8 bit 8
Of A converter monotonicity Rf open 6 bit 9
Max. output voltage amplitude Vpp Rf= 20kO,C=100pF.Rf= 20kO 1 1.7 V 10
Oscillation start time Tose Voo=-2.7--3.3V 50 ms 11
Itot•• During region-wide operation 1.5 mA
kENO During standby 1 pA
Note 2: Applied to .pins ACL, Nl - N4, and EOI - E08.
, Note 3: Applied to pins NI - N8.
Note 4: Applied to pins EOI - E08.
Note 5: Applied to the ACL pin. ,
Note 6: Applied to pins AOI - A08, BOI - B06, and COl - C06.
Note 7: Applied to pinsCE and ROW.
Note 8: Applied to the built-in DA converter. Vss
Note 9: Applied to pin DA2, with resistor Rf connected to pins
DAI and DA2 left open.
Note 10: Applid to pin DAI. The difference in the output vol-
tages at DAI,VOAI (00) and VOAI (FF), obtained when
the input data to DI A converter is 00 and FF, respec-
tively is: VDAI (OO)-VDAI (FF)=Vp-p (where Rf=20
Kno1)_
Note 11: Applied to pins OSCIN and OSCOUT (Co = CG = 5 pF).
Refers to the time required for the LSI to enter the re-
Crystal : 4.l9,4~MHz ceramic oscillator
gion-wide operating status (POW rises) from the rising
edge 'of the N2 pin under standby status, CG=C D=5pF '
Note 12: Measurement circuit
832
(1) Stand-alone LSI configuration
Pressing one, out of the eight switches (N.-NB) The voice output's maximum amplitude is almost
connected to the input pins, produces the corres- equal to the supply voltage. It is amplified by a
ponding speech message. The number of connect- power amplifier to drive a speaker. A simple low-
able switches can be increased to 32 by building a pass filter (CR network, etc.) should be used to eli-
matrix with the output pins. minate RF noise.
Strobe
(2) System combined with a microcomputer The following figure shows a sample system
A microcomputer mllY be used to command the configuration in which serial data is transferred
voice synthesizer LSI to produce a specific speech from the SM-500 to pin Nt of the device:
message. The device can be readily interfaced
with the CMOS version of the SM Series.
Data transfer ACL OINOOUT
Control !--=s"'ign=al:;:.s_ _--t N,

SM-500 output N2 LR3681
Start/Stop
signals DA,
BUSY signal
LCD panel Key input Control signals
Note N2: Starts in the standby mode.
~---'-'---"""'-~SHARP----~'-'-'---
833
..........~~........... . -__,._~............ - ....... - ...........-..r.....
• Developing Procedure
The following table shows a typical procedure for developing the LR3681 with customized specifications:
Parameter Description Responsible Party
1 System specs Determines the 1/0 formats for the LSI, interface with microcomputer, etc. Customer
2 Synthesized voice ·tone Selects the tone from the samples provided by Sharp. CustQmer
Determination of speech Specifies the words to be written into the device, extracts common words, Customer
3
message and creates the recording manuscript. Sharp
As a rule, a professional announcer records the contents of the recording
4 Recording Customer
manuscript onto a tape, in a noise· free environment.
Checks the recorded tape for noise arid proper recording level. If any pro.b·
5 Recorded tape check Sharp
lem is found, Sharp requests the customer to. reco.rd once again.
Inputs the recorded message into. a computer, where it is subjected to voice
6 Voice analysis Sharp
analysis and data co.mpression for writing into ROM.
Writes the resulti"ng voice data into PROM, and programs the control sec·
7 ROM writing Sharp
tion for lIO and other operations.
Emulation for voice tone Emulates the PROM co.ntaining data to evaluate the tone of the recorded
8 Customer
and LSI functions voice as well as the systems operations.
If the result of emulation was positive, Sharp creates the mask for LSI
9 LSI mask generation Sharp
device.
10 TS submission Fabricates test sample devices, tests them, and submits them to the customer. Sharp
11 TS evaluatio.n Custo.mer evaluates the sample devices. Customer
12 ES submission Sharp submits engineering samples. Sharp
834
5 X 7 Dot Matrix Decoder PMOS LSI LI2048
LI2048 5 X 7 Dot Matrix Decoder PMOS LSI

The LI2048 is a PMOS LSI capable of driving 5
X 7 dot-matrix vacuum-fluorescent displays, and
displaying 128 kinds of pattern.
• Features
1. 128 patterns display
2. Direct drive of vacuum-fluorescent displays
3. Printer drive output
4. TTL level voltage drive
~~~~JJ;~J6gJgg6
Top View
• Block Diagram
Dot Select Input GND

~
Dot
Display
Output
Display/ Print S2r----....J

Select Input
.
Dot Display Output
835
....
5X7.D0t Matrix Decoder
•
.-.~...., .......---,...-..
Absolute Maximum Ratings
-~....,~---~--~ ....
.LI2048

Voo -20-+0.3 V
Pin voltage * VN -44-+0.3 V
.'VlIl, .,-44-+0.3 V
Operating temperature' Topr -5-+55 t
Storage temperature Ts... -55-+150 t
, *Referenced to GND.
• Recommeded Operating Conditions
Display voltage VN -40 V
VIH -1.1
Input voltage V
V1L -4.2
VOHl IOH=3.0mA -1.0
Output voltage VOH2 IoH =1.0mA -1.0 V
VOL VIN =-40V -36.5
100 Voo =-9.0V 8.5
Current consumption rnA
IN VN=-40V 3.0
tUl V1N =-40V 4.0
tdl No loading 5.5
Output delay time ps
tU2 VN=-40V 5.0
td2 Loading capacity; 100pF. 15.0
Input resistance RIN VIN =-40V 1.0 MO
• Function
(1 ) Dot matrix arrangement
~ ~ ~ ~ ~
@;) ~ ~ @;] ~
~ @;] ~ @;J @;]
@;] ~ @;J ~ ~
~ ~ ~ @;] ~
~ '~ ~ @;] @;]
,,'@;] ~ @;) [£;J @;J
836,
5X7 Dot Matrix Decoder Ll2048
(2) Dot data output

(i) For low CE l and CE 2 inputs.
Dot data output is determined by input Ao
-A6 •
(ii) For low CE l and high CE 2 inputs.
Dot data determined by input Ao - A6 is
stored by input A 7 - Ag and outputted as
dot data output Dil (i = 1-7) to the
printer.
(iii) For high input CEl.
No dot data output.
Input D-'L output

CEI CE 2 A7 As A9 Dll D21 D31 D41 DSI DSI Dn
1 0 0 Dll D21 D31 D41 DSI DSI Dn
0 1 0 DI2 D22 D32 D42 DS2 DS2 D72
1 1 0 Dl3 D 23 D33 D43 DS3 DS3 D73
0 1 0 0 1 D14 D24 D34 D44 DS4 D64 D74
1 0 1 D I5 D 25 D35 D45 DS5 DS5 D75
0 1 1
1 1 1 No dot data output
0 0 0
5 x 7 dot matrix fluorescent tube display
Di ; Dil (i=1-7)
e =1-7)
j=I-5
Printer
Ao Dot output
Al
A2 Vi-< -40V
A3 VDD -9V
Input
A. Ll2048 GND
As
A6
A7
As
A9
Input
837
LCD Controlier/D-riVer CMOS LSI LH5008
LH5008 LCD -Controller / Driver CMOS LSI

• _Description • Pin Connections
The LH5008 is a programmable LCD controller!
driver which interfaces in serial fashion to the
CPU of a microcomputer application system to
directly control and drive LCDs in static operation
-or dynamic operation (1/2,113 or 1/4-duty cycle).
The LH500? incorporates a segment decoder for
_generating specific segment patterns, and is also
capable of controlling the blinking of the display.
• Features
1. CMOS process
2. Number of display digits
. 7 -s~gment device
1I4-duty cycle ·········16 digits
1/3-duty cycle ......... 10% digits
112-duty cycle ......... 8 digits
Static operation········· 4 digits
• 14-segment-device
1I4-duty cycle 8 digits
3. Operating mode
Static, 112, 113, and 1I4-duty drive
4. Biasing
Static, 112 and 113
5. Segment decoder output
• 7 -segment device ; numerics 0 - 9 and 5
symbols--
. 14-segment device; 36 alphanumerics and
12 symbols
6. Blinking function
7. LCD direct drive
8. Serial input (8-bit unit)
9. Capable of multi-chip configuration
.-------------.---SHARP.,-.-.....-.-.-..-.~-
838
LCD Controller/Driver CMOS LSI LH5008
• Block Diagram
LCD
Segment Output
Synchronous
Signal Input
/Output
Segment
Output
Chip Select
Busy Output
Command/
Data Select
'-v---'
Reset Serial Serial GND
Input Clock Input Data Input VDD
• Pin Description
Pin name No. of pins 110 Connect to Functions
VDD, Vss 3 Power supply for logic circuit
Power supply
VLCI> V LC2, V LC3 3 Power supply for liquid crystal drive
SI 1 Serial data input
SCK 1 Clock input for data shift
CID 1 I MPU Datal command select pin
CS 1 Chip select pin
RESET 1 Reset input
CL l 1 Resistance Internal clock oscillation pin
CL 2 1 Resistance Internal clock oscillation pin
SO-S3l 32 Liquid crystal segment drive signal
0 Liquid crystal
COM o-COM 3 4 Liquid crystal common drive signal
BUSY 1 MPU Busy output
SYNC 1 110 LH5008 Sync. signal
.---------SHARP-.--.------------
839
LCD'Controlier/Driver CMOS LSI LHS008.

Supply voltage Voo . -0.3-+7.0 V
Input voltage VIN ~0.3-Voo+0.3 V 1
Output voltage VOUT -0.3-V oo +0.3 V
Operating temperature ' Topr -10-,+70 "C
Storage temperature J'stg -55-'+150 "C
• Recommend Operating Conditions

Supply. voltage Voo 2.7 5.5 V
R=200kn, Voo =5V±10% 130
Oscillator frequency fose kHz
R=240kn, Voo =3V±10% 100
• DC Characteristics (V oo =,5V±IO%, Ta=-10-70"C)

VIH 0.7Voo Voo V
Input voltage ,
V1L 0 0.3Voo V
I ILIH I VIN=Voo 2 p.A
Input leakage current
I ILIL I VIN=OV 2 p.A
I IWH I VOUT = Voo 2 p.A
Output leakage current
I IWL I VOUT=OV 2 p.A
IOHl SYNC; BUSY VOUT=VDD-O.5V 10 p.A
IOH2 SYNC, VouT=lV 300 p.A
Output current
lOLl SYNC, VouT=lV 900 p.A
IOL2 BUSY, VouT=0.5V 350 p.A
RCOM COM o-COM 3 VOO:<?VLCD:<?2.7V 3 7 kn
Output resistance 2
RSEG SO-S31 VOO~VLCD~2.7V 7 14 kn
Current consumption 100 No-load, external clock fc =200kHz 100 250 p.A
(V DD =?7-4.5V, Ta=-lO-+70"C)
Parameter Symbol Conditions MIN. TYP: MAX. Unit Note
VIHI Except SCK 0.7Voo Voo V
VIH2 SCK O.8Voo Voo V
· Input voltage
VILI Except Except SCK 0 0.3Voo V
VIL2 SCK 0 0.2Voo V
I ILTH I VIN=Voo 2 p.A
Input leakage current
I ILIL I VIN=OV 2 p.A
Output leakage current
I IWH I V6UT=VOO 2 pA
I ILoL I VOUT=OV 2 p.A
IOHI SYNC, BUSY VOUT=VDD-O.75V 7 p.A
IOH2 SYNC, VouT =0.5V 200 p.A
Output current
lOLl SYNC, VouT =0.5V 400 p.A
IOL2 BUSY, VouT=0.5V 150 p.A
ReoM COMo-COM 3 VDD:<?,VLCD:<?2.7V 6 12 kn
Output resistance 2
RSEG SO-S31 VDD~VLCD~2.7V 12 24 kn
No-load, ext~rnal clock fc=160kHz
Current consuinption roo 30 100 p.A
Voo =3V±10%
Note 2: Applicable to static, 112 bias. 1/3 bias; VLCD: LCD drive voltage
840
• AC Electric Characteristics (Voo=5V±10%, Ta=-10-70'C)

Operating frequency fc 50 200 kHz
Oscillator frequency fose R=200kO+5% 85 130 175 kHz
High·level clock pulse width tWHC CLl> external clock 2 16 fiS
Low·level clock pulse width t WLC CLl> external clock 2 16 fiS
SCK frequency tcYK 900 ns
High·level SCK pluse width tWHK 400 ns
Low·level SCK pluse width tWLK 400 ns
BUSY t -+SCK hold time tHBK 0 ns
SI setup time (to SCK t ) tSIK 250 ns
SI hold time (to SCK t ) tHKI 200 ns
Delay of 8th SCK t -+BUSY l tOKB Load capacitance = 50 pF 3 fiS
CS l-+BUSY l delay tncSB Load capacitance - 50 pF 1.5 fiS
C/D setup time (to 8th SCK t ) tSDK 9 fiS
C/D hold time (to 8th SCK t ) tHKO 1 fiS
CS hold time (to 8th SCK t ) tHKCS 1 fiS
High-levellCS pluse width tWHCS 8tcyc * fis
Low-levellCS pluse width twLCS 8tcyc * fis
SYNC load capacitance CLSY tcyC * =5 fiS 50 pF
* tcvc=lIfc
(Voo=2.7V-4.5V, Ta=-10-70'C)

Operating frequency fc 50 140 kHz
Oscillator frequency fosc R=240kO±5% Voo =3V±10% 50 100 140 kHz
High-level clock pulse width tWHC CLl> external clock 3 16 fiS
Low-level clock pulse width tWLC CLl> external clock 3 16 ps
SCK frequency tcYK 4 fis
High-level SCK pluse width tWHK 1.8 ps
Low-level SCK pluse width tWLK 1.8 ps
BUSY t -+SCK hold time tHBK 0 ns
SI setup time (to SCK t ) tsIK 1 ps
SI hold time (to SCK f ) tHKI 1 fiS
Delay of 8th SCK f -+BUSY l tOKB Load capacitance=50 pF 5 fiS
CS l-+BUSY l delay tncSB Load capacitance=50 pF 5 ps
C/D setup time (to 8th SCK t ) tsoK 18 fiS
C/D hold time (to 8th SCK t ) tHKO 1 ps
CS hold time (to 8th SCK t ) t HKCS 1 ps
High-levellCS pluse width tWHCS 8tcyc * ps
Low-levellCS pluse width t WLCS 8tcyc * ps
SYNC load capacitance CLSY tCYC * =6.25 fiS 50 pF
* tcyc= lIfc
841
LCD Controller/Driver CMOS LSI u:iS008
Timing measurement voltage level
______- J
X
.
O.7VDD?/-
. O.3VDD _
./O. 7VDD X···
I/ --......,..O.3VDD _ _
~------
Measurement points
Timing waveforms
t----tCyC (I/fc)--~
tWHCS
~-------------------tWLCS-------~------------~
tDCSB
- tHKCS
----. I
r----'
\
\
\ I \
O.5V I \
------.1.-
SI
eli)
________ ~~~_______________t_S_DK---------~~~~------
*1: Voo-O.5V at Voo=5V±10%. Voo-O.75V at Voo=2.7-4.5V

* 2: O.8Voo at Voo=2.7-4.5V
* 3: O.2Voo at Voo=2.7-4.5V
842
,
~ COMo -COM3
7-segment I6-column LCD
rV
50-531
{').
r-----------,
COMo-COM3 50-531
I I
VDD BUSY BUSY I
*CI I
RESET : RESET
VLCI I
C/i) C/i) I
:: C2 LH5008 Microcomputer system
CS ICS
I
I
VLC2 I
51 151
R3 ::C3 I I
VLC3 SCK SCK I
CLI CL2 Vss
IL __________ J
I
Ii" I I 1
-----~.-..-;...-----SHARP----.----.-----
843
LCD Dot Matrix Controller CMOS LSI LR3691A
LR3691A LCD Dot .Matrix Controller CMOS LSI

The LR3691A is a controller CMOS LSI for dot
matrix graphic LCD units. It stores display data
corresponding to dot patterns from the 8-bit CPU
in the external RAM. From this RAM, it transfers
the display data to the LCD driver and generates
clocks necessary to drive the LCD.
• Features
1. Controller for LCD dot matrix graphic display
2. Maximum display data = 163, 840 dots
(Horizontal X Vertical)
3. General 8-bit CPU interface
4. High -speed write cycle
5. Low frequency due to parallel output of data to
4 divisions of the LCD
6. Selectable display dots
a. The number of horizontal dots
• The LCD without right and left divisions
120,160,240,320,480,640 dots
• The LCD with right and left divisions
240,320,480,640,960,1280 dots
b. The number of vertical dots
· The LCD without upper and lower divisions
32,64, 100, 128 dots
• The LCD with upper and lower divisions
64, 12~ 200, 256,do~
7. Single power supply: 5V (TYP.)
8. CMOS process
844
• Block Diagram
Meory
Address
Output Oscillation
LCD AC Drive
Output
Display Data Shift
CLOCK
Display Data Latch
CLOCK
LCD Control
Memory Common Data Output
Timing Generator
Address
Output
Column Counter
CPU Address Counter Row Counter
Memory Data Bus Test

Supply voltage Vee -0.3-+7 V 1
Input voltage VI -0.3-Vee+0.3 V 1
Output voltage Vo -0.3-Vee+O.3 V 1
Operating temperature Topr -10-+70 °C

Input voltage VI 0 Vee V
Output low current 10L 4 rnA
Output high current lOR -500 f-lA
Clock frequency fose 0.6 6.6 MHz
Note: Any current sinks into the LSI is regarded posititve.
845
• DC Characteristics (Vcc=5V±10%,GND=OV, Ta=-10-+70t)

VaLl IOL=4mA 0.4 V 1,2
Output low voltage
VOL2 IOL=400pA 0.2Vcc V 3
VOH! IOH=-0.5mA 2.4 V 1,2
Output high voltage
VOH2 IOH=-400pA 0.8Vcc V 3
VILI 0.4 V 2,4
Input low voltage
VIL2 , 0.5 V 5
VIHI 2.4 V 2,4
Input high voltage
VIH2 Vcc-0.6 V 5
IlL! VIL=OV -20 pA 4,5
Input low current
, IIL2 VIL=OV -30 -100 pA 2
Input high current IIH VIH = Vcc 20 pA 2,4,5
Current consmnption Icc fosc=6.6MHz 12 36 rnA
MOo -M0 7 and 0 0 -0 7 are 110 pins which are pulled up by Note 2: Applied to pins MOo-M0 7 and 0 0 -0 7 ,
built·in resistors when in input mode. Note 3: Applied to pins CP" CP2. S, M. 01,-01 4 , and OSCOUT
Note 1: Applied to output pins other than CP" CP2. S, M, 01, Note 4: Applied to input pins other than OSC'N, T, andT 2.
-01,. and OSCOUT. Note 5: Applied to pins OSC'N, T .. and T 2.
(1) LCD control timing (Vcc=5V±10%, Ta=-10-+70t)
Parameter Symbol MIN. TYP MAX. Unit

CP 2 clock width tWCP2 ;-50 ; ns
Data setup time tDIS ,; -100 ; ns
Data hold time tDIH ;-100 ; ns
Clock setup time (CP! l -CP 2 l) tLc 20 ;/2 ;12+25 ns
Clock setup time (CP 2 t -CPt f) tCLD 20 ;12 ns
CPt clock width twCP! 2';-50 2; ns
Fall time of CP 1 referring to M signal tM -(~/2+100 - ;12, ; ns
Clock setup time (CP! l - S l) tsc 200 ns
Clock setup time (CP! l - S t) tcs 200 ns
Rise time of CP! and CP 2 tr 30 50 ns
Fall time of CPt and CP2 tf 30 50 ns
Measurement Conditions
~ =lIfosc(fosc=O.6-6.6MHz), CL=50pF. VOLc=O.2Vcc. VOHc=O.8Vcc
Dh-DI.
~46
(2) RAM interface timing (Vee = 5V ± 10%. Ta = -10 - +70t)

Address output cycle time tAC 2 s6 -50 2s6 2s6 +50 ns
MRD setup time (to address) tMRS 0 30 100 ns
Read data setup time tDRS 180 ns
Read data hold time tDRH 15 ns
Memory write pulse width tMWW s6 -50 s6 ns
Write recovery time tDMW 2 s6 -150 2s6 ns
Write data output delay time (to MRD t) tDDW s6 -100 s6 ns
Write data setup time tDWS s6 -100 s6 ns
Write data hold time tDWH s6 -100 s6 ns
MRD time from write data (Hz) tDWZ s6 -100 s6 ns
; =lIfosc(fosc=0.6-6.6MHz). CL=20pF. VOL=0.8V. VOH=2.0V. VIL=0.8V. VIH=2.0V. and hand tr of input signal are less than 50 ns.
MAo-MAi.
MDo-MD7 (READ)
MDo-MD7 (WRITE)
(3) CPU interface (read cycle) timing (Vee = 5V ± 10%. Ta = -10 - +70t)
WAIT output time referring to RD tRDWT 45 150 ns
WAIT rise time referring to MRD tWURD s6 -100 s6 ns
Data output delay time referring to RD tRDHZ 25 150 ns
Data output settling time referring to WAIT t tWTS 2 s6 -150 2s6 ns
Data output hold time referring to RD tRDH 0 20 ns
RD setup time referring to MA tASRD 200 ns
; = l/fosc(fosc=0.6-6.6MHz). CL=ZOpF. VOL=0.8V. VOH=2.0V. VIL=O.~V. VIH=2.0V. and hand tr of input signal are less than 50 ns.
MAo-MAl'
h~-----.lVOH
~~~______~~V~OL~-------------------
----'----SHARp.-.---.-.----.--..
847
LCD Dot Matrix Controller CMOS LSI LR3691A·
(4) CPU interface (read cycle) timing (Vee = 5V ± 10%. Ta = -10 - +70"C)
,Paramerter Symbol MIN. TYP. Mj~.x. Unit
WAIT rise time referring to MRD tWUWR 1> -100 1> ns
Data setup time referring to MWR tDSMW 1> -50 1> ns
Data hold time referring to MWR tDHMW 1> -50 1> ns
WR setup time referring to MRD tASWR 200 ns
WAIT output time referring to WR tWRWT' 45 150 ns
1> = 1/fosc(fosc=0.6-6.6MHz). CL=20pF. VOL,=0.8V. VOH=2.0V. VIL=0.8V. VIH=2.0V. and hand teof input signal are less than 50 ns.
MAo-MA14 ~_ _ _ _ _ _ _ _ _ _ >CJC
MRD VOH
VOL
• Functional Descriptions
and CPU.
(1) Power supply The RS pin specifies the type of data exchanged
The Vee pin requires + 5 VDC to the ground. with the CPU through pins Do-D7, identifying dis·
The GND pin should be externally grounded. play RAM address specification data and display
(2) Clock pulse and divider data.
The OSCIN pin of the device requires constant The data control pin signal timing is' shown in
application of a clock. A clock used for the CPU the paragraph for Electrical Characteristics.
may be used for this purpose. The OSCOUT pin, The input circuit for these control pins have
which provides an inverse of the clock applied to floating gates.
the OSCIN pin, should be left open. (5) WAIT signal
(3) RES pin and reset pulse The display RAM is accessed from both the CPU
The RES pin requires application of a reset and the LCD driver. To avoid contention, the
pulse when power is turned ON to initialize the LR3691A delivers a WAIT signal to its WAIT pin
LR3691A's internal registers. The reset pulse when the LCD driver is accessing the display
should be active high, and should have a pulse RAM, suspending display RAM access from the
width more than 4 time as long as that of the clock CPU.
pulse. " (6) Data input/output
The input circuit for the RES pin uses a floating The LR3691A exchanges data with its host CPU
gate. through its pins Do-D7. The data transferred
(4) Data control pins through these pins are display RAM address data,
The LR3691A is controlled from the host CPU display RAM read data, and display RAM write
through pins CS, .RD, WR,.and RS, The signals ap· data. The data type is specified by controlling a
plied to pins RD, WR, and RS are made valid if the data control pin. The Do-Di pins are. normally con-
CS pin is set to low. nected to the host CPU's data bus. When in the in-
The RD and.WR pins are used to determine the put mode, the Do-D7 pins are pulled up through
direction of data transfer between the display RAM pull·up resistors.
-------~------SHARP.-.-.--~---~-
848
(7) Screen division and dot number selection . CPU. Display data is written and read byte-by-
The LR3691A controls an LCD screen through byte (8 bits). When viewed from the CPU, display
LCD drivers using serial data transfer scheme RAM address alllocations to the display screen
with duty cycle of 1/32 to 1/128. The LCD address are fixed. (To facilitate data readl
screen is often divided into sections to improve write access to the display RAM and to impove
contrast and reduce driving frequency and driving availability of the RAM area, RAM addresses
voltage. are actually translated within the LR3691A befo-
The LR3691A permits division of the LCD re read Iwrite access is performed.) The first
screen into two sections both in the horizontal and addresses of the four sections on the screen are
vertical directions. The ROWand CLM pins have fixed to OOOOH, 4000H, 8000H, and COOOH. An
floating gate inputs with high impedance. example of the relationship between display RAM
(8) Connection to display RAM addresses and screen addresses as viewed from
'The LR3691A should be connected to the dis· the CPU is shown in Fig. 1, where the number of
play RAM as follows: The address data for display pixels per row on the screen is 640 (numbers
RAM is output through pins MA o-MA 14 • If th~ given in parentheses are that of 240).
display RAM consists of more than one chip, the 00) LCD driver control
address data shoud be decoded through an address The LR3691A drives an LCD dot matrix dis-
decoder before being coupled to the display RAM. play panel via LCD drivers using serial data trans-
Display dat.? is transferred through pins MDo' fer scheme. It uses its pins S, M, CPI CP2, and DII
MD 7 • The MRD and MWR pins are used to con- -DI4 for controlling the LCD driver.
trol the display RAM: the MAD pin provides a dis- The S pin provides data signal to the shift regis-
play RAM read command signal; the MWR pin pro- ter input of the LCD driver which drives the com-
vides a display RAM write command signal.' mon electrodes. The M pin supplies a signal
(9) Display screen versus display RAM needed for synchronized AC driving of the LCD
The display RAM is accessed from the CPU or driver.
LCD driver via the LR3691A. Access from the The CP2 pin drlivers a clock signal used to shift
LCD driver occurs every 32 cycles of the system display data. The CPI pin provides a display data
clock (applied to the OSCIN pin), of which one 16 latch signal. The pins DII: -DI4 otuput display data
cycle period is occupied by the LCD driver, and after converting the 8-bit parallel data from the
the remaining 16 cycle period is available to the display RAM into serial data.
o0 0 0 H
o0 0 I H
o0 0 2 H
o0 0 3 H OOOOH looohI OOOh
(OOOOH) (OOOh) I (0002 H) - - - - ----!-=:::=:!~Ti'i:T+-':-~;;"'-I__';';;7;'''+-
0028HJ0029H I 002AH
(OOOFH) (OOIOHU (OOI1H)
4 0 0 I H
,4003 H
I!
1
8000H
(8000H)
800lH
(800h)
8002H
(8002H) --
8027 H
(800EH)
COOOH
( COOOH)
CO 0 I H
(COOl H)
I co 1
I
02H
(C002H) -
~
~~_---
C027H
(COOEH)
80 00
8.0 0 I
H
H
802 S.
(800FH)
80219' H
(80IOH)
802 A H
(8011H) I C028 H
( COOFH)
C029 HI C02AH,
(COIOH) (COlh)
I
I I I I
I I I I
I
CO 0 0 H
CO 0 I H
COO 2 H (Note) Number of pixels per row is 640. (numbers given in ( ) are that of 240)
COO 3 H
I ( b) Display viewed from CPU
Fig. 1 Relationship between display RAM map and

( a) Memory map viewed from CPU
display screen as accessed from the CPU
849
LCD Dot Matrix Controller CMOS LSI lR3691A
0000.
000 1 •
0002 •
0003 •
0004.
0005.
0'006.
0007 •
0008 •
I
I
1
1
1
'I
1
I
(b) Actual display screen

( a) Actual memory map
Fig. 2 Actu~1 relationship beween display RAM map and display screen
Display RAM Display screen
/
Fig. 3 Bit-by-bit relationship of display screen and display RAM
The Dh pin provides display data for the upper • Display Control Method
left section of the display screen; the DIz pin pro, Display control consists of display data proces-
vides that for the upper right section of the screen; sing, RAM addressing, and display screen selection.
the Db pin provides that for the lower left section; (1) Display screen selection
and the DI4 pin provides that for the lower right The LR3961A drives the display screen via
section. shift·register type LCD drivers by, if necessary,
The LCD driver control singnal timing is shown dividing the screen into four sections according to
in the paragraph describing Electrical Characteris- the number of pixels (on the row and column) to be
tics. displayed. The number of pixels per row is speci-
(11) DIsplay enable fied with the CLMo-CLM2 pins. The number of
The DE pin is used to enable or disable display pixels per column (duty) is specified with the
to the screen. If set at low, the entire screen is ROW 0 and ROW 1 pins. See the following table.
blanked. Data display is enabled only when the DE
eLM No. of pixels ROW No. of pixels
pin is set at high. The DE pin is used to suppress
(2.1,0) per row (1,0) per column
meaningless information from the screen pO,wer is
000 120 00 32
being turned on. It has a floating gate input.
001 160 01 64
(12) T1 and T2 pins
010 240 10 100
The T 1 and T2 pins should be connected to the
011 320 11 128
ground. These pins, having floating gate inputs,
100 480
are used for device test and are not available to
101 640
the user.
110 unused
111 unused
.----~--~.-.--SH.A.RP , - . . - - ......... -----~-------

850
If the screen is divided into two half sections

(left and right), the displayable number of pixels
becomes twice the numbers shown in the above left
table. If the screen is divided into upper and lower Address data is transferred in two consecutive
, halves, the displayable number of pixels becomes sequences for upper and lower bytes.
twice the numbers shown in the below-right table (3) Data write into display RAM
on page 850. Data can be written into the specified display
To prevent flicker of the display image, the total RAM location. Specification is conducted by the
number of pixels per section should be limited to RAM address counter through the Do-D7 pins
40,960 of total pixels/divided screens. when the RS is set at zero.
(2) Display RAM address control
The addresses for the display RAM are
apparently specified with 15-bit address data,
Once data is written, the RAM address counter
whose output is implemented through pins
is automatically incremented, so that data may be
MAo-MA14. Meanwhile, the host CPU uses an
written consecutively.
8-bit bus, Do-D7, to address the display RAM. To
(4) Data read from display RAM
specify a full 15-bit address, the CPU must trans-
Data can be read out of the display RAM loca-
fer address data in two consecutive sequences:
tion specified by the RAM address counter. Speci-
first the lower byte, and next the upper byte. At
fication is implemented through the Do-D7 pins
this time the RS pin (address specification) should
when the RS is set at zero.
be set to '1'. Once a display RAM address is speci-
fied, it is automatically incremented each time the
CPU accesses it for read or write operation. So for
display RAM addresses which are consecutive can Once data is read, the RAM address counter is
be accessed by setting only the first address. automatically incremented.
851
~I •
!R
'I r()
C
I
I II, II
~
3 I~
- I~
J CPU , I I [:, I I ,I I , '.. o
o
:J
~--
(Z80 system) CL2 CLI M FCS~ ~CL2 CLI M FCS CLz CLI M FCS ~ fil"
-I IPS' 'PS
rl+ 5V LH5021A
/LH5022 Dil ---
LH5021A I
DO /LH5022 OI I
LH5021A IPS
/LH5022 OIl ---
a0" II
c::::
I ~J
\ Address Bus
1"1" 1"1" Y.O-YI
u
Y.O-Yl
:u;
I Y.UI Y.O-YI
u ::::J
Q.
CD
I
U
"lJ II-II FCS/PS DII'
LH5021A T,
M / LH5022 Y1--------\
I t----v'
,
CLI II
I
I I - - - - - - - - -, - - - - - / - LCD panel-- - - - - - - - - - - - - - - I ~
8
I
FCS/PS DII
) LH5021A
III I, w
M /LH5022Y ,
N RD WR RS CS DE CLI
'D I -0
CP I 1---0-1+--1-+-1---4
if o fr
I
WAIT
CP2 ~--~~
~
M YSO-YI Y.O-YI YSO-Yl
Do- D7 , LH5021A LH5021A LH5021A
I MAo- MA14
LR3691A ILH5022 0 I 1 - DO ILH5022, OIl
FCS
CL2 CLI MIPS
FCS
CL2 CLI MIPS
ILH5022 0I1-
FCS
CL CLI MIPS I
I
I
I
II
I II r
I -;:0
w
I I~
LCD Dot Matrix Controller CMOS LSI LR3692
LR3692 LCD Dot Matrix Controller CMOS LSI

The LR3692 is a controller LSI for dot matrix
graphic LCD unit. It stores display data transfer-
red from 8-bit microcomputer in the external RAM
and generates LCD drive signal suitable as serial
type LCD driver.
Selectable from graphic mode and character
mode using character ROM for character display.
• Features
1. Graphic or character mode selectable
2. Display duty: 1132 - 1/256
3. Maximum display capability
Graphic mode : 640 X 256 dots
Character mode: 80 X 32 characters
(if character font is 8 X 8)
4. Capable of interfacing to an 8-bit CPU
5. Serial! 4-bit parallel output
6. Capable of driving upper and lower divisions DTMG 24 0
LCD 25 26 2
7. Scroll function
8. Cursor display: ON, OFF, and BLINK
9. Character BLINK
10. Display ON, OFF
11. On -chip crystal oscillator
12. Single power supply: 5V (TYP.)
13. CMOS process
11
...--------------SHARP - . - . - - - - - - - - - - -
853
__ .. _.~~"";.-.-..-.-..-.....,..-.r. ____ .~.-~.-
• Block Diagram
Dot a Register
Upper Screen Upper Screen
Display Start Address Counter
pper Screen Lower Screen
Display Start Address Counter Memory
Address
Latch Pulse Period Cursor Address Output
Cursor Position Register
Display Duty·
Character Numher ~
Register Select
Chip Select
Display OFF Input 25
®}
:
71
73
Memory
Data Bus
. Memory Read
Read Input 61 Output
Write Input
Display RAM
Select Input
Display Timming
Output
Busy Output
.
GND
854

Supply voltage Voo -0.3-+7 V 1
Input voltage VIN -O.3-Yoo+O.3 V 1
Nate 1: The maximum applicable voltage on any pin with respect to GND.

Parameter Unit
Supply voltage V
• DC Characteristics (Voo=5V±5%. Ta=0-+50"C)

Input low voltage VILT 0 0.4 V 1
Input high voltage VIHT 2.4 Voo V 1
Input low voltage VilC 0 0.2VDO V 2
Input high voltage VlHC 0.8Voo VOD V 2
Output low voltage . VOLT iOL=2.0mA 0.4 V 3
Output high voltage VOHT IOH=l.OmA 2.4 V 3
Output low voltage VOLC iOL=0.6mA 0.4 V 4
Output high voltage VOHC IOH=0.6mA YDo-O.4 V 4
Pull-up current III VIN=OV 10 pA 5
Supply current IOD fosc = 4MHz
Oscillator frequency fose With crystal oscillator 4 MHz 6
Ext. clock frequency fCl 0.2 4 MHz 6
Ext. clock duty Duty 47.5 50 52.5 % 6
Rise time tRCL 50 ns 6
Fall time tFCL 50 ns 6
!
Note 1: Applied to pins MDo -MD7. RIo-RI? Do·D7. CS. RS. CEo WR, RD. and DOFF.
Note 2: Applied to pins TEST and CGIN. __ __ ~_
/ Note 3: Applied to pins MAo-MAI5. MDo-MD7. MWR. MRD,'Do-D7. BUSY, and DTMG.
Note 4: Applied to pin's CLIo CL 2• S. DUO-OU 3• DLo-DL3. and M. _ _ ~ _ ~_
Note 5: Applied to pins TEST. MAo-MAI5. MDo·MD7, RIo-Ri? Do-D7. CS. RS. CEo WR. RD. and DOFF.
Note 6: Applied to pins CGIN and CGOUT.
855
19D Dot Matrix Controller CMOS lSI lR3692
(1) LCD control signal (Vcc=5V±5%, fosc=4M!Jz, CL=15pF, Ta=;oO-+50"C)
Parameter I Symbol Conditions MIN. TYP. MAX. Unit

Data setup time tsn 100 375 ns
Data hold time tHn 50 125 ns
Clock pulse low width twLC 150 250 ns
Clock pulse high width tWHC 150 250 ns
Clock cycle time tWCL2 500 ns
Clock delay time tOCLl 0 125 ns
Clock pulse width tWCLl 2 4 ps
Clock delay time tOCL2 0 135 ns
Data delay tillie tnM 500 ns
Data hold time tHS 2 ps
Data setup time tss 2 ps
Signal rise time tr 0.1 Vnn-0.9Vnn 50 ns
Signal fall time tf 0.1 Vnn-0.9Vnn 50 ns
DUo-DU3
DLo-DL3
~--tSD'--~-~
CL2
tDCLl
!E---;ofE--- t W C L I - - ¥ -....
CLI
S.
j '-------------'X____
>-------tss--------......---tHS----!J-+J
. . . . - - - . , - - - - - - - - S H A R P -~--.------..-.
856
LCD Dot Matrix Controller· CMOS LSI 'LR3692
(2) Writing display control command (Voo=5V±5%. Ta=0-+50t)
Parameter Symbol Conditions MIN. TYP . . MAX. Unit

,
Signal setup time tSRS 500 ns
Signal pulse width tWWR WR and CS overlap time 220 ns
Signal hold ti!lle tHRS 30 ns
Data setup time tso 250 . ns
Data hold ti!lle tHO 30 ns
RS 2'O~V
O.BV
"-----
tSRS tH!lS
WR,CS
J - - - - . tSD~ tHD~
.
X 2.0V
O.BV
:=
~
------~ "------------
(3) Control signal timing (VoD=5V±5%. fosc=4MHz. CL=15pF Ta=0-+50t)
Parameter Symbol Conditions MiN. TYP. MAX. Unit

Signal delay time tOWR 0.2 1 p.s
Signal delay time tOOT 0.2 1 p.s
Signal setup time tSOT 0.2 1 p.s
Signal delay time tOBU 0.2 1 p.s
Signal delay time tOFF 200 ns
11~
~-.-----.r---SH~RP-'-------
857
.. _.....,....., ....
LCD Dot Matrix Controller CMOS LSI
.............,.......
.....,....., ....,...-.: ....,._.......... LR3692
....,.....,
2.0V
J
O.8V ~
~
~
2.0V '2.0V
O.8V O.8V
J
tOWR
~ tnDu
\ O.8V O.8V
II
J
..... tOOT..,.
DTMG
O.8V,
/ \
MAo-MA15
2.0V
O.8V ( ) 2.0V
O.8V
O_.8_V__________________ ·~;f
BUSY, DTMG, MWR, MRD 2.0V '[
MlAo-MA15 O.8V
L - - - _
(4) Bus timing (Direct mode) (Voo=5V±5%, fosc=4MHz, CL=15pF, Ta=0-+50t)

-- tOMRL 150
MOR delay time ns
tOMRH 150
\
Data delay time tOOR 150 ns
Bus switching time tCOR 0 ns
-- tOLMW 150 ns
MWR delay time
tnHMW 150 ns
Data delay time toow 150 ns
Data hold time tHOW 50 ns
Data hold ti!lle tHMO 0 ns
858
LCD Dot Matrix Controller' CMOS LSI LR3692
tDMRH
MDo-MD7
1/f-
CE
1\ /
1/
WR
/
I~HD:
-----i
~ ~W
\
/
tDDW
---..
---
tHMD
MDo-MD7
) '(
.-.--------------SHARP - - - - - - - . - - - - -
859
LCDE)pt Matrix Controller CMOS LSI ': ! LR3692
(5) Bus timing (I/O mode) (Voo=5V±5%,"fosc=4MHz, CL=15pF, Ta=0-+50"C)

.-
Address delay time tcMO' 150 ns
Address hold time tUMO 1 p.s
tCMO
MAo-MA15
(6) Display RAM access (display busy in 4-blt mode)(Voo=5V±5%, fosc=4MHz, CL=15pF, Ta=0-+50"C)

Data setup time tSMO 200 ns
Data hold time tHMO b ns
Access cycle time tCA 500 ns
tCA
,
MAo-MA15
~ J\
tHMD
tSMD
,
) K
860
• Display Control Commands (5) Setting cursor position

Display control is accomplished by writing com- Register name: Cursor Position register
mands and data into the command and data regis- RS 07 06 05 04 03 1 02 1 01 1 00
ters_ 1 0 0 0 0 o 1 1 1 0 1 0
(1) Mode control 0 0 0 0 0 (CP-1)
When writing data into the data regist~r, write
CPo Specifies the row on which the cursor is located in Charac-
code OOH into the command register to specify the ter mode. The horizontal length of the cursor is identical to
Write Mode Control register- the HP.
Register name: Mode Control register (6) Setting lower byte of display start
RS 07 06 05 04 I 03 I 02 I 01 I 00 . address (upper screen)
1 0 0 0 o I 0 I 0 101 0 Register name: Display Start Address register
0 0 0 0 MOOEOATA RS 07 1 06 1 05 1 04 1 03 1 02 1 01 1 00
Data contents 1 010101011101010
1: 4-bit parallel output 0: 1-bit serial output o Lower byte of start address
1: Character mode 0: Graphic mode
(7) Setting upper byte of display start
02 1: ~isplay ON 0: ~isplay OFF
address (upper screen)
1: Cursor blink (character blink when cursor is off.)
Register name: Display Start Address register
00 1: Cursor ON 0: Cursor OFF
(2) Setting character pitch RS 07 I 06 I 05 I 04 I 03 I 02 I 01 I 00
Register name: Character Pitch register 1 0 I 0 I 0 101 1 I 0 I 0 I 1
o Upper byte of start address
RS 07 I 06 I 05 I D4 03 02 01 I 00
1 o I 0 I 0 I 0 0 0 011 This command sets the display start address for
0 (VP-1) 0 0 (HP) the upper section of the screen. The display start
VP: Vertical pitch in character mode. Invalid for Graphic mode. address refers to the RAM location in which the
HP: Horizontal pitch in character mode. Invalid for Graphic mode. data to be displayed in the upper left corner of the
The HP can take on any of the following three screen is stored.
values. However, when in the 4-bit parallel output (a) Setting lower byte of display start
mode, the horizontal character pitch is fixed at 8. address (lower screen)
HP DI 00 Register name: Display Start Address register
5 0 1 Horizontal character pitch 5
~ ~1~1~1~1~1~1~1~
101 0 I 0 I 0 101 1 101 1
o Lower byte of start address
(3) Setting the number of characters per row
Register name: Characters Per Row register (9) Setting upper byte of display start
address (lower screen)
RS 07 06 I 05 I 04 I 03 I 02 I 01 I 00 Register name: Display Start Address register
1 0 o I 0 I 0 I o· I 0 I 1 I 0
0 0 (HN-1) ~ ~I~I~J~J~J~J~J~
HN: Specifies the number oj characters per row when in the char· 1 0 1 0 101 0 1 0 1 110 1 1
acter mode, and the number of bytes per row when in the
Graphic mode. When in the 4-bit parallel output mode, HN
o .Upper byte of start address
should be set to a multiple of four (4). This command sets the display start address for
Nunmber of pixels per row NX:
NX=HP x HN in Character mode the lower section of the screen. The display start
NX=8 x HN in Graphic mode address refers to the RAM location in which the
(4) Setting display duty data to be displayed in the upper left corner of the
Register name: Display register lower section of the screen is stored.
~ ~I~I~I~I~I~I~I~
1 0 I 0 101 0 I 0 I 0 I 1 I 1
o (NY-1)
NY: Display duty - 1/(32-256)
---~~-----------SHARP .------~-.-.,-,
861
(10) Setting lower byte of cursor address 1/0 mode is selected by writing OCR into the
Register name: Cursor Address register command register. When BUSY = 1, thl! display
~ ~1~1~1~1~1~1~1~ RAM location specified by the Cursor Address
1 0 I 0 I 0 101 1 I 0 I 1 I 0 register can be accessed through DIo-DI7 for read
o Lower byte' of cursor address or write operations.
(11) Setting upper byte of cursor address The LR3692 also permits direct display RAM
Register name: Cursor Address register access using the address data fu~nished from the
CPU. In either case the value of the Cursor
RS D7I Ds I D5 I D4 I D3 I D2 I Dl I Do Address register is incremented each time the dis-
1 0 I 0 I 0 101 1 101 1 I 1 play RAM is accessed.
o. Upper byte of cursor address
This command sets cursor address data into the • System Configuration
cursor address counter. (1) Interface with CPU
(12) Setting latch pulse period As shown in Figs. 1 and 2, the LR3692 (LCDC)
Regipter name: Latch Pulse Period register is connected to the· standard bus of the ZBO-type'
RS D7 Ds I D5 I D4 I D3 I D2 I Dl I Do CPU, using it as a means of transferring data and
1 0 0 I 0 I 0 101 1 I 1 I 1 commands.
0 0 (NLP-l) If the CS is at low and RS is at high, the com-
NLP: HN + 1 ;:;;; NLP ;:;;; 121rwhen in serial mode. mand register within the LCDC is specified and
HN/4 + 1 ;:;;; NLP ;:;;; 128 when in 4-bit mode.
The display frequency fd is related with the latch pulse period the data on the data bus is written in. The write
NLP by the following formula: timing is determined by the WR signal. If the CS is
fd = 1/(8NLP. TXS. NY)
TXS: Shift clock period
at low and RS is at high, the contents of the
·TXS = 500 ns when OSC frequency is 4 MHz. LCDC's internal register requested by the com-
(13) Setting display RAM access mode mand register cannot be read.
RS D7I Ds I D5 I D4 I D3 I D2 I Dl I Do The CE, BUSY, DOFF, and DTMG signals are
1 0 I 0 I 0 I 01 1 I 1 I 0 1 0 used for CPU access to the display RAM.
o DATA
ICE
Ao-Als RS
Z80A LR3692
CPU LCDC
IORQ Decoder CS
RD RD
- WR
WR
WAIT -----------.-- BUSY
---------~ DOFF
DTMG
Do-D7 Do-Dr
MAo-MA1s
MDo-MD7
MRD
MWR
~
I Display RAM I
Fig. 1 Interface with CPU(I/O mode)
- . - . . - - - - . - . - - S H A R P ---.--~------..-.
862
Ao-Al5 RS
Z80A LR3692
CPU LCDC
MREQ j, CE
I
IQRQ Decoder CS
I
I
RD I
RD
-WR I
WR
I
WAIT I-- 1------ -------t-- BUSY
. L DOFF
I LR74HC244X2 DTMG
Do-D7 Do-D7
MAo-MA15
MDo-MD7
MRD
MWR
1!
I Display RAM I
Fig. 2 Interface with CPU (Direct mode)
(2) CPU access to display RAM ly to the display RAM. The Cursor Address regis·
CPU access to the display RAM includes the 110 ter is incremented at the rising edge of the RD or
mode which is made through the LCDC, and the WR signal. The functions of the BUSY and DOFF
Direct mode which is directly performed from the signals are identical to those in the 110 mode.
CPU. Note: In either mode the BUSY signal is output only when the
CD 110 mode A sample system configuration CPU is accessing the display RAM. (When CE = 0 in
Direct mode; when CS=O, RS=O and the command regis·
for 110 mode access is shown in Fig. 1. A value for ter value is OCH in I/O mode.) The BUSY is set to high in
OC. is first set into the command register. If the all other cases.
BUSY is high. CS is low. ap.d RS is low. the RD.
WR. and Do-D7 lines are linked to the MRD. MWR. • LCD Control
and MDo-MD7 lines. respectively. At this time the (1) Graphic mode
value of the Cursor Address register is output at The Graphic mode is selected by the Mode Con-
the MAo- MAls pins. The Cursor Addre~register trol register value. In this mode each bit of the dis-
is incremented at the rising edge of the RD or WR play RAM corresponds to each pixel on the LCD
signal. The BUSY line is set to high during the fly- screen.
back period in which the LCDC does not access the CD Screen configuration The numbers of
. display RAM. Setting the DOFF to low causes the pixels per row and per column are determined by
BUSY to be set to high. making the display RAM the values of the Character-Per-Row register and
accessible at any timing. At this time. the LCD dis- Duty register.
play is turned off. No. of pixels per row: HNx8, HN= 16 to 128
® Direct mode A sample system configura- No. of pixels per column: NYX2, NY=32 to 256
tion for Direct mode access is shown in Fig. 2. The (When both the upper and lower sections of the
Direct mode is selected if the value of the com· screen are used.)
mand register is anything but OCH. If BUSY is ® Display start address The display start
high and CE is low, the RD, WR and Do-D7 pins address refers to the first location of the di~play
are linked to the MRD, MWR, and MDo-MD7 lines, RAM area to displayed, specified by 16-bit data.
respectively. At this time the DTMG is set at low Independent specification for the upper and lower
and the MAo-MAl5 pins are set to high impedance, sections of the screen is possible. Further, the uti-
to transfer the address specified of the CPU direct- lization of display start address makes page con-
----..--.-..--SHARP-.-.------~
863
LCD Dot Matrix Controller CMOS LSI 'LR3692
Display RAM
MSB LSB
LCD panel
ll'"'·~-- .sXHN line ~I

Upper sc~een start address !a7 as as a4 aa a2 al ao ila7as as Maa a2 al ao
t-
NY line Upper screen
Lower screen start address b1 ba bs b4 ba b2 bl bo b, ... b, '" b, b, b, b
NY line Lower screen
L~_---,
Fig. 3 Screen configuration (Graphic mode)
trol and screen scroll possible. @ Character font The character font is
(2) . Character mode specified by the value of the Character Pitch reg·
The Character mode is specified by the value of ister.
the Mode Control register. In this mode pixel pat· Horizontal pitch: HP=5, 6, 8
terns are displayed by combining character codes Vertical pitch: VP = 1-16
of the display RAM with the corresponding char· Fig. 4 shows an example of character font. If HP=
acter patterns of the character generator ROM. 5 or 6, the LSB side of the Rlo-Rlt is invalid.
(CGROM). ® Cursor display The cursor display mode
CD Screen configuration The numbers of is determined by the value of the Mode Control reg·
characters per row and per column are determined ister. The cursor position.is specified by the vahte
by the content of the Character-Per Row register, of Cursor. Address register. Since the character
Duty register, and Character Pitch register. code address on the display RAM is specified for
No. of characters per row: HN = 16 to 128 cursor position specification, screen scrolling is
No. of characters per column: NYx2lVVP, NY= 32 accompained by cursor scrolling.,
x256 The cursor position in a character font is speci·
(When the upper and, lower sections of the screen fied by the Cursor Position register.
are used.) @ Cursor blink Cursor or character blink·
The numbers of pixels per row and per column ing is controlled by the Mode Controll register.
are determined as follows:
.r- =-:1
No. of pixels per row: HHYx2
CGROM address
HP
MAls MA14 MAla MA12
o o o o
r ~o:~~~:~~ol
o o o 1
o o o
.000.0 o o 1
,
VLP
0 • • • • • 00
~~: ~ ~ ~ ~ ~~
OD'D 0 0 0
••••••
.0 0 0 0 0 DO 0
: J CP
o
o
o
o 1
o
o
o
o
1
o
0
o
1
"0
1
o
Fig.4 Example of character font (HP=8, VP=10, CP=9)
864
LR3692
LCDC
Rlo-Rh DUo-DU3 ===¢
--
MA12-MAI5 DLo-DL3 ===¢ Liquid crystal
--
MAo-MAll CLI panel
--
MDo-MD7 CL2
r- MRD M
MWR s--
JI
I
Do-D7
CGROM
Ao-AI5 Display RAM
I
Fig. 5 Connections to CGROM and LCD panel
Blinking is performed for approx. 1H (64 frams) at (TXS=500 ns when OSC frequency is 4 MHz.)
1/2 duty. ® Flyback period The LCDC does not ac-
(3) Parameter setting cess the display RAM during fiyback period.
CD Display frequency The LR3692 uses Flyback period TDIS:
the two-frame AC display system. The display sys-
When in Serial mode: TDIS= 18 (NLP-1)-8HN I
tem. The display frequency is determined by Dis-
. TXS
play Duty and the value of the Latch Pulse Period
register.
When in 4-bit mode: TDIS= 18 (NLP-1)-2HN I
.TXS
One frame period: Td=8NLP.TXS.NY
Display frequency: fd=l/Td
Retrace time
I"
CLI _ _ _ _ _ _ _ _ _ _ ~
~I
n ~ ____________
r Retrace time
"I
~I I IL-
Fig. 6 Flyback period
865
LCD Dot Matrix Driver CMOS LSI . LH5006A
LH5006A LCD Dot Matrix Driver CMOS LSI

The LH5006A has 2 sets of 20-stage bidirec-
tional shift registers, 2 sets of 20-bit latches and 2
sets of 20 LCD drivers, so it converts serial char-
acter pattern data to parallel data and provides
selected or nonselected waveforms output in
accordance with mode select signal.
• Features
1. CMOS process
2. 40-LCD driver circuit
(a half of 40 drivers can be used either as seg-
ment signal drivers or as common signal
drivers)
3. Single power supply: -.5V (TYP.) Top View
• Block Diagram
Output Output
-------~------~
__ ------A~------ __
Output Output
Data I/O Shift Shift Data I/O

Direction Direction
Select Select
866
LCD Dot Matrix Driver CMOS LSI LH5006A
• Pin Description
Pin name Name I/O Functions
YI-Y20 Ch. 1 liquid crystal output
Y 21 -Y. O
Liquid crystal output a Ch. 2 liquid crystal output
~ SHL I DLI DRI Shift direction

Ch. 1 data shift
SHL I I Low IN OUT SR I -SR 20
direction selection
High OUT IN SR 20 -SR I
SHL 2 DL2 DR2 Shift direction

Ch. 2 data shift
SHL z I Low IN OUT SR 21 -SR 40
direction selection
High OUT IN SR.o-SR zl
FCS Mode
FCS Ch. 2 mode selection I High Common signal drive mode
Low Segment signal drive mode
Common signal drive mode Segment signal drive mode
Non- Non-display
Clock for liquid crystal M Display M Display
M I display Ch.l Ch.l
drive circuit
High V2 V6 High VI Vs V3
Low VI Vs Low V2 V6 V.
DLI> DRI Ch. 1 input/output
Data output I/O
DL 2 , DR2 Ch. 2 input/output
CL I, CL z Clock I Clock for data latch
VI> V2 Durling select
Liquid crystal drive circuit
V3, V. I Ch. 1 durling non-select
output voltage supply
V 5 , V6 Ch. 2 durling non-select
VDD For logic circuit (- 5V)
VEE Power supply For liquid crystal drive circuit (-17V)
Vss GND
----------SHARP-.-------
867
LCD Dot Matrix Driver CMOS LSI LHS'006A

Applied voltage * (logic) VDD +0.3--7.0 V
Applied voltage *
VEE +0.3--13.5 V
(LCD drive circuit)
Input voltage'" VIN ,+0.3-V DD -0.3 V
Storage temperature TS'l< -55-+150 "C
*The maximum applicable voltage on any pin with respect to Vss.
• DC Characteristics (Vss=GND, VDD =-5±5%, VEE =-lOV±lO%, Ta=-10-+70"C)

Input low voltage V1L -3.5 V
Input high voltage VIH -1.5 V
Output lo~ voltage VOL IOL =O.4mA VDD +O.4 V
Output high voltage VOH VoH =O.4mA -0.4 V
Voltage drop between VOl When ImA current flows into one of the pins Y1 through S40 1.1 V
Y1-Y 1 VD2 When O.2mA current flows into each of pins Y1 through S40 1.5 V
Input leakage current I ILl I 5.0 pA
Output leakage current I ILO I 10.0 pA
Logic current consllmption ILOG Logic clock 1.6MHz 3.0 mA
LCD driver current consul!lption IDRv LCD driver clock 1kHz 10.0 pA
• AC Characteristics (Vss=GND, VDD =-5±5%, VE~=-18--16V, Ta=-10-+70"C)

Clock high width tcWH 250 ns 1
Clock low width tCWL 250 ns 2
Data setup time tsu 70 ns 3
Clock setup time (CL 2....CL 1) tSL 200 ns 1
Clock setup time (CL 1....CL 2 ) tLS 200 ns 1
Output delay time tod CL=15pF 180 ns 3
Clock rise/fall time I:c, 50 ns 1
Note 1: Applicabte pins CLIo CL 2
Note 2:. Applicabte pin CL 2
Note 3: Applicabte pins DL" DR" DL2, DR2
868
LCD Dot Matrix Driver CMOS LSI LH5006A
• Timing Diagram
DATAIN ____________~x~_____
DATAoUT
FLM
-- I I
M CPl CP2
I I
M CL2 CLI
VDD VDD
>-- FCS Segment driver r- FCS Segment driver
>-- SHLI LH5006A r- SHLI LH5006A
- SHL2
DLI -
- SHL2
DR2
Yl-Y4o Yl-Y40
M
CP2 f - -
CPl !------'
-M
L...- CP 2
Vf ~D
FCS SHLI SHL2
U ~
...
.!! - CPl
Common driver Yl
\
~ LCD panel
DLI LH5006A
...
'0
....c DRI
Y.o -/
0
C,)
[ DL2
DR2
---....-----.-~--SHARP .....-..-.-------
869
LCD Dot Matrix Driver CMOS LSI . LH5021 AlLH5022
LCD Dot Matrix Driver

LH5021A/LH5022 CMOS LSI
LH502lA/LH5022 is an LCD driver LSI which
. . rn .. ~.3u..:;..:~..::~o_~21 o~~ ...
can receive either serial input data or parallel in- ~~»UZQQQQ>Q~U>~~~»
899994990 65848281
put data. In case of the serial input mode, it can
be connected in series. It converts -character pat- o
tern data input to parallel data output with 80-bit
latch circuit and provides character pattern wave-
forms output in accordance with mode select signal.
• Features
1. CMOS process
2. 80-LCD driver circuit
3. 4 functions selectable as follows
(a)Segment signal drivers on the serial input
mode
(b)Segment signal drivers with the chip-select-
able function on the serial input mode
(c)Segment signal drivers with the chip-select-
able function on the parallel input mode
(d)Common signal drivers on the serial input
mode
4. Auto count function ; in a chip selected state,. o 51 Y5I
counts 80 input data automatically and stops 312 6 9144456784950
the internal clock CL,
5. Power supply voltage: - 5V (TYP.) Top View
6. Display voltage
LH5021A: -17V (TYP.),
LH5022: -24V (TYP.)·
870
LCD Dot Matrix Driver CMOS LSI LH5021 AlLH5022
• Block Diagram
Chip Select
Output
r------{:MI}-----~
Alternate 85
Signal
Cloak 87}-------~
1-;::===1.....L.....I.....I.....I--::-;;:~~::~.....I.....L.....L"""1I-__+-_+_r:>-_..{89 Serial Data

Output
-.-....-.------SHARP--------
871
• Pin Description
VDD For logic circuit (- 5V)
VEE Power supply For liquid crystal drive circuit (LH502IA: -17V, LH5022: -24V)
Vss GND
V 3, V 4 Liquid crystal drive circuit Durling non-select, however Vss > (V3, V 4»VEE
0
Yl-Y SO output voltage supply
CL I For data latch *Must be applied when 4 times the shift clock
Clock I
CL 2 For data shift
FCS PS Mode Chip select DO out

I-bit serial input
Low Low
segment driver
X 0
4-bit parallel input
Low High
segment driver
0 High
I-bit serial input

High Low
segment driver
0 High
Commnn driver
High High
(serial input)
X 0
FCS,PS Mode select I
Note 1: In the serial input mode, data is supplied from
the 011 pin.
Note 2: The relationship between data input during 4·bit
parallel input and the Y output is as follows.
• 011 : Y b Y5 , Y9 , ••• Y 13 , Y77
• 01 2 : Y2 , Y6 , Y lO , ... Y74 , Y78
• 01 3 : Y3, Y7 , Y ll , .,. Y75 , Y79
'01 4 : Y4, Ys , Y12 , ... Y76 , Yso'
Note 3: When used as a comon driver, the clock used for
transfer is input to the CL 2 pin. CL I is internally
fixed.
Note 4: To minimize current consumption, it is necessary
to fix unused input pins to the same level as the
Vss pin or the V DO pin.
Common signal drive mode Segment signal drive mode
Latch data M Yout. Latch data M Yout.

Liquid crystal drive waveform
M I Low Low V3 Low Low V3
AC conversion signal input
(non·display) High V4 (non-display) High V4
High Low VEE High Low GND
(display) High GND (display) High VEE
When used with a common driver and in the serial input
01 1-01 4 Display data input I mode, supply the data to the 011 pin. In this case, it is
necessary to fix 01 2 - 014 to the Vss level or the VDO level.
DO Serial data output 0 When used in the chip select mode, it becomes high level.
EI For I Used only in the chip select mode.
ED chip select 0 (1) The (CL 1 • CL 2) timing causes EO to become low level.
(2) After (1), the device is set to the select mode by inputting
a high signal to EI, and the input data is read in accord·
ing to the timing of the fall of CL 2 •
(3) When 80 items of input data (equivalent to 80 CL 2 clock
cycles in the serial mode or 20 CL z clock cycles in the
4·bit parallel mode) have been read in, EO automatically
becomes high level and data read in is terminated. EO is
reset 1.5 cycles later.
872
LCD Dot Matrix Driver CMOS LSI LH5021 A/LH5022

(4) When two or more devices l:lre used in the chip select
mode, EO of the first stage and EI of the second stage are
connected and used.
1. EO of all devices connected is reset by (1) and goes
to the non·select condition and waits for EI input.
2. When a high signal is applied to EI of the initial de·
vice in the cascade connection, this device performs
the operations in (2) and (3).
3. Connecting EO of the initial devices to EI of the next
devices causes the devices perform the operations in
(2) and (3) after the initial device. This operation is
repeated in the same manner for all subsequent de-
vices.
In the non-select condition, the shift clock CL 2 stops in-
ternally, so power consumption becomes extremely small.

LH5021A LH5022
Ratings Ratings
Applied voltage (logic) Voo -7-+0.3 -7-+0.3 V 1
Applied voltage
VEl -20-+0.3 -30-+0.3 V 1
(Liquid crystal drive circuit)
Input voltage (logic) VIN VDD -0.3-+0.3 Voo -0.3-+0.3 V 1
·Operating temperature Topr -20-+70 -20-+70 "C
Storage temperature T st" -55-+150 -55-+150 t
Note 1: The ~aximum applicable voltage on any pin with respect to Vss.
LH5021A *1 LH5022*2
Parameter . Symbol Conditions Unit
Input low voltage VIL 0.8Voo 0.8Voo V
Input high voltage VIH 0. 2Voo 0. 2Voo V
Output high voltage VOL IOL =O.4mA VDD+OA ~DD+OA V
Output low voltage VOH IoH =O.4mA -0.4 -0.4 V
1 rnA to one of
Voltage fall between Vi - Yi VOl 1.1 1 V
YI-Y SO
0.2 rnA to each
Voltage fall between Vi-Yi VD2 1.5 1.5 V
of YI-Y SO
Input leakage current I Iu I 1 1 pA
Output leakage current I ILO I 10 10 pA
1 bit serial
2.2 6.0 2.0 5.0 rnA
Logic circuit selection transfer (3.3MHz)
ILOG
current consumption 4 bit parallel
1.0 2.0 1.0 2.0 rnA
transfer (2.0MHz)
*1 VEE =-17V±1V
*2 VEE =-24V
873
LCD Dot Matr.ix Driver CMOS LH5021 A/LH5022
(1) 1-blt Serial Input Segment Driver (PS=FCS="Low") (Voo =-5V±10%, vss=ov, Ta=-20-+70t)
Parameter Symbol Conditions'" 1 MIN. MAX. Unit Applicable pins
Clook frequency tc 300 ns CL 2
High-level clock width tcwH 130 ns CL 2
Low-level clock width tcWL 130 ns CLl> CL 2
Data hold time tH 50 ns 011
Output delay to CL =15pF 230 ns DO
High-level latch clock width t LwH 130 *3 ns CL I
Clock margin time
tc12 20 ns CLl> CL 2
(from CL I ~ to CL 2 l )
Clock margin time ... 2
tc2l 200 ns CLl> CL 2
(from CL 2 l to CL I l )
Clock margin time
tp2l 20 ns CLl> CL 2
(from CL 2 t to CL I t )
Clock t, l time tcT 50 ns CLl> CL 2
Overlap time of
tov 130 ns CLl> CL2
CL 2 "L" and eLl "H"
Test conditions
Input frequency: O.8VOlh O.2Voo: Input reference level: O.8V oo• O.2Voo: Output reference level: O_2V oo• O.8Voo
*1 LH5021A VEE =-17V±lV, LH5022 : V EE =-24V
*2 Internal shift register determination time
* 3 1.5tc-tC12-tp21 - 3tCT
tCT
DIt
DO Valid
tov
tP2I t CT tCT
t C2I --t-t-l-.... t C12
YI-YSO
-~""-~-""""--SHARP---'-'''''''''''--~
874
(2) 4-blt Input Segment Driver (PS="High", FCS="Low") (VDD=-5V±10%. vss=ov. Ta=-20-+70"C)
Parameter Symbol Conditions * I MIN. MAX. Unit Applicable pins
Clock frequency tc 500 ns CL 2
High-level clock width tcWH 230 ns CL 2
Low-level clock width tcWL 230 ns CL h CL 2
Data setup time tsu 70 ns Dlh Dl 2• Dl3• Dl4 • EI
Data hold time tH 50 ns Dlh Dl 2• Dl 3• Dl4 • EI
Output delay tD CL=15pF 230 ns EO
High-level latch clock width tLWH 130 *3 ns CLI
Clock margin time
tcl2 20 ns CL h CL 2
(from CLI ~ to CL 2 ~ )
Clock margin time * 2
tc21 200 ns CL h CL 2
(from CL 2 ~ to CLI l )
Clock margin time
tp21 20 ns CL h CL 2
(from CL 2 t to CLI t)
Clock t. ~ time tcT 50 ns CL h CL 2
Overlap time of
tov 130 ns CLl> CL 2
CL 2 "L" and CLI "W
Test conditions
Input frequency: O_BV OD• O_2Voo; Input reference level: O.BVoo. O_2Voo: Output reference level: O.2V DO• O_BVoo
*1 LH5021A VEE =-17V±lV. LH5022: VEE =-24V
* 2 Internal shift register determination time
* 3 L51:c-1:c12-tp21-3I:cT
EI
-~++ ... tC12
EO
to tD to
-------------SHARP-.-.--..-----
875
(3) Common Driver (PS="Low", FCS = "High") (VDD =-5V±10%, Vss=OV, Ta=-20-+70·C)
Parameter Symbol Conditions * 1 . MIN. MAX. Unit Applicable pins

Clock frequency tc 1000 ns CL 2
High-level clock width tCWH 130 ns CL 2
Low-level clock width tcwL 830 ns CL 2
Data hold time tH 50 ns 011
Output delay tD CL=15pF 500 ns DO
Clock t , ~ time tCT 50 ns CL 2
Test conditions
Input frequency: O.SV DD, O.2V DD; Input reference level: O.SV DD, O.2V DD; Output reference level: O.SV DO, O.2V DD
*1 LH5021A VEE =-17V±lV, LH5022: VEE =-24V
CL2
~J---tCWH
DO Valid
Yt-YBo
.-.---.-.---SHARP------------
876
LCD Dot Matrix Driver CMOS LSI LH5021 A/LH5022
(4) 1-bit Serial Input Segment Driver (PS="Low", FCS="High")

(VDD=-5V±10%, vss=ov, Ta=-20-+70"C)
Parameter Symbol Conditions * I MIN. MAX. Unit Applicable pins

Clock frequency te 380 ns CL 2
High·level clock width teWH 170 ns CL 2
Low-level clock width teWL 170 ns CLIo CL 2
Data setup time tsu 70 ns DIb EI
Data hold time tH 50 ns DIb EI
Output delay tD CL=15pF 230 ns EO
High-level latch clock width t LWH 130 *3 ns CL I
Clock margin time
tel2 20 ns CLIo CL 2
(from CL I ~ to CL 2 ~ )
Clock margin time * 2
tC21 200 ns CLIo CL 2
(from CL 2 ~ to CL I ~ )
Clock margin time
t p21 20 ns CLIo CL 2
(from CL 2 t to CL I t )
Clock t, ~ time teT 50 ns CLIo CL 2
Overlap time of
tOY 130 ns CLIo CL 2
CL 2 "L" and CL I "H"
Test conditions
Input frequency: O.8V DD, O.2V OD ; Input reference level: O.8V oo• O.2Voo; Output reference level: O.2VDO• O.8VOD
*1 LH5021A VEE =-17V±1V. LH5022: VEE =-24V
* 2 Internal shift register determination time
* 3 1.5tc-tc'2-tp2,-3tcT
Ell
----oo+-loo-o·t C12
EO
to to to
877
~I • Ig
en
I '<
!e.
Ii.
CD
II~~~~~~~-~~~--- ~~~-.
3
I CPU
-1
-----, I I
,..,J-,..L--L........J.,..,
1"- 0
- I~
0
:::l
I (Z80 System)
+5V
CL. CLI M FCS
LH5021A IPS ___
CL, CLI M FCS
LH5021A IPS
/LH5022 Dh r- -- DO /LH5022 Dh
CL. CLI M FCS
LH5021A IPS
CL,'CLI M FCS
LH5021A IPS
/LH5022 Dltf----- DO /LH5022 Dhf-
10"
a0"...
t:
I ..l~ 1[" 1[" Yao-YI Yao-YI Yao-YI ' Yao-YI
I!
:::l
U "'-.J. {J,. U m
I
\ Address Bus
\ Data Bus
.!...> II II
I
FCS/PS DII
M LH5021A ~
I )(
D)
1r .!...> II /LH5022Y :
3
I \ Control Bus
.! .!.
CLI
CL2
r---v' I I II
"0
CD
I
I
I,
\y. . ~ ~IDEClOD~~ER
RD IORQ . WR '-----.--...1 :
FCS/PSDII ----'----~-------LCD IPanel - - - - - - - - - - - -

I '_
r-
LH5021A ~
M /LH5022Y~
IT! N
I
jjJ, :
f--- r- I
"I -'\
WAIT
RD WR RS CS DE
CPI
CP2
M
CLI
CL2
I
fr
Yao- YI
fr
Yao-YI
1t1'f"
Yao-YI .
Yao-YI
I
II
---,/ Do- D7 LH5021A LH5021A LH5021A LH5021A
LR3691A DI _ ILH5022 Dh ----- DO ILH5022 Dh ILH5022 Dh 1----- DO ILH5022 Dh r-
I- FCS FCS FCS FCS
I
---;== MAo- MAI4 DI2 -
Dh
DI.
=jl CL, CLI MIPS
T ___
-__
CL, CLI M IPS CL. CLI MIPS
_
CL. CLI MIPS
__ ---1 I
___ ----.J
I
I r:
MDo- MD, MWR MRD
11
:::
-=~=
--------1
:=~ 1Ir
I
I
I
I
..!
DECODER
CS Do-D, WE OE
DISPLAY RAM
Ao-AI5
II ~
~
I I~
LCD Dot Matrix Driver CMOS LSI LH5821/LH5822/LH5823
LH5821/LH5822/LH5823
LCD Dot Matrix Driver CMOS LSI
The LH58211LH5822/LH5823 are CMOS driv-
30 dj~u ~ -<:O:~O:O:O:cCd:
er LSls for LCD dot matrix display. :: '" <- '"
oo~~~~~>oo>u~~»~~~~~~~
M _
• • Y5YHNDUDWoaUMOMUUOM
Anyone of display duty ratio, 117 - 1/20 can be
selected by programming.
Write and read to/from the built-in RAM of dis-
play data can be made only by 3 signals, serial
data, synchronous signal, and transfer clock.
The LH5826 is available for segment output ex-
pansion.
• Features
1.
Display data RAM: 1280bits
2.
10-bit serial data transfer
3.
Built-in oscillator for display
4.
Duty (Selectable by programming)
LH5821: 1/7-1120 Top View
LH5822: 1/7-1118
* 37 pin 38 pin 63 pin 64 pin
LH5823: 1/7-1116 LH5821 BPIlI BPlo BP n BP14
--- f------'----
LH5822 BPlo BP1 7
5. Segment output S" S"
LH5821 : 44bits
LH5823 S" S" s" s"
LH5822 : 46 bits
LH5823 : 48 bits
6. Common output
LH5821 : 20 bits
LH5822 : 18 bits
LH5823: 16 bits
7. Clock output for double voltage
8. Power supply voltage: 5V (TYP.)
9. Display voltage
LH5821, LH5822 : 12V (MAX.)
LH5823 : lOV (MAX.)
-'---~'-'--SHARP'-------'-
879
LCD Dot Mattix Driver CMOS LSI LH5821/LH58221LH5823
• Block Diagram
Frame Sync. 8
Clock
RAM
64 X 20 bits
.Display Clock 7
Load Control 49)------~---..I...-__,
~------~vr------~
Output
.-.------~--SHARP-.---.-.---
880

Vee -0.3-+7 V 1
Pin voltage *
Vop -0.3-+13(+11) V 1
Operating temperature Topr -5-+55 t:
Storage temperature T stg -5-+150 t:
Note 1: Referenced to GND. Value in parentheses ( ) applies to LH5823.

Supply voltage Vee 4.5 5.5 V
Display voltage Vop 6 12(10) V '2
Note 2: Value in parentheses ( ) applies to LH5823.
• DC Characteristics (V ee =4.5-5.5V, Ta=-5-55t:)

V IH Vee- O.S Vee
Input voltage V 3
V lL 0 O.S
IIH VIH=Vee 25 50
Input current pA 4
IlL VlL=OV 1
V OH IoH =410 pA 2.4
Output voltage V 5
VOL IOL =1.6mA O.S
RQ Vee=5V, Vos=1.0V SO 0 7
RSEG 1.0 30 kO S
Output resistance
ReoM Vop=6V, Ta=25t:, Vos=IV 1.5 4.5 kO 9
Rv 40 1 0 10
Input leakage current I IL I pA 6
Durling no-load blank display
Ieel 200 500 pA
f; = 100kHz, fcLo=OHz, Ta=25'C
Durling data write (write cycle 1145 MHz)
Current consumption Iee2 2 rnA
f; = 100kHz, ho=IMHz, Ta=25'C
Durling no-load blank display
lop 5 10 pA
VDP =12V, f; = 100kHz, 1116 duty
Note 3: Applied to pins CLo, LC, SDo
Note 4: Applied to pin LC
Note 5: Applied to pins SDo, H, {-
Note 6: Applied to all pins except LC
Note 7: Applied to pins Q, Q
Note 8: Applied to segment output pin.
Note 9: Applied to common output pin.
Note 10: Applied to pins VA, VB
Parameter . Symbol Conditions MIN. TYP. MAX. Unit
CLo cycle time t Re 1 ps
LC hold time tLD 0 ns
LC setup time t LS 100 ns
SDo setup time tsso 100 ns
SDo input/output switching time to C L=50pF SO 450 ns
~'--~----SHA~P------'-'---
881
LCD Dot Matrix'Driver CMOS LSI . LH5821 ILH5822lLH5823
CLo
LC
tSSD
SOo (Input)
S 00 (Output)
0:X UMdm~±
--Input mode - - - - ! E - - - - - O u t p u t mode ~Input mode
• Functions
(1) Pin description

Pin name No: of pins I/O Functions
Vee, GND 3 Power supply for logic circuit
Vop, VA, VM, VB 4 Power supply for liquid crystal drive
LC 1 I Serial data transfer sync. signal
CLo 1 Serial data transfer clock input
RX 1 Input clock oscillation pin
RY 1 Input clock oscillation pin
1 Clock output for display
'"
if 1 Liquid crystal frame sync. signal
Q,Q . 2 Clock output for double voltage generation
S20-S63 (LH5821) 44 0
S1S-S63 (LH5822) 46 Liquid crystal segment drive signal
S16-S63 (LH5823) 48
BPo-BP 19 (LH5821) 20
BPo-BP 17 (LH5822) 18 Liquid crystal common drive signal
BPo-BP 15 (LH5823) 16
SDo 1 I/O Serial data input/output
(2) Relationship between 10-bit serial data and modes

lO·bit data/mode CO C1 Do D1 D2 D3 D4 D5 D6 D7
Chip select/duty setup mode 0 0 Chip select data I Duty data
RAM address setup mode 0 1 Ao A1 A2 A3 A4 A5 A6 A7
8-bit data write mode 1 o· Data
8-bit data read mode 1 1 Data
(C" C2 : Control data, Do-D7 : Data)
882
• LC single • (> signal

The LC signal is a sync. signal for serial trans· The (> signal is the clock output for display and
fer, and when LC is low, LSI remains in the stand· is supplied to LH5826.
by condition regardless of the condition of SDo and • H signal
CL o, When' LC becomes high and clock CLo is sup- The H signal is the frame period signal for the
plied, the LSI is enabled. liquid crystal and is supplied to LH5826. When
• CL signal the power is turned on, the timing signal in each
The CL signal is the clock signal for serial trans- device is in an unsynchronized condition, and after
fer and is used to write and read serial transfer the H signal is generated, they are synchronized.
data SDo. • Auto clear
• SDo signal When th'e power is turned on, the display signal
The SDo signal is lO-bit serial transfer data of generates an OFF pattern. Auto clear is canceled
which the first 2 bits are control data and the re- when all of the duty data of the chip select duty
maining 8 bits are data. In the read mode the SDo data are made" 1" and input, and then the contents
pin becomes an output pin and outputs the 8-bit of the RAM are displayed. The chip select duty
RAM data in serial. After the write or read mode does not change at this time.
has been executed, the lower 6 bits, Ao-A5, of the- • Double voltage clock
RAM address are automatically incremented, but A double voltage clock is output from pins Q and
As and A7 do not change. Q. The Q and Q signals are clock signals made by
• Chip select dividing the display clock (> by 2, and their re-
In the LSI, the chip select code is set at "0000", spective polarities are opposite.
so by inputting the chip select code "0000" through
the SDo pin, this chip is selected:
The RAM address setting and writing and read-
ing of the 8-bit data is executed only for the chip
selected, and once a chip is selected, it remains in
the selected condition until a select code for the
next chip is input.
~ Dot matrix LCD

~
20
BPo-BP19
~) 64r
So S63
S20 S63
.- RX
H eS3 I -
H
RY
~ RX LH5821
¢
GND
¢
GND
LH5826'
CS2 ~
CSI f-
Vee Vee
CS~ r- - +5V
SDo LC CLo VDP VA VM VB +!V 7, SDo LC CLo VDP VA Vo
I f j J
CPU
{ 1
R r r R
VDP
Cl: ~C2 : i:C3 : ~C4
,
----------SHARP-----.---
883
lCO Dot Matrix Segment Driver CMOS LSI 'LH5826
LH5826 LCD Dot Matrix Segment Driver CMOS LSI

• De$cription • Pin Connections
The LH5826 is a segment driver CMOS LSI for :: ......... .., .... ~QtL,j~ulC<." ........... :::=
~~~oo~oo>oo>u~~»oooooooooooooo
LCD dot matrix display. Write and read to/from 5 5 54 3 5 51 4 4 4 4 4 42 41 40
the built-in RAM of display data can be made only
by 3 signals, serial data, synchronous signal, and
transfer clock.
The LH5826 is available for segment output ex-
pansion of the LH5821, LH5822 and,LH5823.
• Features
1. Display data RAM: 1280 bits
2. lO-bit serial data transfer
3. Segment output: 64 bits
4. Up to 15 drivers expandable
6. Display voltage: 12V (MAX.)
Top View
--------.----.----SHARP -----.-.---.-,-.---
884
LCD Dot Matrix Segment Driver CMOS LSI LH5826
• Block Diagram
Segme'!,t Output
,--------------------------{15 ---- ----- 46
Frame Sync. 8
Clock
RAM
64x20bits
Dislay Clock 7
Load Control
Segment Output

Parat:neter Symbol Ratings Unit Note
Vee -0.3-+7
Pin voltage V 1
VDP -0.3-+13
Note:1 Referenced to GND.

Supply voltage Vee 4.5 5.5 V
Display voltage VDP 6 12 V
- - - - - - - - - - - - S H A R P . -.......... - - - - - - - - -
885
• DC Characteristics (Vcc=5V±10%, Ta=-5-+55t)

VlH Vee-O.S Vee
Input voltage V 2
VIL 0 0.8
IlH VlH=Vee 25 50
Input current pA 3
IrL VIL=OV 1
VOH IOH=400pA 2.4
Output voltage V 4
VOL IOL=1.6mA O.S
I/O leakage current I IL I 1 pA 5
Output resistance RSEG Vop=6V, Vos=lV, Ta=25t 10 30 kO 6
During still image display under no load
Icc! 200 500 pA
ft} =100kHz, fcLO=OHz, Ta=25t
During data write (write cycle 1145 MHz)
Current consumption Icc2 2 mA
ft} =100kHz, f~LO=lMHz, Ta=25t
During still image display under no load
lop 5 10 pA
Vop=12V, ft} = 100kHz, 1I20duty
Note 2: Applied to pins CLo, LC, SDo. H, and "'.
Note 3: Applied to pin LC.
Note 4: Applied to pin SDo.
Note 5: Applied to all pins other than LC.
Note 6: Applied to pins SO,S63.
• AC Characteristics (Ta=25t)

CLo cycle time tRC 1 ps
LC hold time tLB 0 ns
LC setup time tLS 100 ns
SDo setup time tsso 100 ns
SDo 1/0 switching time tLD CL=50pF SO 450 ns
CLo
\fV\JV (
LC
tsso
SDo (Input)
SDo (Output)
--Input mode----'i-'----:. Output mode

U~dmOO ± Input mode
.---....-.~-----SHARP ---...---------
886
~ Dot matrix LCD

I""
20
BPo BPl9
j::j {s:j
S20 S63 SO-S63
~ RX
H CS3 r-
H
RY
{ RX LH5821
¢ ¢
LH5826
CS2 r-
GND GND
CSI r-
Vee Vee
SDo LC CLo VDP VA VM VB Jv ""
SDo LC CLo VDP VA VB
CSot---:-t- +5V
! t $ i ""
CPU
{ 1
R r r R
VDP
TCl : C2 : j:C3 ~C4
1.
887
LCD Dot Matrix Segment Driver CMOS LSI LH5826·
• Functions
(1) Pin Description
Signal No. of pins JlO Function
VDP, VA, VB 3 LCD driving power
<} 1 Display clock input
H 1 I LCD frame sync signal
CSo-CSa 4 Chip select input
LC 1 Serial data transfer sync signal
CLo 1 Serial data transfer clock input
RX 1 Connected Vee or GND
So-S6a 64 0 LCD segment driver signal
SDo 1 JlO Serial data JlO
r-
(2) 10-blt serial· data versus mode
lO-bit data/mode CI C2 Do DI D2 DaD4 D5 D6 D7
Chip Select Duty Setting Mode 0 0 Chip Select Data I: Duty Data
RAM Address Setting Mode 0 1 Ao Al A2 Aa A4 1\.5 A6 A7
8-bit Data Write Mode 1 0 Data
8-bit Data Read Mode 1 1 Data
(CI, C2: Control Data, Do-D7: Data)
• LC signal
The LC is a serial transfer sync signal input. If 0001 and 1111 for CS"a, CS2, CSI, and CSo, re-
the LC is at low, the LH5826 maintains standby spectively. Chip select code DODO, used to select
status ignoring the statuses of SDo and CLo. The the; LH5821-5823, cannot be used for the
device enters the enable status when the LC is set LH6826.
at high and the clock CLo is supplied. • <b signal
• CLo signal The 1> is a display clock input. The clock is
The CLo is a serial transfer clock input used for supplied from the LH5821-5823.
writing or reading serial transfer data SDo. • H signal
• SDo signal The H pin accepts an LCD frame sync signal
The SDo is a 10-bit serial transfer data line. from the LH5821-LH5823. When power is turned
Data consists of two control bits and 8 data- bits. on, the internal timing signals of each device are
When in the Read mode, the SDo pin functions as asynchronous with each other. They are synchro-
an output to deliver 8-bit RAM data in serial nized when the H signal is activated.
form. When read or write operation is completed, • Auto clear
the lower 6 bits, Ao-A5, of the RAM address are When power is turned on, the display provides
incremented. Bits A6 and A7 do not change, an OFF pattern (screen clear). The Auto Clear fea-
however. ture is deactivated when all the chip select duty
• CSo-CSs pins data are set at "I" whereupon the contents of RAM
The CSO-CS3 are chip select inputs. On: the are displayed on the screen. At this time the chip
LH5826, select duty does not change.
the chip select code can take on a value between
.--.......-.----,---SHARP---.-.--.-~
888
LCD Dot Matrix Segment Driver CMOS LSI LH5035A1LH5036A
LH5035A/LH5036A
LCD Dot Matrix Segment Driver CMOS LSI
The LH5035A/LH5036A are segment driver LH5035A~ :::: ~ ;:: al ..; ~::t: en Iii eli Jl :2 ~ t3..3 U 0 en <:> _ '" '" ...
~~oo~»>UUUUU~~>U~~::t:oooooooooo
CMOS LSls for LCD dot matrix graphic dis- 7 71 1 69 6 67 66 6 64 6 62 61 60 59 5 5 56 5 54 53 52 51 50 49
play. To change the built-in 3.2K bit RAM con-

o
tents enables the display pattern to be changed.
• Features
1. Display data RAM: 3200 bits
2. Segment output: 80 bits
3.1/32 or 1/40 duty
4. Automatic address modify
5. Scroll function
Top View
LH 5036A _ ¢ _ N 0 _ 0 0 ._
""., '"' _ =
-<: :::UCIlif:JfflffJZO
;:)..JU 000 0 N ... or> '"
IfJlfJlfJoo»>ZUUUU~OO>U..J~XlfJlfJlfJrnrn
7 71 7 69 68 67 66 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Top View
--.-------SHARP-.-.------
889
LCD Dot Matrix Segment Driver CMOS LSI LH5035A/LH5036A
• Block Diagram
LCD Power
, Supply
Frame
Sync. 5'~--<P--;"'----------------'
Clock Display Controller 1---->01
RAM
40 X SObits
Display
Clock
GND
Load Serial Data CH (NCO)

Control Input I Output
o (NC') is for LH5036A.
.• Absolute Maximum Ratings

Parameter Symbpl Ratings Unit Note
Vee -0.3-+0.7 V 1
VOP -0.3-+16 V
Pin voltage
VTl -O.3-V ee +0.3 V 1,2
VT2 -0.3-Vop +0.3 V 1,3
Storage temperature T s '" -55-+150 "C
Note 2: Applied to pins HSi, ~ 0, LC. CL o• SDo• CSO-CS 3, CH
Note 3: Applied to pins V~. VB. SO-S79

Supply voltage Vee 4 6 V
Display voltage Vop 9.6 14.4 V
--~---""""'~-SHARP,'-'-----------
890
LSD Dot Matrix Segment Driver CMOS LSI LH5035A1LH5036A
• DC Characteristics (Vee=4.0-6.0V, Vop =6.0-15V, Ta=-5-55t)
Parameter Symbol Conditions MIN. TYP .. . MAX. Unit Note

VIH 2.4 Vee
Input voltage 1 V 4
V1L 0 0.8
VIH 3.2 Vee
Input voltage 2 V 5
V1L 0 0.8
VOH IOH=400pA 2.4
Output voltage V 6
VOL IOL =1.6mA 0.8
IOH VOP-VOHI =lV 100
Output current pA 7
IOL VoL =lV 100
Vop =15V, Vee=6V .pA
Logic current consumption lee 50 300
Durling no· load display
f~ =4kHz
Display current consumption CLo=OHz pA
lop 1 20
1140 duty
Input current I ILl I V1N=OV or Vee 0.1 1.0 pA 8
Output leakage current I lLO I VOUT=OV (Va) or Vee (V A) 0.1 10 pA 9
Note 4: Applicable to pins LC, CL o, 50 0 , CS O-CS 3 , CH; Vce =4.5-5.5V
Note 5: Applicable to pins ;'0, HS;; Vcc =4.5-5.5V
Note 6: Applicable to pins 500 ; Vcc =4.5-5.5V
Note 7: Applicable to pins 50 -5 79 ; VOH " VOHl is light signal output "High", "Low" voltage
Note 8: Applicable to all input pins
Note 9: Applicable to all output pins, ( ) applicable to segment output
Vee + Vee t t ~
[ CLoLSDo (10 HSi
CH LC
t-i.
,,--CS
L CLo LSDo (10 HSi t...L
CH LC 'CS
LH5035A LH5035A
VDP VA VB
r--n"-+-+--+-IVD~X RY DYoDYl
C~· R
~o
......... I.......................,H VA BPo ~ 0 0-- ---- 79 - - --- - - - -- ---- - - - - - --- -- ---- -- 560 - - ---·639
C~· r LH5030 I ..!Q.../ I
WI VM BP3.' 39
IC~' r BP40 ~ 0 Dot matrix LCD
~:"""-R-~VB BP7•.AQ,,; 3~ 0 ------79 - - -- - -- -- - --- - - - - -- - - - -- -- - - ---- - 560 ---- --639

~-+----4GND
7," vr ¢Jo HSi
~~~~~--------------------------~~~~~~~
80 801
Vee SO-S7' SO-S7'
LH5035A LH5035A
4 4
CS-f-.. LC1CHh CS-f-." LC1CHh
HSi (10 SDo CLo I '1Ir HS, (10 SDo CLo I '1Ir
Vee, GNO 5 iii TiT T
VDP'VA'VB~:=!;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cpu{ ============~:±==================~t==~
.---~-------SHARP -.------,-------
891
LCD Dot Matrix"Common Driv~r CMOS LSI LH5030
LH5030 LCD Dot Matrix Common Driver CMOS LSI

The LH5030 is a common driver CMOS LSI for
LCD dot matrix graphic display. A built-in CR l~~~~E<~=U~~~»~oOO ~~~~~
~~~~Z»»Z>Q~Q~~~~~~~~~~
oscillator generates synchronous signal and clocks 717 6766 6266 5 5 5 5549
8 BPs
necessary for display to send to a segment driver. 0 47 BP6 .
46 BP1
45 BP,
44 BP,
43 BP10
• Features BPlit 42 BPIl
1. Common outputs : 80 bits

BPe8
BP61 ,
41 BP12
BPIJ
BP66 BPI4
2. Built-in CR oscillator BP658 BPIS
3. Selectable duty ratio

1/32,1140, 1164, 1180 duty
(2 pairs of common output, if 1132, 1140)
1111 4116171819 12
Top View
• Block Diagram
Frame Sync. Clock

r-----~55ir------------,
LCD Driver
Test 54
Input
LCD
Decoder AC
Generator
Frame
OSC Counter Sync.
Controller
L---------------{i56r-------{
Display Clock
892
LCD Dot Matrix Common Driver CMOS LSI LH5030

Vee -0.3-+7.0 V 1
VDP -0.3-+16 V 1
Pin voltage
VTl -0.3-V ee +0.3 V 1,2
VT2 -0.3-VDP +0.3 V 1,3
Storage temperature Totg -55-+150 "C
Note 1: Referenced to GND
Note 2: Applicable to pins HS" ; 0, RX, RY, DY 0, DY 1
Note 3: Applicable to pins BP o-BP79, V A, VB, VM

Display voltage VDP 6 15 V
• DC Characteristics (Vee=5V±lV, VDP =6-15V, Ta=-5-+55"C)

VIR 2.4 Vee
Input voltage V 4
V1L 0 0.8
VOH IOH=400pA 2.4
Output voltage V 5
VOL IOL =1.6mA 0.4
IA VDP -V A=lV, VDP =6V 10 30
mA 6,8
Is VB =lV, VDP =6V 10 30
Output current IOH VDP -VoH =lV, VDP =6V 1.5 5
10M VM-V OM =lV, VDP =6V 1.5 5 mA 7
IOL VoL =lV, VDP =6V 1.5 5
Input leakage current I ILl I V1N=OV or Vee 0.1 1 pA 4
HSi. Po: VOUT=OV or Vee
Output leakage current I lLO I BPo-BP79: VOUT=OV or VDP
0.1 1 pA
Icc VDP =15V. Vee=6V no load 50 150 pA

Current consumption
IDP Durling no-load display (f ~ =8kHz. 1/80 duty) 2 6 pA 9
Note 4: Applicable to pins DY o• DY 1; Vcc =5V±10%
Note 5: Applicable to pins HS i• ;0; V cc =5V±10%
Note 6: Applicable to pins VA, VB
Note 7: Applicable to pins BPo- BP 79
VOH and VOL are the high and low voltage resulting when the scan signal is output to the common pin. When the voltage
division resistance R for display equals r. (See System Configuration Example.)
Note 8: This specification prescribes the internal transistor drive force of the LSI. The normal maximum effective current of IA • IB is 10
mAo -
Note 9: When pins VA. V M and VB are open.
893
• AC Characteristics (V ee =5V±IV, Vop =6-15V, Ta=-5-+55"C)

Sync. signal delay to ~ 0, HSi pin load CL =15pF 50 100 ns
Display clock frequency ( ~ 0) f~ Rf=R~±2%, Vee =5V±10% fo-30% fo fo+30% 1,2
Note 1: When f+ =l/tRc, Ro=530kO, fo=3.0kHz
Note 2: When fo=2.24kHz-8.0kHz (Combination range of R, resistance)
i----tRCo-----.f
• Pin Description
Pin name No. of pins I/O Functions
Vop, VA, VM• VB 4 Power supply for liquid crystal drive
DYo• DY 1 2 I Duty selectinput
T 1 Test input
RX 1 Internal clock oscillation pin
RY 1 Internal clock oscillation pin
HS j 1 Frame sync. signal
0
~o 1 Display clock
BP o-BP 79 80 Liquid crystal common drive signal
894
.. v
L l l 1
L
Vr CLo SDo ;0 HSi 4
I-f-cs
L
CLo SDo ;0 HSi 4.
CH LC CH LC ~S
LH5035A --------------------- LH5035A
VDP VA VB ~Vr~ SO-S79 SO-S79
~. R
V RX RYDX.DYI
DP ~~ ~~
\' ~
II
VA BPo 0 0------79 - - --- - - - -- - - --- - - - - --- -- ---- -- 560 - - ----639
C~·
___ I ~r \
VM· LH5030 BP 39 Pl!...V 39
~. r BP •• 0 Dot matrix LCD
~ 39
i. \ \
VB
C: R'
GND
BP79 0------79 -- --- ----- --- - - - --- - ---- --- - ---- - 560 ------639
Vee 1/10 HSi
8~ 8~
"'" J
Vee SC-S79 SO-S79
~--------------------
LH5035A LH5035A
4 4
CS~ GND LClCH CS-+--"
~
HSi _. SDo CL. LClCH
HS; ~o SD. CL.
Vee, GND
VDP,VA,VB·
5 TTT f f t f
CPU{
" ..--..-~------SHARP-.-.-.-----
895
LH5031 LCD Dot Matrix Common Driver CMOS LSI

The LH5031 is a common driver CMOS LSI for
LCD dot matrix graphic display. A built-in CR
oscillator generates synchronous signal and clocks
necessary for display to send to a segment driver.
• Features
l. Common output: 32 bits
2. Built-in CR oscillator
3. Duty ratio: 1/32 duty
Top View
• Block Diagram
Output
______ __________
~ ~~A ~,
Frame Sync. Clock
}----'---(24}---------.,
LCD Driver
Test 23
Input
LCD LCD
Decoder AC Power
Generator Supply
Frame
OSC Counter Sync.
Controller
L-------------~25r-------------------------------------~
Display Clock
--------SHARP------------
896
(

Vee -0.3-+7 V 1
Vop -0.3-+16 V 1
Pin voltage
VTl -0.3-Vee +0.3 V 1,2
VT2 -0.3-Vop +0.3 V 1,3
Storage temperature -55-+150 "C
T s'"
Notel: Referenced to GND
Note 2 : Applied to pins HS;, 1> 0, RX, RY, DY o, DY 1
Note 3 : Applied to pins BP o-BP 79, VA, Va, VM

Display voltage Vop 6 15 V
• DC Characteristics (Vee=5V±lV, Vop =6-15V, Ta=-5-+55"C)

VOH IoH =400 pA Vee- O.S
Output voltage V 4
VOL IOL =1.6mA O.S
IA VOP-VA=lV 10 30
rnA 5
IB VB=lV 10 30
Output current IOH Vop -VoH =lV 1.5 5
10M VM-V OM =lV 1.5 5 rnA 6
IOL VoL =lV 1.5 5
HS j , ~ 0 : VOUT=OV or Vee
Output leakage current Iw 0.1 1 pA
BPo-BP 31 : VOUT=OV or Vop
Icc Vop =15V, Vee=6V Durling 25 SO
Current consumption pA
lop no· load display (f ~ = 3.2kHz) 1 3
Note 4 Applicated to pins HSi, 1>0; Vcc =5V±10%
Note 5 Applied to pins VA, Va
Note 6 Applied to pins BPo, BP 31
V OH and VOL are the high and low voltages resulting when the scan signal is output to the common' pin.
---------SHARP---~------
897
• AC Characteristics (V ee =4-6V, Ta=-5-+55t:)

Sync. signal delay time tn 50 ns
Display clock frequency ( <} 0) f~ Rf =Ro ±5% fo -30% fo fo+30% 1,2
Note 1 :. When f~ =lItRc, Ro =850kO, f o=2kHz
Note 2 : When fo= 1012kHz-3.2kHz (Combination range of R, resistance)
i----tRc----ooj
1/>10
• Pin Description
VDP, V A, VM, VB 4 Power supply for liquid crystal drive
I
T 1 Test input
RX 1 Internal clock oscillation pin
RY 1 Internal clock oscillation pin
HSi 1 Frame sync. signal . ,
0
<}o 1 Display clock
BPo -BP 31 32 Liquid crystal common drive signal
VDP 'fA VB ~
VDp RX RY
~~ Rl
~~ ~r VA. BPo 0,
V LH5031 I ~ :
,
Dot matrix LCD
Ca" M BP31 ---y'
::'1
r
VB
31 0------ 79------------- ----------- ---------- 560----·-639
C/" ER
11 ls~
GND
~Ir
Vee "'0 H8; 8
vL 80-879
----------------------
SO-S79
LH5036A LH5036A
4 4
C8-+" CS+-;>
HS, ¢o SDo LC CLo HS; ;0 SDo LC CLo

Vcc, GND
VP,VA,VB
5 Tf i iii
cpu{
.---~----SHARP.-..------.- ...... - -
898
LCD Character Display CMOS LSI LH5003/LH5004
LH5003/LH5004 LCD Character Display

CMOS LSI
LH5003
The LH5003/LH5004 are dot-matrix LCD con-
troller driver capable of displaying 128 kinds of u~ "~ ~ ~ Q
U Q z _ _ ;>
alphanumeric and symbolic characters. They are the
most suitable LSls for constructing small dot-ma-
trix LCD systems under under the control of 4-bit
or 8-bit microcomputer.
• Features
1. CMOS process
2. 5 X 7 dot-matrix LCD controller/driver
3. Display data RAM
240 bits (LH5003)
320 bits (LH5004)
4. Character Generator 128 patterns N_ln..,.""'="'_'"''''
5. Driving method duty··· 118 duty 0000000>0000000
Top View
6. Character configuration is 5 X 7 dots plus
cursor LH5004
LH5003 (Master) 6 digits ~ ~ ~ ~ z
u CG U .0 S
LH5004 (Slave) 8 digits
7. LCD drive circuit
LH5003 ; Common signal 8 bits
Segment signal 40 bits
LH5004 ; Segment signal 30 bits
8. Single power supply: - 5V (TYP.)
Top View
......-.---------SHARP--~---------
899
• Block Diagram
LH5003 Common Output··
Clock
Segment
Output
Data Input
,
Segment Output
LH5004
Segment Output
Display
Control
Signal
Data
Control
Signal Segment
Output
Data Input
.
Segment Output
-"~------SHARP-'-'------
900

Voo -0.3-+8.0 V
Pin voltage
VIN -0.3-V oo +0.3 V

Supply voltage Voo 4.2-6.3 V
Oscillator frequency fCLK 32-320 kHz
• Electrical Characteristics (V oo =5V,GND=OV, Ta=-10-+60"C)

VIL 1
1
VIH 4
r--
Input voltage VM 2.5 V
~
VA
VB
3.5
0
4
1
5
1.5
c--L
4
IlL VIN=OV 1
Input current pA 1
IIH VIN =5V 1
VaLl VB V B+O.2
No-load condition 5
VOHI V A-0.2 VA
r--
VaLl I 10L I =50 pA 0.8
6
Output voltage VOHI 10H= 50 pA 4.2 V
VOL3 0 0.2
r--
VOM -- No-load condition V M -0.2 VM VM+0.2 7
VOH3 4.8 5
1m fCLK =32kHz 28 50
Current consumption 102 fCLK =64kHz 60 100 pA 8
103 fCLK =320kHz 220 400
Note 1: Applied to pins 10 -1 7, VFL, CLK, RST, CE, DISP, DIN
Note 2: Applied to pin VM
Note 3: Applied to pin VA
Note 4: Applied to pin VB
Note 5: Applied to pins OU-OS5
Note 6: Applied to pin CS
Note 7: Applied to pins HI-Hs
Note 8: Output pin is opened and input pin set to GND level.
------------SHARP----------
901
• Functions
Pin description
Pin name No. of pins' 110 Connect to Functions
Voo, GND 3 Power supply for logic circuit
Power supply VM=VOO/2
VA, VB, VM 3 Power supply for liquid VA=VM+~V
crystal drive VB=V M- ~ V (~V=1.0-VM)
Character code input (10 - 16 ) from MPU
10 -1 7 8
Cursor display data input (I7)
High: character data read
DIN 1
I one character shift in display memory
"High" : Display mode
DSP 1 MPU "Low" : Blank mode
(reset of cascade control data
transfer control circuit)
CLK 1 Clock pulse input
"High" : Operation start signal
RST 1 (reset of cascade controller, cascade control
data transfer control circuit, ring counter, etc.)
Power
CE 1 Chip enable pin
CS 1
supply (CS) *
CE . Chip select pin
-
LCD frame frequency swithcing signal
VFL 1 0 MPU "High: 111024 of clock frequency
"Low" : 11512 of clock frequency
H1 -H 2 8(0)* LCD common signal drive signal
Liq uid crystal
0 11 -0 15 30(40)* LCD segment signal drive signal
*Applied to LH5004
• elK signal The clock signal is a clock pulse • RST Signal The RST signal is used to in-
used to operate LH5003 and LH5004 and is con- itialize the internal control circuits of the LH5003
tinually applied while the power is on. For the CLK and LH5004 by applying the pulse of the RST sig-
signal, apply the clock pulse made in the micro- . nal to this pin immediately after the power is
computer system or a pulse made by dividing this turned on. Synchronize the fall of the RST pulse
clock pulse and in sync with the microcomputer with the rise of the clock pulse, and set the pulse
system. width of the RST pulse to at least four times that of
• DIN signal The DIN signal is used to set the the normal clock pulse width (4 T CK .)
data in the display memories of LH5003 and • 10-17 signal The 10-17 signal is an 8-bit par-
LH5004. Each time the DIN signal rises, it reads allel signal that determines the characters and sym-
display data corresponding to the character code bols to be displayed. Select the desired characters
applied to pins 10 through 17 into the display mem- using the data of pins 10-16 (see the table relating
ory and shifts the existing contents of the display input codes with displayed characters and sym-
memory one character. Set the pulse width of the bols). When the h signal is high, the cursor is dis-
DIN signal to at least two cycles of the clock pulse playep, and when it is low, the cursor is displayed,
(a pulse width of 2TCK or greater when the clock and when it is low, the cursor is blanked out.
pulse period is T CK.) LH5003 and LH5004 are controlled from the mi-
• DSP signal The DSP signal determines the crocomputer system by the following procedure.
display condition. When it is high, the display (1) The clock pulse is applied continually to the
mode is set and when it is low, the blank mode is CLK pin during the period from immediately
set and the cascade controller and data transfer after the power is turned on until it is turned
control circuit are reset. Normally, the nsp signal off.
is made high after setting the data in the display (2) Immediately after the power is turned on, the
memories of the LH5003 and LH5004. RST pulse is applied to the RST pin.
902
(3) The DSP and DIN pins are made low. (Not (6) Steps 4 and 5 are repeated for each display
necessary if they are already low.) position.
(4) The character code of the character to be dis- (7) The DSP pin is made high level. (This condi-
played is output to pins 10-17. tion sets the display mode.)
(5) The DIN pin becomes high level and -then low (8) The contents of the display are changed by re-
level again. (Apply one pulse to the DIN pin.) peating steps 3 through 7.
• Input Codes and Displayed Characters and Symbols
(LH5003/LH5004)
- - - - - - - - S H A R P --.-.....-.-..------------
903
LCD Character Display, CMOS LSI LH5003/LH5004
- -\ H -H8 5x7 dot matrix LCO (with cursor)

1
~
0 11 -065 0 71 ,-0 145
8 ,..... ............. 0,
30 40
r-- ~-t-lI -l}

10 l?
U
10 l?
n
(;11-( 65 0 11 0 85
- GNO
Micro computer
I
J
H 1 -H 8
LH5003
iJ LH5004
GNO
system VM
I r--- CE CS, CE
I OSP
eLK DSP DINRSTVDD VA VB CLK DIN RSTV D VA VB
I r t f t
CLK
OSP
DIN 1
Jf
RST
V DDJ
Rl"i ::Cl
___ -II
R21 ::C2
~
Rs ,.C s
R.
U C•
1."
904
VFD Grid Driver PMOS LSI LH1001
LH100 1 VFD Grid Driver PMOS LSI

The LHIOOI is a VFD (Vacuum Fluorescent Dis·
play) grid driver with an internal 20-bit serial
shift register. Can be easily cascaded to extend
the display.
• Features
L Included 20-bit shift registers in a serial input
2. Data controlled by shift clock and chip select
3. Blanking input controlled by duty cycle
4. High output voltage: - 50V (MAX.)
5. High output current: 20mA (MAX.)
6. Built-in output load resistor
Top View
• Block Diagram
Serial Data Output

~----------------------------{6r-----------~------------,
Serial{ 8
Data
Input 9
Chip Select 1 r---------.,>i 20bit Serial Shift Register Serial Data
Blanking 2}------------i;.j Output
Serial 3}----------i-L________________---.-r________________--.J
11 VN (-50V)
Clock
Input
~--------------~vr--------------~
Output
-------------SHARP---------
905

Voo -20-+0.3
Pin voltage'" VN -55-+0.3 V
VIN -55-+0.3
V ss allowable current Iss 70 rnA
Storage temperature T sto -55-+150 'C
*Referenced to GND.
Supply voltage Voo -9.9 -8.1 V
Display voltage VN -40 V
(V oo =-9V, Ta=25'C)
• DC Characteruistics
VIH -1.1
Input voltage V
VIL -4.2
VOH IoH =20mA -1
Output voltage V 1
VOL VN =-50V -48
IOH VoH =-1.1V 50
Output current pA 2
IOL VoL =-4.2V 3
100 Voo =-9V 1.5 .3
Current consumption rnA
IN VN=-50V 4.0 8
Note 1: Applied to pins DG 1 -DG 20
Note 2: Applied to pins SOlO. SOzo
• AC Characteruistics (V oo =-9V, Ta=25'C)

CK frequency tcK 40 kHz
CK cycle time t KSY 25 ps
CK high·level width tKH 12 ps
CK low· level width tKL 12 ps
SI setup time tSIS 6 ps
SI hold time tSIH 6 ps
CK high active time tcSBKL 0 ps
CK low active time tCSBKH ' 6 ps
CK ! -+ SO delay time tKso CL=10pF 20 ps
tu 3 5
Output delay time VN =-50V, CL=100pF ps
to ... 15 20
-~------"'-'-'-----SHARP --------.-
.906
CK
CS
BK
SOlO
S020
Sh
SIz
10%
• Pin Description
Von, GND 3 Power supply for logic circuit
VN 1 Power supply for display
CS 1 Chip select ... select condition when CS="Low "
BK 1 I Blanking ...... blanking when BK="High"
CK 1 Serial clock
Silo SI2 2 Serial data input
SOlo, S020 2 Serial data output
0
DG 1 -DG 20 20 Digit output for fluorescent display tube
l="High" level, O="Low" level
q.
Sh S020
SI2
CS
input BK lHIOOI Dfl 5 x 7 dot matrix fluorescent tube display
CK DG20
VN VDD GND Dot output
Dij
-40V VN
-9V O - - -......-+----------iVDD j=I-5CEl
(i=1-7)
~------------__IIIGND l12048CE2 J<;:::J Input
Ao-A9
*CS input must be high level when power is turned on.
Input
-..--.-------SHARP--------
907
CMOS Driver
~-- .......-,....,.-.--..... --~ -
............... ..........
LH50l0/LH5011
LH5010/LH5011 CMOS Driver

The LH5010/LH5011 are 6-circuit CMOS driv-
ers with 2-common INHIBIT inputs (AIN, BIN).
The LH5010 is a non-inverting type and the
LH5011 is an inverting'type.
The outputs have an open drain construction
'fabricated using a P-channel MOS FET. 15 OUT1(OUTd
They are used as drivers for VFD and interfaces 14 OUT 2 (OUT 2 )
between CMOS LSI and high-voltage MOS LSI. 13 OUT3(OUT 3)
12 OUT.(OUT.)
II OUTs (OUTs)
IOOUT6(OUT6)
• Features
1. CMOS process '( )= for LH5011
2. 6 independent driver circuits
3. INHIBIT input port
4. Non-inverting type······ LH5010 Top View
Inverting type ........... LH5011
5. I6-pin dual-in-line package
• Block Diagram
High Voltage High Voltage

lnput Output Input Output
(Invert Signal)
(LH5010) (LH5011)
----------SHARP.--.--..-~-------
908
CMOS Driver LH5010/LH5011

Supply voltage VDD VscO.5 - Vss+ 2O V
Input voltage VIN Vss -0.5-V oo +0.5 V
Output voltage VOUT Voo-50-Voo+0.5 V
Operating temperature To ~ -40-+85 "C
Storage temperature T sto -55-+125 'c
Supply voltage VDD 3 18 V
Input voltage VIN 0 VDD V
VDD -40"C 25"C 80"C
(V) MIN. MAX. MIN. TYP. MAX. MIN. MAX.
5 4.95 4.95 5.00 4.95
I louT I ~1 pA 10 9.95 9.95 10.00 9.95 V 1
VIN=VSS or VDD
15 14.95 14.95 15.00 14.95
VoH =3V(V oo -2V) 5 -6 5 -9 4
VoH =2V(V oo -3V) 5 -9 8 -11 6
Output high current IOH rnA 1
VoH =7V(V oo -3V) 10 -12 -10 -28 --:8
VoH =12V(V oo -3V) 15 -17 -15 -39 -12
VouT=0.5V,4.5V 5 3.5 3.5 2.75 3.5
VIH VOUT -1.0V, 9.0V 10 7.0 7.0 5.5 7.0 V 2
VouT =1.5V, 13.5V 15 11.0 11.0 8.25 11.5
Input voltage
VouT=0.5V,4.5V 5 1.5 2.25 1.5 1.5
VIL VOUT= 1.0V, 9.0V 10 3.0 4.5 3.0 3.0 V 2
VouT =1.5V, 13.5V 15 4.0 6.75 4.0 4.0
IIH VIH =18V 18 0.3 10 5 0.3 1.0
Input current pA 3
IlL VIL=OV 18 ~0.3 -10 5 -0.3 1.0
Output leak·off VOUT=OV 15 3 3 10
IOFF pA 1
current VOUT =V DD -45V 15 10 10 20
5 4.0 4.0 30
Static current VIN=VDD, Vss
IDD 10 8.0 8.0 60 pA 4
consumption output open
15 16.0 16.0 120
Note 1: Applicable pins OUT j -OUT 6
Note 2: RL =20kO, Applicable pins 1N.L:1N6' AIN BrN
Note 3: Applicable pins IN j -IN 6 AlN, BrN
Note 4: No load condition
-------------SHARP.-.---.-.---
909
CMOS Driver LH5010lLH5011
• Truth Table
Input Output
AIN B; IN LH5010 LH5011
L H L HZ ' High
L H H High HZ·
L HZ HZ
*
H * HZ HZ
*
HZ : High impedance
*
*: Don't care
• Logic Diagram
• LH5010
• LH5011
IN, IN2 INs IN. INs INs

OUT, OUT2 OUTs OUT. OUTs·· OUTs
910
CMOS Driver LH501 OD/LH5011 D
LH5010D/LH5011D CMOS Driver

The LH5010D/LH5011D are 7 -circuit CMOS
drivers with 2 common INHIBIT inputs (A IN , BIN).
The LH5010D is a non-inverting type and the
LH5011D is an inverting type.
The outputs have an open drain construction 17 OUT 1 (OUT I )
fabricated using a P-channel MOS FET.
They are used as drivers for VFD and interfaces
150UT3(OUT3)
between CMOS LSI and high-voltage MOS LSI.
140UT.(OUT.)
130UT,(OUTs)
120UT6(OUT6)
11 OUT 7(OUT7)
•. Features
1. CMOS process
)= for LH5011D
2. 7 -independent driver circuits
3. INHIBIT input port
4. Non-inverting type ...... LH5010D Top View
In verting type . . . . .. .. ... LH 5 011 D
5. 18 -pin dual-in -line package
• Block Diagram
Inhibit Signal
High Voltage Input High Voltage

Input Output
Output
(Invert ~ignaI)
Inhibit Signal Inhibit Signal
(LH5010D) (LH5011D)
'-'-'-'---~--SHARP------------"-'
911

Par.ameter Symbol Ratings Unit
Supply voltage VDD Vss-0.5- Vss+20 V
Input voltage VIN Vss -0.5-V oo +0.5 V
Output voltage VOUT VoO -50-V DD +0.5 V
Operating temperature Topr -40-+85 °C
Storage temperature Tst£ -55-+125 °C
- -40·C 25"C 80"C
Parameter Symbol Conditions Vnn 'Unit Note
(V) MIN. MAX. MIN. TYP. MAX. MIN. MAX.
5 4.95 4.95 5.00 4.95
Output high
voltage
VOH I louT I ~1 pA 10 9.95 9.95 10.00 9.95 V 1
15 14.95 14.95 15.00 14.95
VoH =3V(V DD -2V) 5 -6 -5 -9 -4
Output high VoH =2V(V DD -3V) 5 -9 -8 -11 -6
IOH rnA' 1
current VoH =7V(V DD -3V) 10 -12 -10 -28 -8
VoH =12V(V nn -3V) 15 -17 -15 -39 -12
VouT=0.5V,4.5V 5 3.5 3.5 2.75 3.5
VIN VouT =1.0V,9.0V 10 7.0 7.0 5.5 7.0 V 2
VouT =1.5V, 13.5V 15 11.0 11.0 8.25 11.5
Input voltage VouT=0.5V,4.5V 5 1.5 2.25 1.5 1.5
VIL VOUT= 1.0V, 9.0V 10 3.0 4.5 3.0 3.0 V 2
VouT =1.5V, 13.5V 15 4.0 6.75 4.0 4.0
IIH VIH =18V 18 0.3 10 5 0.3 1.0
Input current pA 3
IlL VIL=OV 18 -0.3 -10 5 -0.3 -1.0
IOFF pA 1
current VOUT=VDD-45V 15 10 10 20
5 4.0 4.0 30
IDD 10 8.0 8.0 60 pA 4
15 16.0 16.0 120
Note 1: Applicable pins OUT1-OUT7,"VIN=Vss or VDD
Note 2: RL=20kO, Applicable pins IN1-IN7, AIN, BIN
Note 3: Applicable pins IN1-IN7, AIN, BIN
--.----~-SHARP-.--'--~-----.-
912
• Truth Table
Input Output
AIN BIN IN LH5010D LH5011D
L H L HZ High
L H H High HZ
L HZ HZ
*
H * HZ HZ
*
HZ : High impedance
*
* :Don't care
• Logic Diagram
• LH5010D
IN7
OUT, OUT. OUT. OUT. OUTs OUT6 OUT 7
• LH5011D
IN, IN. IN3 IN. INs IN6 IN7

OUT, OUT. OUT. OUT. OUTs OUT6 OUT 7
- - - - - - - - - - S H A R P -........... . . . - . - - - - . . . . . . . . . ,
913
LH5012/LH5013 CMOS Driver

The LH5012/LH5013 are 7 -circuit CMOS
drivers. The LH5012 is a non-inverting type and
the LH5013 is an inverting type.
fabricated using a P-channel MaS FET. 150UT 1 (OUT 1 )
They are used as drivers for VFD and interfaces 14 OUT 2 (OUT,)
between CMOS LSI and high-voltage MaS LSI. 130UT 3 (OUT 3 )
120UT,(OUT,)
II OUTs(OUT s )
IOOUT 6 (OUT 6 )
9 OUT 7 ( OUT 7)
• Features
1. CMOS process )= for LH5013
2. 7 independent driver circuits
3. Non-inverting type ...... LH5012
Inverting type ........... LH5013
• Block Diagram
High Voltage High Voltage

Input Output Input Output
(Invert Signal)
(LH5012) (LH5013)
----------~--SHARP---'" ........... - . - . - . . . . - -
914

Supply voltage Voo Vss -O.5-V ss +20 V
Input voltage VIN Vss-O.5- Voo+O.5 V
Output voltage VOUT Voo -50-V oo +O.5 V
Operating temperature Toor -40-+85 'c
Storage temperature T st• -55-+125 'c
r-- -40"C 25"C 80"C
Y{?r MIN. MAX. MIN. TYP. MAX. MIN. MAX.
5 4.95 4.95 5.00 4.95
Output high
VOH IouT ;;;;l1'A 10 9.95 9.95 10.00 9.95 V 1
voltage
15 14.95 14.95 15.00 14.95
VoH =3V(V DD -2V) 5 -6 -5 -9 -4
Output high VoH =2V(V OD -3V) 5 -9 -8 -11 -6
IOH rnA 1
VoH =12V(V oo -3V) 15 -17 -15 -39 -12
VouT=4.5V 5 3.0 3.0 3.0
VIH VouT=9.0V 10 8.0 8.0 8.0 V 2
Input voltage VouT=13.5V 15 12.5 12.5 12.5
(LH5012) VouT=0.5V 5 1.0 1.0
VIL VOUT =1.0V 10 2.0 2.0 V 2
VouT =1.5V 15' 2.5 2.5
VouT=0.5V 5 3.5 3.5 2.75 3.5
VIH VOUT =1.0V 10 7.0 7.0 5.5 7.0 V 2
Input voltage VouT =1.5V 15 11.0 11.0 8.25 11.0
(LH5013) VouT=4.5V 5 1.5 2.25 1.5 1.5
VIL VouT=9.0V 10 3.0 4.5 3.0 3.0 V 2
VOUT=13.5V 15 ,4.0. 6.75 4.0 4.0
IIH VIH =18V 18 0.3 10 5 0.3 LO
Input current I'A 3
IlL VIL=OV 18 -0.3 -10 5 -0.3 -1.0
Output leak -off VOUT=OV 15 3 3 10
IOFF I'A 1
current VouT=Voo-30V 15 10 10 20
5 4.0 4.0 30
IDD 10 8.0 8.0 60 I'A 4
15 16.0 16.0 120
Note 1: Applicable pins QUT,-QUT7, V'N=VSS or Voo
Note 2: RL=20kO, IouT;;;;lI'A, Applicable pins INI-IN7
Note 3: Applicable pins IN,-IN7
'--~--'-'----SHARP----'-----
915
• Logic Diagram (1 circuit)
• LH5012
Voo
I--C
Vss
• LH5013
Voo
·IN-C
Vss
-.-------~-SHAR/P - - - - ......... --------------...

916
CMOS Driver LH5012D/LH5013D
LH5012D/LH5013D CMOS Driver

The LH50I2D/LH50I3D are 8-circuit CMOS
drivers. The LH5012D is a non-inverting type
and the LH50 I3D is an inverting type.
fabricated using a P-channel MaS FET. o 170UT j (OUT j )
They are used as drivers for VFD and interfaces
between CMOS LSI and high-voltage MaS LSI. 150UT 3 (OUT 3 )
140UT 4 (OUT 4 )
13 OUTs (OUTs)
120UT 6 (OUT 6 )
11 OUT,( OUT,)
• Features
100UT s (OUT s )
1. CMOS process
2. 8 independent driver circuits )= for LH5013D
3. Non-inverting type ...... LH50I2D
Invertingtype ........... LH50I3D
4. I8-pin dual-in-line package Top View
• Block Diagram
Input High Voltage Input High Voltage

Output
Output
(Invert Signal)
(LH5012D) (LH5013D)
'-'---~--~SHARP--------
917

"

Supply voltage VDD Vss -O.5-Vss +20 V
Input voltage VIN Vss -O.5-V DD +O.5 V
Output voltage VOUT VDD -50-VDD +O.5 V
Operating temperature , Toor -40-+85 °C
Storage temperature T.t2 -55-:-+125 °C
Supply voltage VDD : 3 18 V
,-- -40"(; 25"(; 80"(;
y.qf MIN. MAX. MIN. TYP. MAX. MIN. MAX.
,J 5 4.95 4.95 5.00 4.95
Output high voltage VOH I louT I ~lpA 10 9.95 9.95 10.00 9.95 V 1
15 14.95 14.95 15.00 14.95
VoH =3V(V DD -2V) 5 -6 -5 -9 -4
Output low VoH =2V(V DD -3V) 5 -9 -8 -11 -6
IOH mA 1
VoH =12V(V Do -3V) 15 -17 -15 -39 -12
VouT=4.5V 5 3.0 3.0 3.0
VIH VouT=9.0V 10 8.0 8.0 8.0 V 2
Input voltage VouT=13.5V 15 12.5 12.5 12.5
(LH5012D) VouT=0.5V 5 1.0 1.0
VIL VOUT =1.0V 10 2.0 2.0 V 2
VouT =1.5V 15 2.5 2.5
Vn,=0.5V 5 3.5 3.5 2.75 3.5
VIH VOUT =1.0V 10 7.0 7.0 5.5 7.0 V 2
Input voltage VlL =1.5V 15 11.0 11.0 8.25 11.0
(LH5013D) VOuT=4.5V 5 1.5 2.25 1.5 1.5
VIL VouT=9.0V 10 3.0 4.5 3.0 3.0 V 2
VouT =13.5V 15 4.0 6.75 4.0 4.0
IIH VIH =18V 18 0.3 10 _5 -0.3 1.0
Input current pA 3
IlL Vu;=OV 18 -0.3 -10 5 -0.3 -l.0
IOFF pA 1
current VOUT=VDD-30V 15 10 10 20
5 4.0 4.0 30
Static current VIN=VDD• Vss
IDD 10 8.0 8.0 60 pA 4
consumption ,output open
15 16.0 16.0 120
Note 1: Applicable pins OUTI-OUTs. VIN=VSS or VDD
Note 2: RL=20kO. IouT;:;>;lpA. Applicable pins INI-INs
Note 3: Applicable pins IN.-INs
-.-----~~-SHARP'~.....--~~-~--
918
• Logic Diagram (1 circuit)
• LH5012D
VDD
IN-t
• LH5013D
IN~
919
___.-__.-_.-_..........
Analog .Olock CMOS IC
_:.iI._~ .._......,...._ LR34~6
LR3428 Analog Clock CMOS IC

The LR3428 is a CMOS IC for electronic clocks
using a 4.19MHz crystal, 23-stage frequency di-
vider, motor drive circuit and alarm output buffer.
• Features
l. Low power consumption
2. Low impedance output buffer
3. Modulated alarm output
4. Single power supply: + l.5V
5. 1Hz stepper motor drive
6. 4.194304MHz crystal oscillator
7. 8-pin dual-in-line pac.kage
Top View
• Block Diagram
ll-stage 12-stage Output

Divider Divider Control
Circuit , ---'l/"
Alarm
Control 6 Alarm Output
Circuit
VDD(1.5V) Reset Input
920
Analog Clock CMOS IC LR3428

VDD -0.3-+2.5 V
Pin voltage * VIN -0.3-V oo +0.3 V
VOUT -0.3-V oo +0.3 V
* Referenced to Vss
• Operating Conditions (Ta=25'C)

Supply voltage VDD + 1.15- + 1.80 V
Oscillation start voltage Vose 1.15 V
• Electrical Characteristics (fosc=4.194MHz, CG =C o =15pF, C1 =400, Ta=25'C)

Current consumption IDD VDD =1.5V 25 50 p.A
Oscillation stability Mlf Voo= +1.2-+ 1.7V 1 ppm
Rsatl
Output on resistance Voo=1.2V, RL =1800 50 100 0
(P+N)
Rsat2
Alarm output on resistance Voo=1.2V, RL =9000 150 300 0
(P or N)
RESET pin pull up resistance RR Voo =1.5V, VIN=OV 10 kO
--...-...-..--.----.-SHARP . - . - . - - - - - -
921
Analog Clock CMOS IC
• Output Waveform
_
........................... ....................-..-........................ .
J
LR3428
(1) OUT1,OUT2
-.;o+-+-:31.25ms
,
t-ls~
I
I
I
z
OUT _ _---I "----i--,....--Ir
:":18...
. . -----Jn~-+!
i:
---
I I I
RESET U
I
LJi--~
I I
1
(2) Alarm output
,4t'-6.25ms -t-t-125ms ~8kHz
ALoUT III~III"III~, J~IIIIIIII~II 1111111111111111111\ 11111111,1111111
.. ~OOm!1500m _ I
0(
:
I ~~
'1
i
I
1,
-----------~' ~'-----------
RESET LJ
o
+-------12
Alarm Output
L -_ _--{ M }--_ _ _--l
Stepper Motor
I'
.--.------------$HARP .-----.-.....-.-..----
922
Analog Clock CMOS IC LR3429·

using a 4.19MHz crystal, 23-stage frequency di-
• Features
4. Single power supply: + 1.5V
6. 4.194304MHz crystal oscillator
Top View
• Block Diagram
Output
ll-Stage 12-Stage Control } Mo<o< Dd",
0,,;11 ."•• { Divider Divider Output
Circuit
Alarm
~
Control 2 Alarm Output
Circuit
Vss(OV) VDD (l.5V) Alarm Input
.--------SHARP-------.-
923
Analog Clock CMOS IC
~.-:~
•
....--..-..
Absolute Maximum Ratings
-.-..-..-..-.~.-..-..-..-..-..-
. LR3429
Parameter Symbol Ratings Unit·

Voo -0.3-+2.5 V
Pin voltage * VIN -0.3-V oo +0.3 V
VOUT ' -0.3-Voo +0.3 V
* Referenced to Vss
• Operating Conditions (Ta=25"C)

Supply voltage ,Voo + 1.15- + 1.80 V
Oscillation start voltage Vase 1.15 V
• Electrical Characteristics (fosc=4.194MHz, CG=C o =, 15pF, C1 =40.0, Ta= 25"C)

,
Current consumption 100 Voo=1.5V 25 50 p.A
Oscillation stability ~f1f Voo= + 1.2- +1.7V 1 ppm
Rsatl
Output on resistance Voo=1.2V, RL =180n 50 100 .0
(P+N)
Rsat2
Alarm output on resistance Voo=1.2V, RL =900n 150 300 .0
(P or N)
T 1 pin pull up resistance RT Voo =1.5V, VIN=OV 10 k.o
)
- -.......... ---~.--:r-SHARP-----~---~-
924
• Output Waveform
(1) OUT" OUT2
OIlT, ~~_ _ _ _ _=:rr-_.... 31.25ms.

··ni...---
31.25ms
'----:--------\
l L...--_
~ls-Lls~
~2S---;oj
(2). Alarm output (Tl pin connected to Vss)
f-------ls-----~
When T 1 pin is connected to V DD (+) or open.

the alarm output is at V DD (+)
Alarm 0
Output en 7
N
v
(Y) CD
D::
Stepper ....
Motor
Crystal
.--,------~SHARP-.----~---
925

using'll 32.768kHz crystal, 16-stage frequency di-
• Features
6. Included oscillator output capacitor CD
7. 32.768kHz crystal oscillator
Top View
• Block Diagram
Oscillator 4-Stage 12-Stage Output Motor Drive

Circuit Divider Control } Output
Divider
Circuit
Alarm
VDD Control 2 Alarm Output
Circuit
Vss(OV) VDD(1.5V)
.--....-.... .......... - - - - - - - - - - S H A R P - - - - - - ........... - - - - -

926

Voo -0.3-+3.0 V
Pin voltage' VIN -0.3-V oo +0.3 V
VOUT -0.3-V oo +0.3 V
* Referenced to VDn
• Operating Conditions (Ta=25'C)

Supply voltage Voo +1.10-+1.80 V
Oscillator frequency fase 32.768 (TYP.) kHz
. Oscillation start voltage Vase 1.2 V
• Electrical Characteristics (fosc =32:i68kHz, Cc =22pF, C1 = 20kn, Ta=25'C)

Current consumption 100 Voo=1.5V 1 3 pA
Oscillation stability Mlf Voo= + 1.2- + 1.7V 6 ppm
Rsatl n
Output on resistance Voo=1.2V, RL =300n 50 100
(P+N)
Rsat2
Alarm output on resistance Voo=1.2V, RL=900n 150 300 n
(P or N)
ALIN pin pull up resistance RAL Voo =1.5V, VIN=OV 10 kn
Oscillation start time Tosc Voo=1.2V 10 s
Oscillation circuit built-in
Co 25 pF
capacitance
-- VIH Voo=1.5V 1.35 1.5 V
ALIN input voltage
VIL Voo=1.5V 0 0.15 V
----------SHARP------.-.-.-..........."
927
• ,Output Waveform
(1) OUll, OUl2
·li31.25ms
OUT! ---1l n. . ._~nL...__
l--2s~
1- 1
1s 1 r-31.25ms
OUT2 n'--_-'n rL
(2) Alarm output (ALIN connected to Vss)
ALIN - - - - - - - - - - - - - - - - - - - - - V s s
62.5m~ each
lot tt t t t" ~2'()48HZ

ALouT_ _ _ _ ~
~ ---!I
L......_ _ _ .' Vss
VDD
1s ...
When the ALIN input is connected tOVDD or open, the alarm output is at Vss.
When the ALIN input is set at approx. 1/2 VDD, a continuous output of 2,048Hz appears at the alarm output.
o
Alarm ~--~2
Output
Stepper
Motor
928
Analog Clock CMOS IC. LR3468

using a 32.768kHz crystal, I6-stage frequency di-
VDD OSCIN
Vss
o OSCOUT
• Features OUT, ALouT
1. Low power consumption AC OUT2
6. Included oscillator output capacitor CD
• Block Diagram
Output
Oscillator 4-Stage 12-Stage 3 } Motor Drive.
·Control
Circuit Divider Divider Output
Circuit
Alarm
CQnt~1 6 Alarm Output
VDD Circuit
L -____________ ~ } ________ ~ } ________ ~.(}_----------------~
Vss (OV) VDD (l.5V) ;Alarm Control
'--''-~--,----SHARP-~'-------
929
. Analog Clock CMOS IC LR3468

VDD -0.3-+3.0 V
Pin voltage * VIN -O.3-V DD +0.3 V
VOUT -0.3-V oo +0.3 V
Storage temperatllre Tstg .... 55-+1'50 t
* Referenced to VDD
• Operating Conditions (Ta=25t)

Supply voltage Voo +1.1-+1.9 V
Oscillation start voltage Vose 1.3 V
• Electrical Characteristics (fosc =32.768kHz, CG =22pF, C1 =20kO, Ta=25t)

Current consumption Ioo Voo=1.5V 10 p.A
Oscillation stability Mlf Voo= + 1.1- + 1.7V 2 ppm/OJ V
Rsatl
Output on resistance Voo=1:2V, RL =6000 120 0
(P+N)
Rsat2
Alarm output on resistance Voo=1.5V, IouT =lmA 200 600 0
(P or N)
AC pin pull up resistance RAL Voo=1.5V, VIN=OV 10 kO
Oscillation start time Tosc Voo=1.5V 5 s
Oscillation circuit built-in
Co 25 pF
capacitance
- VIH Voo=1.5V 1.4 .1.5 V
AC input voltage
V1L Voo=1.5V 0 0.1 V
930
• Output Waveform
(1) OUT1, OUT2
OUT,
-.fl---------------l-.1 -
n----------------
-r--t-' 31.25 ms .
----·VDD
--- Vss
I: Is
-2s
'"I
n----------
~31.25ms
OUT2
n L -_ _ _ _ _ _ _ _ _ _--'_ - --
VDD
Vss
(2) Alarm output (AC input open)
11..-'11' •...,""----------- VOD

ALoUT
------------ Vss
f-I.-----Is----~.I
CG=22pF
.--~----~--SHARP------.------
931
.-..-.~~ .....
Analog Clock CMOS LSI with Electronic Melody Generator
.-.~
,
................................
' ,
~~.-... ..... Ut3465

~
Analog Clock CMOS LSI With Electronic Melody

LR3465 Generator
using a 32.768kHz crystal with stepper motor
drive circuit and melodies, alarm functions.
• Features
1.
Low resistance outputs for stepper motor
"Seconds" stop function
2.
3.
Melody performance with accompaniment
Mask ROM programmable
4.
5.
8 melodies (3-melody select inputs)
6.
Loudness volume control function'
7.
Melody envelope controlled by external CR cir-
cuit
8. 32;768kHz crystal oscillator Top View
9. Single power supply: - 1.5V
10. CMOS process
• Block Diagram
"Seconds"
Stop Input
r-----~----------------------------~~1r_----~
Motor
Oscillation { }
Drive Output
Vss
( -1.5V)
VDD
(OV)
-;; "
"s..e"" :is ...El ~ ...
.~ .~ .~
1~
., ...
0'"
"i.!
.S
:>!
"" c
~~ e~
. . '"
3,e- Il.._ ..
t::
rn
;;;00
-< "
<0
932
Analog Clock CMOS LSI with Electronic Melody Generator LR3465

Vss -0.3-+0.3 V
Pin voltage * , VIN Vss -0.3-+0.3 V
VOUT Vss -0.3-+0.3 V
Operating temperature Tonr -10-+50 "C
* Referenced to VDD
Oscillation start voltage Vose -1.4 V
• Electrical Characteristics (Voo=OV, Vss =-11.5V, Ta=25"C)

Isss Standby no load 5 pA
Issa Melody-ON no load 1 mA
Oscillation start time Tosc Voo=1.4V 10 s 1
V!H -0.3 V
Input voltage 2
V1L -1.2 V
Input current 1 I!HI VIN=OV 2 10 pA 2
Input current 2 I!H2 V1N=OV 10 200 pA 3
Output current 1 IOHI VouT =-0.5V 250 pA 4
IOH2 VOUT= -0.5Y. 3 pA
Output current 2 5
IOL2 VOUT =-1.0V 3 pA
Output current 3 6
Output current 4 7
Output voltage VOUT Vss= -1.2V, RL =3000 0.9 V 8
Output pulse width t 31.25 ms 9
Output cycle TI 2 s 9
Output phase difference T2 1 s 9
Oscillation stability Mlf Vss =-1.7-1.2V 2.5 PPIlVO.IV 1
Note 1: Cn=Cc=22pF ,
Note 2: Applies to STl, ST, -S3, MA pins
Note 3: Applies to SI pin. Melody OFF time
Note 4: Applies to EVl, EV, pins
Note 5: Applies to SOl, SO, pins
Note 6: Applies to ML pin. The value of 10H for melody OFF time.
Note 7: Applies to MH pin. The value of IOL for melody OFF time.
Note 8: Applies to PI, p, pins. RL= 300 (} (Refer to the right figure.
Note 9: Refer to clock specifications.
933
AnaJog Clock CMOS LSI with Electronic Melody Generator LR3465
• Clock Specifications <Command organization>

<Step motor drive output> Predominant melody interval
Predominant envelope control
~t~ Accompaniment interval
'PII J41..-~_"""",n ___ Accompaniment envelope control
I.TI~ Note length control
I
,I
P 21 :
'--T~
n ...---.. .rL <Music selection>
According to the state of the music select in-
I ,I put Sl-S3, one music will be selected from the
By altering PLA, the output pulse width t 8 pieces of music available. The pull-down
can be selected from the following: 15, 31, 46, ,resistor built into the music select pins allows
62, 78, 93, 109 (ms) the pins to be used either connected to Vss or
<Second stop function> open.
Second counting will be performed and the If the music select input state is altered in the
output for the step motor will turn off while middle of performance, the music then speci-
the SS input is ON. On turning the SS input fied will be performed from the start. A
OFF, the second counter is enabled to start. music selection for the LR34651 in which 8
(Maximum error: 31.25ms). pieces of music is written in is shown in the
table below.
• Melody Specifications
<Number of music> Up to 8 pieces Music select Tem- Number of
<ROM> 600 steps X 13 bits input Name pf music po repetitions
<Sound source> 2 sources SI S2 S3 J = T3=VDD T3=V55
<Range> 2.5 octaves H H H Westminster 68.6 1 1
For the sounds in parentheses ( ), only L H H Westminster 96 1 1
H L H 96 8 1
the attack sound output will be generated.
*
Spring (Four
L L H 96 10 1
seasons) Vivaldi
Autumn (Four
H H L 96 8 1
seasons) Vivaldi
Winter (Four
L H L 40 5 1
<Tempo> 15 speeds for each music (The mini- seasons) Vivaldi
mum note length shall be selected from between 31 H L L Chime 192 Endless Endless
-468ms). L L L Alarm 240 Endless Endless
<Note length> 2 kinds (Other notes of different * Twinkle twinkle little star French music
length can be represented by the different number Ii: VDD L : Vss or open
of steps.) <Melody start, stop>
, (Example) If the fastest note in a music is " (1) One shot type
the kinds of note that can be specified by 1
step are '_and 1>. The note length control is Start input ST Jl......___.....;._~n..____
by "I" and "0".
J = 1> (1) + 1> (0) ............................... 2 steps Mode input MA
J. = 1> (1) + 1> (0) + 1>(0) ····,··············3 steps ON
iY = 1> (1) + )l (0) .............................. 2 steps Melody output OFF
The number in parentheses ( ) repre- Auto stop Forced stop

sents envelop control.
<Number of performances> 1-15 times, endless
1
<Commands> Melody command .
snooze command
Control command Jump command
Repetition number setting
comniand '
End command
934
Analog Clock CMOS IC with Electronic Melody Generator LR3465
_ _ _. -_ _. - _. . . .. - . - . -. . .ra. . . . . . ._ . - _
(2) Hold type (Number of repetitions 1-15 (3) Hold type (Number of repetition Endless)
times)
Start input ST.J L
S tart input S T
Mode input MA--------------

Mode input MA
ON'
ON
Melody output OFF...J
r------------------,L-
Melody output OFF' Forced stop/
Forced stop
<Snooze function>
Snooze function allows each music to be
programmed into the mask ROM independent-
ly_ However, the number of musics that can be
selected will be reduced because a program in
snooze function is one of the melody programs.
• System Configuration (LR34651)
3.3JlF
+
LR34651
L5V 33JlF
Note TR,: 2SC1383

TR,: 2SA683
Envelope waveform is determined by

the value of R applied to pins No. 14
and No. 15.
Make sure that pins No. 10 and No.
12 are to be connected to No. 11.
Make sure that pin No.2 is to be con-
nected to pins No. 11 or No. 21.
935
LCD Digital Clock CMOS LSI LR3441
LR3441 LCD Digital Clock CMOS L8.I

The LR3441 is CMOS LSI for LCD display
clocks with a basic three function, daily alarm,
hourly alarm and timer.
• Features
1. Three functions ("Hour", "Minute", "Second")
"Second" display by colon
2. Alarm function with Snooze function
3. Hourly alarm
4. Timer function
5. Instant second set function (1 - 59 sec ..... No
carry to the minute digit)
6. 3V dynamic LCD drive
8. Single power supply : - 1.5V (with voltage
doubler)
• Block Diagram
Control Circuit
Switch Input Segment Output "Common

Output
936

Vss -2.0-+0.3 V 1
VEE -4.0-+0.3 V 1
Pin voltage VIN Vss -0.3-+0.3 V 1,2
VOUTl Vss -0.3-+0.3 V 1,2
VOUT2 VEE-0.3- +0.3 V 1,3
Operating temperature Tope -10-+60 ·C
Storage temperature T stg -5.5-+150 ·C
Note 1: Referenced to VDD
Note 2: Applies to Vss pins
Note 3: Applies to VEE pins
• Operating Conditions (Ta=25·C)

Vss -1.8--1.2 V
Supply voltage
VEE 2Vss (TYP.) V
Oscillator frequency fase 32.768 (TYP.) kHz
Oscillation start voltage Vase -1.4 V
• Electrical Characteristics (Voo=OV, Vss =-1.5V, VEE =-3.0V, Ta=25·C)

Current consumption I tota 1 No load 1.5 3.0 flA 4
Oscillation start time Tosc Vss= -1.4V 10 s 4
Segment output current los Vos=0.5V 20 flA
Common output current loc Vos=0.5V 60 flA
DDC output current 100 Vos=0.5V 60 flA
Vc output current lov Vos=0.5V 120 flA
AL (ACloUT. TSoUT
IOHl VouT=-0.2V 200 flA
Output current
AL (DCloUT' SLoUT• TMouT
IOH2 Vos=0.2V 100 flA
Output current
RSI VIN=OV 700 kO 5
Pull down resistance RS2 VIN=OV 500 kO 6
RT VIN=OV 100 kO 7
VIH Vss =-1.8--1.2V -0.1 0 V 8
Input voltage
VIL Vss =-1.8--1.2V Vss Vss+O.l V 8
Note 4: Co=Cc=22pF, Cl=C2=O.1 pF
Note 5: Applies to O.5HIl H, SF pins
Note 6: Applies to ZA, S" S2, SN ISLoFF, SL, AL pins
Note 7: Applies to TE, TI" Tl2, IR pins
Note 8: Applies to O.5HIlH, SF, ZA, S" S2, SN/SLoFF, SL, AL, IND·SEL, ALoFF, 12H/24H pins
........-..-.-.-.----SHARP--------
937
LCD. Digital Clock CMOS LSI LR3441
,• Specifications
(1) Input control
Symbol Content LR3441
Sl "Hour" set Pull down to V1m
S2 "Minute" set Pull down to VDO
SF Safety Pull down to VDO
ZA o adjust Pull down to VDO
AL Alarm mode switch Pull down to VDO
SL Sleep timer mode switch Pull down to VDO
SN/SLoFF Snooze "ON" sleep "OFF" . Pull down to VDO
ALoFF Alarm output "OFF" Open' drain
12H124H 12 hours/24 hou~s switch Open' drain
INDSEL Indicator select Open' drain
IR Initial . reset Pull down to VDO
O.5HIlH Sleep time 32 minutes/64 minutes switch Pull down to VDO
(2) Operation flow

(i) Function read operation (iii) 0 adjust
Operates only when the switch is
ON and returns automatically
after OFF
I...._ _ _ _ _ _...J 1-59 seconds are truncable
(iv) Alarm time display adjust operation
(ii) Time display adjust operation 1 push 1 word forward

ON more than 2 seconds
hour digit 1Hz forward
minute digit count up 5 minutes
at a time
(v) Sleep time display adjust operation
1 push 1 word forward

ON more than 2 seconds
hour digit 1Hz forward
minute digit count up 5 minutes
at a time
Correct from 1 push 1 word count down
(Example) 2 --+ 3 --+ 5 --+ 10 ... whichever was ON more than 2 seconds count
sel<\cted.0.5H/IH down 5 minutes at a time
-----------SHARP-----P.....-...-..-"------
938
I
I
(vi) Mode display format (iii) Whenever the SN/SLoFF pin is turned ON
while the sleep timer is in operation, the sleep out
Mode Display will go OFF.
Time display (iv) If the SL is turned ON during the alarm out-
HH : MM
Time display SF & S, ON *1 : MM put, the TMoUT and AL(DC)oUT will be output for
adjust operation SF & S2 ON HH *2 another 32 or 64 minutes. The timer interval can
ALON HH : MM be selected by the 0.5HIlH pinto either 32 or 64
Alarm minutes except in the sleep operation.
AL & S, ON *1 : MM
time (v) When S2 has been depressed to set the sleep
AL & S2 ON HH *2
Sleep SL ON MM timer to "0" in rapid feed, it will stay at "0" on
timer SL & S2 ON *3 further depression of S2.
1 Hz flashing
(3) Timer out
* 1 S, 1 count-up with each ON The TM output (DC) will be generated when
* 2 S2 1 count-up with each ON_ Rapid feed by 5 minutes if S2 either the sleep output or the alarm output (DC) is
held ON for more than 2 seconds_
* 3 S2 1 count-down with each ON. Counts-down by 5 minutes generated. The timer out is an OR-circuit of the
if S2 held ON for more tban 2 seconds_ sleep out and AL(DC)oUT. If the ALoFF is ON with
only AL(DC) as the output, the timer out will also
be turned OFF.
• Functions (4) Time Signal
(1) Alarm function The TSouT pin that outputs time signal is pro-
(i) If the set alarm time coincides with the real vided. The output starts at 59 minutes 57 seoncds.
time, the following outputs will be generated at (See the figure below.)
each of the following outputs.
• At AL(AC)ouT 4 minute tone output of 2kHz X
8Hz X 1Hz
• At AL(DC)ouT approximately 32 (64) minute con-
troloutput
• At TMoUT approximately 32 (64) minute control
output 59min OOmin
(ii) When the SN/SLoFF is turned ON while the 57 sec 58sec '59 sec OOsec
alarm output is being g~nerated, the output will be (5) In the case of alarm and sleep overlap
interrupted for approximately 7 minutes until the (i) The figure below shows the state of each
output generation is resumed. Called snooze func- output pin when the sleep timer goes into operation
tion, it can be repeated fot either approximately 32 during the alarm output.
minutes or 64 minutes. When the SL is turned ON, the AL(DC)oUT and
(iii) The alarm indicator selected by the INDSEL TMouT intervals will be s~t to another 64 min/32
pin with the alarm timer being set can "be dis- min. When the SN/SLoFF is turned ON, the TMouT,
played. ALoUT, and SLOFF will be turned OFF.
(iv) With ALoFF switch connected to Vss, the
alarm indicator will not be displayed and alarm AL(AC)OUT ~'--_ _ _ _ _ _ _ __
will not be output even if the alarm time and the
AL(DC)OUT ~I---------"'L
real time coincide. I
I
(v) The alarm control output time can be SLOUT
: L
selected by the 0.5HIlH pin to either 32 or 64 mi- I
I
nutes except when alarm output is being generated. ™oUT ~ 1 ~

I r---64min----,
(2) Sleep timer functio!,) The S W that turns
the AL (DC)auT, I,ALoFFsW'I' SL/SLoFF SW+-
(i) If the SL is depressed with no TMoUT output, TMoUT, and
AL output synchroni zed
either 32 or 64 will be selected according to the SLOUT OFF_
with real time
state of the 0.5HIlH pin and TMouT and SLOUT will
be output.
(ii) The remainder of the time can be displayed
if the SL is turned ON while the sleep timer is in
operation.
--------------SHARP -~.---.-........,.--
939
.-....,~.....,~- ... r..--II:.....,.....,.....,~ ..... ~--~ __........
(ii) When the alar~ time and the real time coin- In this case if the SN/SLoFF i~ turned ON, the
cide while the sleep timer is in operation togener- AL(DC)oUT and AQ(AC)OUT will go OFF never to be
ate the alarm. output, the SLOUT and TMouT intervals output even 7 minutes later. When the ALoF~ is
will be set for another '64 min/32 min. turned ON, only the AL(AC)oUT will go OFF.
(6) Initial reset·
SLOUT ~
. I
I~ If the IR pin is connected to Vss, initial reset will
I I
be applied to immediately reset all the counters and
AL(AC)OUT
~---r:-----;fl~--~----~'--- AM 12 : 00 or a : 00 will be displayed depending
AL(DC)wr
:I
I
I
~ on the 12H system in the case of the former, 24H
TMoUT I i I system in the case of the latter..
~: ' ~
r----64min--r
Switch to put I
(7) Indicator select
AL(DC)OUT
TM OUT and SLOUT
!r-----+!:SN/SL",.,SW --r---J The INDSEL pin can select either the bell mark or
into the OFF state SLo~ ALoUT syncronized
with real time
the note mark.
Note mark: with Voo connected or open
Bell mark: with Vss connected
24J----~
'LCD
:>---'---i46
48
O.l,uF
O.l,uF
0_1,uF
Note) 0.5H/1H : 0.5H : with Von connected or open

1H : with V 55 connected
12H/24H: 12H: with Voo connected
24H : with V 58 connected
940
Digital ON/OFF Clock Timer CMOS LSI LR3419
LR3419 Digital ON/OFF Clock.Timer CMOS LSI

The LR3419 is a CMOS LSI designed to provide
clock and timer functions. The base frequency is
selectable: 50 Hz or 60 Hz line input or 32.768kHz
crystal. It is also capable of driving fluorescent
displays tube (VFD) directly.
• Features
1. "flours-Minutes' display
2. Timer function that permits both ON/OFF
times to be set
3. Power failure indication
4. Directly static-drive a VFD
5. Time base: 50/60Hz line or 32.768kHz crys-
tal Top View
6. Power supply voltage: + 5V
7. CMOS process
8. 48-pin quad -flat package
• Block Diagram
GND
Cont ral Input Test
~=:=~=!=~:::!=~I_~Timer
r
ON/OFF
Detector
Timer
Output
Hour Advance
lO-min Advance
Min Advance 2
Timer ON/OFF 2
Real Time Mode
Timer ON Set Mode
Timer OFF
Set Mode
Segment Decoder/Driver
Segment Output
941
Digital ON/OFF Clock Timer CMOS. LSI

Supply voltage Voo Referenced to GND -0.3-+7.0 V
Inp·ut voltage V IN Referenced to GND -0.3-(Voo+0.3) V
Output voltage BV IMerenced to GND V oo +0.3--23 V 1
Power consumption Po Ta~+25'C J 550 mW
derating ratio Ta>+25'C 5.4 mW/'C
±2.0 1
Pin current II rnA
±1.0 - 2
Storage temperature T st• -40-+100 'c
Note 1: Applies to al-4, bI-a, CI--I, da--t, el-I, ft-1, gl-..a, QL, QH, QT pins
Note 2: . Applies to 110 pins except Note 1
Parameter . Symbol Conditions MIN . TYP. MAX. Unit
Supply voltage Voo Referenced to GND 4.5 5.0 5.5 V
Input voltage V IN Referenced to GND 0 Voo V
Output voltage VQlIT Referenced to GND -21 -19 0 V
• Electrical. Characteristics
VIH Applies to all input pins 4.0 V OD
Input voltage V 3-7
VIL Voo=5.0V 0 0.4
IIHI VIN=VOO 1.0
pA 3
IILl VIN=GND -1.0
IIH2 VIN=VOO 5.0 30
Input current pA 4
.' IIL2 VlN=GND -1.0
IIH3 V'N=VOD · 1.0
pA 5
I'L3 VIN=GND -0.5 -3.0
IIH4 VIN=VOJ) 1.0
pA 6
IIL4 VIN=GND -10 100
11115 VIN=VOJ) 0.5 3.0
pA 7
I'Ls V'N=GND -0.5 -3.0
Input amplitude VI f=50 or 60Hz 4.0 Voo Vp~p
Vom Io [[=0.5mA, Voo=5.0V 4.5 4.9

V 1
VOLI Connects to -19V at RL =100kO -19.0 -18.0
Output voltage VOH2 lo[[=0.2mA, VOJ)=5.0V 4.5 4.9
V 8
VOL2 IOL =-0.2mA, Voo=5.0V 0.1 0.5
CONI =GND, CON 2=GND 50
Time' base f CONI =VoJ), CON 2 =GND 60 kHz
CON I =GND, CON2=V~J) 32.768
f=50Hz, VI=VOJ)V~~p 50 1
Current consumption 100 f=60Hz, Vi=VOJ)VD~D 50 pA 8
With 32.768kHz crystal 50 9
Note 3: Applies to CONI, CON" 12114 pins
Note 4: Applies to PI-3, SH, ST, SM, TI pins
Note 5: Applies to ACL pin
Note 6: Applies to TE, TI pins
Note 7: Applies to XI pin
Note 8: Applies to Tom pin
Note 9:. Clock display mode
942
Digital ON/OFF Clock Timer CMOS LSI. LR3419
• Specifications (iii) Timer ON (OFF) time setting operation

(1) Basic time base
Time base select input Time base input pin
Time base
CONl CON, Xl Xc
50Hz 0 0 50Hz OPEN
60Hz 1 0 60Hz OPEN P,(P3) and either SH, ST
32.768kHz 0 1 or S M simultaneously
Disable 1 1
*
* Oscillator feedback circuit that consists of crystal and
capacitance
(2) Operation flow chart

o Setting will be complete when P2(P3) is OFF.
( i) Function readout operation o While being adjusted, the 10 minute digit does not increment
the hour digit, nor does the minute digit increment the 10 mi·
Transits only when SW
==> is ON. Returns automatically
after it is turnd OFF
o
o
nute digit.
In the timer ON (OFF) time set mode, timing will not stop.
In the timer ON (OFF) time set mode, timer output will not be
affected even if the timer ON (OFF) time coincides with the time
display.
(iv) Simultaneous depression of setting

switches
Normally only one of Pl, P2, and P3 goes ON. If
more than two of these are depressed simultaneous-
ly, they enter no input and go into the time display
mode.
(v) Simultaneous depression of rapid feed

switches
Note:· Hour rapid feed (SH) will proceed as follows. Normally only one of SIl, ST, and S" goes ON. If
more than two of these are depressed simultaneous-
12-hour representation
r
12--'1 --.2·············· ·--.1 0--'11
L-.~---AM/PM c h a n g e - - - - - - - - -
ly, the following operation will proceed.
(a) If one input goes ON followed by another in-
put that ON
24-hour representation
C 2--.13--.14···· .... '--.23--.0--'1 --.2· .. ····· '--.11 J
(ii) Hour display adjust operation
SM -i-,_ _-<,~--!,...J i I 1-,----

'-------' i-----------i i--------.i
Hour Decade Minute
forward minute forwrd
forward
o Counter digit below

second will be reset
(b) More than 2 inputs go ON simultaneously
SH~ J
iI ~r---------
I I
S r------1 I ;
T ~ ~i----+:-..J i
SM i : r--~I-~---'I--
i
~
l lI~
~
I I
o After P is turned OFF, timing starts from 00 second. , Hour forward I Minute forward
o While being adjusted, the 10 minute digit does not increment
the hour digit, nor does the minute digit increment the 10 mi-
nute digit.
~-:-'---'''---SHARP---'---'------
943
Digital ON/OFF Clock Timer CMOS LSI LR3419
(vi) Power failare display function flashing will stop. And on the next PION, timing
In any mode, LSI will be initialized inside on ap- starts.
plication of ACL to display: (vii)' Auto clear circuit
With 12 hour repres~ntation PM 12 : 00 The internal state on power-up will be as fol-
With 24 hour representation 12: 00 lows.
This whole display goes flashing, 0.5 second ON (a) Time display
and 0.5 second OFF. The display stays in the ini- 12 hour representation PM 12 : 00
tial state. J To stop flashing, go into the time dis- 24 hour representation 12 : 00
play mode (PION) and then timing starts with PI And the second, counfer will be reset. From the
turned ON. time when the auto clear input ceases to 'exist, it
On application of ACL with PI set to ON, the dis- will operate according to the mode input (PI, P2, P3).
play will s,tay in the initial state without flashing. (b) Time ON and Timer OFF time '
On the next PION, the display still in the initial With 12 hour representation PM 12 : 00
state will go flashing. Then on the next PION, With 24 hour representation 12 : 00
FIP5B13S
VI
23 24 25 26 27 V,
VB (-19V)
VDD(+5~)
+
22I00-I--+1 GND(OV)
21I00-I--+1
20 i-+--.-I;I!II
181-+-.....-/·
17 t--\-.....J.
16H--.-f.
15 I-o-f-.....J.
141-+-~141
13H---,-.....!ii5\
12H-.....-/'
llt--\-.....J,
10t-t-....-f~18I
91--i--4----'
3}6,7'H--+----l
2) 4,1--i~-4----~
Note 1: Set to side 2 under 24 hour system, Note 3: Time base input circuit
and set to side 1 under 12 hour system (alAt 50Hz, 60Hz (plAt 32.768kHz
Note 2: Time base selection
CONI CONz O.lJlF.r-@
50Hz side 1 side 1 O-;f-:I:.@
60Hz side 2 eide 1 SlJlIJlF
32.758kHz side 1 side 2
o ®
Note 4: Fluorescent display tube FIP5B135
The number indicates the pin number.
The figure in ( ) is for 12 hour system.
944
VTR Program Timer CMOS LSI LR3472
LR3472 VTR Program Timer CMOS LSI

The LR3472 is a CMOS LSI for a 6 events 1 week
VTR program timer. It can directly drive a fluores- cS c3
cent display tube (VFD).
• Features
1. "Hours-Minutes" display
2. Selectable 12/24 hr. format
3. Max. of 6 events 1 week
4. 6-daily and I-weekly reservation
5. Directly drive a VFD
6. Time base: 32.768kHz crystal
7. Supply voltage: - 5V
8. CMOS process >2 ,;: :2 :2
Top View
• Block Diagram
~ /'"~ Error Colon

UI' Down Rec. Power~
Grid
K Input hr Set
.---.-.----~-SHARP'-.-.-~-----
945
VTR Program Timer CMOS LSI L.H3472

Parameter Symbol Ratings Unit.
Supply voltage * 1 Voo +0.3--7.0 V
Input voltage * 1 V IN +0.3-V DD -0.3 V
Output voltage * 1.2 VN +0.3--40 V
Operating temperature Toor -10-+60 ·C
*1
*2
Refer~ to Vss
Applies to Rl-I-R'-I,DI-Ds, S,-Sh pins
Parameter Symbol MIN. TY? MAX. Unit
Supply voltage * 1 Voo -5.5 -5.0 -4.5 V
Input voltage * 1 V IN Voo 0 V
Output voltage * 1.2 VN -32 V
• Electrical Characteristics (V oo =-5.0V±10%, V N=-.32V, Ta=25"C)

VIII -0.5 0
Input voltage V 1
V IL Voo Voo+0.5
IIIn VIN=OV 10
p.A 2
IILl VIN=Voo -1
IIH2 VIN=OV 5
p.A 3
Input current IIL2 VIN=VOO -1
11113 VIN=OV 1
p.A 4
IIL3 VIN=VOO -5
11114 VIN=OV 4
p.A 5
IlL4 VIN=VOO -1
V OHl IoH =-6mA ~2.0
.'
V 6
VOLI RL =120kO to VN V N+1.2
V OH2 IoH =-12mA -2.0
V 7
Output voltage V OL2 RL =120kO to VN V N+1.2
V OlI3 IoH =-2mA -2.0
V 8
V OL3 RL=120kO to VN V N+1.2
V OH4 IoH =-3mA -2.0
V 9
V OL4 RL=120kO to VN V N+1.2
Oscillator frequency fose 32.768 kHz
IODI No lo~d, uniterrupted power condition 300
Current consumption p.A 10
1002 No load, interrupted power condition 40
Note 1: r,
Applies to Vee, ACL, TI", T2, fi, a, K,-K. pins
Note 2: Applies to Kl - K. pins
Note·3: Applies to a, fiJins Vss
Note 4: Applies to Vee, r pins
Note 5: Applies to ACL pins OSCIN
Note 6: Applies to S.-Sh pins
Note 7:. Applies to D,- D8, pins
Note 8: Applies to RI-I-RI-4~ R2-1-R2-'
Note 9: Applies to Ra-l-Ra-4, R'-I-R4-.' OSCOUT
Note 10: Test circuit (right figure)
946
• Specifications these keys to execute one by one the data being dis-
played on the fluorescent display tube. With each
(1) Input keys and operations depression of these keys, the data gets renewed by
1. But if they are held pressed for longer than 0.5
second, the data gets renewed by 1 every 0.25
second.
CSUn---i>Mon---i>Tue-+wect-:ThU-+Fri-+sa:-----YAlI daY~
In current data setting, the Day key should be

( i ) Clock Call key depressed 7 times to return to the origin. But in
When to set the current time, depress the Day, timer ON time setting, it should be depressed 8
Hour, and Min keys one after another while holding times because of the additiona of "everyday".
the key pressed. When both the Clock Call key and (iv) Data renewal by the Hour key
anyone of the Day, Hour, and Min keys are re- In current time setting or recording time setting,
leased, the clock starts from 00 second. Depression the data will be renewed in any of the following
of the Clock Call key in other mode (time set mode) manners depending on whether the clock is under
causes the data that has been displayed on the 12 hour system or 24 hour system.
fluorescent display tube stored and at the same • Under 12 hour system
time goes back into the clock mode. CPM12--+PMl--+PM2-+-~PMll-AM12~.AM]----+----+AM11~
(ii) Timer Call key

This key is for calling the 6 timers in sequence. • Under 24 hour system
With each depression, this along with the symbol CO ------+ 1 ---> 2 ---> 3 ---> m ____ m m ___ -- 23~
will be displayed on the fluorescent display tube in

the order shown in the figure below. Only the data In recording time setting, the data is renewed in
called by the Timer Call key to the fluorescent dis- the following manner.
play tube can be altered in timer setting and CO -- 1 ---> 2 ---> 3 ~ ------------------->11 ~
clearing.
The recording time can be set to up to 11 hou'rs
and 59 minutes. '
(v) Data renewal by the Min key

CO - - 1 ---> 2 ---> 3 -+--------------->58->59~
(vi) Clear key

This key is used to clear the data of the timer
that is set. First depress the Timer Call key to call
the timer then depress the Clear key to clear the
stored data of the timer that was called to the
flourescent display tube.
The recording time data can be cleared indepen-
dently but if their recording start time is cleared,
the recording time data of the same timer will also
be cleared. This key has a function of stopping the
execution of timer recording. In other words, while
timer recording is being excuted, only this key
along with the Timer Call key and the Clock key
that are used to confirm the preset time can be
accepted and clears in the clock mode only the data
of the timer which is executing recording to bring it
to a forced stop.
Simultaneous depression of any other key than
(iii) Day, Hour, Min key the Clock Call cannot be accepted. A new key input
To set the current time or set the timer, depress cannot be recognized until all the keys are released.
-.-----.-~-SHARP--.-.-------
947
(vii) Other inputs' And unless this input is "High", tne timer output T p
(a) 12 hour/24,hour swiching input and T R will not go ''.l{igh'' even if the current time
(b) Tape end input ' and the recording start time coincide in the clock
mode.
This input gone "Low" is r~cognized as the tape
end and causes the timer outputs Tp andT R to.go (c) Power failure detect output
"Low'" for the timer operation to come to an end.
(2) Display and outputs
Sh
r--~ r----'
I SAT I I I
B: :
I I I I
I I I I
I I I I
I Start :RH
I' I I
I .I Length I R,-,
I I I
I I IR'_3
I I I Error I
L___ J !.. ____ J
(i) Display flashing, depress the Clock Call key.

The clock has 12 hour system/ 2 4 hour system
(3) Initial mode
switching capability. Under the 12 hour system,
.[CH1 ..... CH14 key--Shift the channel by Cu,
AM/PM change-over occurs bet~een 11 o'clock
and CD.
and 12 o'clock.
Clock Call key --For clock setting mode
When the clock is under 24 hour system, so is
the ti~er ON time. The display "PRO" indicates the Goes into this mode after auto clear is reset on
time is set to the timer and lights up when setting. power-up. This mode accepts only the CHI-CH14
The colon fashes 0.5 second ON and 0.5 second keys and the Clock Call key for clock setting. Once
OFF while the clock is in operation. The character the Clock Call key is deressed, timing of the clofk,
in the g7 position indicates the timer number in reo and timer operation are disabled. Timing cannot be
cording start time setting and recording time set- performed until the clock is set.
ting. Error lights up when more than two timers
overlap.
(ii) Outputs
The LR3472 has the following outputs.
Channel control output 2-bit Cu, CD Initial state display
Timer power output I-bit Tp SUN
Timer rec output I-bit T R
The channel control output is for controlling the
channel selector IC. The timer output T p goes
0·0 D
"High" in rec9rding start time and recording time Display after depression of the Clock Call key
setting. And in the clock mode, it goes "High" 1 mi- (Note) The colon is lit.
nute before the recording start time. The timer out-
(4) Clock setting mode
put T R in the clock mode goes "High" if the current
time coincides with rhe timer ON time in the clock
mode. Power failure causes all the displays to go [
Clock Call key 1 Day key - - d + 1 ---- d
Hour key - h+1 - - h
bla'nk and resets the output. When the power comes ...,,-,----,_'-::-.,., __ Min key - m + 1 --m
back on, the power failure indication will be dis- Clock Call, Day, Hour, Min key
played during the. next 1 minute. If the power fai- The LR3472 stays in this mode while the Clock
lure occurs while recording, T p goes "High" (on Call key is held pressed. This mode accepts the
channell now) and another 1 minute later, TR goes Day, Hour, Min keys and allows for current time
"ijigh" (on the preset cha,nnel) to resume recording. setting. Note that the minute digit does not incre-
The power failure display is indicated, by flash· ment the hour digit and the hour digit does not in-
ing 1 second ON and 1 second OFF. To stop the crement the day digit.
948
(5) Clock mode
Tape End - - - ' L - T n:(T m-l)nl>n--- T p

Tn-Tm
Clock Call key ~ Day key 3 TH
Hour key -~---+--- Current time set mode

. Min key
Timer Call key - - - - - - - - - - - Recording time set mode
CH1-CH14 key C", Cn channel shift
TPITn=T'm Lm=l, m=everyday-T p , TH Tn ; Current time
m1'1, m = everyday - T p, T R, m clear T m; Timer ON time
Clear key m1'1, m = everyday - T p, T R, m clear T'm ; Timer OFF time
Tape End _ _ _-1
This mode is an ordinary timer operation mode output T p is "Low".

in that the timer output T p goes "High" 1 minute (6) Recording start time set mode
before the preset recording start time with the
Tape End - - - - Tp
Tape End input "High" and when the current time
Daykey---- d + l-+d Day shift
coincides with the preset recording start time, the
Hour k e y - - - - h + l-+h Hour shift
timer output T R goes "High". Even when the cur-
Min key m + l-+m Minute shift
rent time reaches one minute before the preset re-
CH1-CH14 key- ClI , Cn Channel shift
cording start time or when it coincides with the re-
Clock Call key - - Display-+Memory, For the
cording start time, the timer outputs, T p and T R
clock mode
will not go "High", nor will preset content be
Timer Call key - - Display-+Memory, Timer
cleared if the Tape End input is "Low".
address shift, For recording
When the timer output T p is "Low" (when timer
time setting mode
recording is not being executed), if the Clock Call
Clear key - - - - Recording start time clear,
key and either of the Day, Hour, and Min key are
Recording time clear
depressed simultaneously to go into the current
time setting mode, the current time can be adjusted. This mode is the recording start setting time mode.
And when the timer recording is not being ex- The display in the state in which the called timer
ecuted with the T p "Low", the Timer Call key is de- has been cleared or in which the non-set timer has
pressed to go into the recording start time setting been called is shown as below.
mode to allow what is now being displayed to be Day digits are all OFF.
the recording start time and the preset channel for
the timer 1. On reaching the time where there is no
- -: -
.
- B I
The timer number is
that of the timer called.
(1-6)
recording time left with the timer output T R "High" ......_ _ _ _ _ _ _ _ _ _-' The colon- is flashing.
(when timer recording is being executed), the timer Ti;"er display when the
outputs T p and T R go "Low" to have the corres- preset is cleared
ponding memory content to be cleared except in the The channel is set initially to channel 1. This
case that the memory content for the corresponding can be adjusted by the CHI-CH14 keys. The CHI
time happens to be "every day" and the correspond- -CH14 keys and Day, Hour, and Min keys can be
ing timer happens to be the No.1 timer. This indi- depressed in any order and if unnecessary need not
cates that the timer 1 is preset for every week. be depressed at all.
If either the Clear Key is depressed or the Tape To exit for the mode in which to set recording
End input goes "Low" with output T.p "High" (when time for the same timer, depress the Timer Call
timer recording is being executed), the timer out- key. In which case the timer output T p remains
puts Tp and TR go "Low" to have the memory con- "High". In this mode, the recording time memory for
tent for the corresponding timer to be cleared ex- the same timer will be cleared on depression of the
cept in the case that the preset content for the cor- clear key. This mode disables timer recording.
responding timer happens to be "every day" and
the corresponding timer happens to be the No.1
timer. The CHI-CH14 keys can be accepted for
the channel signal to be generated, while the timer
-..-..----~--SHARP--------
949
VTR Program Timer CMOS LSI
~~~.-.
(7) Recording time set

...... .---,.-.. --.-..-.~-- ...........................
LR3472 '
tion by the Clock Call key to the clock mode. By th-e

. Timer Call key, this is the same operation as the
Tape End -~-- Tp
recording start time setting for the next timer.
Hour key h + I-h Hour shift
This mode disable timer recording.
Min key m + l-+m Minute shift
Clear key Recording time Clear
(8) Others
Clock Call key - - Display-+Memory, For the
( i ) Error indication
.clock mode
The error indication lights up when more than 2
Timer Call key - - Display-+Memory, Timer
of the preset timer contents overlap and the num-
.address shift. For recording
bers overlapped will be alterl!ately displayed as in
time set mode
the example.
This mode is the mode in which to set the record· (Example) When the timer No.1, No.2, and No.3
ing time. The display in the state in which the reo overlap
cording timer for the called timer has been cleared 1-+2-+3-+ 1-+2-+3-+·········
and in which the not·set time~ pas been called is Note that more than 2 sets of overlaps cannot be
shown as below: distinguished from each one of the sets.
If the recording time is not set, overlapped preset
I- - : -
.
I
The day digits are all OFF.
. The timer number (1-6)
...:.. B
d~splayed is that of the
tim er called.
io-_ _ _ _ _ _ _ _ _- ' The colon is flashing.
times give no error display.
Error indication does not prevent transition to
the program that starts halfway through.
This mode does not respond to depression of any Timer~ (M>N . I)

of the Day key, and CHI-CHI4 keys. If not reo . NM, N are timers,
Tlmer~ No. 1-6
quired, the recording time setting procedure by the
Hour and Min key can be skipped so that the Clock
Call key and the Timer Call key may be operated to In the figure above, the timer M is the first to be
proceed to. the next step. If timer recording is executed. In which case the memory for the timer M
attempted with the recording time cleared, either gets cleared on completion of the timer M recording.
the Tape End signal goes "Low" or the recording The timer N completes recording the following
will continue until the timer recording gets inter· week to be cleared.
rupted by the Clear key. (ii) Preset for the second week
With the recording time set to 00 hour 00 mi· If the current time is already past the recording
nute, the Tp goes "High" 1 minute before the restart time, it is considered as the preset time for
cording start time, but on reaching the recording one week away.
start time, the Tp and T R go "Low" to disable reo
cording. In this mode, the T p goes "Low" on transi·
950
VTR Program Timer CMOS LSI .LR3472
AC !OOV ~
Ip-
I~ I Fluorescent tube display
..
.,,
:( ~.
~~
~
.. ! !tal =~rt.ttlLtltft.t t
r47l r4~ r4~ 1441 ~~ 1421 F r4~ 13~ 138\ r3~11
~ I 0 ~
"''..." ~ ;: r"""'"
[[ ;: f""Mr'
[! ~~
Tape -end detector
. rs
.-= J21 f""Mr'
-=
I circuit
~ 3Jl
H LR3472
~~
~
Clock Clear 13 9 5 ~.9
.1 On
~~
Day ime ·14 10 6 2..m ~~
~our 11 7
'ii
3 I26If""I""'
Min 12 8 4 .;r.
-,g @.IN''-
"-
if 15 16 Ll;!1 Ll~ ~ ~
-
~i5
I!fJ I!2J
L
Channel selector
I
~'-.--'--------SHARP _ . - . i - - _ _ _ _ _ ____
951
Remote Control Transmitter CMOS LSI LR3715M
LR3715M Remote Control Transmitter CMOS LSI

• Description • PinConnections
The LR3715M is a CMOS LSI developed for use
in infrared remote control transmitters.
• Features·
1. 56-channel of data can be transmitted
2. Transmission code: PPM
3. Time base: 455kHz ceramic oscillator
4. Supply voltage : 3V
5. CMOS process
Top View
• Block Diagram
VDD GND System Address
... ....
.; ·s...
'o·" " Data
."
"... U DATA
Expansion
Key· "c U Inverter
Use
Input ~ ... Circuit
.S '"
."
0
Signal
~
"c
Test
DA T A Counter
Control
Key Circuit
Scan
Output'
Oscillation·
-'---'-'---~-----SHARP~""""""---"""-'--
952
.-.-.- ...... - . -..... ............... .......................... -
Remote Control Transmitter CMOS LSI
.- I
.-
LR371Srv1

Parameter Symbol Conditions Rating Unit Note
Supply voltage Voo Referenced to GND -0.3-+6 V
Input voltage VIN Referenced to GND -0.3-+6 V
Supply current 100, lEE ±5 mA 1,2
Output current lOUT ±2 mA 2
Power consumption Po Ta=25°C 483 mW
Note 1: IDD refers to the current that flows into the VDD pin; lEE refers to the current draining from the GND pin.
Note 2: The direction of current flowing into the device is defined as positive: that draining from the device is defined as negative. This
definition is also applied to the electrical characteristics.
• . Recommended Operating Conditions

Supply voltage Voo Referenced to GND 2.2 3 3.3 V
In put' voltage VIN Referenced to GND 0 Voo V
Oscillator frequency , fose 455 kHz
• Electrical Characteristics (Voo=3V, Ta=25"C)

Supply voltage Voo 2.2 3 3.3 V 3
Current consumption 100 All input pins open

I fosc oscillated 0.5 mA
3
I fosc stopped 1 flA
VIN Voo-O.6 Voo V 4
Input voltage
VIL 0 0.6 V 5
IIHl VIN=VOO 1
flA 4
IrLl VlN=GND -1
Input current
IIH2 VIN=VOO 1
flA 5
IIL2 VlN=GND -150
VOH! IOH= -5 flA VOD-OA Voo
V 6
VaLl IOL=400 flA 0, 0.4
Output voltage
VOH2 IOH=-0.5mA Voo-OA Voo
V 7
VOL2 IOL=1mA 0 0.4
Oscillator frequency fosc 455 kHz
8
Feedback resistor Rib 1 5 Mil
Note 3: Applied to pin VDD,

Note 4: Applied to pins CI·CS. C12. CI3
Note 5: Applied to pins Ko·K6. TI. T2 '
Note 6: Applied to pins SO,S7,
, Note 7: Applied to pin OUT
Note 8: Applied to pin OSCIN. OSCOUT
.-~------SHARP---------.-.
,,953
o0 0 0 1,0 0 0 1 00 0 0 0 O. (3) . Precautions in preparing a receiver

CD Make sure that the non-inVerse and inverse
I I I I I
I
I
I
I
I
I
I
I
I
I
signals are transmitte'd alternately. Be sure to
I I I I I
I
I
I
I
I
I
I
I
I
I
verify that bit number 15 (K) is alternately set t?
I I
:01010:0
I I I
1
"1" and "0". It is not enough only to ~ompare bits
I I I I I
C6 -C14 either after inverting them or before in-
verthing them.
® The PPM signal status "1" or "0" may be
identified by checking its pulse interval as follows
(fo=455 kHz):
@ Modulator circuit While it is possible to Tp<0.42 ms ... Non-PPM signal
transmit serial 15-bit PPM signals directly, it 0.42 ms~Tp<1.69 ms ... "0"
causes the broadening of occupied bandwidth, To 1.69 ms;;;;';Tp<3.37 ms ... "1"
prevent this, the device samples the 15-bit PPM 3.37 ms;;;;';Tp ... Non-PPM signal
signa with a 37.9 kHz (When fo=455 kHz) signal If a non-PPM signal is received, the device
and transmits PPM signal at 100% amplitude mod- clears all bits and begins processing with the first
. ulation. bit again .
® If 16 bits (17 pulses) or more of PPM sig-
nal are received, the device identifies it as a non-
PPM signal, clears all bits, and begins processing
with the first bit again.
IEnlarged diagram @ The correct data should be identified by
+ matching the system addresses and data expansion
bits of the transmitter and receiver.
JlfUU1J1JUUlJlJ (f=455kHz)
U
26.4)<s
r-----67.5ms
J0?W&'-------'~
,'" 67.5ms---1
P7;~'7?7?':'l'II
Forward signal Reverse signal Forward signal
1 8
I II
S7 S6 S5 S. S3 S2 SI So CI
Ko System.
9 16 C2
KI address
17 24 . C3
K2
25 32 C. set circuit
K3 LR3715M
33· 40 C5
K.
41, 48
Ks I Signalset circuit
49 56 C12
K;6 for data expansion
C13'
VDD
OSCIN
GND OSCOUT OUT
~t
FD~
Key matrix
I y
~ r r
--....--------------..-SHARP -..-....-...-.-.-------.-.-
-
954
As / shown in the above figure, the non "-iriverse location of the memory. The following table shows
and inverse signals alternately repeat in series at the key arrangement and command numbers. If one
a certain interval. The receiver reconstructs the desires to transmit command number 3, the key at
original data by identifying non-inverse or in- the matrix point, Ko-S 2 ,' can be pressed.
verse signal according to the status of the data
judging bit
® Mask bit C14 Fixed at "0" (low) within the Ko--+-+-+-+-+-+-+-+-
device K1--1-1-1-+-+-+-+-+--
(2) Device operation timing K2--+-+-+-+-+-+-+-+-
The LR3715M is a transmitter LSI device de- K3--~~~+-+-+-+-~
K.--~~~+-+-+-+-~
signed for use in an infrared remote control unit
K5--+-+-+-+-+-+-+-+--
It consists of an oscillator, key scan signal gener-
Ks--+-+-+-+-+-+-+-+--
ator- key encoder, memory, data inverter, parallel!
serial converter, and output circuit The device can 5can signal
accept a 7xB key matrix and transmit up to 56 50 51 52 53 5. 55 56 57
types of commands in 6-bit code_ For power sav- Ko 1 2 3 4 5 6 7 8
. ing, the internal oscillation is stopped when no key K1 9 10 11 12 13 14 15 16
is pressed. If double key operation is made, the de-
vice stops transmission.
=
.S
K2
'" K3
17
25
18
26
19
27
20
28
21
29
22
30
23
31
24
32
~
CD Key scan signal generator When a key :.:: K. 33 34 35 36 37 38 39 40
K5 41 42 43 44 45 46 147 48
entry is made, a flip-flop reverses its status to re-
K6 49 50 51 52 53 54 i 55 56
set the Oscillation Clear signal and start internal
oscillation. The key scan outputs provide the sig-
nals shown below. Given fo = 455 kHz, the pulse ® Data inverter If the 6-bit data is identi-
period is 33.B ms, and pulse width is 4.2 ms. fied to be correct, it is transferred to the data in-
verter, where system address, data expansion bit,
50 LJ UU mask bit, and data judging bit are added to it to
generate 15 - bit data.
51 --:-u U U If the data judging bit is zero, the following data
will be produced in the data inverter.
52 --U U U (Example) When the key numbered B is pressed:
53 U U U--
5. U U U- If the data judging bit is "1", the data except for
55 U U LJ the system address, is inverted by the inverter-
56
J U U lJ
57 LJ U U L The parallel 15 - bit signal is then converted into
serial PPM signal by the parallel/serial converter.
® Key encoder, encoder, and memory The
key scan signal lines are combined with key input
lines, Ko-K6, to produce a 7xB key matrix external
to the device. The Ko-K6 input pins have built-in
(f=455kHz)
pull-up resistors.
r--67.5ms _IE 167.5ms-----"'j
If a key at the matrix point, K1-S3, is pressed,
the signal output at pin S3 is input to pin K1 , to be ~oL..._-J-~ ~i=~~"L
Forward signal Reverse signal Forward signal
encoded into a 6-bit binary code by the key encod-
er and encoder before storage into memory. If two
keys are pressed at the same time, the double key
prevention logic clears the data in the pertinent
.-.--------SHARP.-----.-..----
955
Remote Control Transmitter CMOS LSI
........
~.-~ ..............,.-..... - . -.....---,.-..... -~-...: .....
,lR3715M
• Function CH C6 C7 C8 C9 CIO C11 CH C6 C7 C8 C9 CIO Cl l

(1) Transmission scheme
1 1 0 0 0 0 0 29 1 0 1 1 1 0
The LR3715M uses the PPM (pulse position
2 ,0 1 0 0 0 0 30 0 1 1 1 1 0
modulation) system for 15-bit signal.
The device alternately transmits non-inverted
3 1 1 0 0 0 d 31 1 1 1 1 1 0
4 0 O. 1 0 0 0 32 0 0 0 0 0 1
15-bit data and inve~ted 15-bit data (system-
5 1 0 1 0 0 0 33 1 0 0 0 0 1
address bit 5 is not inverted, however) . The re-
6 0 1 1 0 0 0 34 0 1 70 0 0 1
ceiver re-inverts the inverted data into the origin-
7 1 1 1 0 0 0 35 1 1 0 0 0 1
al form and compares it with the preceding non-
8 0 0 0 1 0 0 36 0 0 1 ,0 0 1
inverted data to be sure the two pieces of data are
9 1 0 0 1 0 0 37 1 0 1 0 0 r
identical. Discrimination between inverted and
10 0 1 0 1 0 0 38 0 1 1 0 0 1
non-inverted is achieved by checking the judging
11 1 1 0 1 0 0 39 1 1 1 0 0 1
bit. Reception becomes valid only after the data
12 0 0 1 1 0 0 40 0 0 0 1 0 1
pieces prove identical.
13 1 0 1 1 0 0 41 1 0 0 1 0 1
The PPM system arranges pulses as follows to
14 0 1 1 1 0 0 42 0 1 0 1 0 1
discriminate logic "1" from "0".
15 1 1 1 1 0 0 43 1 1 0 1 0 1
( a) Logic ''1'' ( b) Logic ·0" 16 0 0 0 0 1 0 44 0 0 1 1 0 1
17 1 0 0 0 1 0 45 1 0 1 1 0 1
JUL
W
18
19
20
0
1
1
1
0
0
1
0
0
1
1
1
0
0
46
47
48
0
1
1
1
1 1
1 1
0 1
0 1
1 1
0 0 0 0 0 0 0 0
Tpf2
21 1 0 1 0 1 0 49 1 0 0 0 1 1
If the interval between two pulses is Tp, the sig- 22 0 1 1 0 1 0 50 0 1 0 0 1 1
nal is identified to be logic "I", whereas if it is Tp/ 23 1 1 1 0 1 0 51 1 1 0 0 1 1
2, the signal is identified to be "0". the device thus 24 0 0 0 1 1 0 52 0 0 1 0 1 1
constructs 15-bit serial data as follows. For exam- 25 1 0 0 1 l' 0 53 1 0 1 0 1 1
ple, a binary code "000010001000000" is con- 26 0 1 0 1 1 0 54 0 1 1 0 1 1
verted into a pulse array as follows: 27 1 1 0 1 1 0 55 1 1 1 0 1 1.
28 0 0 1 1 1 0 56 0 0 0 1 1 1
0000 1000 1 000000
® Data expansion bits C12, CI3 These bits
are used to increase available command types.
@) Data judging bit K This bit K is unique
The following shows bit assignments to data: to Sharp's remote control system, and is used to in-
dicate whether the preceding data is inverted or
ICI Ic21 Cal c.1 Csl c61 c71 Cal c91cIO ICIIICI2IClaIC141 K I non-inverted:
, SystemVaddress ,,' , D;ta ~ M~sk \ (a) Non-inverted data
, expansion F or data
decision 000010001000000
CD System address CI -C 5 These bits are

set up with switch and allocated to different sys- (b) Inverted data'
tem. Up to 56 types of commands and two expan- 00001 101
sion bit can be transmitted for each system. For
system address allocation, be sure to contact us.
® Data code C6 -Cn The Data code C6 -Cn When the data judging bit is set to zero, the de-
are allocated to key numbers as shown in the fol- vice transmits non-inverted data. When it is set to
lowing table: one, the device transmits'inverted data (inversion
of C6 -C14 and K).
956
Remote Control Receiver CMOS LSI LU59001
LU5900 1 Remote Control Receiver CMOS LSI

The LU59001 is a CMOS LSI developed for in-
frared remote contorol receivers.
Used together with the LR3715M transmitter, a
VDD
remote control system can easily be realized. 0 R22
R30
R21
R20
• Features R13
1. 56-channel of data can be recognized R12
2. The serial or parallel data can be transfered to R3I
the external system Rl1
3. Time base: 455kHz ceramic oscillator R,O
4. CMOS process
5. 20-piri dual-in-line package
Top View
-'--~----SHARP-'--'--'-'--"'-'-'
957
• Block Diagram
Parallel or Serial I/O Port

)
lr '---
ROM RAM
(508X8bit) (32X4bit)
1
l PC
I r-
S Auto
SR
.....- P CG clear
'-
~-------------------------------------------{7r-----~6r-------~
Clock Parallel or
Serial I/O Port
Symbol description & Clock
Acc : Accumulater C : Carry F/F

BL, BM : RAM address register PC : Program counter .
CG : Clock generator ALU : Arithmetic logic unit
SR : Stack register SP : Stack pointer
X : Temporary register R [0] - R [3] : Output latch

Supply voltage VDD -0.3-+7.5 V
Input voltage VIN -O.3-Yoo+O.3 V
Output voltag~ VOUT -O.3-Yoo+O.3 V
IOH 120 rnA 1
Output current.
IOL 20 rnA 2
Storage temperature Tstg -55-+150 t
Note 1: Total output high current.
Note 2: Total output low current .
. - - . - . - - - - - S H A R P - . -......... ---....----~
958

Voo=5V±10% 2 50
Command execution time t fls
Voo=3V±10% 4 50
• AC Characteristics of External Clock Input Signal

Input rise time tR Voo=2.7-5.5V 0.1 fls
Input fall time tF Voo=2.7-5.5V 0.1 fls
tL Voo=5V±10% 0.2 6.3 fls
Clock pulse width
tH Voo=3V±10% 0.4 6.3 flS
• Electrical Characteristics (Voo=2.7V±5.5%, Ta=-10-+70t)
Paramater Symbol ConditionsMIN. TYP. MAX. Unit Note

VIHI 0.7Voo Voo V 3
VILI 0 0.3Voo V 3
Input voltage
VlH2 VOD-O.5 Voo V 4
VIL2 0 0.5 V 4·
VIN=VOO, Voo=5V±10% 70 250 750 flA 7
I!HI
VIN=Voo, Voo=3V±10% 15 70 200 flA 8
Input current
VIN=Voo, Voo=5V±10% 20 60 flA 5
I!H2
VIN=Voo, Voo=3V±10% 7 20 flA 5
Voo=5V±10%, VOH=Voo-2V 10 rnA 6
10HI
VOH=Voo-0.5V 1 rnA 7.
Voo=5V±10%, Voo=O.4V 1.6 rnA 6
lOLl
VOL=O.4V 0.8 rnA 6
Voo=5V± 10%, VOH=Voo-2V 4 rnA 8
IOH2
VOH=Voo-0.5V 0.5 rnA 8
Output current
Voo=5V±10%, VOL=O.4V 15 flA 7
IOL2
VOL=O.4V 8 flA 8
Voo=5V±10%, VOH=VOH=Voo-2V 1 rnA 9
IOH3
VOH=Voo-0.5V 0.15 rnA 9
Voo=5V±10%, VOL=O.4V 0.6 rnA 9
IOL3
VOL=0.4V 0.3 rnA 9
t=8,8flS, Voo=5V±10% 230 600 flA 10
Current consumption lop
t=8.8flS, VDo=3V±10% 120 230 flA 10
Note 3: Applied to pins R03, RI0-~13, R20-R23, R30-R32.
Note 4: Applied to pins ACL, CLl:
Note 5: Applied to pin ACL.
Note 6: Applied to pins Roo-Ro2.
Note 7: Applied to pin R03.
Note 8: Applied to pins R20-R23.
Note 9: Applied to pin CL2.
Note 10: No load status.
-~"'-''-''''''''''''---SHARP'---~------
959
..................
•
....,-....---...
.Remote 'Control Receiver CMOS LSI,.
Oscillator Circuit
......, ............................,.....
.
~-
Lu59001
Example Iisi!lg CSB455E (Murata)

CI=C2=220pF
Rd=2.2kn
• Switching Characterlsti.cs (OSC Frequency: 455 kHz)

(1) Receive signal (DIN)
Parameter Unit
Receive signal pulse width ,.,.s
(2) Serial transfer (with internal clock)

RDY ON time tON 2 ms
RDY OFF time (DIN-ROY) tOFFl 53 ms
ROY OFF time (SDO-RDY) toFF2 53 ms
Duration of CKI at high tCKIH 1 ms
CKI end .time tCKIE 0 ms
CKI standby time tCKISl 52 ms
CKO delay time tCKOD 635 flS
Duration of CKO at high tCKOH 285 flS
Duration of CKO at low 1 tCKOLI 80 flS 11
Duration of CKO at low 2 tCKOL2 825 flS 12
CKO setup time tSTOP! 95 fiS
Note 11 : For tran'sfer rate of 0.32 ms/bit.

Note12: For transfer rate of 1.05 ms/bit.
(3) Serial transfer (with external clock)

ROY ON time tON 2.25 ms
RDY OFF time (DIN-ROY) tOFF! 53 ms
RDY OFF time (SDO-RDY) tOFF2 53 ms
CKI standby time tCKIS2 0.45 52 ms
Duration of CKI at high tCKIH 635 flS
Duration of CKI at low tCKIL 380 flS
CKI setup time tsTOP2 255 flS
CKI clock frequency fcKI 100 920 Hz
(4) Parallel transfer

Data ON time tPDON 2.65 ms
Data OFF time tPDOFF 53 ms
960
• Timing Diagrams
(1) Receive signal (DIN)
OON
(2) ROY ON/OFF timing
DIN
ROY
SOO ____________________ ~n~ ____ ~n~

;t-
___
(3) Serial transfer (with internal clock)
ROY ~r--------------------------------------
tCKISl tCKIH tCKIE
CKI
SOO
CKO
I.. ,./
tCKOD tCKOH
(4) Serial transfer (with external clock)
ROY J
I tCKIS2 tCKIH tCKIL
.. 'I' 'I" ~I
CKI
SOO J,--...;C;.;;.,6 ----,X C7~~P2 C~8 ~Xr----~X~--~C~13---x:

___ __
DIN
PDli
961
• Functions
(1) Operation
The LU59001 is designed for 15-bit PPM sig-
S2 Sl Transfer mode Transfer rate R01(CKO) R23(CKI)
nal reception. For more information. see the de-
0 0 Internal 0_32ms/bit Transfer Request to
scription of the LR3715M Remote Controller
0 1 Clock Mode l.05ms/bit Clock transmit signal
Transmitter. The LU59001 basically consists of a
External 1.1-lOms
decod-er which decodes PPM signal into binary 1 0 High Transfer clock
Clock Mode Ibit
data. formatter. system address check logic. and
data transfer block. OSC frequency; 455 KHz
(2) Decoder (a) Internal Clock mode If a Request to
Received signal (DIN) is converted into binary Transmit signal (CKI) is applied to the R23 pin when
code according to the conditions shown.in the fol- the device is in data transfer mode. it starts data
lowing table. If an interval. Tp. between pulses is transfer sequence. The'Roo pin outputs serial data
in the range of 2.95 msSTp S 52.7 ms. it is iden- (SDO) in the order of C6. C7 ..... C13. and the R01 pin
tified as a separator between 15-bit data items. If provides a transfer clock (CKO). In the Internal
Tp is equal to or larger than 52.7 ms, it is identi- Clock mode a transfer rate from 0.32 ms/bit to 1.05 .
fied as the end of transmission. ms/bit can be selected using the Mode Select signals
SI- and S2.
Conditions Identification
(h) External Clock mode If an external transfer
Tp;;;;O.85ms Noise
clock (CKI) is applied to the R23 pin when the device is
in the data transfer mode, it starts serial data
transfer. The Roo pin outputs serial data (SDO) in the
2.95ms;;;; Tp;;;; 5 2. 7._m.c::s_+-__E_nd-,--"o_f_1--,-5.c::-b'--.itc-d:...:a""ta=--_
order of C6. C7 ... ·C13 in synchronicity' with the
52.7ms;;;;Tp End of transmission
external clock. The allowable transfer rate is limited
OSC frequency: 455 KHz to 1.1 to 10 ms/bit.
(3) Coincidence judgment @ Parallel transfer
When the device starts reception, it checks the When the device enters the data transfer mode.
system address and mask bit. and performs coinci- pins Roo. ROI. R02, R03. R20. R21. R22. and R23 output
dence check on inverted and non-inverted data. It parallel data (PDo-PD7). Parallel data bits corres-
first checks if the received system address. C1-C5, pond to received data bits as follows:
matches the preset system address (SYS1-SYS5). and
Pin Roo ROl R02 R03 R20 R21 R22 R23
verifies that the mask bit is "0". Next the device
Parallel
checks coincidence of a non-inverted data item with PDo PD1 PD2 PD3 PD4 PD5 PD6 PD7
'Data
its inverted counterpart.
Received
'If concidence is found. the device becomes ready C6 C7 C8 C9 CIO Cl1 C12 CI3
Data
for data transfer (C6-Cl3) to an external system. If
coincidence is not found, comparison is made with ® Data transfer mode
the precedfng or succeeding 15 bit data. Compari- When the device completes decoding and coinci-
son is repeated until coincidence is not found_ Once dence check on received data. it enters the data
the device starts data transfer it no longer decodes transfer mode. Entry into the serial data transfer
subsequently received data_ mode is indicated by the RDY signal appearing at the
(4) Data transfer R02 pin.
Data transfer formats include serial and parallel That into the parallel data transfer mode is
transfer. If the R03 and R22 pins are both connected indicated by the OR output of the parallel data
to VDD. serial transfer is selected when the device is (PDo-PD7) (all bits of parallel data are not set at '0'
reset. In any other case. parallel transfer is selected at the same time).
when the device is reset. The data transfer mode continues until all data
CD Serial transfer has been transferred or for 52.7 ms after serial data
Serial transfer includes three modes. A mode is transfer has been completed. After that. the device
selected by the Sl and S2 signals applied to the R20 waits for data reception.
and R21 pins. The following table shows the modes
versus Sl and S2 signals (Sl = S2 = 1 is inhibited):
962
(1 ) Serial transfer
VDD
SYS. SYS3 SYSs
SYS2 SYSI
LU59001
o
a SDo
~
"',.,
...,"'
....C
CKo
CKI
"
>iI
RDy
~
PD. DIN
PDs
PD6 SYS2 SYSI
VDD SYS. SYS3 SYSs
Ei
2
,.,"'
.."
"'
...
LU59001
" 0
"
>iI
PDo
PDl
PD7
PD2
IPD3
963
Up/pown Counter CMOS LSI with LCD Decoder-Driver' LR3617
LR3617' Up / Down Counter CMOS LSI with LCD

Decoder-Driver
_ N
The LR3617 isan up/down counter with a de- ~~,§g-tj~ c:Z~r:Z::<

coder driver for 3 1 / 2 digit LeOs. It is best suited QQ»»E-<UUUCIlCll
to tape counters for use in micro cassette tape recor-
ders and VTRs.
• Features
1. 3 % digit static LCD
2. Leading zero suppression
3. Minus sign floating position
4. Memory stop
5. End-of-tape stop
6.-Single power supply: - 1.5V
7. CMOS process
-8. 48-pin quad-flat package
Nop is connected to the internal circuit.
To be used in the open state.
Top View
• Block Diagram
Segment Output
Test
Operation Input
Count Pulse Input
Pause Input
Memory Input
Up/Down Inpu~
Reset Input
Mode Input
Initial Set
Stop Output Alarm Output
964
Up/Down Counter CMOS LSI with LCD. Decoder-Driver LR3617

VTl 0.3--2.5 V 1
Pin voltage * VT2 0.3--5.0 V 2
VT3 +0.2-V oo -0.2 V 3
*Referenced to Vss
Note 1: Applies to Voo, VOOI pins
Note 2: Applies to VEE pin
Note 3: Applies to all input pins except V5S, VEE, VOO, Vaal pins
Supply voltage * Voo• VOOt -1.3--1.8 V 4
Input voltage * VIN O-Voo V 5
Note 4: Do not allow a sudden change to occur even within the rated value.
Note 5: Applies to SCK, SACL, SMEN, SPAl!, SOPR, SALM, SON, SR pins
• Electrical Characteristics I
Parameter Symbol Conditions MIN. TYP. MAX. Unit l Note
All input pins VS5,
Current consumption (Ioo+Iootl 13.5 25 pA ) 6
fose=64kHz, with no load
VIH -0.3
Input voltage V 7
VIL Voo+0.3
IIIl VIH=OV 5
Input current pA 7
ILL VIL =Voo 5
CR oscillator frequency fose Rt =5.1k!l, R2 = 150k!l, C=47pF 32 48 64 kHz 8
IOHl Vo ][=-0.5V, VEE =-3.0V 10
Output current 1 pA 9
lOLl VOL =-2.5V, VER =-3.0V 10
IOH2 VoH =-0.5V, VER =-3.0V 100
Output current 2 pA 10
IOL2 VOL =-2.5V, VE =-3.0V 100
IOH3 VolI=-OAV 10 pA
Output current 3 11
IOL3 VoL =-1.1V 10
Note 6: Total power consumption at fosc=64kHz
All output pins open
All input pins connected to the V55 pin DDC r
+
VOOI pin connected to Voo pin O.lpF
Note 7: Applies to all input pir,s except V5S, VUOI, DDC2
VOO, VEE, CRI, CR2, CR., pins
Note 8: The constant values shown in the right figure are used in the ,I- Vss
O.lpF
oscillation circuit. VEE
Note 9: Applies to segment output pins
Note 10: Applies to common output pins
Note 11: Applies to STP, ALM pins
.-----.-----SHARP.--..----~---
965
Up/Down Counter CMOS LSI with LCD Decoder-Driver LR3617
• Sample Displays and Font (2) Count input cycle

The count input signal waveform is as follows.
TH: 5ms (MIN. ) , TL : 5ms (MIN.)
(3)The relationship between count input,
,-,, ,, ,--I -, ,-,, ,- ,,-7 -,, I 7 , I

0 1 2 3 4 5 6 7 8
I-I
9. count content, and display
The LR3617 changes its display. output each
'- -' -' time 3 pulses get applied to the count input pin.
,, -', , '-I ,-, (4) Count input recognition

Sample display 1999 .=, -' The LR3617 recognizes as one count pulse en-
,, ,--I L'"
tered a transition that occurs in the up-counter
-120 mode when the counter input pin SCK connected to
-20 , I
,-, VS5 is to be reconnected to V 00 (or open) or a tran-
sition that occurs in the down-counter mode when
LI the count input pin SCK connected to V00 (or open)
0
,-, is to be reconnected to V ss.
'-'
,-, Up . counter
M30 M -'
-' '-'
display
Down' counter
• (1)
Count Function
Count range
display
Shown below are the count methods.

(5) Up/down input
The LR3617 works as a down-counter when the
Up' count Down' count up/ down input pin is connected to Vss, and as an
1999 up-counter when the up/down input pin SON is con-
-1999
t nected to V DO (or open).
t
-1998 1998 With the stop signal output pin STP at V S5 level
t t due to the tape end mode (discussed later) or the
memory stop mode (discussed later) operation,
when the up-down input pin SON connected to V DD
(or open) is to be reconnected to V ~s, the state of
-2 2 the stop signal output pin STP will be inverted to
t t produce V DO level output.
-1 1 (6) Counter reset
t t Connecting the reset input pin SR to V S5 resets
0 0 the counter content to O. Note that the counter does
t t not operate with the reset input pin SR connected to
-1 Vss·
t
2 -2
t t • Memory Stop Mode
(1)
Memory stop mode and its resetting
~ When the memory input pin SMEM connected to
1998 -1998
V00 (or open) is to be reconnected to Vss, the mem-
~ ~
ory stop mode will be entered, and M sign be dis-
1999 -1999
played on LCD.
In memory stop mode, when the memory input
pin SMEM connected to V DO (or open) is to be recon-
-----....-.----.-~-SHARP - - - - - - - - - - . . . - . : -
966
Up/Down Counter CMOS LSI with LCD Decoder-Driver LR3617
nected to Vss, the memory stop mode will be reset VDD to Vss level with the stop signal output pin
and the M display on the LCD will disappear. STP at Vss level in the tape end stop mode, the
Altering the memory input pin SMEM connection state of the stop signal output pin will be inverted
does not affect the counter content. to produce VDD level output.
(2) Memory stop mode operation (2) Tape end alarm mode
When the counter content changes in memory The tape end alarm mode will be entered when
stop mode from the value other than 0 to 0 (when 2 the mode input pin SALM is connected to Vss. And if
pulses are applied to the count input pin after the it is decided that it is the tape end, a 500 -1000Hz
display has turned 0, in the case of display chang- pulse will be applied to the alarm signal output pin
ing from 1 to 0, or when the display turns 0 in the ALM.
case of display changing from -1 to 0), the stop When the operation input pin SOPR is turned VDD
signal output pin STP will produce Vss level out- level with a 500-1000Hz pulse being applied to
put. However, in the case of counter content change the alarm output pin ALM in the tape and alarm
from the value other than 0 to 0 due to reset input mode, the alarm signal output pin ALM produces
SR" the stop signal output pin STP will not go Vss V DD level output. However with the STP at Vss
level and stays at VDD level instead. level output, the ALM output is disabled.
When the stop signal output pin STP produces (3) Operation input (SOPR)
Vss level output due to the counter content change When the tape recorder is in PLAY, RECORD,
from the value other than 0 to 0, the memory stop FF, REW, CUE, REVIEW state, or in operation,
mode will be reset and with it the M display on the Vss level input is applied. And when the tape re-
LCD will disappear. corder is out of operation, V DD level input is ap-
With the counter content at 0, the memory input plied.
pin SMEM connected to V DD (or open) is reconnected
(4) Pause input (SPAU)
to Vss to enter the m~mory stop mode.
To be connected to Vss when the tape recorder is
And the stop signal output pin does not produce
in normal operation, or to be connected to V DD (or
Vss level output but stays at VDD level.
open) when the tape recorder is out of operation or
The reset input SR does not affect the memory
in the pause state.
stop mode.
When no pulse has been applied to the count in-
The memory input pin SMEM is always in effec-
put pin SCK for 4-8 seconds with the pause input
tive operation as long as the LSI is supplied with
pin connected to VDD (or open), nor is it decided
power. The timing of the reset input SR and the
that it is the tape end.
memory input SMEM is as follows.
(5) Tape end alarm display
SR ~--------r
I ,
Tape end alarm mode allows for the mode indica-
SMEM~ ___ ~ tion in LCD static display.
I I I J
: : I l (6) Chatter killer
Counter contents -------1: reT ~
(Display) --------Lf---'--~ : The LR3617 has its operation input pin SOPR,
Memory stop mode ru--u~ pause input pin SPAU, mode input pin SALM, up-
(M display) down input pin SDN, memory input pin SMEM, reset
input pin SR, and count input pin SCK equipped
• Tape End Detection Function. with built-in chatter killers, the timing of which is
When no pulse has b.een applied to the counter shown in the figure below.
input pill SCK for 4 - 8 seconds with Vss level input
being applied to both the operation input pin SOPR, LSI input
and the pause input pin SPAU, it will be decided LSI
that it is the tape end to be followed by the opera- acknow ledgement
• t
tions described below. , , , , , , , , I I , , I ' , I ' I I '
In the case of an input pin other than SCK (3.9-7.8ms/div)

(1) Tape end stop mode
The tape end stop mode is a state in which the LSI input
mode input pin SALM is connected to VDD (or open). LSI
acknow ledgement
And when it is decided that it is the tape end, the !, "" I I!,,!, ,
stop signal output pin STP will produce Vss level In the case of SCK (O_25-0.5ms/div)
output. Changing the operation input pin SOPR from
.-.-.--.----SHARP--------..-.·
967
Up/down Counter CMOS LSI with LCD Decoder-,Driver LR3617
(7) Initi.al set Stop signal output pin STP VDD level output
By connecting the initial set input pin SACL to Alarm signal ou(put pinALM V DD level output
VDD , the internal LSI and each output will be in- The LSI retains the state as described above
itialized as follows. with the initial set input pin SACL connected to
Counter display 0 VDD •
Memory stop function reset (therefore no M .dis·
play)
VDD- _ -... 1----.--.
LR3617
Co : For chatter killer of input signal

Alarm C1 : For setting clock frequency
C2 : For level shift coupling
C3: For smoothing after level shift
VDD-~---~~-~
C 4 : For initial set
C5 : For power supply hold
R 1 : F or setting frequency
~: ~ } For regulating current
968
\
VTR Data Back CMOS LSI LR3727
LR3727 VTR Data Back CMOS LSI

The LR3727 is a CMOS LSI which provids date
informations on video recordings.
• Features
1. Date information data store function
(4-bit parallel BCD code)
2. Data display function
4. CMOS process
Top View
• Block Diagram
Display Data
Output 14
25 Horizontal
Display Inhibit 15 Position
2 Display Time
22 Display Start
Vertical
Position
Vertical sync.
Signal
Input Switching
~---t13 Clock Input
(oo)W@X!9--~
Data Input Data Select
---~---------------SHARP--'----'-~'-'
969
VTR Data Back CMOS LSI LR3:r27

Parameter Symbol Rating Unit
Supply voltage * 1 VDD -0.3-+7.0 'V
Input voltage'" 1 VIN -0.3-(V DV +0.3) V
Pin current I ±10 mA,
Power consumption *2 PD 450 mW
*1 Referenced to GND
*2 Ta=60t
Supply voltage * 1 VDD 4.5 5.0 5.5 V
Input voltage * 1 VIN 0 V DD V
External oscillation k!l
resistance Rcp 3.3
• Electrical Characteristics (VDD=5.0V, Ta=25°C)

In display mode, Rcp =3.3k!l 5.0
Current consumption IDD mA
Standby mode 0.1
VIH 4.0 5.0
Input voltage V 1
V IL 0.0 1.0
IJHl V]N=5.0V 0.0 1.0
Input current 1 I'A 2
IILl VIN~ -100
IIH2 VIN=5.0V'-~>.P 0.0 1.0
Input current 2 I'A 3
IIL2 VIN=OV 0.0 -1.0
VOHl 5.0V at 1M!l 4.0 5.0
Output voltage 1 V 4
VOLl IOL =lmA 0.0 0.5
VOH2 5.0V at 1M!l 4.0 5.0
VOL2 IOL =lmA 0.0 1.0
VOH3 IOlI=-lmA 4.5. 5.0
VOL3 IOL =lmA 0.0 0.5
Clock oscillator frequency fcp External resistance= 3.3k!l 2.5 3.0 3.5 MHz
Note 1: Applies to all input pins
Note 2: Applies to Do-D3 pins
Note 3: .Applies to input pins except Do- D3 pins
Note 4: Applies to HCR, TCR pins
Note 5: Applies to Sl -S, pins
Note 6: Applies to DOliT pin
--~-----SHARP~-'-'------
'970
VTR Data Back CMOS LSI
• Operation V12B V64 V32 VI6 VB V, V2 VI set value

(1) Data store operation L L L L L L L H 1
L L L L L L H L 2
( i) Input data switch (CNT pin) The input
data switch input pin is a pin that switches the way
the input data is taken in. As will be shown later, it L H H L L L H H 99
is suited for data setting by digital switch when
this input pin is "Low" and for reading in the data
L I H I H I L I L I H I
"
L I L I 100
from the external LSI when it is "lIigh".

"
(ii) Input data select outputs (SI ...... S6 pins) H H H H H H H L 254
As will be shown later, these outputs produce
the output of strobe signal for each digit when the
H I H I H I H I H I H I H I H 255
Set value=128' V12B+64' V6.+32· V32+16' VI6+8' VB
CNT pin is "Low" and produce the output of inter- +4' V.+2 • V2+VI
face signal for the external LSI when the CNT pin
is "High".
Through the combinations in the table above
(iii) Data input (Do ...... D3 pins) Enter the data
any set value can be selected from 1 to 255. Th~
selected by the data select outputs. The data inputs
display starts in the position (set value + 4) scan
is by entering 6 times serially negative logic paral-
lines from the fall of VSYNC.
lel BCD codes with each dight consisting of 4 bits.
(iv) Oscillator input and output (OSGN, OSCoUT
The data input is in the following order: 10 years'
pins) The frequency of the built-in oscillator is
digit, 1 year's digit, 10 months' digit, 1 month's
determined by the external resistor connected be-
digit, 10 days' digit, and 1 day's digit.
tween these pins. The oscillator frequency of this
Note that with each data, the Do pin is LSB, and
oscillator determines the horizontal size of the
the D3 pin is MSB.
character.
(iv) Data clock input (DCLK pin) Enters
(v) Display time input (TCR pin) Input pin
the fundamental clock input for data transfer when
for time constant of one-shot multivibrator' that de-
the CNT pin is "High". This clock sets up the data
termines how long the characters shall be display-
transfer timing. With the CNT pin "Low", zero
ed on the screen. By varying the time constant of
blanking input for the 10 months' and 10 days'
the external CR, display time can be changed.
digit occurs. When the DCLK pin is "High", zero
(Vi) Display data output (DouT pin) Display
blank is enabled. And when it is "Low", no zero
data output pin that produces "Low" output when
blank is enabled. Note that zero blank is disabled
no character is being displayed and produces
when the CNT pin is "High". '
"High" or "Low" output according to the display
(2) Display operation
when character(s) is(are) being displayed.
(i) Horizontal sync signal and vertical sync
(Vii) Display blanking input (BL pin) Input
signal input (HSYNC, VSYNC pin)
that disables the display data output (DOl'T pin).
To synchronize the picture, the positive-going
When this pin goes "High", the DOtTT pin always will
horizontal sync pulse and vertical sync pulse are to
go "Low" level. This pin only disables the DouT out-
be applied to these input signal pins. The pulse
put and does not affect the internal working of the
width required is more than Ips for the horizontal
LSI.
pulse, and more than twice the horizontal pulse
~ii~ Display start input (START pin) Input.
width for the vertical pulse.
for not only starting to read external data into the
(ii) Horizontal positioning (HCR pin)
[ill
LSI but also for displaying this data on the screen
Input pin for the time constant of the one-shot
after the data is read.
multi vibrator positions the horizonal display in
the picture. By varying the time constant of the ex-
ternal CR, horizontal display position can be
When this input changes from "Low" to "High",
the one-shot multivibrator that determines the dis-
play time will be triggered.
10;=_
changed.
The data display time is determined by the time
(iii) Vertical positioning (Vl ...... V126 pins)
constant of the CR externally connected to the dis-
Input pins for positioning. The level of this pin
play time input pin.
determines the vertical display position.
--~--'-'---SHARP'-'-------
971
VTR Data Back CMOS LSI ·LR3727
• Display P3 D2 D, Do Indication
The display is a total 6-digit, I-line display of
~
year, month, and day each consisting of 2 digits;
The character organization and character array Low High High Lbw
are as follows_
D3 Dz D, Do Indication
r-----'
I I
I I
High High High High

[OJ Low Low Low
(1) Character organization

Low : (blank):
I
I
L_____ J
I
I
The display character is of 5 X 7 numerics and
~
dots that separate year, month, and day. The dots
High High High Low
are fixed and not erasable.
(2) Character array
The character organized as described above will
2
be displayed in array as follows. And the character
High
size, and spacing are as shown in the figures A and
High Low High
B.
A : Approx. 550ns (when the frequency of the
built-in oscillator is 1.8MHz)
3]
B : Scan line_ ... _.3 lines/field
High High Low Low
%
Character array
High Low High High
High Low High Low

§J •
Display of October 25,' 81
Description of Operation
(1) On application of the source voltage V oo ,
the capacitor externally connected to the timer T
[§
starts charging. And when the pulse is applied to
High Low Low High each of.the VSYNC and HSYNC pins, display func-
tion is enabled. The display this time is not consis-
,
tent, but most of the time, only the dots that sepa-
rate the digits are displayed and the characters
that would otherwise follow get blanked.
High Low Low Low
No input signal should be applied prior to pow-
er-up because the LR3727 is of CMOS structure. It
should be remembered that source voltage should al-
ways be kept turned on because of the LSI's small
current consumption except when displaying.
Low High High High
[8J When the capacitor externally connected to the
timer T finishes charging, the LR3727 will go into
the standby mode.
(2) Apply.the horizontal sync pulse and vertical
-.-.-..-.-------SHARP - - - - - - - - - -
972
sync pulse to the HSYNC and VSYNC pin respec- mined by the time constant of the CR externally
tively. Until the START signal is applied, the connected to the TCR pin. Therefore, if the TCR is
whole LSI is in static state and retains the initial left connected to GND, the operation time of the LSI
state with the DouT pin "Low", oscillator in static will be infinitely long and go into continuous dis-
state, Sl-SS in high impedance state ("High"), and play. (However, if the CNT pin is "High", the dis-
each of the time constant input pins (TCR pin, HCR play data will be read into the LSI only once im-
pin) in high impedance state ("High"). mediately after the START signal input. Even in
continuous display, the START signal should be
VSYNC pin~...J"L.......fl
entered again to alter the display.)
START pin ~i-------------~i------:--- (4) On the top signal going "High", the external
TCR pin - - - - , : . ~~ : data will be read into the LSI with the timing as
I
shown in Fig. 1 and Fig. 2. In the data read timing
TP signal -.l (I:
r---
I
LSI function TP - :
chart, the CR time constant of the TRC pin (or TP
signal output time) is shown to be long enough com-
(3) Vary the START input pin from "Low" to pared to the vertical sync signal cycle (longer than
"High" to enter the START signal. As shown in the 2 cycles). With the CR time constant of the TCR pin
following figure, the TP signal is generated in the short (shorter than the vertical sync signal cycle),
LSI while the TP signal is in sync with the VSYNC the complete external data cannot be read into the
signal. More than 1 JL s of the width START input LSI.
signal is required. The TP signal width is deter- The HP signal in the timing chart just discussed
HSYNCpm ~~__~L__~~__~~__~~~'L-~'~~I~-4I__~__~~__~~!L-~I~-4I~~__~L__
I I I I I I I I I I I 1 I
I I I I I I I I I I I I I I
START pin ~r--r--rl --r--r--:--1--r-l--t--~-T--1--i--~1 --
!
VSYNC pin
TP' signal J I I
' I! :
I
1
1
I 1
1
I
I
I
I
I I
I
I I I
I : : : I
I
I
I I
I I I : ! I I
I I I I I I I I I I I
I I I I I I I I I I 1
HP signal _____.I.
I I I
------~I I I I
S1 pin I---! I I
1 i I
S2 pin ---------+-......,~ : !
Sa pm
-----------~~I~..,l~ ~:I--~~~__--------------------
i r '_ _
I I
--------~~+-~~II~U~~·-------------------
HI
I I I I
S5 pin
I I I I
S6 pin
I 1 II II ~I1---------------------
1 I I -
I 1 I I I
Do-D3 pms aOOZ77710zwm
\110· II
1 ,I "
I
t •
flO II I 10 I
~
*t
"
I
I
"Iday'si
I
tJpmIMWl77ZmmmOV77m
.
D 't C years year s months month s days d' 'I D 't Care
on are digit digil digit digit digil IgJ . on
Fig. 1 Data read timing (eNT pin "Low")
.-~----.-~---SHARP~-----.---
973
. . . ._ . . . . .. -......NII-..~_. . . . .. - .. . . . ._ ........................._
Start pin ---fI-'----------------------------

DCLK pin
I ,
,
,I'
VSYNC pin
_--;._ _....11
I
,
,,
TP signal ,
_.......- _...1• I1
I
SI pin -"'T'".....,~
S2 pin, --+----+--,
S3 pin, ---iL.----+---+-~r_-+_-"'T""-_+-__1
S. pin ------+,---1
,
,
S5 pin ------+,--.,~___1
,
I
S5 pin
!I I
I
I
I
I
I
I
, .
I .
I I I , I I ,
Do - D 3 pins""'''''''''''''''''77'77'77:'77:'77:'77:'77:~
I 10 II ear's pO II I 10 I Ida 's I

Don't Care I years' I ~. ,months' I month's I days' I d'! I Don't Care
digit gtt digit digit digit 19tt
Fig. 2 Data read timing (eNT pin "High")

is a signal in sync with the rise of the horizontal The data for the dots that separate each digit will
sync signal applied to the HSYNC pin and has a, be set up in the LSI as fixed data. These character
pulse width that is determined by the time constant data o~ fixed data are to be through the multiplexer
of the CR externally connected to the HCR pin. to the character generator.
Duty varies with the horizontal display position on (5) The data read time is followed by the di,s-
the screen. play time if the TP signal is "High". The display
The external data applied to Do - D3 pins goes time lasts while the TP signal maintains "High" and
into sync with the rise of the horizontal sync signal comes to an end when the TP signal goes "Low".
applied to the HSYNC pin when. the CNT pin is During the display time, it is so designed, the V
"Low", or goes into sync with the rise of the clock address counter counts the HP signals (the pulse
applied to the DCLK pin when the CNT pin is width of which is determinerl by the time constant
"High", to be read into the LSI. Note that while the of the CR externally connected to the HCR pin) that
LSI is reading external data, the display gets blank- . is in sync with rise of the horizontal sync signal
ed and therefore the DouT pin maintains "Low". applied to the HSYNC pin, collects out of the char-
The external data read into the LSI is a 6 character generator the character data output produced
acter data and is stored in a 6 X 4 shift register. du'ring each horizontal scan time, and produces
- - - - - - - - - - - - - - S H A R P - - - . - . . . . . - r ........... . - - -
974
VTR Data eack CMOS LSI LR3727
serially through the 5-bit shift register the charac- Fig. 3 shows the timing chart of the 1 field im-
ter outputs one by one at the DouT pin_ mediately after data read. One character is divided
In the meantime, the H address counter counts into 7 parts with each part displayed during the 3
the timing pulses HC that occur during 1 horizontal horizontal scan lines per field so that vertical size
time to construct a character address and transmit of one character is 21 horizontal scan lines high
6 character data and 2 dot data to the character per field. During the display time, this operation
generator. repeats with each input of vertical sync signal ap-
The oscillator operates only part of the horizon- plied to VSYNC pin.
tal time (when HP is "Low") where display is to be Fig. 4 shows the timing chart of 1 horizontal
performed, to generate not only 5-bit shift register time during the display. One character is di~ided
data but also the clock for the timing circuit and horizontally into 5 parts so that their signal out-
load sequentially 6-character 2.:dot data into the puts will be produced from the DouT pin.
5-bit shift register.
H.SYNC n.
pm ....,'-f~,IL..~L-fIL.-~L-1I"--~L..-IL--IIL...-iL~iL-~L.-!'L.-~L..-!'-' ....-1L~
HP signal -1"\ ' ,

VSYNC :
pin ~~f--~~-~~~~4-~-~!-+--+-~~~~4-~-+--+-r--t~~~-1--i----
,
I
.
VPsignal ----,L-~-r-~~~4--4-+__+i-~-r-~~~--~-+-+-~-r-ii~-i--t-~---
I
I
,
I
I
I
Oscillation
interval
DOUTpin __________~
1
2
3
4
5
6
7
Fig. 3 Display timing in 1 field (TP signal = "High")
HSYNCpin -1l~ __________________________________________________________

HPs~al~ ______________________________________________________________
oSCouTpin
HC signal
DOUT pin IIIIII arm 0 arm ann 0 mm arm 0
Fig. 4
II~II~II~
Display timing in 1 horizonal time (TP signal = "High")
.--.--------SHARP-----------
975
VDD (+5V)
GND
VDD or GND ;;-0
OSCIN,OSC OUT
Horizontal
sync signal
CNT
Vertical
Output
sync signal VSYNC LR3727
Start signal r START
Set 10th digit of the year

VDD
Set last digit of the year
Set 10th digit of the month
Set last digit of the month
Set lOth digit of the day
Set last digit of the day
'-'-"'-'~~-'---SHARP---------
976
Phase Locked Loop Frequency Synthesizer CMOS LSI LR3652.
Phase Locked Loop Frequency Synthesizer

LR3652 CMOS LSI

The LR3652 is a CMOS LSI designed for PLL
frequency synthesizer AM/FM radios. It can be
controlled directly by the Sharp 4-bit I-chip
SM-4A or SM-5A microcomputers. GND
Co
Cl
NC
C2
• Features NC
1. Reference frequencies C3
FM mode NC
2.25kHz, 2.5kHz, 12.5kHz, 25kHz, 50kHz OSCoUT' 9 FM
AM mode OSCIN AM
1kHz, 4.5kHz, 5kHz, 9kHz, 10kHz PSC
2. Frequency division ratio: 113 - 11999
3. FM mode: pulse-swallow type
4. Charge-pump output port and an N-channel Top View
open drain transistor are contained for use in
LPF amp.
5. 5-bit input ports
6. Time base: 3.6MHz crystal
8. CMOS process
• Block Diagram
4 Lock Detector
Programmable Divider
Strobe Programmable Counter

for Prescaler Control Prescaler
FM Local Control
OSC.
Frequency
AM Local
OSC.
Frequency
977
Phase Locked Loop Frequency Synthesizer CMOS LSI LR3652
__. - . - . - . - . - . - . - . - . - . - . - . - . - r........ -....... -

/ Parameter Symbol Ratings Unit Note
Supply voltage V DD -0.3-+6.0 V
External voltage Vee -0.3-+18 V 1
Input voltage V IN -0.3-+6.0 V
Current consumption IDD ±10.0 rnA 2
Output current lOUT ±2.0 rnA 2,3
Operating temperature Topr -20-+60 V
Storage temperature -55-+125 V
T st "
Note 1: Applies to DI. Dz pins.
Note 2: The direction of flowing into the LSI is defined as positive, and flowing out of the
LSI as negative.
Note 3: Applies to output pins.
Supply voltage V DD 2.7 3.0 3.3 V
External voltage Vee 0.0 15.0 V 1
Input voltage V IN 0.0 V OD V
Oscillator frequency fose 3.6 MHz
• Electrical Characteristics (VDD=3.0V, Ta=25"C)

fose= 3.6MHz
Supply voltage V DD 2.7 3.0 3.3 V 4
FM or AM=3.0MHz, 0.3V p - p
fose=3.6MHz, output pin open
Current consumption IDD 2.5 5.0 rnA 4
FM or AM=3.0MHz, 0.3V p - p
Vm 2.6 3.0
Input voltage V 5
V IL 0.0 0.4
1111 1.0
Input current VIN=3.0V pA 5
IlL -1.0
Input frequency fIN Sine wave VIN =0.3V p - p 3.0 MHz 6
VOH1 Connects to V DD at 100kO 2.6 3.0
V 7
VaLl IOL = 100 pA 0.0 0.4
V OH2 IoH = -200 pA 2.6 3.0
V 8
Output voltage V OL2 IOL = 200 pA 0.0 0.4
VOll3 IOlI =-200pA 2.6 3.0
V 9
VOL3 IOL =200 pA 0.0 0.4
Vee =15Vat 100kO
VOll4 14.80 14.95 15.00
with G1 and G 2 grounded
V 1
IOL = LOrnA,
VOL4 ' 0.0 0.4
with (;1 and Gz grounded
Oscillator freq uency fose 3.6 MHz 10
TLH V IN =3.0MHz, sine wave 300
PSC delay time ns 8
TilL 0.5V p - p 300
Note 4: Applies to Voo pin
Note 5: Applies to ST, Co, CI, C2, C3, pins
Note 6: Applies to AM, FM pins
Note 7: Applies to LK pin
Note 8: Applies to PSC pin
Note 9: Applies to CP, CPz pins
Note 10: Applies to OSCIN, OSCOUT pins
,-----------'SHARP----------------
978
• How to Use Pins Programmable counter for counter range

prescaler control .................. = 4
(1) OSCIN, OSCOUT (Crystal oscillation)
If a prescaler with its frequency dividing ratio
switchable between 1/40 and 1/44 is used:
OSC 1N OSCOUT GND Mode ................................................... ·····.· ... ·················FM
Channel space ····················································10OkHz
Crystal Frequency dividing ratio.................................. 1/123
3.6MHz Count range of the counter for
Co prescaler .................................. 4
ST Co Cl C2 C3 Function
With MF "Low" and "High", AM mode and FM mode respectively.
1 MF Ml M2 Ma
For Ml - M3, refer to the other table.
P31-P3' set the frequency dividing ratio for the 100's digit of the
2 P3l P3Z P33 P3'
programmable counter.
P21 - P2. set the frequency dividing ratio for the 10's digit of the
3 P21 PZ2 P23 P2.
programmable counter.
PIl - PI. set the frequency dividing ratio for the l's digit of the prog-
4 Pll PIZ PI3 P14
rammable counter.
PI- p, set the count range of programmable counter for pulse swal-
5 PI P2 P3 p,
lowing.
6 "Low" "High" "Low" "High" Indicate the end of data input and data latch.
Reference frequency (kHz) (2) Co, C" C2, Cs, ST

MI Mz M3 These are the data input pins for selecting FMI
FM mode (MF"Higb") AM mode (MF"Low")
"Low" "Low" "Low" 2.25 1.0 AM, setting reference frequency, FMI AM input
"High" "Low" "Low" 2.50 4.5 frequency dividing ratio, and the count range of
"Low" "High" "Low" 12.50 5.0 programmable counter. The following 2 different
"High" "High" "Low" 25.00 9.0 data inputs are available.
"Low" "Low" "High" 50.00 10.0 ( i ) Using 4-bit data and strobe The data
will be read into LSI by strobe function after 4-bit
FM mode data is set. It takes 6 times of strobe to complete
25kHz 1 2 3 4 Latch data reading.
I" _:E !lIe: alE _Iii!! -I. ;IIi
Iii iii i (ii) Using one pin each for data, strobe, and
ColII~il
II
1 1
I I I
latch 20-bit data is entered serially through
the data input pin Co. With one strobe, the data is
I 1 I 1 1 I
read one bit and will be latched by the C1 input
Cl~ after data reading is completed. C2 and C3 shall al- .
I 1 I i i 1 :
Cz~ ways stay at "High" level.
e3 1
:
1
1
I
!
; 1
111
I I ~
I
n
1 1
:~r-Jrl~ri~
ST~
1
LJ LJ ~ !-.J LJ I
.1 14
1
t;<;2t<s
The input described above provides

1
.!
1
I~
t;<;2t<s
ST
Co
ST
10
P23
20
l!!
Co PI
Mode ................ ·.. ·· ..·............ ·· ........ ·.. ·· .. ·..........·..·..·· ..·· .. FM
Phase comparision frequency ......................·..·25kHz
Programmable counter for frequency deviding
FM,AM input ...... ratio = 11123
. - - - - - - - - - s H A R p . -............ - . . . - - . - - - - - - -
979
PhaSe Locked Loop frequency SyntheSizer CMOS LSI LR3652
Latch
~S+M~Ml~MF+P.. -l j.P.-P~
I , r---t-+--I
I '~
~ ____ .J I I I
H
I
I
I
I
II :I IIi
I
I
:
'
--
:
I
i
I
I
, I
!
I
1-----"-- I I
ri I
~:::::::J.J1.Ji...W
1 I I I I I I
--r--;-- -++-- --+-t-l---
t;O;:2,us . t~2,us
(iii) _FM, AM (Station originatng input)

t, t;O;:2,us
I, GND. LK Voo
I I Station ---f IF,~J

r'! LR3652
FM
TTCI
AM station
C2 o:ig inating
signal
Prescaler
PSCL---r--..J
prescaler originati?n
(iv) CP" CP2, G1, G2, D" and D2

(Constitute a low pass filter circuit)
(v) LK (lock output)
Goes "High" (the transistor turns off) if the PLL
loop is locked.
(vi) PSC (~rescaler control output)
• Reception Frequency Range (1)

Band Area MF Ml M2 M" Frequency dividing ratio Comparison frequency
1165-1179*2
Japan "High" "High" "High" "Low" 25kHz
(4-2)*1
FM 1149-1159*2
USA "High" "Low" "Low" "High" 50kHz
(4-3)*'
11196-11229*,2
Europe "High" "Low" "High" "Low" , 12.5kHz
(6-0)*'
Japan "Low" "High" "High" "Low" 11109-11228 9kHz
AM USA "Low" "Low" "Low" "High" 1180-11184 10kHz
Europe "Low " "High" "High" "Low " 11109-11228 9kHz
*1 Count range of prescaler control counter
*2 When to be used in the FM mode, an IC that, as a prescaler, allows frequency dividing ratio to be switched between 1140 and
1/44 is used.
• Reception Frequency Range (2)

Band Area Reception frequency range Intermediate frequency Station originating frequency Channel space
Japan 76.1-':89.9MHz -10.7MHz 65.4-79.2MHz 100kHz
FM USA 88.1-107.9MHz +10.7MHz 98.8-118.6MHz 200kHz
Europe 87.6-103.8MHz +10.7MHz 98.3-114.5MHz 50kHz
Japan 531-1,602MHz +450MHz 981-2,052kHz 9kHz
AM USA 540-1,580MHz +260MHz 800-1,840kHz 10kHz
Europe 531-1,602MHz +450MHz 98J1-2,052kHz 9kHz
--------SHARP--------
980
FM/AM
selection
LK
r-t-----~ FM
'-----+------IPSC OSCou
L - - - - - - - - - - - 1 - - - - - - - j CP2
LR3652
r----~----------------~AM Co
I
C3
~--------------_iCPl ST
~--.-.---------SHARP-.-.-------
981
Notes
SHARP
SHARP CORPORATION Japan
International Sales Dept.

IC Group
2613-1 Ichinomoto-Cho Tenri-City Nara 632, Japan
Phone: (07-136) 5-1321
Telex: 5522-364 SHAPEL J ! 5522-363 SHAPEX J
NORTH AMERICA: SHARP ELECTRONICS CORPORATION

Electronic Components Division
Sharp Plaza, Mahwah, New Jersey 07430, U. S. A.
Phone: (201) 529-8757
Telex: 426903 (SHARPAM PARA)
EUROPE: SHARP ELECTRONICS (EUROPE) GmbH

Electronic Components Dept.
SonninstraBe 3,2000 Hamburg 1, F.R. Gerinany
Phone: (040) 23775-0
Telex: 2161867 (HEEG D)
©SHARP CORP. Mar86 S4EI Printed in Japan


MOS

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MOS

Uploaded by

Copyright:

Available Formats

SHARP

8-Bit 1-Chip Microcomputers [!

16-Bit Microprocessor and Peripheral LSls ~

Peripheral LSls for Microcomputers ~

Support Tools for Microcomputers[ZJ

LSls for Telephone ~

In recent years, the seemingly unlimited

1. General Information ................................................. ;. 1

Quality Assurance ................................................. 25

• 8-Bit 1-Chip Microcomputer

• 8-Bit CMOS 1-Chip Microcomputer

• a-Bit Microprocessor and Peripheral LSls

Supply Current Clock

Supply Current Clock

. ; Microcomputer Development Support System

• Pulse / Tone Dialer

F'unction Model Process Features Package Page

Function Model Process Features Package Page

Package Outline (Unit: mm)

40PBP 8.9 TYP .

'::' --+-------'- '"~

36QFP p-o.8 TYP• 36 -0.38±o.1 0.15±o.o5

44QFP _liE 0.15-{l.tl5

80QFP p-0.8 TYP. O.15±0.01

80QFP 1'-0.8 TY I'· 0.15±o.05

96QFP p-O.FYP' O.15±O.05

DIP : Dual-In-Line Package

Sharp develops and manufactures a wide range

Process Control items C

Appearance, film thickness Confirm the absence of pin

Visual inspection Development, etching Check the suitability of development and

On line QC Wire width Control the wire width.

Die inspection Appearance Confirm the absence of breakage and

Fig .. 2 Example of process quality control

Table 1 shows examples of material qualification agement.

Development plan decision (New production planning collferen~e)

General evaluation (New product debut conference)

production go - ahead conference)

Fig.4 (a) Quality assurance system (SHARP side)

Fig. 4 (b) Quality assurance system (User side)

associations such as the International Electronics

Fig. Failure analysis procedure

SM-3A PMOS 4-Bit I-Chip Microcomputer

• Absolute Maximum Ratings

• Electrical Characteristics (V DD =-15.0V±10%, VN=-38V, Ta=,-10-+60"C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

• System Configuration (for VTR program timer)

Control signals For channel selection

Fluorescent tube display

SM-IOO/SM-I05 PMOS 4-Bit I-Chip

• Absolute Maximum Ratings

• Recommended Operating Conditions

• Electrical Characteristics (V oo =-9.0V±10%, V N=-38V, Ta=25·C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

PMOS 4-Bit I-Chip

• System Configuration (Video timer)

Sun MOD Tue Wed Thu Fri Sat

R14 Memory indicator

Clock Timer 50/60

T I For test (Connected to V00 normally)

• Absolute Maximum Ratings

• Recommended Operating Conditions

• Electrical Characteristics (V oo =-9V±10%, VN (MAX.)=-35V, Ta=-10-70'C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note