Q bank VLSI (3361104) EC department, GP, Palanpur

2 marks:

Chapter 1

1. List VLSI design style:

VLSI design styles are:
 FPGA ( Field programmable gate array)
 Gate array design
 Standard cell based design
 Full custom design
2. Explain standard cell based design in brief
 It is full custom design style
 It requires development of full custom mask set
 In this design style all the commonly used logic cells are designed and stored in standard cell
library.
 Library contains inverters, gates, complex AOI, OAI, D-latches, Flip flops etc.
 Each cell(gates or AOI or OAI) is available in different size, fan-out capability, delay time,
capacitance etc.
 Power and ground rails run parallel to the upper and lower boundaries of the cell.
 nMOS are located close to ground lines and pMOS transistors close to power rail.
 Advantages: save design time and money, reduce risk compared to full-custom
 Disadvantage: long processing time with respect to FPGA
3. List different types of FPGA and explain in brief:
 Based on the technology used FPGA are classified in 3 categories:
o Antifuse programmed
o SRAM programmed
o EEPROM/ Flash programmed
o Antifuse:
 These devices are only one-time programmable.
 In it antifuse is positioned between two interconnect wires. It consists of three layers:
the top and bottom layers are conductors, and the
middle layer is an insulator.
o When programmed the interconnect acts as low resistance link between interconnect
wires.
o Advantages: they are non – volatile, delay due to routing are small, are faster, require
low power.
o Disadvantage: they are one time programmable. Requires special programmer.
o SRAM :
o These are reprogrammable devices.
o They are volatile.
o They are prone to bit errors. Consumes more power.
o The FPGA by SRAM can be changed in the field. As it uses pass transistors and
multiplexers.
o Flash:
o Flash cells in FPGA are used as either control cells or as programmable swithches.
o Are non volatile in nature. Can be reprogrammed.
o These are low power device and secure like antifuse technology.
4. Write Four advantages of full custom design style.
Advantages of full custom design are:
  Geometry and placement of every transistor can be optimized.
 More opportunity to improve circuit performance.
 Higher level of performance.
 Optimized silicon area utilization.
 Complete flexibility.

5. Differentiate between full custom design and semi custom design

Full custom Semi-custom
Longer design time until maturity Shorter design time
Geometry and placement of every transistor Uses standard cell based design for the devices
can be optimized
More opportunity to improve circuit Less opportunity for improvement
performance.
Product having high performance Less overall performance
Uses less silicon area Uses more silicon area
High cost in terms of design time Low cost in terms of design time
Miss the technology window Will not miss technology window

6. Explain MODULARITY:
 Modularity in design means that the various functional blocks which make up the larger system must
have well-defined functions and interfaces.
 Module can be designed independently
 Modules (blocks) can be combined easily at the end.
  Parallel design process is possible
 Use of generic modules is easy.

7. Give the full form of MOSFET, CPLD, VLSI, and CMOS.

Metal Oxide Semiconductor Field Effect Transistor,
Complex Programmable Logic Device,
Very Large Scale Integration
Complementary Metal-Oxide-Semiconductor

8. Give full form of VLSI, VHDL, FPGA and CPLD

Very Large Scale Integration
VHSIC Hardware Description Language,
Field Programmable Gate Array
Complex Programmable Logic Device,

9. What is top to down and bottom to up approach in VLSI design flow?

 The top-down approach divides a top level blocks into multiple sub blocks required for top level block.
 These sub blocks are further divided until the resulting module cannot be further divided.
 After achieving a certain level of modularity, the decomposition of modules is stopped.


Bottom up approach:
 In it all basic modules are decided first.
 These modules are combined to make higher level modules.
 Until the top level block, smaller blocks are combined.

10. Draw energy band diagram of MOS system.

11. Draw Energy band diagram of a p type silicon substrate.

12. Define Threshold Voltage (VT) in MOSFET

The minimum gate – to – source voltage required to create surface inversion or conducting channel in a
MOSFET is called threshold voltage.

13. What is threshold voltage? Write polarity of Vth in n-MOSFET, p-MOSFET.

 Threshold voltage is the minimum gate – to – source voltage required to create surface inversion or
conducting channel in a MOSFET.
 Vth in n-MOS is positive, and in p-MOS is negative
14. Explain W/L ratio.
The distance between drain and source diffusion region is called channel length L.
Lateral extent of channel is called channel width W. The ratio of width/length of the NMOS or PMOS
device is W/L ratio which controls the drain current value and other MOSFET parameters.
15. Define 1) Enhancement type MOSFET 2) Depletion type MOSFET
MOS transistor having no conducting channel at zero gate bias is called an enhancement- type
MOSFET.
MOS transistor having conducting channel at zero gate bias is called depletion type MOSFET.

16. Draw symbol of N channel and P channel MOSFET.

17. List different operating region of MOS system under external bias.
Cut off region: ≤ Linear: > , ≤ -
Saturation: > , > -
18. Explain PINCH OFF point. / define pinch off point
When drain voltage is increased d > , > - , the drain voltage becomes large enough that
the gate to substrate potential at the drain is smaller than threshold. Therefore re the channel thickness at
drain end goes to zero. This is called as pinch off point.
When = = - , QN (L) = −Cox [ VGS − VDS – VT] = 0,, charge at the drain is zero,
hence no channel exists at the drain end.

19. Explain Substrate Bias Effect

Substrate is applied zero potential in general, but when substrate is applied a negative bi
bias, the source to
substrate and drain to substrate junction remains in reverse bias. This modifies threshold voltage. This
effect is termed as substrate bias effect.
VTN = VTO + γ ( (2 + ) − 2φ F )
Chapter 2

1. Define VOH, VOL, VIL, and VIH or Define VOL and VIL.
VOH: it is the minimum output voltage for logic high where dVout/dVin = -1.
VOL: it is the maximum output voltage for logic low where dVout/dVin = -1.
VIL : it is the maximum input voltage for logic low where dVout/dVin = -1.
VIH: it is the minimum input voltage for logic high where dVout/dVin = -1.
2. Draw a circuit of Enhancement load N MOS Inverter

3. Differentiate between enhancement type MOSFET and Depletion type MOSFET.

Enhancement type load inverter Depletion load inverter
VoH= VDD -VT,load for saturation load and VoH= VDD
VoH= VDD for linear load
Suffers high stand-by power dissipation Comparatively lower stand-by power
dissipation
Fabrication process is simple Slightly more complicated design process.
VTC is not that sharp compared to depletion Sharp VTC
load inverter.
Noise margin in saturation load is low Higher noise margin
Linear load requires double power supply Requires single power supply
For better noise margin, it requires higher It requires lower driver-to-load ratio hence
driver-to-load ratio hence occupies more requires less area.
area.
4. What is C MOS inverter?
CMOS inverter are the complementary MOS inverter, it consists of the enhancement
enhancement-type nMOS
transistor as driver and pMOS transistor as load.
Topology is push-pull,
pull, for high input nMOS drives output node(pull-
node down) and pMOS acts as load, for
low input pMOS drives output node (pull-up) and nMOS acts as load.

5. List advantages of CMOS inverter.

 Steady state power dissipation is negligible, only small power dissipation due to leakage current.
 VTC is full voltage swing between 0V to Vdd.
 VTC is very sharp.
 VTC is similar to that of ideal VTC.
6. Why CMOS is more preferred over other inverters?
 Steady state power dissipation is negligible, only small power dissipation due to leakage current.
 VTC is full voltage swing between 0V to Vdd.
 VTC is very sharp.
 VTC is similar to that of ideal VTC.
7. Draw circuit diagram of Cascaded CMOS Inverter.

Cascaded two inverters are connected as shown in figure. Parasitic capacitances comes into picture.
Cgd and Cgs are gate overlap capacitances.
Cdb and Csb are voltage dependent junction capacitances.
Cg is due to thin oxide capacitance over gate.
Cint is the lumped capacitance due to metal connections between two inverters
Csb,n and Csb,p have no effect on the transient analysis as voltage between gate to substrate is Zero.
Cgs,n and Cgs,p have no effect at the output terminal as they are connected between
between input and ground.
Cload = Cgd,n + Cgd,p + Cdb,n + Cdb,p + Cint + Cg
This Cload causes changes in the transient analysis of the inverter.
 8. Draw circuit diagram of three Cascaded Inverter with VOH, VOL, VIH, VIL
notation
If the input of first inverter is VOH then the output of inverter 1 is VOL.
For inverter 2 due to interconnect the VOL may be interpreted as logic high.
Same applies to inverter 2

9. Define TPHL, TPLH, Trise, and Tfall

TPHL : It is the time delay between the V50% transition of the rising input voltage and V50% transition of the
falling output voltage.
TPLH : It is the time delay between the V50% transition of the falling input voltage and V50% transition of the
rising output voltage.
Trise : time required for the output voltage to rise from V10% to V90% level.
Tfall : time required for the output voltage to drop from V90% to V10% level.
Tp : average propagation delay is the average time required for the input signal to propagate through inverter.

V50% = ½ ( VOL + VOH)

TPHL = t1 – t0
TPLH = t3- t2
TP = (TPHL + TPLH)/2
V10% = VOL + 0.1(VOH – VOL)
V90% = VOL + 0.9(VOH – VOL)
T fall = tB - tA
T rise = tD - tC
Chapter 3
1. Draw circuit diagram of two input NAND gate with depletion nMOS load

2. Draw circuit diagram of two input depletion load NOR gate

Chapter 4,5

1. List VHDL programming methodology.

VHDL programming can be done in three different design styles:
 Behavioral – In this modeling style, the statements are executed sequentially. In this style process is
used for sequential execution. It describes functions without giving implementation details.
 Dataflow – In this modeling style, the flow of data is expressed using concurrent statements. All the
statements are executed in parallel. It describes functions by logical equations.
 Structural – This modeling style, describes how the output is derived from the inputs using structured
statements. In this style only mapping of predefined components is done for final execution of
program. It describes functions by interconnections of gates.

2. Explain difference between signal and variable in terms of VHDL.

Signal Variable Constant
Definition It represents interconnection It is used for local It names specific
wires that connect component storage of temporary values.
ports together data, visible only
within process.
Declaration Signal signal_name: signal_type Variable Constant
[:= initial value]; variable_name: constant_name:
variable_type[:= type_name[:=
value]; value];
Value Needs to be scheduled. Assignment happens
scheduling immediately
Assignment <= := :=
Memory More information required for Less memory
scheduling and attribute required
Usage In package, entity, architecture. Only in sequential
In entity all ports are signals code within process,
function or
procedure
3. Define IN, OUT, INOUT and BUFFER signal types
A VHDL port may have one of four modes:
IN (input only): Used for the signals that is an input to an entity. Values of input port can be read only
within entity model.
OUT (output only) : Used for signals that is an output from an entity. Values of output can be updated
only within entity model and cannot be read.
Signals can appear only to the left of <= operator.
INOUT (bidirectional): Used for signals that is both an input to an entity and an output from the entity.
Values can be read and updated within entity model.
BUFFER : Used for a signal that is an output from an entity. The value of the signal can be used inside a n
entity, which means that in an assignment statement, signal can appear both on left and right sides of the
operator <=.
Values can be read and updated within entity model.
4. Explain CASE statement in VHDL.
It is used whenever a single expression value can be used to select between number of actions.
Syntax:
Case expression is
When choice1 => sequential statement s1;
When choice2 => sequential statement s2;
...
When others => sequential statements1;
End case;

Here the expression is evaluated first.

If it is equal to choice 1 then sequential statement 1 is excecuted.
If it is equal to choice 2 then sequential statement 2 is excecuted.
All possible values of the expression must be included in the choices.
If all the possibilities are not given then others statement would be excecuted.

Example:

Case sel is
When “00” => Y <= I0;
When “01” => Y <= I1;
When “10” => Y <= I2;
When “11” => Y <= I3;
When others => Y <= ‘Z’;
End case;

5. Explain ENTITY in VHDL.

Entity is the basic building block in a design.
The input, output signals in an entity are specified in Entity.
Name of entity can be any legal name.
Input and output signals are specified using keyword PORT.
Mode of the port defines whether the port is input, output or bidirectional.

6. Define Entity in VHDL program.

7. What is entity? Write down it’s syntax with example.

Syntax:
 Entity <entity_name> is
[Port(list- of-interface-signals: mode type [:= initial-value]); ]
End [entity] [entity_name];

<entity_name> will contain name of entity

Port list is optional, it contains list of interface signals with mode as IN, OUT or INOUT

Example:
Entity andgate is
Port( a,b : in std_logic;
C: out std_logic);
End andgate;
8. Write an entity for half adder circuit in VHDL.
9. Write an entity for full adder circuit in VHDL
10. Write the VHDL Code for NOT gate
11. Implement AND GATE using 2 to 1 Multiplexer.
12. Define component of 2×4 decoder in VHDL
13. Fill in Blanks – In General _____data flow______modeling used to implement combinational logic and
_behavioral___________ modeling used to implement sequential logic in VHDL.

3 marks

Chapter 1

1. Explain design hierarchy with example. 3 marks , Explain structural decomposition of 4-bit full adder (
4 marks)

 Definition: Dividing module into sub module and repeating this operation on sub module until
the complexity of smallest part becomes manageable.
 Based on divide and conquer
In fig.,CMOS four-bit adder into its components.
The adder can be decomposed progressively into one bit adders, separate carry and sum
circuits, and finally,into individual logic gates.
  At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined
Boolean function is much more easier to handle than at the higher levels of the hierarchy.

1. Define regularity, modularity and locality.

Regularity: Decomposition of a large system in simple and similar blocks as
much as possible.
Example: Uniformly sized transistors, identical gate structure
Advantage: reduce number of modules that are required to be tested and designed.
Modularity: Modularity in design means that the various functional blocks which make up the larger
system must have well-defined functions and interfaces.
Modularity allows that each block or module can be designed relatively independently from each
other.
All of the blocks can be combined with ease at the end of the design process, to form the large system.
The concept of modularity enables the parallelization of the design process.
Use of generic module is easy.
Locality: The concept of locality also ensures that connections are mostly between neighboring
modules, avoiding long-distance connections as much as possible
2. Explain MOS system under external bias. Given in notes
3. Short note : Full Custom Design. From the table of 2 marks
4. Short note : FPGA
Field programmable gate array
 An FPGA is a device that contains a matrix of reconfigurable gate array logic circuitry.
 When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware
implementation of the software application.
 
Logic block : logic block of an FPGA can be configured in such a way that it can provide functionality as
simple as that of transistor or as complex as that of a microprocessor.
It can used to implement different combinations of combinational and sequential logic functions.
Logic blocks of an FPGA can be implemented by any of the following:
1. Transistor pairs
2. combinational gates like basic NAND gates or XOR gates
3. n-input Lookup tables
4. Multiplexers
5. Wide fan-in And-OR structure.
Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via
electrically programmable switches.
Characteristics:
 FPGA is a high capacity programmable logic device.
 A FPGA consists of an array of programmable basic logic cells surrounded by programmable
interconnect.
 Introduced in 1985 by Xilinx.
 Can be configured/programmed by end-users (field-programmable) to implement specific circuitry.
 Can implement combinational and sequential logic.
 Capacity: 1K to 1M logic gates.
 Speed: up to 100MHz.
 Popular applications: prototyping, FPGA-based computers, on-site hardware reconfiguration, DSP, logic
emulation, network components, etc.
5. Short note : Standard Cell Based Design Given in 2 marks
6. Write short note on Standard cell based design.
7. Short note : Regularity
8. Draw symbol and structure of n channel MOSFET : 2 marks symbol and structure in hand out
9. Explain operation of MOSFET beyond saturation with movement of pinch off point. Given in hand out
Chapter 2

1. Explain Voltage Transfer Characteristic of inverter : hand out

2. Explain Noise Immunity and Noise Margin. : hand out
3. Explain noise immunity and noise margin for nMOS inverter : hand out
4. Explain Enhancement load nMOS inverter. Hand out and difference in 2 marks
5. Explain MOS inverter with enhancement type load
6. Draw depletion load nMOS inverter with Voltage Transfer Characteristic : Hand out
7. Explain operation of CMOS Inverter circuit with diagram
8. Explain Circuit diagram and operation of CMOS Inverter.
9. Draw and explain Cascaded CMOS Inverter.
10. Draw and explain depletion load nMOS inverter.
11.

Chapter 3

1. Write short note on OAI gates

2. Write short note on AOI gates.
3. Explain OAI logic with suitable example.
4. Draw and explain the generalized NAND multiple input structure with Depletion NMOS load.
5. Draw truth table and circuit diagram of two input NOR gate using Depletion nMOS load.
6. Explain NOR2 gate using Depletion load nMOS.
7. Explain transient analysis of 2 input NOR gate
8. Explain transient analysis of 2 input NAND gate
9. Explain EX OR gate using CMOS logic gate.
10. Draw two input XNOR gate using CMOS.
11. Draw circuit diagram of two input NOR gate with CMOS logic circuit.
12. Draw circuit diagram of two input NAND gate with CMOS logic circuit
13. Implement the logic function G = (AD +BC+EF)’ using CMOS.
14. Draw logic function Z = [(D + E + A) (B + C)]’ using Depletion nMOS load OAI Style
15. Implement Boolean function ((A·B + C·D )·EF) with CMOS gates.
16. Implement the logic function G = (A (D + E) +BC)’ using CMOS
17. Implement the logic function G = (PQ +R(S+T))’ using CMOS.
18. Implement the logic function C = (AB +PQ+EF)’ using NMOS Load.
19. Implement the logic function G = (AB + CD)’ using nMOS.
20. Draw circuit diagram of CMOS SR latch using NOR gate.
21. Explain Clocked SR latch using NOR gate.
22.
Chapter 4,5

1. Compare Signal and Variable.

2. Compare Concurrent and Sequential statements.
3. Explain PROCESS statement.
It is used for sequential logic in VHDL.
Process takes the form as:
Process ( sensitivity_list)
Begin
Sequential statements;
End process;

Here whenever one of the signal in the sensitivity list changes state sequential statements are excecuted
in sequence one time.
Example:
Process(B,C,D)
Begin
A <= B;
B <= C;
C <= D;
End process;
4. Explain various types VHDL programming methodologies in brief
5. Explain Structural model with example in VHDL.
Structural Models
Structural models consist of code that represents specific pieces of hardware.
 This modeling style, describes how the output is derived from the inputs using structured statements.
In this style only mapping of predefined components is done for final execution of program.

It enables easy configuration, easy testing and implementation

It provides design in modules.
Modules are first developed in VHDL codes and then are called as components in the actual code.
Syntax:
Component Declaration Syntax:
Component <Component_Name>
Port (<Port_name> : <Signal_Mode> <Signal_Type>);
End Component;
Component Instantiation Syntax:
Label: <Component_Name> Portmap (Signal mapping);
Example of AND using NAND

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andStur is
Port ( A,B: in STD_LOGIC;
Y : out STD_LOGIC);
end ;
 architecture dataFlow of andStur is
component nand1
Port ( A,B: in STD_LOGIC;
Y : out STD_LOGIC);
end component;
signal P:std_logic;
begin

c1: component nand1 port map(A,B,P);

c2: component nand1 port map(P,P,Y);
end DataFlow;

6. Write VHDL CODE for two inputs AND gate.

7. Write VHDL code to implement NAND gate.
8. Write VHDL code to implement OR gate.
9. Write VHDL code to implement AND gate
10. Write VHDL code to implement Full adder.
11. Write down VHDL code for full adder as A, B, C as input and SUM, CARRY as output
12. Write a VHDL program to implement half –substractor
13. Write VHDL code to implement 4 to 1 Multiplexer.
14. Write a VHDL program for 4×1 de-multiplexer
15. Write VHDL code to implement 2 to 4 decoder
16. Write a VHDL program for D flip flop with reset (active high) input
17.

4 Marks

Chapter 1

2. Explain structural decomposition of 4-bit full adder

3. Write Short Note on Standard Cells Based Design.
4. Write a short note on Gate array design.
5. Draw and Explain Y chart design flow in brief.
  The Y-chart consists of three major domains:
o Behavioral domain
o Structural domain
o Geometrical domain
o
6. Explain Y chart
7. Draw Y-chart design flow and explain in brief
8. Explain VLSI design flow with diagram
9. Draw the energy band diagram of P-type silicon substrate and define following term.
(i) Fermi potential (ii) Electron affinity (iii) Work function.
10. Explain MOS system under external bias.
11. Explain MOS system under external bias in detail.
12. Explain operation of MOSFET
13. Explain Gradual Channel Approximation.
14. Derive the equation for junction capacitance for MOSFET
15.

Chapter 2

1. Explain Voltage Transfer Characteristic of inverter.

2. Explain operating mode and VTC of Resistive load inverter circuit.
3. Explain circuit diagram and VTC of NMOS inverter.
4. Explain Resistive load inverter with diagram.
 5. Explain Resistive load MOS inverter. Write equations of VOH, VOL, VIH, VIL
6. Explain enhancement load nMOS inverter with its disadvantages.
7. Explain Enhancement load nMOS inverter
8. Compare enhancement and depletion load nMOS inverter.
9. Explain Depletion load nMOS inverter.
10. Draw CMOS inverter and explain its operation with VTC.
11. Describe cascading of CMOS inverter.
12. Short note: CMOS Inverter.
13.

Chapter 3

1. Draw and Explain OAI gate.

2. Explain OAI logic with suitable example Implement and explain CMOS circuit of EX-NOR function.
3. Realize XOR gate using CMOS logic.
4. Explain NOR2 gate using Depletion load nMOS.
5. Draw Two input NAND gate using CMOS & Depletion nMOS load.
6. Implement logic function Z = (A (D + E) + C)’ using CMOS
7. Draw logic function Z = (A (D + E) + BC)’ using CMOS.
8. Implement the logic function G = (AB + CD)’ using CMOS
9. Implement Boolean function (a+(b+c) · d)’ with CMOS gates
10. Implement Boolean function ((A·B + C·D )·E)’ with CMOS gates
11. Realize Y= (A+B)C + D + E using CMOS logic.
12. Draw and explain NOR2 gates based CMOS SR latch circuit
13. Draw and Explain CMOS SR latch using NAND gate.
14. Draw and Explain Clocked CMOS SR Latch circuit on NAND gate
15. Draw circuit diagram of CMOS SR latch using NOR gate.
16. Draw and Explain NAND2 based SR latch.
17. Explain Clocked CMOS SR latch using NAND gate.
18.

Chapter 4 5

1. List various types of VHDL programming methodologies and Write VHDL CODE for two input XOR
gate.
2. Write VHDL code for 1:4 DeMultiplexer.
3. Write VHDL code for Encoder.
4. Write VHDL code for Parity Generator.
5. Write VHDL code for 8:1 Multiplexer.
6. Write a VHDL code for 8x1 multiplexer
7. Implement 1 to 4 Multiplexer using VHDL.
8. Implement 2 to 4 Decoder using VHDL.
9. List Modeling styles and explain any one of them.
10. Explain Data flow model with suitable example
11. Explain Structural model with suitable example
12.
13. Implement Half Adder using VHDL.
14. Implement JK Flip Flop using VHDL
15. Write VHDL code to implement Half subtractor.
 16. Write VHDL code to implement EX NOR gate using data flow model.
17. Write VHDL code to implement Half Adder.
18. Write VHDL code to implement NOR gate using structural model.
19. Write VHDL code to implement Parity Generator
20. Write VHDL code to implement D flip flop
21. Write VHDL code to implement R S flip flop.
22. Write a VHDL program for D flip flop with reset (active high) input.
23. Write VHDL code to implement T flip flop
24. Write VHDL code to implement Down counter.
25. Write VHDL code to implement Up counter.
26. Write VHDL code to implement 8 to 3 Encoder.
27. Write a VHDL code for 3 to 8 decoder.
28. Write VHDL code to implement EX OR gate
29.
7 marks:

Chapter 1

1. Explain FPGA structure in detail with its advantages, disadvantages and

application
2. Write a short note on FPGA.
3. Write short note FPGA with its advantages, disadvantages and application.
4.
5. Explain n-channel MOSFET with the help of its Current-Voltage
characteristics.
6. Explain VLSI design flow using Y-chart.
7. Explain VLSI Design Flow.
8. Explain VLSI design using Y chart in detail.
9.

Chapter 2

1. Explain Voltege Transfer Characteristics (VTC) of CMOS inverter.

2. Explain the working of Resistive load n-MOSFET inverter.
3.

Chapter 3

Chapter 4 5

1. Write a VHDL code for 4×1 Multiplexure circuit.

2.