Clock Tree Synthesis Techniques For Timing Convergence & Power Reduction of Soc Partitions

Clock Tree Synthesis Techniques for Timing Convergence & Power Reduction of SoC Formatted: Font: 12 pt
Partitions
Aim: The aim of this project is toDesign of propose efficient Clock Tree Synthesis techniques Formatted: Font: (Default) Times New Roman
to for convergeing the Server SoC Partitions.
Problem Statement: The design of the clock network in the SoC has come under increasing Formatted: Font: 12 pt
scrutiny for a number of reasons, ranging from its share of overall power consumption to the Formatted: Font: 12 pt, Highlight
performance limitations caused by increasing on-chip variation (OCV) (only one reason given,
Formatted: Font: 12 pt
but is says number of reasons). It has been observed that Tthe performance of the clock network
can beis highly temperature dependent, potentially leading to the meeting chip meeting timing
requirements under some PVT corners but not others (? Be specific). So, there is a need of for
an efficient CTS methodology, which can tackle all these issues (only one issue?).
Objective of the Project: The objective of this my Master’s project is to develop efficient
clock tree synthesis techniques for meeting timing, area and power requirements. The Proposed
techniques mentioned will be implemented on SoC chassis partition. The synthesis will be
carried out on the RTL with the timing constraints and design planning for the floorplan. The
Hold fixing and skew balancing will be done in clock tree synthesis. After the database (?) is
obtained, all the analysis will be done (Not clear, Rewrite). The analysis which are will be
carried out done include timing, power, DRC (Design Rule Checks), shorts, opens, LVS
(Layout vs Schematic), ERC (Electrical Rule Checks), Functional Equivalence & Power
Format checks. With all the analysis reports, the comparison is will be made to prove the
efficiency of the techniques used. Formatted: Font: 12 pt, Not Bold
Methodology:
Various steps can be outlined as following:
1) Converting a A high level description of the design will be converted into an optimised Formatted: Font: 12 pt
gate level representation given for a standard cell library and under certain given design Formatted: Font: 12 pt
constraints by using given synthesis tool. Formatted: Font: 12 pt
2) Place and route techniques will be used to reduce timing and area.
3) For timing optimization, we will concentrate on repeater trees, logic restructuring,
choosing physical realization of gates (Sizing and threshold voltage assignment) and Formatted: Font: 12 pt
adjusting cell position in layout. Formatted: Font: 12 pt

4) After timing optimization, we will do quality check will be carried out to prevent silicon Formatted: Font: 12 pt
failures under any working conditions. To carry out this task, and for this we will need Formatted: Font: 12 pt
to satisfy the rule set on various issues like clocks, connectivity (max length of wire, Formatted: Font: 12 pt
input slopes etc.), margins ( additional margins to overcome real delays).
5) For power reduction, clock gating, multi VDD analysis following approaches will be
usedcarried out. like clock gating, multi VDD. Formatted: Font: 12 pt
6) To get evenFor getting improved result better results completely new clock tree Formatted: Font: 12 pt
synthesis techniques will be used taking into account the results from along with above Formatted: Font: 12 pt
steps. Finally this and then the results will be compared will be compared with previous Formatted: Font: 12 pt
value. Formatted: Font: 12 pt
Key tools to be used:
1) Synopsys Design Compiler (For synthesis) Formatted: Bulleted + Level: 1 + Aligned at: 0.25" +
2) Synopsys IC Compiler 1 (For place and route) Indent at: 0.5"
3) StarRC (For RC extraction)

4) Synopsys Prime Time (For Static timing analysis)
5) Duet (Quality related checks)
6) Conformal LEC (Formal equivalence verification)
7) Synopsys Prime Time-PX (Power analysis)
8) Synopsys Prime Time-SI (Noise analysisis) Formatted: Font: 12 pt
In the project, I will be dooing clock tree mesh synathesis (CTMS) instead of conventional Formatted: Normal, No bullets or numbering
CTS ( clock tree synthesis). Since CT Mesh will be used, it is expected that there will be a zero Formatted: Font: (Default) Times New Roman
clock skew up-to a certain point and from there we will route to sequential (?) through Formatted: Justified, Pattern: Clear
RCB(regional clock buffer) and LCB (local clock buffer).
Formatted: Font: (Default) Times New Roman
For far away data routing with high latency through CTS in design we can reduce latency and Formatted: Font: (Default) Times New Roman
thus improve timing, power as well as on chip variation. It is expected to show the improvement Formatted: Font: (Default) Times New Roman
in timing and power. Formatted: Font: (Default) Times New Roman
Submitted by:
Name: - Nimish Khanna Formatted: Font: (Default) Times New Roman
Reg. No.:- 17MT001505 Formatted: Font: (Default) Times New Roman

Internal Guide: - Dr. S.S.Jamuar
Formatted: List Paragraph
External Guide:- Selvaraj Subramanian
Place of work and Internship: - Intel Technologies India Pvt. Ltd.(b) Formatted: Font: 12 pt
External Guide:- Selvaraj Subramanian Formatted: Font: 12 pt

Clock Tree Synthesis Techniques For Timing Convergence & Power Reduction of Soc Partitions

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Clock Tree Synthesis Techniques for Timing Convergence & Power Reduction of SoC Formatted: Font: 12 pt

adjusting cell position in layout. Formatted: Font: 12 pt

3) StarRC (For RC extraction)

Reg. No.:- 17MT001505 Formatted: Font: (Default) Times New Roman

External Guide:- Selvaraj Subramanian Formatted: Font: 12 pt

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