Clock Tree Synthesis Techniques for Timing Convergence &

Power Reduction of Complex SoC Partitions

Aim: The aim of this project is to propose efficient Clock Tree Synthesis techniques to achieve better
timing and power optimization and converge the complex SoC Partitions.

Problem Statement: The design of the clock network in the SoC has come under increasing
scrutiny for a number of reasons for high speed circuits ranging from its share of overall power
consumption and clock skew to the performance limitations caused by increasing on-chip variation
(OCV). The performance of the clock network can be highly temperature dependent, potentially leading
to the chip meeting the timing constraints under some PVT corners but not others. So, there is a need
of an efficient CTS methodology which can tackle all these issues.

Objective of the Project: The objective of this project is to develop efficient clock tree synthesis
techniques for meeting timing, area and power requirements. The techniques mentioned will be
implemented on SoC chassis partition. The synthesis will be carried out on the RTL with the timing
constraints and design planning for the floorplan. The timing fixing and skew balancing will be done in
clock tree synthesis. After the database is obtained, all the analyses will be done. The analyses which
are done include timing, power, DRC (Design Rule Checks), shorts, opens, LVS (Layout vs Schematic),
ERC (Electrical Rule Checks), Functional Equivalence & Power Format checks. With all the analyses
reports, the comparison is made to prove the efficiency of the techniques used.

Methodology:
1) Converting a high level description of the design into an optimised gate level representation
given a standard cell library and certain design constraints using given synthesis tool.
2) Place and route techniques will be used to reduce timing and area.
3) For timing optimization, we will concentrate on repeater trees, logic restructuring, choosing
physical realization of gates (Sizing and threshold voltage assignment) and adjusting cell
position in layout.
4) After timing optimization, we will do quality check to prevent silicon failures under any work
conditions and for this we need to satisfy the rule set on various issues like clocks, connectivity
(max length of wire, input slopes etc.), margins( additional margins to overcome real delays).
5) For power reduction, following approaches will be used like clock gating, multi VDD.
6) To get even better results completely new clock tree synthesis techniques will be used along
with above steps and then the results will be compared.

Key tools to be used:

1) Synopsys Design Compiler (For synthesis)
2) Synopsys IC Compiler 1 (For place and route)
3) StarRC (For RC extraction)
4) Intel Internal Tool (For Static timing analysis)
5) Duet (Quality related checks)
6) Conformal LEC (Formal equivalence verification)
7) Intel Internal Tool (Power analysis)
8) Intel Internal Tool (Noise analysis)
Submitted by:
Name: - Nimish Khanna

Reg. No.:- 17MT001505

Internal Guide: - Dr. S.S.Jamuar

Place of Internship: - Intel Technologies India Pvt. Ltd.(b)

External Guide:- Selvaraj Subramanian

Signature:

(Selvaraj Subramanian)