TN 423: VLSI CIRCUITS

Lecture 9b

HARDWARE DESCRIPTION
LANGUAGE (HDL)

Ngeze, LV TN 423: VLSI Circuits

 Outline
Ω What and why HDL
Ω Verilog HDL
Ω Modelling a simple circuit.
 Delays
 Stimulus
Ω Abstraction Levels
 Gates
 Dataflow
 Procedural

Ngeze, LV TN 423: VLSI Circuits

 Objectives
Ω At the end of this lecture, you will be able to:
 Understand keywords, white spaces, data types and
operators
 Create a basic Verilog module
 Understand Verilog data types and operators and
their uses
 Model hardware and test using behavioral modeling
constructs
 Model hardware and test using structural modeling
constructs
 Simulate some simple digital circuits

Ngeze, LV TN 423: VLSI Circuits

 Gate Delays
Ω All physical circuits exhibit a propagation delay between
the transition of an input and a resulting transition of an
output.
Ω When an HDL model of a circuit is simulated, it is
sometimes necessary to specify the amount of delay
from the input to the output of its gates.
Ω In Verilog, the propagation delay of a gate is specified in
terms of time units and by the symbol #(delay).
Ω The numbers associated with time delays in Verilog are
dimensionless.
and #(30) G1 (w1, A, B);
not #(10) G2 (E, C);
or #(20) G3 (D, w1, E);
Ngeze, LV TN 423: VLSI Circuits
 Adding Delays
Ω To simulate a circuits real world behaviour it is
important that propogation delays are included.
Ω The units of time for the simulation can be
specified with timescale.
 Default is 1ns with precision of 100ps
Ω Component delays are specified as #(delay)

Ngeze, LV TN 423: VLSI Circuits

 Simple Circuit Boolean Expression
Example: Given the circuit below, write a Verilog
program to include delays as shown:

and gate with a delay of 30

or gate with a delay of 20
not gate with a delay of 10

Ngeze, LV TN 423: VLSI Circuits

 Simple Circuit with Delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule

Ngeze, LV TN 423: VLSI Circuits

Simple Circuit Boolean Expression

x = A.B + C
y=C

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 Boolean Expressions
//Circuit specified with Boolean
equations
module circuit_bln (x,y,A,B,C);
input A,B,C;
output x,y;
assign x = (A&B)|~C;
assign y = ~C ;
endmodule
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Example 1

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Example 1

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Example 2

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Example 2

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 Design a Circuit
// Verilog model: Circuit with Boolean expressions

module Circuit_Boolean_CA (E, F, A, B, C, D);

output E, F;
input A, B, C, D;
assign E = A || (B && C) || ((!B) && D);
assign F = ((!B) && C) || (B && (!C) && (!D));
endmodule

Ngeze, LV TN 423: VLSI Circuits

 QUESTIONS
Qn 1: Find the syntax errors in the following
declarations (note that names for primitive gates
are optional):

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 QUESTIONS
Qn 2: Draw the logic diagram of the digital circuit
specified by the following Verilog description:

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 QUESTIONS
Qn 3: Draw the logic diagram of the digital circuit
specified by the following Verilog description:

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 QUESTIONS
Qn 4: Draw the logic diagram of the digital circuit
specified by the following Verilog description:

Ngeze, LV TN 423: VLSI Circuits

 Multiplexor
Ω Multiplexor is a combinational circuit where an
input is chosen by a select signal.
 Two input mux
 output =A if select =1
 output= B if select =0

A
x
B

Ngeze, LV TN 423: VLSI Circuits

 Two Input Multiplexor
Ω A two-input mux is actually a three input device.

s A B x
0 0 0 0
0 0 1 1
A
x 0 1 0 0
B
0 1 1 1
1 0 0 0
s
1 0 1 0
1 1 0 1
x = A.s + B.s
1 1 1 1

Ngeze, LV TN 423: VLSI Circuits

 Dataflow description of 2-input Mux

Ω Conditional operator ?:takes three operands:

condition? true_expression : false_expression

module mux2x1_df (A,B,select,OUT);

input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule

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 Behavioural Modelling
Ω Represents circuits at functional and algorithmic
level.
Ω Use proceedural statements similar in concept
to proceedural programming languages (e.g. C,
Java),
Ω Behavioural modelling is mostly used to
represent sequential circuits.

Ngeze, LV TN 423: VLSI Circuits

 Behavioural Modelling
Ω Behavioural models place proceedural
statements in a block after the always
keyword.
Ω The always keyword takes a list of variables.
The block of statements is executed whenever
one of the variables changes.
Ω The target variables are of type reg. This type
retains its value until a new value is assigned.

Ngeze, LV TN 423: VLSI Circuits

Behavioral description of 2-input mux

module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule

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Write a Verilog program for a 2-to-4 Line
Decoder

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 Decoder

A decoder is a circuit that changes a code into a set of

signals. It is called a decoder because it does the reverse
process of encoding.

A common type of decoder is the line decoder ( n to 2n )

. eg 1-to-2 line decoder , 2-to-4 line decoder.
 2-to-4 line decoder

Ω A decoder that has two inputs, an enable pin and four

outputs as shown in next slide.

Ω The 2-to-4 line decoder will switch on one of the

four active low outputs, depending on the binary
value of the two inputs and if the enable input is
high.
 2-to-4 line decoder

Block diagram of 2-to-4 line decoder

2-to-4 Line Decoder Dataflow Verilog
 2-to-4 Line Decoder circuit diagram

The following is the circuit diagram of 2-to-4 line

decoder.
g1

g7
g2

g4 g8

g9
g5

g10
2-to-4 Line Decoder: Structural Verilog HDL Description

module decoder_2_to_4(EN, A0, A1, D0, D1, D2, D3);

input EN, A0, A1;
output D0, D1, D2, D3;
wire A0_n;
wire A1_n;
wire N0;
wire N1;
wire N2;
wire N3;
not g0 (A0_n, A0);
not g1 (A1_n, A1);
 Cont…

and g3(N0, A0_n, A1_n);

and g4(N1, A0, A1_n);
and g5(N2, A0_n, A1);
and g6(N3, A0, A1);
and g7(D0, N0, EN);
and g8(D1, N1, EN);
and g9(D2, N2, EN);
and g10(D3, N3, EN);
endmodule
Ngeze, LV TN 423: VLSI Circuits
 HDL Summary
Ω Hardware Description Languages allow fast
design and verification of digital circuits.
Ω Accurate simulation and testing requires delays
and inputs to be specified.
Ω There are three different levels of abstraction
for modelling circuits.

Ngeze, LV TN 423: VLSI Circuits