LAB 1

Q1) Write down 3 notable products/projects where 8086 or similar microprocessors have
been used.
Auto Controlled Lights.
Gate Controller, Automated
A Basic 16-bit calculator

Q2) What are the types of microprocessors currently used in the industry?

Complex Instruction Set Microprocessors

Reduced Instruction Set Microprocessor
Superscalar Microprocessors
Digital Signal Multiprocessors
The Application Specific Integrated Circuit

Q3) List down the major manufacturers of microprocessors and one of the notable
products of each manufacturer.

Intel 4004 (1971) Breakthrough application: Busicom 141-PF Calculator (1971)

Intel 8080 (1974) Breakthrough application: MITS Altair 8800 (1975)
Acorn Computers ARM2 (1986)
Intel 8088 (1979)
MOS Technology 6502 (1975)
Zilog Z80 (1976)
AMD Opteron 240 (2003)
RCA COSMAC CDP 1802 (1976)

Q4) list down the components present in the CPU & Memory section of the 8086 trainer
board along with their functions in your own words.

The two typical components of a CPU include the following:

The arithmetic logic unit (ALU), which performs arithmetic and logical operations.
The control unit (CU), which extracts instructions from memory and decodes and executes them,
calling on the ALU when necessary.
Memory
☞Monitor EPROM: 0000 –FFFF (SEGMENT)
☞System RAM: 0000 –FFFF (SEGMENT) 1000 – 3FFF (Reserved For Monitor
program)
☞User RAM Area: 1100 – 3FFF
TASK 1:Do further research on 8088 and 8086 based microprocessor boards.

1. Size:-
8085 is 8 bit microprocessor whereas 8086 is 16 bit microprocessor.

2. Address Bus:-
8085 has 16 bit address bus and 8086 has 20 bit addres bus.

3. Memory:-
8085 can access up to 2^16 = 64 Kb of memory whereas 8086 can access upto
2^20 = 1 MB of memory.

4. Instruction Queue:-
8085 doesn't have an instruction queue whereas 8086 has instruction queue.

5. Pipelining:-
8085 does not support pipelined architecture whereas 8086 supports pipelined
architecture.

6. Multiprocessing Support:-
8085 does not support multiprocessing support whereas 8086 supports.

7. I/O:-
8085 can address 2^8 = 256 I/O's and 8086 can access 2^16 = 65,536 I/O's

8. Airthmetic Support:-
8085 only supports integer and decimal whereas 8086 supports integer, decimal
and ASCII arithmetic.

9. Multiplication and Division:-

8085 doesn't support whereas 8086 supports.

10. OperatingModes:-
8085 supports only single operating mode whereas 8086 operates in two modes.

11. External Hardware

8085 requires less external hardware whereas 8086 requires more external
hardware.

12. Cost:-
The cost of 8085 is low and 8086 is high.

13. Memory
In 8085, memory space is not segmented but in 8086, memory space is segmented.
Task 2 a block diagram of a single board computer made using 8088.
 Lab 2

Familiarize yourself with operating conditions of a TTL chip and input and
output voltages and currents for high and low state.

Refer to the data sheet of 74245 bi-directional octal buffer, and understand its
function table and schematic. Identify inputs, outputs and control pins of the
74245.
Familiarize yourself with Fan-in and Fan-out concept.
Fan-in is the maximum number of inputs to a gate. Although physical considerations limit fanin,
more pragmatic factors, such as limitations on the number of pins possible on IC packages
and their standardization predominate. TTL NAND gates typically provide 1, 2, 4, or 8 inputs.
If more than eight inputs are required, then a network of NAND gates must be employed.
Fan-out specifies the number of standard loads that the output of a gate can drive without
impairing its normal operation. A standard load is defined to be the amount of current required
to drive an input of another gate in the same logic family. Due to the nature of TTL gates, two
different fanout values are given, one for HIGH outputs and one for LOW outputs. Typically
when an input is at logic 1 at most 40μA flows into an input (IIH(max), see Lab 1), and it must
be provided (sourced) by the driving output. For logic 0, at most 1.6 mA flows from the input
(IILmax), which the driving output must "sink". By convention the current flowing into an input
or output is considered positive while a current flowing out of an input or output is considered
negative; hence, IILmax = -1.6mA. A typical TTL gate can source 400 μA (I0H(max)) of
current and can sink 16 mA (I0L(max)).

Refer to a TTL data sheet and write down the meanings of VOH, VIH, VOL,
VIL, IIH, IOH, IIL, IOL:

VIH Input HIGH Voltage

VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
IIH Input Current
IIL Input LOW Current
IOH Output HIGH Current
IOL Output LOW Current

Q2 Find the VIH and IIH, VOH and IOH of 74245:

Task 1: Define TTL logic and state threshold voltages for TTL

The logic family refers to the general physical realization of a logical element, such as the TTL,
Emitter-coupled logic (ECL) , or complementary metal-oxide semiconductor (CMOS) logic
Families. Within each logic family are one or more logic series that have distinctive
Characteristics, relative to other series within the same logic family. For example, in the TTL
logic family, there are several logic series: the 74 standard, 74L low-power, 74H high-speed,
74S standard Schottky, 74LS low-power Schottky series, and 74ALS advanced low-power
Schottky series.

Task 3: What would happen if Fan-out spec were violated? What if Fan-in spec is violated?

Fan In: The fan-in defined as the maximum number of inputs that a logic gate can accept. If
number of input exceeds, the output will be undefined or incorrect. It is specified by
manufacturer and is provided in the data sheet
Fan Out: The fan-out is defined as the maximum number of inputs (load) that can be connected
to the output of a gate without degrading the normal operation. Fan Out is calculated from the
amount of current available in the output of a gate and the amount of current needed in each
input of the connecting gate. It is specified by manufacturer and is provided in the data sheet.
Exceeding the specified maximum load may cause a malfunction because the circuit will not be
able supply the demanded power.

Task 5 :What are the main differences between TTL and CMOS gates?

CMOS compared to TTL:

CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS
power consumption increases faster with higher clock speeds than TTL does. Lower current
draw requires less power supply distribution, therefore causing a simpler and cheaper design.
Due to longer rise and fall times, the transmission of digital signals becomes simpler and less
expensive with CMOS chips.
CMOS components are more susceptible to damage from electrostatic discharge than TTL
components.
 LAB 3
Q1 identify the types of latch and their differences

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can
store one bit of information. The main difference between latches and flip-flops is that for
latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes. There are basically four main types of latches and flip-flops: SR, D, JK, and T. The
major differences in these flip-flop types are the number of inputs they have and how they
change state. For each type, there are also different variations that enhance their operations. In
this chapter, we will look at the operations of the various latches and flipflops.

Q2 Familiarize yourself with operation and features of a D latch

Just like the SR latch with an enable input, the D latch can also have an enable input as shown in.
When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the latch
is said to be “open” and the path from the input D to the output Q is “transparent”. Hence the
circuit is often referred to as a transparent latch. When E is de-asserted (E = 0), the latch is
disabled or “closed”, and the Q output retains its last value independent of the D input. A sample
timing diagram for the operation of the D latch with enable is shown in Figure 9(d). Between t0
and t1, the latch is enabled with E = 1 so the output Q follows the input D. Between t1 and t2, the
latch is disabled, so Q remains stable even when D changes

Q3 refer to the datasheet of 74373 octal transparent latch, and understand its function
table and schematic. Identify inputs, outputs and control pins of the 74373.
POSTLAB

TASK 1 From your observation, is the 74373 octal latch an inverting or non inverting
latch?
Non inverting

TASK 2 What is the purpose of 74373 octal latch with 8088 microprocessor.

An octal latch is an integrated circuit (IC) that contains eight binary digital circuits called latches.
A latch is a form of sequential logic circuit. A simple latch has two stable logic states. The latch
maintains its states indefinitely until an input pulse called a trigger is received

TASK 3 Refer to 74245 data sheet and record the IIH and IIL of the buffer

TASK 4 Refer to 8088 data sheet and find out IOH and IOL of 8088. Compare the input
and output currents.
 LAB 4
Identify what a crystal oscillator is and how it works.
A crystal oscillator is an electronic oscillator circuit which is used for the mechanical resonance
of a vibrating crystal of piezoelectric material. It will create an electrical signal with a given
frequency. This frequency is commonly used to keep track of time for example: wrist watches
are used in digital integrated circuits to provide a stable clock signal and also used to stabilize
frequencies for radio transmitters and receivers.Quartz crystal is mainly used in radio-frequency
(RF) oscillators. Quartz crystal is the most common type of piezoelectric resonator, in
oscillator circuits we are using them so it became known as crystal oscillators. Crystal oscillators
must be designed to provide a load capacitance.

POSTLAB

Task1 Review the 8088 CPU signals and pins. Divide the signals into four categories: (1)
address lines, (2) data lines, (3) bus and other control, and (4) memory and peripherals
controls. Identify the signals of each group.
8088 has Address lines A0-A15 and an eight-bit external data bus instead of the 16-bit bus of
the 8086.
execution unit (EU)—only the bus interface unit (BIU)
Intel 8282/8283: 8-bit latch
Intel 8284: clock generator
Intel 8286/8287: bidirectional 8-bit driver. Both Intel I8286/I8287 (industrial grade) version
were available for US$16.25 in quantities of 100.
Intel 8288: bus controller
Intel 8289: bus arbiter
Intel 8087: Math Co-Processor

TASK 2 Review the clock generator 8284 and identify the three major functions that this
device can operate.

1) The 8284 clock generator uses a crystal oscillator that must be 3 times the frequency of
the CPU(15 MHz Crystal).
2) IT creates an electrical signal with a very precise frequency.
3) It ensures better intelligibility of the signal with stable frequency.
 Lab # 5
Post Lab Tasks:

Task#1:
Identify the pins of 8088 used in de-multiplexed bus and write down their functionality.

40 pin dual-in-line (DIP) package

Pin functions
• Most pins are independent and serve a single function
• Examples: CLK—clock, INTR—interrupt request ,READY—bus ready .
• Some multi-functions pins– different times/different mode
• Examples: AD0-AD15– multiplexed address/data lines at different times, A16/S3—
multiplexed address and status line at different times, IO/M* or S2* Control line in one mode or
bus status line in other mode.

Task#2:
What is bus contention? Write down a brief description.

Bus contention, in computer design, is an undesirable state of the bus in which more than one
device on the bus attempts to place values on the bus at the same time. Most bus architectures
require their devices to follow an arbitration protocol carefully designed to make the likelihood
of contention negligible.[1] However, when devices on the bus have logic errors, manufacturing
defects, or are driven beyond their design speeds, arbitration may break down and contention
may result. Contention may also arise on systems which have a programmable memory
mapping when illegal values are written to the registerscontrolling the mapping.
Contention can lead to erroneous operation, excess power consumption, and, in unusual cases,
permanent damage to the hardware—such as burning out a MOSFET.

Task#3:
How can the data bus be used by multiple devices , what
changes are required in the circuit ?

In general, a data bus is broadly defined. The first standard for data bus was 32-bit, whereas
newer data bus systems can handle much greater amounts of data. A data bus can transfer data to
and from the memory of a computer, or into or out of the central processing unit (CPU) that acts
as the device's "engine." A data bus can also transfer information between two computers.
The use of the term "data bus" in IT is somewhat similar to the use of the term "electric busbar"
in electronics. The electronic busbar provides a means to transfer the current in somewhat the
same way that the data bus provides a way to transfer data. In today’s complicated computing
systems, data is often in transit, running through various parts of the computer's motherboard and
peripheral structures. With new network designs, the data is also flowing between many different
pieces of hardware and a broader cabled or virtual system. Data buses are fundamental tools for
helping facilitate all of the data transfer that allows so much on-demand data transmission in
consumer and other systems.
 Lab # 6
Lab Task #1:
Q1 what is timing delay in logic ICs?
Propagation delay, symbolized tpd, is the time required for a digital signal to travel from the
input(s) of a logic gate to the output. It is measured in microseconds (µs), nanoseconds (ns), or
picoseconds (ps), where 1 µs = 10-6 s, 1 ns = 10-9 s, and 1 ps = 10-12 s.

Q2 why is IOSEL connected using two inverters?

Providing the battery bank capacity can handle then draw off both inverters then it is oK to run
them off the same DC battery bank . But keep the AC circuits separate. If you have your 3
batteries in parallel then your terminal take off should be diangonally of the first and third
battery. ie +ve from battery one and -ve off battery three, tapping individual batteries paralled
together is bad practice, I think Mike has a link to a good page on wiring batteries in series and
parallel.

Q3 Define the functions of the output pins of memory control logic?

CE and OE pins are control pins. Chip enable (CE) has to be low. Then Output enable has to be
low for data to be sent/read to the CPU. The functions of the output pins of memory control logic
is to read and sent data.

Lab Task#2:
Q1 what logic allows 3 devices connected to the same bus to operate independently?
A Tri-state Buffer can be thought of as an input controlled switch with an output that can be
electronically turned “ON” or “OFF” by means of an external “Control” or “Enable” ( EN )
signal input. This control signal can be either a logic “0” or a logic “1” type signal resulting in
the Tri-state Buffer being in one state allowing its output to operate normally producing the
required output or in another state were its output is blocked or disconnected.

Q2 how do we write some data to the latch?

We use LAT register to write data to the latch.

Post Lab tasks:

Task#2:
Identify memory map of the 8088 and describe how the memory used in the lab will
allocate to this memory map.

The processor can usually address a memory space that is much larger than the
memory space covered by an individual memory chip.
In order to splice a memory device into the address space of the processor, decoding is
necessary.
For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address
space.
However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.
A decoder can be used to decode the additional 9 address pins and allow the EPROM
to be placed in any 2KB section of the 1MB address space
To determine the address range that a device is mapped into:

This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H).
NAND gate decoders are not often used.
Rather the 3-to-8 Line Decoder (74LS138) is more common.

Task#3:
Identify the types of memory ICs available and write down their differences.

Following are the types of memory ICs , DRAM, EEPROM, Flash, FRAM, MRAM , Phase
change memory ,SDRAM, SRAM.

DRAM:Dynamic RAM is a form of random access memory. DRAM uses a capacitor to store
each bit of data, and the level of charge on each capacitor determines whether that bit is a logical
1 or 0.
EEPROM:This is an Electrically Erasable Programmable Read Only Memory. Data can be
written to it and it can be erased using an electrical voltage.
EPROM: This is an Erasable Programmable Read Only Memory. This form of semiconductor
memory can be programmed and then erased at a later time.
Flash memory:Flash memory may be considered as a development of EEPROM technology.
Data can be written to it and it can be erased, although only in blocks, but data can be read on an
individual cell basis.
F-RAM: Ferroelectric RAM is a random-access memory technology that has many similarities
to the standard DRAM technology
MRAM: This is Magneto-resistive RAM, or Magnetic RAM. It is a non-volatile RAM memory
technology that uses magnetic charges to store data instead of electric charges. Unlike
technologies including DRAM, which require a constant flow of electricity to maintain the
integrity of the data, MRAM retains data even when the power is removed.
 LAB # 7
Task1:
Answer the following questions:

Q1 Name the general registers in 8086 and explain their uses?

General-purpose Registers:
Four general-purpose registers, AX, BX, CX, and DX. Each of these is a combination of two 8-
bit registers which are separately accessible as AL, BL, CL, DL (the "low'' bytes) and AH, BH,
CH, and DH (the "high'' bytes). For example, if AX contains the 16-bit number 1234h, then AL
contains 34h and AH contains 12h.

AX (accumulator):
Some of the operations, such as MUL and DIV, require that one of the operands be in the
accumulator. Some other operations, such as ADD and SUB, may be applied to any of the
registers (that is, any of the eight general- and special-purpose registers) but are more efficient
when working with the accumulator.

BX (base register):
It is the only general-purpose register which may be used for indirect addressing. For example,
the instruction MOV [BX], AX causes the contents of AX to be stored in the memory location
whose address is given in BX.

CX (count register):
The looping instructions (LOOP), the shift and rotate instructions
(RCL, RCR, ROL, ROR, SHL, SHR), and the string instructions (with the prefixes REP, REPE,
and REPNE) all use the count register to determine how many times they will repeat.

DX (Data register):
It is used together with AX for the word size MUL and DIV operations, and it can also hold the
port number for the IN and OUT instructions, but it is mostly available as a convenient place to
store data, as are all of the other general-purpose registers.

Q2 Name the flag registers in 8086 and explain their uses?

Status registers FLAGS:

It is a collection of 1-bit values which reflect the current state of the processor and the results of
recent operations. 9 of the 16 bits are used in the 8086.
Carry (bit 0): set if the last arithmetic operation ended with a leftover carry bit coming
off the left end of the result.

Parity (bit 2): reflects whether the number of 1 bits in the result of an operation is
even or odd.

0– odd, 1-even

Auxiliary Carry (bit 4): set when the result of an operation causes a carry from bit 3
to bit 4.

Zero (bit 6): set if the result of an arithmetic or logical operation is zero. After a
comparison (CMP, CMPS, or SCAS), this indicates that the values compared were
equal (since their difference was zero).

Sign (bit 7): set when the result of an arithmetic or logical operation generates a
negative result.

Trace (bit 8): determines whether or not the CPU is halted after each instruction.
When set, this puts the CPU into single-step mode.

Interrupt (bit 9): when set, interrupts are enabled. This bit should be cleared while
the processor is executing a critical section of code that should not be interrupted
(for example, when processing another interrupt).

Direction (bit 10): when clear, the string operations move from low addresses to high
(the SI and DI registers are incremented after each character). When set, the
direction is reversed (SI and DI are decremented).

Overflow (bit 11): set when the result of a signed arithmetic operation is too wide to
fit into the destination. Indicating that the signed two's-complement result would not
fit in the number of bits used for the operation.
 Q3 What are segment registers and instruction pointers?

Instruction pointer IP: It gives the address of the next instruction to be executed, relative to the
code segment. The only way to modify this is with a branch instruction.

In 8086, memory has four different types of segments. These are:

Code Segment CS – holds base location for all executable instructions in a program.
Data Segment DS – default base location for variables.
Stack Segment SS – Base location of the stack.
Extra Segment ES – additional base location for memory variables.
These registers are 16-bit in size. Each register stores the base address (starting address) of the
corresponding segment. Because the segment registers cannot store 20 bits, they only store the
upper 16 bits.

Task2:
Run the following assembly code and write down the final values in the registers:

Addition Division
MOV AX,15H MOV AX,5
ADD AX,15H MOV BX,2
Subtraction DIV BX
MOV AX,20H Increment
SUB AX,25H MOV AL,01H
Multiplication INC AL
MOV AL,25H INC AL
MOV BL,10H INC AL
MUL BL

AX BX CX DX CS IP SS SP BP SI DI DS ES
002A 0000 0006 0000 0700 011A 0700 FFFE 0000 0000 0000 0700 0700
FFFB 0000 0006 0000 0700 011A 0700 FFFE 0000 0000 0000 0700 0700
0250 0010 0006 0000 0700 011A 0700 FFFE 0000 0000 0000 0700 0700
0002 0002 0008 0001 0700 011C 0700 FFFE 0000 0000 0000 0700 0700
0004 0000 0008 0000 0700 011C 0700 FFFE 0000 0000 0000 0700 0700
Post-Lab Tasks:
Task1: Identify the difference in architecture between 8088 and 8086?

8088
S. 8086
NO. MICROPROCESSOR MICROPROCESSOR

1 The data bus is of 16 bits. The data bus is of 8 bits.

It has 3 available clock
speeds (5 MHz, 8 MHz
(8086-2) and 10 MHz (8086-
2 1)).
The memory capacity is 512
3 kB.
It has 3 available clock speeds (5
MHz, 8 MHz)
The memory capacity is
implemented as a single 1 MX 8
memory banks.

It has memory control pin It has complemented memory

4 (M/IO) signal. control pin (IO/M) signal of 8086.

It has Bank High Enable

5 (BHE) signal. It has Status Signal (SSO).
It can read or write either 8-
bit or 16-bit word at the It can read only 8-bit word at the
6 same time. same time.

Input/output voltage level is Input/output voltage level is

7 measured at 2.5 mA.
It has 6 byte instruction
8 queue.
It draws a maximum supply
9 current of 360 mA.
measured at 2.0 mA
It has 4 byte instruction queue as
it can fetch only 1 byte at a time.
It draws a maximum supply
current of 340 mA.

Task 2 Write a code in assembly to add your birthday to your birth month, multiply it to
your birth year. And display the output?

ORG 100H
MOV AX, 00H
INT 10H

MOV AX, 26
MOV BX, 7
ADD AX, BX
MOV BX, 1999
MUL BX

MOV DX, BX
MOV AX, 06H
INT 21H

RET

LAB # 8
Task:

Generate six different types of patterns using assembly language and write/attach the code
and the output from dot matrix display

EXAMPLE

ORG 1000H
MOV AL, 100000000H
OUT 1EH, AL
;
MOV AL, 11111111B
OUT 18H, AL
;
MOV AL, 11111111B
OUT 1CH, AL
;
MOV AL, 11111110B

L2:
OUT 1AH, AL
ROL AL, 1
CAL DELAY
JMP L2

DELAY:
MOV CX, 0FFFFB

T1:
LOOP T1

RET
CODE ENDS
END
Post-Lab Tasks:

Task 1 Identify the commands used in your assembly code and write down there functions?

Assembly language statements are entered one statement per line. Each statement follows the
following format −
[label] mnemonic [operands] [;comment]

Some Common Mnemonics

 Lab 9
Task1:
Find the errors in the following assembly code and run it in 8086EMU

Names: Numbers: Operands:

COUNTER1 11011 MOV AX, BL

@character 11011B MOV AL, BL
TWO WORDS 64223 MOV AH, BL
SUM_OF_DIGITS 21843D MOV i, j
$1000 1,234 MOV AL, i
2abc 1B4DH ADD 2, AX
Done? 1B4D ADD AX, 2
.TEST FFFFH
A45.28 0FFFFH

Solution:

TWO WORDS: 11011: MOV AX,BL:

Wrong Parameter as there is no Wrong Parameter as the suffix ‘b’ Wrong Parameter as the source is
space in between. is missing. of 8bit while destination is of 16
1B4D: bit.
2abc: Wrong Parameter as the suffix ‘h’ ADD 2, AX:
Wrong Parameter as it starts with is missing. Wrong Parameter as a constant
the digit.. can’t be a destination in assembly
language.
A45.28
Wrong Parameter as its not the
first character.

POSTLAB
MODEL SMALL
.STACK 10H
.CODE
A DW A2
B DW 5
SUM DB ?
.DATA
MAIN PROC
; initialize DS
MOV AX, @DATA
MOV DS, AX
; multiply the numbers
MOV AX, A
ADD B, AX
SUM, AL
; exit to DOS
MOV AX, 4C00H
INT 22H
MAIN ENDP
END MAIN

Solution:
Org 100h
TITLE PRGM1
.MODEL SMALL
.STACK 10H
. DATA
A DW A2
B DW 5
SUM DW?
ENDS
. CODE
MAIN PROC
; initialize DS
MOV AX, @DATA
MOV DS, AX
; multiply the numbers
MOV AX, A
ADD BX, AX
MUL AX
MOV AX, 4C00H
INT 21H
MAIN ENDP
END MAIN

Task1Write assembly code to display some text using correct syntax throughout

name "hi"

org 100h
jmp start ; jump over data declaration
msg: db "Hello, World!", 0Dh,0Ah, 24h
start: mov dx, msg
mov ah, 09h
int 21h
mov ah, 0
int 16h
ret
Task 2 Write assembly code to calculate power using current and resistance using correct
syntax throughout
ORG 100H
MOV AL, 2
MOV AH,3
MUL AH
MOV BL, 5
MUL BL
RET

LAB 10
Q1 Make a program that takes a character as input from the keyboard and displays it on
the console window:
Solution
.MODEL SMALL
.CODE
MOV AH, 00H
INT 16H
MOV AH, 2
MOV DL ,AL
INT 21H

Q2 Make a program that takes a string as input from the keyboard and displays it on the
console window:

Solution:
.MODEL SMALL
.STACK 10H
. DATA
Buff db 25 dup(0),10,13
1 buff EQU ($ - BUFF)
. CODE
MOV AX , @ DATA
MOV DX, AX
MOV AH, 0AH
MOV BUFF, AH
INT 21H
MOV AV, 4000H
MOV BX, 1
MOV CX, 1BUFF
MOV DX, OFFSET BUFF
INT 21H
MOV AH,4CH
INT 21H
END MAIN
Post lab:
Task 1 Write assembly code to input two numbers from console add them and display the
output on the console
SOLUTION:
DATA SEGMENT
NUM1 DB ?
NUM2 DB ?
RESULT DB ?
MSG1 DB 10,13,"ENTER FIRST NUMBER TO ADD : $"
MSG2 DB 10,13,"ENTER SECOND NUMBER TO ADD : $"
MSG3 DB 10,13,"RESULT OF ADDITION IS : $"
ENDS
CODE SEGMENT
ASSUME DS:DATA CS:CODE
START:
MOV AX,DATA
MOV DS,AX
LEA DX,MSG1
MOV AH,9
INT 21H
MOV AH,1
INT 21H
SUB AL,30H
MOV NUM1,AL
LEA DX,MSG2
MOV AH,9
INT 21H
MOV AH,1
INT 21H
SUB AL,30H
MOV NUM2,AL
ADD AL,NUM1
MOV RESULT,AL
MOV AH,0
AAA
ADD AH,30H
ADD AL,30H
MOV BX,AX
LEA DX,MSG3
MOV AH,9
INT 21H
MOV AH,2
MOV DL,BH
INT 21H
MOV AH,2
MOV DL,BL
INT 21H
MOV AH,4CH
INT 21H
ENDS
END START

Lab 11
Task 1:
While-loop in C:
while(x==1){
//Do something}
The same loop in assembler:
jmp loop1 ; Jump to condition first
cloop1 nop ; Execute the content of the loop
loop1cmp ax,1 ; Check the condition
je cloop1 ; Jump to content of the loop if met

Task 2:
Post Lab Task1
 Lab 12
Task 2:
ORG 100H
.MODEL SMALL
.STACK 100H
.DATA
NEWLINE DB 0DH,0AH,'$' ;NEW LINE
.CODE
FUN PROC
MOV CX,5
MOV BX,5
L1:
MOV CX,BX
L2:
CMP CX,0
JZ EXIT
MOV DL,1
MOV AH,02H
INT 21H
LOOP L2
DEC BX

LEA DX,NEWLINE
MOV AH,09H
INT 21H
LOOP L1
ENDP
EXIT:MOV AH,4CH
INT 21H
RET
Post Lab Task 1: