136 (IJCNS) International Journal of Computer and Network Security,

Vol. 2, No. 10, 2010

Design of CMOS Active-RC Low Pass Filter

Using 0.18 µm Technology
Dilip Singar1, D.S. Ajnar2 and Pramod Kumar Jain3
1
Department of Electronics & instrumentation engineering,
Shri G.S. Institute of technology and science
23, Park Road, Indore (M.P.)
dilip.singar@gmail.com
2
Department of Electronics & instrumentation engineering,
Shri G.S. Institute of technology and science
23, Park Road, Indore (M.P.)
dajnar@sgsits.com
3
Department of Electronics & instrumentation engineering,
Shri G.S. Institute of technology and science
23, Park Road, Indore (M.P.)
pramod22in@yahoo.co.in

Abstract: In this paper advances on analog filter design for

telecom transceivers are addressed. Portable devices require a
strong power consumption reduction to increase the battery life.
Since a considerable part of the power consumption is due to the
analog baseband filters, improved and/or novel analog filter
design approaches have to be developed. We design an active RC
filter for this application in this paper. To demonstrate the
proposed techniques, a ±0.8 V, 2-MHz second-order filter
fabricated in a conventional 0.18 µm CMOS process is
presented. The filter achieves a THD of 40 dB. The measured
power consumption for the filter alone consumes about 0.19
mW for a supply voltage of ± 0.8 V. Design and simulation of
the circuit is done in Cadence specter environment with UMC
0.18 µm CMOS process.
Keywords: Analog IC design, active RC filter, THD, op amp,
telecom transceiver
1. Introduction
The active filters are widely used in instrumentation and
communication systems. Technical evolution and market
requirements demand for high-performance fully integrated
telecom transceivers. The most popular receiver architecture
is the Direct Conversion (DC) one: for this case, the
following discussion is applied. Figure.1 shows the typical
DC receiver architecture.
The signal from the antenna is processed
by an external prefilter to reject an amount of the out-of-
band interferers. The front-end consists of LNA and a
quadrature mixer that down converts the signal. The
baseband part is composed by the low-pass filter (LPF),
variable gain amplifier (VGA) and analog to digital
converter (ADC). LPF and VGA perform the following
functions:
- The LPF selects the channel and reduces the noise and the
out-of-band interferes, relaxing ADC requirements.
- The VGA increases the in-band input signal in order to
optimize analog to digital conversion performed by the
following ADC.
Figure1. Block Diagram of Direct Conversion (DC) receiver
For example: in the UWB systems, the input signal power
are typically very low (about -40dBm) therefore it needs to
be amplified by more than a 40dB Factor [2].
The LPF can be implemented with different solutions,
depending on several reasons as:
- The power consumption minimization is strongly required
by portable devices to increase the battery life;
- Different communication standards require strongly
different analog active-RC filter’s performances in terms of
bandwidth, distortion, Noise.
2. Circuit Implementation
2.1 Architecture of Filter
Figure 2 shows the Active-RC low pass filter using the AM
biquad topology. It is the suitable filter structure needed to
achieve high filter pole frequency for a given unity
bandwidth. The biquad is the slightly modified form of the
original AM biquad. In which C2 will be omitted and a
resister will be added in parallel with C1 of the first
integrator to control Q factor. The advantage of the
modification is that it allows the adjustment of Q factor by
adjusting the value of C2 only for given value of C1. The
pole frequency is depends on the value of C1 and C2. In the
above figure four op-amp filters (so called quads) are used in
one integrated circuit. The circuit can be adjusted in a non-
interactive manner for precise filter parameter. A3 is non-
inverting op-amp amplifier and A1, A2, A4 are the inverting
 (IJCNS) International Journal of Computer and Network Security, 137
Vol. 2, No. 10, 2010

amplifier. The A1 and A3 have no dc-feedback path in Power dissipation ≤ 0.52 mW

between and converted the signal directly.Quality factor is
set by the resistor QR. PSRR(Vdd) ≥ 29dB

2.2 OP AMP Design:

Design of op-Amp: operational amplifier is very important
to get accurate result. The Op-Amp is characterized by
various parameters like open loop gain, Bandwidth, Slew
Rate, Noise and etc. The performance measures are fixed
due to design parameters such as transistors size, bias
current and etc. Transistors M8 and M9 functions as a
constant current source, and transistors M1, M2 and M3
functions as two current mirror 'pairs'. The transistors M4,
M5, M6 and M7 are the differential amplifier. Transistor
M10 is an output amplifier stage [4]. Figure 3 represents the
op amp design which is used in the filter.

Figure 2. Schematic on CMOS active-RC low pass filter

The output of a second-order low-pass filter with a very high
quality factor responds to a step input by quickly rising
above, oscillating around and eventually converging to a
steady-state value. The low pass filter gain is controlled by
R/K, varying the value of this resistor the gain can be
adjusted to our specifications of the filter. We will consider
this on the Ackerberg-mossberg circuit shown in figure 2.
The low pass output filter realizes for C1, C2 and indicated
resistors [2].
The transfer function is given by

(S) = =- =
We have chosen, as shown in figure 2 two identical
capacitors to keep with common, and have identified the Figure 3. Schematic of CMOS Op-Amp
quantities K and Q at the corresponding resistors that
determine these filter parameters. The two resistors R1 and 3. Measured Performance
R2 of the inverter are arbitrary. Let us employ a fourth op-
The active RC filter is designed and simulated in Cadence
amp as a summer, shown in the lower part of figure 2.
spectre environment with UMC 0.18-µm silicon technology.
This equation has four solutions bandwidth (BW), the two
The whole circuit is biased with a supply voltage of ± 0.8 V.
positive ones are ω1and ω2 and their difference can be
Figure 4 plots the open loop gain of filter. It shows that the
shown to be
open loop gain is found to be 40 dB with 3 dB bandwidth of
BW= ω2 – ω1 = ω0 / (Q (1) 2MHz. It has unity gain frequency of 80 MHz. With the
Let us determine the value of Q required meeting the sweep of ± 0.8 V of supply the Dc sweep response represents
specified 1/q over a band ∆f that the offset voltage is reduced to 5 mV. Figure 5 plot the
change in power supply rejection ratio (PSRR) with
(2) frequency.It is found that the PSRR of filter is 28 dB.
The specifications for the desired filter are given in the table
I.
Table 1: Specification Results

Experimental Value
Results
Open loop Gain ≥ 23 dB
3dB frequency ≥ 1.5 MHz
Input referred ≤ 160
noise(1KHz) nV/√Hz
138 (IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 10, 2010

The third order harmonic distortion plot is shown in figure

7.THD performance versus different peak-to-peak
magnitudes at the low-pass output of the main filter for two
different frequencies (5 and 100 kHz). Less than -40 dBc of
THD can be achieved for a peak-to-peak output voltage. The
final output results of active RC filter with comparisions are
represented in table 2.

Figure 4. Simulation result of Gain and phase response

Figure 7 Simulation result of Total harmonic distortion

Table 2: SUMMARY OF EXPERIMENTAL RESULTS

Figure 5. Simulation result of PSRR Response Experimental This Ref [2]

If a voltage source inserted in series with the input source Results Work
generates the input referred noise. Input referred noise at Open loop Gain 40 dB 23dB
1KHz has been found 62.08 nV/sqrt (Hz), the input referred 3dB frequency 2 MHz 1.5MHz
plot is shown in figure 6. Since the first-order components Unity Gain 80 MHz 50 MHz
grow linearly and third-order components grow cubically, Frequency
They eventually intercept as the input power Input referred 62 160 nV/√Hz
level increases. The IP3 is defined as the cross point of the
noise(1KHz) nV/√Hz
power for the 1st order tones, w1 and w2, and the power
for the 3rd order tones, 2 w1 and w2 & two w2 and w1 on Output referred 30 120 nV/√Hz
the load side. The input intercept point (IIP3) was found to noise (10KHz) nV/√Hz
be 0.448 dBm.
Power dissipation 0.19 0.52 mW
mW
Input Offset 5.34 8 mV
Voltage mV
PSRR(Vdd) 29 dB 29 dB
Total harmonic 40 dBm 60 dBm
distortion

4. Conclusion
In this design, a low-voltage CMOS active RC low pass
filter is designed using a Akerberg Mossberg topology. The
Figure 6. Simulation result of Input referred noise response proposed techniques can be used to design low-voltage and
 (IJCNS) International Journal of Computer and Network Security, 139
Vol. 2, No. 10, 2010

low-power active RC low pass filter in a standard CMOS
process. To demonstrate the proposed techniques, a ±0.8V
and 2-MHz second-order filter implemented in a standard
0.18µm CMOS process.
profession since 1988. He is now working as Reader in
Department of Electronics & Instrumentation Engineering,
S.G.S.I.T.S. Indore India. His interested field of research is analog
circuit design.

Reference

[1] A. M. Durham, W. Redman-White, and J. B. Hughes,

“High linearity Continuous -time filters in 5-V VLSI
CMOS,” IEEE Journal of Solid-State Circuits, volume
27, page no. 1270–1276 Sept.1992.
[2] M. De Matteis1, S. D Amico A.Baschirotto “Advanced
Analog Filters for Telecomm-unications’’, IEEE Journal
of Solid-State Circuits, volume 65, page no. 06–12, Sept.
2008.
[3] H. Huang and E. K. F. Lee, “Design of low – voltage
CMOS continuous time filter with on chip automatic
tuning ,” IEEE Journal of Solid-State Circuits, volume
36 page no. 1168–1177 Aug. 2005.
[4] Eri Prasetyo, Dominique Ginhac Michel Paindavoine,’’
Design and Implementation a 8 bits Pipeline Analog to
Digital Converter in the Technology 0.6 um CMOS
Process’’. Makalah ada di prosiding ISSM05, Paris, 30th
September – 1st October 2005.
[5] AKERBERG, D:' Comparison of method for active RC
telecommunication Theory, Royal Institute Technology,
Stockholm, Sweden, technical report 19, June 1999

Authors Profile

Dilip Singar received the B.E. degree in

Electronics and Communication Engineering
from Rajiv Gandhi Technical University
Bhopal, india in 2008 and M.Tech in
Microelectronics and VLSI Design from
S.G.S.I.T.S. Indore, India in 2010. Recently
he is working with analog filter design and
analysis.

D.S.Ajnar received the B.E. degree in

Electronics and Communication Engineering
from D.A.V.V.University, India in 1993 and
M.E. Degree in Digital Techniques &
Instrumentation Engineering from Rajiv
Gandhi Technical University Bhopal, India in
2000. He has been teaching and in research
profession since 1995. He is now working as
Reader in Department of Electronics &
Instrumentation Engineering, S.G.S.I.T.S, and Indore, India. His
interest of research is in Designing of analog filter and Current-
Conveyor.

P.K.Jain received the B.E. degree in

Electronics and communication Engineering
from D.A.V.V. University, India in 1987 and
M.E. Degree in Digital Techniques &
Instrumentation Engineering from Rajiv
Ghandhi Technical University Bhopal, India in
1993. He has been teaching and in research