IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO.

5, MAY 1993 289

A Wide Range Differential Difference

Amplifier: A Basic Block for Analog
Signal Processing in MOS Technology
Shu-Chuan Huang, Student Member, Mohammed Ismail, Senior Member, IEEE, and Seyed R. Zarabadi, Member, IEEE

Abstract-This paper presents a CMOS implementation of a

wide input range differential difference amplifier (DDA) using a
V-I converter with large signal handling capability. It introduces
the wide range DDA as a basic building block for continuous-time
analog signal processing systems. The basic features of the DDA
are verified experimentally using a 2-pm CMOS process MOSIS
chip. The paper shows that it is generally possible to develop
DDA-based analog circuits, such as an adderlsubtractor and
Fig. 1. Symbol of the DDA
differential integrators, with almost infinite input impedances,
low component count and without matching requirements of
componentddevices external to the DDA. DDA-based circuits
such as amplifiers, a MOS grounded resistor, four quadrant mul-
tipliers and amplitude modulators are presented. Such circuits
constitute basic building blocks in modern analog VLSI signal vo
and information processing systems. Moreover, the applications
of the DDA in the implementation of frequency selective circuits,
e.g., resonator and state-variable second-order filters are also
given. All proposed circuits and design techniques are experi- Fig. 2. Block diagram of the DDA.
mentally verified and demonstrate that DDA-based circuits offer
a competitive design choice to op-amp-based circuits.
where A , is the open-loop gain of the DDA. When a negative
feedback is introduced, i.e., to V,,, and/or V,,, which appear in
I. INTRODUCTION (1 ) with a negative sign, the following expression is obtained:

T HE DIFFERENTIAL difference amplifier (DDA), whose

symbol is shown in Fig. 1, is an emerging CMOS analog
building block [1]-[3]. It has recently been used in a limited
number of applications including the implementation of fully
differential MOS switched-capacitor filters [ 11, common-mode
detection [4], [5], telephone line adaptation [6] and continuous-
time filters [4], [7], [8], [9]. As discussed in [2], the DDA is an
extension to the concept of the op-amp. The main difference
is that instead of two single-ended inputs as is the case in
op-amps, it has two differential input ports ( lip, - V,,,) and
(Vn, - Vnn).Therefore, the output of the DDA can be written
as
Manuscript received June IS, 1992; revised January 7, 1993. Parts of
this work were presented at the 10th Norchip Seminar, Helsinki, Finland,
Nov. 1992, and included in the Seminar’s proceedings, pp. 9-14. This
work was supported in part by NSF Grant MIP-8896244, by Semiconductor
Research Corporation contracts 90-DJ-066 and 91-DJ-066, and in part by the
Norwegian NTNF, SINTEF, and Nordic VLSI. This paper was recommended
by Associate Editor D. J. Allstot.
S.-C. Huang and M. Ismail are with the Solid-State Microelectronics
Laboratory, Dept. of Electrical Engineering, Ohio State University, Columbus,
OH 43210-1272.
S. R. Zarabadi was with Ohio State University. He is now at Delco
Electronics Corp., Kokomo, IN 46904-900s.
IEEE Log Number 9208315.
1057-7130/93$03.00 0 1993 IEEE
V,, - V,,, = V,, - V,, with A , -+ cc. (2)
For a finite open-loop gain A,. the difference between the
two differential voltages increases as A , decreases. Therefore,
the open-loop gain should be as large as possible in order to
achieve high-performance operation. According to (2), some
interesting circuits can be realized with the DDA and without
using components [2] or matched components [8] external to
the DDA, as will be shown in Section 111.
In practice, the DDA may be implemented as shown in Fig.
2 [2], where two V-I converters (the two input ports of the
DDA) convert the two differential voltages into currents which
are then subtracted, converted into voltage and amplified.
From (2), one can see that although the difference of the
two differential input voltages is virtually zero, the single-
ended voltages VPpand V,, (V& and Vn,) do not have
the property of the virtual short circuit, which exists in op-
amp circuits. That makes the DDA in some sense similar to
the operational transconductance amplifier (OTA), and thus a
linear V-I converter with a wide input range is needed for
large signal applications.
This paper presents a CMOS architecture of a wide input
range DDA and introduces it as a basic block in modern
analog signal and information processing applications. The
design of a wide input range DDA achieved by using a
~

290 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO. 5 , MAY 1993

tunable linear CMOS V-I converter with large signal handling in the common-source differential pair can be obtained by
capability will be presented in the next section. The circuit applying the simple square law equation:
was fabricated in a MOSIS 2-pm p-well process, and some
basic parameters extracted from the test chips will be given. Id = I1 - 1’2
In Section 111, application examples of the DDA in the
design of an adder/subtractor, a MOS grounded resistor and
PP
-[(-vs1
= 2 +v +vTp)* - (-vjc2 +vc +VTP)~]
a four-quadrant multiplier will be discussed, and experimental
results will be included. Frequency selective circuits are also
- PP
- - Y(vz1- vz2)(-vxI - vz2 + 2vc f 2vTp) (5)
presented. Differential integrators as well as compensation
where & = ppCozW/Land is the threshold voltage of
methods for phase errors, due to the frequency-dependence of
the PMOS transistors. Similarly, the differential current of the
the open-loop gain, will be discussed in Section IV. Finally,
common-gate differential pair is given as
design examples of DDA-based second-order filters are given.

11. DESIGNOF THE DDA

Id = 11- 12 = -( v,1 - ~ Z Z ()v,i
PP
2
+ v,2 - +
2v 2 v ~ p ) (6)
.

As mentioned in Section I, the DDA can be partitioned into
two part-an input stage formed by two V-I converters and
a gain stage. The simplest way to implement the DDA is to
use two differential pairs to realize the V-I converters [2]. One
can recall that the differential current I d of a differential pair
biased by a constant current source I , is given by
where V , is the input differential voltage and /3 = pC,,W/L.
where ,LL is the mobility, CO, is the gate oxide capacitance
per unit area and W / L is the width to length ratio of the
input devices. For linear conversion, I d should be proportional
to v
d only; however, the existence of the square-root term
results in nonlinearity in I d : which is defined as the percent
deviation from the ideal value of g m v d . where ,y, is the
transconductance at v d = 0. That is,
(4)
According to the above equations, linear relations between
(V,l - Vz2) and (11 - 12) can be achieved if V,1 V,2 is+
constant (class AB [I I]) or alternatively if VZl and V,Z are
driven in a balanced mode. That is, V,1 = VCM ux and +
V,2 = Vcnf - 7 l x . where V c n ~ is a constant representing the
common-mode input component. However, balanced inputs
are usually not readily available; therefore, the inputs of the
V-I converter should be converted into balanced signals. The
circuit used to create balanced signals is shown in Fig. 4 so
that its outputs (Vzl and Vz2)are used as inputs to the PMOS
differential pairs. Ml-M4 ( P d ) and M5-M8 (,&) are matched
respectively and M11 and M12 are matched simple current
sinks biased by Vb3. All the transistors are operating in the
saturation region with their sources and substrates connected
together to reduce distortion, or otherwise the body effect
has to be taken into account in the analysis. Writing down
the current equations at nodes V,, and V,p, one can obtain
expressions for (V,, - Vz2) and (V,l +
V,z). The current
equations give

Due to the virtual short property in op-amps, the differential

where v ~ sand
, VGs.2are the gate-source voltages of Ml(M3)
pair is always operating at Vd z 0 and therefore the transcon-
and M4(M2), respectively, and VT, is the threshold voltage of
ductance of the differential pair is approximately g n L . Unlike
the NMOS transistors. V,, and V,, can then be expressed as
the case in op-amps, the two inputs of the V-I converter in the
DDA are not virtually shorted, and the differential pairs are not
operating at a fixed v d . As v
d increases, the transconductance (9)
of the differential pair decreases, and becomes zero for 1 Vd I 2
Jm. The reduction of the transconductance due to the
nonlinearity of the V-I converter may significantly degrade
the open-loop gain of the DDA, which makes (2) no longer
valid. Therefore, V-I converters with wide linear input ranges Therefore,
are essential for the design of a wide input range DDA.
There are several linear V-I converters in the literature [lo],
[ 111 and they all can be incorporated to the design of the
DDA. Here we propose a linear CMOS V-I converter whose
transconductance can be tuned by a bias voltage. To realize the
linear V-I converter, PMOS transistors operating in the satura-
tion region configured as a common-source or a common-gate
differential pair as shown in Fig. 3 are considered first. The where vd = Vi - V2 = V ~ s -
l V G Sand
~ V G S ~ VGSZ= +
differential current of the two transistors (assumed matched) 2v& + J-V,” + (4I/,&) for the simple differential pair
HUANG el al.: WIDE RANGE DIFFERENTIAL DIFFERENCE AMPLIFIER
vxl-l * VC
T
I1 I2 -I vx2
Fig. 3. PMOS differential pairs. (a) Common source. (b) Common gate.
composed by M I and M4 (M3 and M2). Since transistors
M5-M8 are matched and conduct the same amount of current,
By substituting (11)-(14) into (3,i.e., using the outputs of
Fig. 4, V,l and Vz2, as inputs of Fig. 3(a), the differential
current of the common-source differential pair is obtained as
The nonlinearity of the differential current is due to the
nonlinear term J m J - V : + (41//&), which can be min-
imized by properly selecting a small ratio of & ( ( W / L ) d )
and /3u((W/L)u).For instance, if we let V, = V d d = 5
V, V T ~ = -0.73 V, VT, = 1.068 V, P d = 3 0 p A N 2 and
I = 125 PA, the value of J-V," +
(41//3d) varies from 4.082
V to 3.221 V with V d increasing from 0 to 2.5 V. Also, the
+ +
constant term V k = V, - V d d 2VTn VT, = 1.406 V, and
the variation of the nonlinear term for Jm-
= 0.134 is
AV = 0.134 x (4.082 - 3.227) = 0.115 V, which is rather
small compared to V k . That is, the nonlinearity is negligible,
and the V-I converter is considered to be practically linear. For
2.5-V differential input, the THD calculated by SPICE using
the above parameters and level 2 transistor models is 0.23%.
On the other hand, a simple common-source PMOS differential
pair, having the same p p used above and biased for minimum
distortion (using a single MOSFET sourcing 3.565 mA), can
operate at only 0.54 V for the same THD level of 0.23%.
The same NMOS architecture proposed to create balanced
signals is used equally well with the PMOS common-gate
differential pair shown in Fig. 3(b). The resultant CMOS
circuit shown in Fig. 5 should have a linear performance
criteria similar to the CMOS circuit obtained by combining
Fig. 3(a) and Fig. 4, and should exhibit superior high frequency
performance due to the common-source common-gate (no
Miller effects) folded-cascode circuit in the signal path. Since
V,, and V,, are now sinking current into the PMOS transis-
tors, the analysis is not as simple as that performed earlier.
Writing down the current equations at nodes V,, and V k 2 ,
291
Vdd
T
V
. s
Fig. 4. Circuit generating balanced signals.
Vdd
hi5
t I M6
' VI1 VZY+
V-
Fig. 5. Linear CMOS V-I converter using common-gate differential pair.
one can derive an approximate expression for the differential
current as demonstrated in Appendix A with d m
assumed
small. The current is given by
where uo and al are dependent on the bias voltages and tran-
sistor parameters, and their expressions are given in Appendix
A. The transconductance of the V-I converter is designed as
before by properly sizing M5-Ml0 and is tuned by the bias
voltage V,. With V, = 0 and Vd = 312.5 V, the total harmonic
distortion of the circuit obtained from SPICE is 0.24% with
the same device sizes used in the common-source circuit (Fig.
3(a) and 4 combined).
The SPICE results obtained have taken into account the
mobility degradation effect, and Ucxp is 0.1428 and 0.2152
for N- and P-MOSFET's, respectively, where the mobility p 3 ,
taking into account the degradation in the surface mobility
p o , is given by [ 141
. rT
With Uexp= 0, p, = po and no mobility degradation effect is
involved. The results with different Uexp are shown in Table I,
where the differential input amplitude is 2.5 V. It is interesting
to note from the table that mobility degradation in the NMOS
292 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO. 5 , MAY 1993

VU
*

1
V I

Fig 6 Wide input range DDA circuit

TABLE I TABLE I1
OF THD WITH I,,,,
VARIATIONS DEVICESIZESOF THE DDA
NMOE‘MOS 0.2152 0.0 @
Device Names wfL (Pm)
0.14286 0.239% 0.1S0% MAl.MA2.MA3. I NMOS I 30150
0.0 1.09% 1.070% MA4, MBI, MB2,

M A 5 , MA6, MA7, NMOS I0013

circuit improves the linearity. This is due to the fact that MB5, MB6,
MB7, MB8
as the effect becomes more significant, the nonlinear terms
MA9, MA10, MB9, PMOS 10014
become more negligible. However, the mobility degradation MB
effect of the PMOSFET’s distorts the output, because higher M A I MAl2, NMOS 40014
order terms are introduced in ( 5 ) and (6). MBI I . MB12
The overall DDA circuit using the common-gate V-I con- MI, M2, M3, M4 PMOS 30017
verter is shown in Fig. 6, where M1-M10 form a cascode M5, M6, M9, M I 0 NMOS 20017
gain stage, and V b l and V b 2 are the bias voltages. A matched M7, MX NMOS 37/40

otherwise (1) has to be rewritten more generally as [3]

V = Ap(Vpp- Vpn)- &(V& - VI,). (18)

However, the focus here is on the case: A, = A,, = A,.
Therefore, special layout techniques are required to improve
matching. Also, V, of each converter can be used as a tuning
parameter to match the transconductances.
The frequency-dependent output voltage of the DDA can
be approximated by

where p is the dominant pole due to the load capacitance and

output resistance of the DDA. A, is the dc open-loop gain,
Fig. 7. Photomicrograph of 2 DDA’s, a part of an array of 6 DDA’s on a
and is approximately given by Tiny MOSIS chip.

AO = ggm8{ [gm4Tds4Tds2] I ( [ , ~ m 6 ~ d s 6 ~ d s 8 ] ) / , ~ r r l l(20)

O
where g is the transconductance of the V-I converters, and gr7,
and T d s are the small signal parameters of the MOS transistors.
The CMRR can be obtained in a manner similar to that used
with op-amps as discussed in [ 2 ] .
The DDA has been laid out and fabricated in a 2-pm P-well
MOSIS CMOS process with the device sizes shown in Table
11. A common centroid layout technique was used to improve
the matching of the devices incorporated in the input stages.
The photomicrograph of 2 DDA’s in a MOSIS Tiny test chip
containing an array of six identical DDA’s is shown in Fig. 7,
and the layout area is about 0.58 mm2 for each DDA. Some
of the DDA parameters with power supplies f 5 V and V, = 0
V are summarized in Table 111, where the DDA was measured
by configuring it as an op-amp. The open-loop output noise
measurements with zero inputs and power supplies on and off,
respectively, are shown in Fig. 8. With the use of the linear
V-I converter, the input range of the DDA is now extended!
This will be experimentally illustrated in the discussion of its
applications.
HUANG et al.: WIDE RANGE DIFFERENTIAL DIFFERENCE AMPLIFIER 293

"+%h
TABLE 111
SUMMARY
OF THE DDA PARAMETERS

Parameter Experimental Results

dc eain 63 dB v2+ vo
GR 1 MHz*
CMRR 69 dB**
Fig 9 DDA adderlsubtractor
CMR - 3 . j \. - 4.0 1.
OutDut swing - 3 . 1. - 3.5 \.
Slew rate 2.5 Vlris
~~
Settling time
~
1.6 L I S ( I Vp-p) 4 , .

Power Consumption 13.46 mW*** v. v.

*measured also by SPICE with a simple buffer (Cl, =21.8 pF)
**measured at low frequency
***measured by SPICE

4 JOO m v i e l v
o l f s e l 0 GO0 V

Fig. 10. Experimental results of the DDA inverter.

I
I
L;
_.,__ I
,
I i I

50K lDOK
Frequency (Hz)

Fig 8 Noi\e measurements of the DDA

111. DDA-BASED A D D E ~ ~ U B T R A C T O R ,
GROUNDED RESISTORAND MULTIPLER
In this section we present simple DDA-based circuits that 40
D 05 1 15 2 25 3 35
I
4
are ideally frequency-independent. Basic circuits such as an
Vm@ut-pl*) 0
adderhbtractor, a MOS voltage controlled grounded resistor
and a four-quadrant multiplier/modulator are discussed and Fig I I Total harmonlc distortion curves of the DDA inverter
experimental results will also be given to verify the con-
cepts. These basic circuits find important applications in both
traditional analog signal processing and modem information
processing in analog VLSI 1121, [131.
Adder/Subtractor: By applying ( 2 ) with Vi,] = TI:+. V,, =
V-, V,, = V2+ and KLp= V, (negative feedback) as shown
in Fig. 9, the output of the DDA circuit is given by

v, = VI+ + v2+ - v-. (21)

Note that not only are no additional components needed, -2 50000 i s 0 00000 5
500 u s / a l v
2 50000 I t

but high input impedances are also achieved. Some special

functions can therefore be realized by this circuit. For ex-
ample, with VI+ and Vz+ grounded, the circuit becomes a
voltage inverter. The experimental result with a I-V amplitude
sinusoidal input at 1 KHz is shown in Fig. IO. The THD
of the inverter obtained both from SPICE simulations and
experiments are plotted in Fig, 11, where the differences
between the simulation and experimental results are mostly
due to the distortion of the sinusoidal input generated by the
signal generator. It can be found that the THD is less than 1%
Fig. 12. Experimental results of the DDA doubler.
with 4- Vpeak-prak input due to the use of the linear V-
I converter. A voltage doubler, a basic block in a pipeline
implementation of an algorithmic A/D converter [14], can
also be realized by connecting VI+and Vz+ as the input and
grounding the V- node. The experimental result is shown in
Fig. 12. In addition, a level shifter and a voltage subtractor
can be implemented by the same architecture.
294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:
Vl.
Fig. 13. DDA grounded resistor,
VG
4 ov
3.5v
3.0V
2.5V
2 ov
.o
Fig. 14. Experimental results of the DDA grounded resistors.
MOS Grounded Resistor: An equivalent grounded resistor
can be realized by a MOS transistor operating in the triode
region with its drain and source voltages out of phase [15] as
shown in Fig. 13(a). Using the simple drain current equation
for an NMOS enhancement transistor in the triode region, one
may obtain the current 1,:which is linearly dependent on V,
and is given by
where is the transconductance parameter and VT is the
threshold voltage of the transistor. The complete circuit of
this grounded resistor is shown in Fig. 13(b), where the DDA
inverter is connected between the drain and the source nodes
of the transistor. The equivalent resistance R is given by
Experimental results of the voltage-controlled resistor are
shown in Fig. 14, where the transistor in the circuit is imple-
mented by two NMOS transistors connected in series (in the
same RCA-CD4007UB chip) and configured with their gates
connected, their sources and substrates connected together and
their drains being the new drain and source of the composite
device. This implementation reduces the body effect and
allows the use of practical values for VGto tune R. The /3 and
VT of the composite transistor were measured by an HP4145B
and were found to be approximately 370 PAN' and 1.5 V,
respectively.
ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO. 5 , MAY 1993
vc
vo
Fig. 15. DDA-based multiplication/modulation cell
MultiplicatiodModulation Cell: A four-quadrant multipli-
cation/modulation cell is realized using a circuit concept
similar to that of the linear grounded resistor and is shown
in Fig. 15, where Vhf is a dc bias and U, is an ac signal.
Due to the virtual short property between the two differential
input ports of the DDA with negative feedback, we have
V,, = -Vc. The current I is therefore linear and given by
2 p ( V%f+,U, - VT)V,with the transistor operating in the triode
region, where and VT are the transconductance parameter
and the threshold voltage of the transistor, respectively. As a
result, the output of the cell is given by
v, = -v, - 2pR(v\f + 21, - VT)V
= -[1+ 2PR(VM - VT)]
+
where V,,+ii, 2 I V, I VT for a NMOS transistor. Recall that
an amplitude modulated (AM) waveform can be expressed by
d)AM(t) = A(1 +mfm(l))coswct (25)
where A is a dc signal and f m ( t ) and cos w,t are the mod-
ulating and carrier signals, respectively. m is the modulation
index, where m 5 1 is required for demodulation using an
envelope detector. Comparing (24) and (25), one can see that
11, operates as the modulating signal and V, as the carrier
signal, and thus an AM signal can be generated by the circuit.
Fig. 16 shows the measurement of V, with U, (100 Hz and
amplitude 1 V), V, (not shown with 1 KHz and amplitude 1
V) and R = 220R. The transistor in the circuit is built by a
series combination of 2 SK9 160 depletion transistors (which
have their sources connected to the bulks) with their gates
connected to form a composite device similar to that used
in the grounded resistor. The depletion mode transistors were
chosen to simplify the experiment since they are normally
on (no dc component, V,,, is required). It can be seen from
Fig. 16 that the envelope of the output is proportional to the
modulating signal 71,.
To implement a threshold-voltage-independent multiplier,
the circuit shown in Fig. 17 is developed, and the output is
given as
v, = 2gR(v,l - Kn2)Vc (26)
where M1 and M2 are assumed matched. One of the inputs,
V, = Vml - Vm2, and the output are differential. If a
single-ended output is desired, a differential-to-single-ended
converter is easily implemented by the DDA in Fig. 9 with
HUANG et al.: WIDE RANGE DIFFERENTIAL DIFFERENCE AMPLIFIER
Ac rurlnlng
,- I 1
. K
-10 onoc ss 0 ooow s 10 0000 m s
2 00 n s / d i b
Fig. 16 Experimental results of the DDA modulation cell
Vml 11 R
U+1/ -
I
Fig. 17. Threshold-independent four-quadrant multiplier
either VI+ and VZ+grounded (see (21)). Programmable all-
MOS implementations of the circuits in Fig. 15 and 17 are
easily achieved using voltage-controlled floating MOS resis-
tors to replace R. e.g., the MOS floating resistor developed
in [16]. In this case the output V, is programmed by the dc
voltage controlling R.
IV. DDA-BASEDFREQUENCY-
SELECTIVE
CIRCUITS
Differential integrators are key components in many
frequency-selective analog systems such as filters and
oscillators. There are several ways to realize continuous-
time differential integrators by using op-amps as basic blocks
[ 171-[22]. However, these differential integrators whether
implemented using discrete RC components or in monolithic
form suffer from low input impedances and R. W / L . and
C component-matching requirements, needed for creating
differential inputs. Mismatch in these components leads to
phase and magnitude errors [17] and increased harmonic
distortion particularly in monolithic implementations where
matching is essential for nonlinearity cancellation [ 191-[22].
In contrast, the DDA compares two differential voltages
instead of single-ended voltages, and therefore it would lend
itself naturally to the implementation of CMOS differential
integrators. Fig. 18 shows two possible ways to realize lossless
differential integrators (excluding R,) with DDA’s. Since the
inputs of these two circuits are directly the inputs of the
DDA’s (gates of MO$ transistors) the DDA-based differential
integrators have high input impedances. In addition, only a
single resistor and a single capacitor are used; hence, there are
no passive component matching requirements. The output of
the two circuits found by using (2) is identical and is given
295
h
1 500 I V / d l ” v2+ -\
of1se1 -35 00 mV
I 000 1 OL
- Vm L 2 I I I L A A---’
4 500 n V / d i r I I
ofrset -35 00 V.
I 000 I IC
Fig, 18. DDA-based differential integrators
by (assuming ideal DDA’s)
vo T T r r
+ VI - vz
v,= ___
sRC ‘
A lossy integrator can be achieved by parallelling a resistor
R, with the capacitor in the lossless integrator. The resultant
output is
We see that the two integrator circuits perform the same
function, but the integrator in Fig. 18(b), or simply integrator
(b) employs an extra DDA but uses a grounded resistor in its
lossless implementation. Grounded resistors are much easier
and simpler to be implemented by MOS circuit techniques than
floating resistors. This second DDA also functions as a buffer
stage, where the output impedance of the DDA used is small.
The integrator in Fig. 18(a), integrator (a), on the other hand,
must drive a high input impedance node in order to maintain
proper operation when cascaded. Fortunately, if the output is
directly connected to the input of anothr DDA, no bufer stage
is used. However, the parasitic capacitances associated with
the input of the latter DDA may result in variations in the
integrator time constant, which should be incorporated in the
design process.
With R = 100KR and C = 2.2 nF, the measured ac
response of the DDA differential integrator (a) is shown in
Fig. 19, where a straight line can be found within a certain
range, which is limited by the frequency response of the
DDA designed. With a square wave used as the input, the
measured output is a triangular wave, which is demonstrated
in Fig. 20 with I-V amplitude 1-KHz input signal. When the
resistor is replaced by the voltage-controlled all-MOS floating
resistor developed in [ 161, the triangular wave amplitude is
programmed as shown in Fig. 21 by changing the control
voltage, V,. of the MOS resistor.
Similar to op-amp-based integrators, finite gain-bandwidth
(GB) also results in excess phase lag in DDA-based integra-
tors, which causes Q-enhancement of the response of filters
built by these integrators. If the DDA’s frequency-dependent
296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO. 5 , MAY 1993

I ' *

Fig. 19. Frequency response of the DDA integrator. Fig. 22. DDA integrators with phase lag compensation.

-___- - - -- -
1
.. - - - - - __- ~f --- - Y">C The errors caused by the finite GB of the DDA's are
I U'IU 1 a.

I---- s 92

GB1 GB~w,
&(s) = L3

l+L+-+-
GBI G'L, G L p (
If-
:GI) +-G B5.2I G B ~
for integrator (b). (32)
Fig. 20. Output response of the DDA-RC integrator with a square wave
input. First, integrator (a) is considered. According to E,(s). a
negative parasitic pole in the s plane (phase lag) is introduced
by the nonideal open-loop gain. To circumvent this problem,
the same techniques used in op-amp-based integrators, i.e.,
passive or active compensation [22], apply to those of the
DDA as well. Two possible passive approaches are shown in
Fig. 22 to compensate for the finite GB effect of integrator (a).
Let w, = 1/R,C (w,= l/RC, in compensation circuit (b)).
The resultant output of the nonideal integrators is
w, s
~ v, -
-
1_
x-
GB _
G+GB . (33)
VI - V2 +
.sRC W , w, w,(w, GB) s+ +-
'-1 4 8 46 -04 0 2 0 02 04 06 08 1
GB(w,+w,) GB
1 (.Dc) x10 3
The phase & ( U ) at frequency w of the error term can easily
Fig 21 Programmable outputs ot dn all-MOS DDA integrator be found as

open-loop gain is approximated by .4(s) = G B / s . the non-

ideal transfer functions of the two differential integrators can
be found as follows, where w, = l/RC. For integrator (a), Therefore, the phase error 4,,could be minimized by tuning
R,. or C, such that
w, = GB. (35)

and for integrator (b) with A l ( s ) = G B l / s and A ~ ( S=) Note that R, in Fig. 22(a) can be implemented by a single
GB2 / S . MOSFET operating in the triode region. Its small signal
channel resistance, which is controlled by the gate voltage,
is linear since the ac voltage across its drain-source terminals
is practically very small and is not going to affect the linearity
S S2
of the integrator.
Similar techniques are also used to compensate for the phase
error of integrator (b). However, since & ( s ) has two zeros
(one positive and one negative) and two negative poles, the
HU.4NG rf al.: WIDE RANGE DIFFERENTIAL DIFFERENCE AMPLIFIER 291

compensation methods (adding R , or C,) cannot fully correct

Rl
the phase error throughout the entire frequency range. It will
be shown that the operating range is limited by the location
vi*
of the zeros. With compensation, the overall transfer function
(assuming GB1 = GBp = G B ) is given as
&

Fig. 23. Op-amp-based resonator filter.

w,
- x-
GB
( :::>+
GB 1 + -
w~ G B
. fwc
I -
__--
GB2

s WO

\
[++ &)
1+-

1+-
w,
WO

1
(1 + &)
Fig. 24.
I

DDA-based resonator filter.

To minimize the phase error, the two zeros must have the
same absolute value (*w2).That is, the first-order s-term of
the numerator is zero,
WO WO
= 0. (37)
w, GB
Therefore,
w, = G B . (38)
The values of the compensating time constants are the same
as those used in integrator (a). However, due to the two zeros
(located at * w Z ) . the slope of the magnitude response is
shifted from -20 dBIdecade to 20 dB/decade at frequencies
higher than w,. With compensation, the range of operation of
Fig. 25. Frequency response of the resonator filter with R I = 6'2 = X:r =
integrator (b) is then limited to a frequency U ? . where 100I<C2 and ('1 = C, = 2.2 nF.

where w,,= 1/JR1R2C1C2and (2 = R 3 J W . To

simplify the design, let R I = R2 = R and = G2 = C.
4.1. DDA-Based Filters As a result,
In system level applications, DDA-based filters can be 1
built by using the basic cells discussed in previous sections. w,, = ~

Two examples, a state-variable filter and a resonator filter
will be developed and compared with their op-amp-based
counterparts.
Resonator Jilter: An op-amp-based configuration of a res-
onator filter is composed by a lossy integrator, a lossless
integrator, and an inverter, as shown in Fig. 23 [ 181. A DDA-
based resonator is developed as shown in Fig. 24 using the
integrator of Fig. 18(a) as a basic block. Note that the DDA
circuit needs only two DDA's to build the filter, a lossy
integrator and a lossless integrator. The function of the inverter
in Fig. 23 is implemented by exploiting the differential feature
of the DDA. If the DDA's are assumed to be ideal, the transfer
function of the bandpass and low-pass outputs are given by
!
i
RC
(2 = R.J/R. (43)
Therefore, high C) can be achieved by increasing the R3/R
ratio. Infinite C? (jw-axis poles) is achieved by disconnecting
RJ. With R I = R2 = R3 = 100KR and C1 = C2 = 2.2 nF,
the resultant measured outputs are shown in Fig. 25, where
the curves obtained by (40) and (41) are also shown. A test
chip containing an array of 6 DDA's is used. The passive
components were connected off-chip. By increasing R3 to 1
M R , Q is increased 10 times; the results are shown in Fig.
26.
State-variable Jilter: A state-variable filter [ 181, [22] real-
ized by op-amps is shown in Fig. 27, where 1 f ~ p . v and ~ ~ .
V L are ~ the outputs of the high-pass, the bandpass, and the
low-pass functions, respectively. The DDA counterpart shown
in Fig. 28 is achieved by converting the op-amp building
blocks into the corresponding DDA-based circuits. The ideal
transfer functions of the filter are given below.
298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11:
F~T-Y (Hz)
Fig. 26. Frequency response of the resonator filter with R I = R2 = 100 KR.
R
VBP
7+r
Fig. 27. Op-amp-based state-variable filter.
Fig. 28. DDA-based state-variable filter.
S state-variable second-order filters, leap-frog ladder high-order
1 [ 161 and must use proper automatic tuning to compensate for
where w, = 1/JR1R2C1C2 and Q = J R ~ C I / R ~ CThe ~.
experimental results with RI = R2 = 100KR and C1 =
C2 = 2.2 nF are shown in Fig. 29. With R I changed to 1
MO, the responses are given in Fig. 30, in which it is seen
that the gain at resonance (wn)of the bandpass output, which
is independent of R I , remains almost unchanged.
According to the above two examples, one may observe that
the DDA-based filters are simpler than those of the op-amp.
High input impedances and minimum number of resistors are
achieved in DDA-based filters. However, a drawback of these
filters is the fact that the filter outputs (except for VHPin Fig.
28) are not taken at an amplifier output which may require the
use of a buffer stage, or altematively the differential integrator
ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 40, NO. 5, MAY 1993
Fig. 29. Frequency response of the state-variable filter with R I = R.L =
1 0 0 K R and C1 = C2 = 2 . 2 nF.
F"Y (Hz)
Fig 30 Frequency response of the state-variable filter with R1 = 1hfn.
R L = 100 hfl. and C1 = CL = 2 . 2 nF.
of Fig. 18(b) as a basic block. In addition to resonator and
filters can also be built by DDA integrators in a straightforward
manner [8], [9]. All-MOS monolithic implementations of these
filters will make use of MOS voltage-controlled resistors [ 151,
random process variations [23].
V. CONCLUSION
A CMOS DDA with a wide input range has been proposed.
It is shown that the input range of the DDA is widened by
the use of a simple linear (class AB) V-I converter with large
signal handling capability. Applications of the DDA in analog
signal and information processing have also been discussed at
both the circuit and system levels. It is interesting to note that
the DDA is a circuit element similar to the OTA at the input
side (particularly when single-ended inputs are considered)
and to the op-amp at the output side. Consequently, one
is able to design DDA-based circuits which combine the
properties of OTA' s, especially high input impedance and
low component count with the low output impedance and
low distortion of op-amps. The resultant circuits, although
HUANG er al.: WIDE RANGE DIFFERENTIAL DIFFERENCE AMPLIFIER 299

operating in the frequency range of op-amps, possess attractive (A5) (see bottom of page) where
features that do not exist in both traditional (discrete) and
modem fully integrated op-amp circuits. Moreover, DDA-
c1 = Pur + PpL~uv;2
based circuits could be implemented without the requirement c 2 =P P m v k 2
of component matching external to the DDA, which is a basic c
3 =W p n , V k 2
requirement in almost all op-amp circuits. As a result, DDA-
c
4 = PuPd
based continuous-time analog signal-processing circuits offer
a competitive design choice to op-amp-based circuits. and u o ,ul , u2, . . . are the coefficients of f l (Vd)expanded into
A compact DDA structure would make use of simple V-I Taylor’s series. a0 and a1 are given as
converters, e.g., a converter that exploits the body effect to I -
improve linearity [20]. The extension of DDA’s to multiple
inputs is a straightforward task [4]. A compact multiple input
CMOS DDA based on charge sharing of multiple gates in a
floating gate transistor was recently described [24]. 1 1

VI. APPENDIXA
U1 =-
2
(c,+c4

Cl fC3 -

The differential current of the V-I converter shown in Fig.

5 is derived in this Appendix. Vxl and Vx2 in the circuit
can be found by using the square law equations of the MOS
Since V,l(Vd) = Vz2(-Vd),one can easily find that
transistors, and are given by
j,(Vd) = f i (-Vd) = a0 - alVd + a2Vj - a3V2 + u4v; +. . . .
V X I =
i P , ( V C - V T p ) - P u ( V z 1 - VTn)] + . f l ( V d ) (A,1)
- 8, Therefore (please see top of next page). By selecting a small

vx2 =
Pp

[@p(,(vc - V T p ) - f l u ( % 2 - V T n ) ]+ f Z ( V d )
(A.2)
Jm. it is found that
P, - Pu (10 >> a2r1
where fl(Vd and f 2 ( V d ) are as shown at the top of the page.
{ a1 >> for n = 1 , 2 , 3 , .. . (‘4.6)

From (11) and (12), and the nonlinear term m J - V : + (41//&) is negligible.
As a result, (V.1 - Vz2)and (Vxl + Vx2)are simplified to

Substituting (A.3) and (A.4) into fl(Vd) and assuming V k 2 =

+
V, - V d d ~ V T-, V T ~one. can rewrite f l as shown in (vl)
300 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11:
The differential current of the circuit is therefore approximated
as
(A.9)
ACKNOWLEDGMENT
The authors would like to thank R. Brannen and S. Sakurai
of the Ohio State University for their help in testing DDA
circuits, R. Wassenaar and Remco Wiegerink of the University
of Twente, The Netherlands, for his useful comments on the
V-I converter, and M. Force of McDonnell Douglas, Saint
Louis for his early work on DDA circuits and specifically
for contributing the integrator circuit of Fig. 18(b). They also
thank D. Allstot and the reviewers for their comments to
improve the presentation.
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[ l ] A. D. L. Plaza and P. Morlon, “Power-supply rejection in differential
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[2] E. Sackinger and W. Guggenbiihl, “A versatile building block: The
CMOS differential difference amplifier,” IEEE J. Solid-State Circuit.>,
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[3] S. R. Zarabadi, F. Larsen, and M. Ismail, “A configurable op-amp/DDA
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484487, June 1992.
[4] S. T. Dupuie, S. Bibyk, and M. Ismail, “A novel all-MOS high-speed
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(ISCAS), pp. 6 7 5 4 8 0 , May 1989
[5] T. Kwan and K. Martin, “An adaptive analog continuous-time CMOS
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June 1991
[ 6 ] 0 Alrmnde, U. Gatti, V Liberali, F Maloberti, and P O’Leary, “An
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[7] M. Ismail and J Prigeon, “A novel technique for designing continuous-
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[8] S.-C Huang and M Ismail, “Novel fully-integrated active filter3 using
the CMOS differential difference amplifier,” in Proc 32nd Mzdwest
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[Y] S -C. Huang, “A wide dynamic range CMOS differential difference
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[IO] R Unbehauen and A Cichocki, MOS Switched-Capacitor und
Continuous-Time Integrated Circuits and SI\terns Berlin. Spring-
Verlag, 1989.
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Pp - Pu
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Boston: Kluwer, 1989.
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[ 151 H. Wallinga and K. Bult, “Design and analysis of CMOS analog signal
processing circuits by means of graphical MOST model,” IEEE J.
Solid-State Circuits, vol. 24, pp. 672480, June 1989.
[161 S. Sakurai and M. Ismail, “A CMOS square-law programmable floating
resistor independent of the threshold voltage,” IEEE Trans. Circuits
Syst.-fI. vol. 39, pp. 565-574, Aug. 1992.
[ 171 L. C. Thomas, “The biquad: Part I-Some practical design consider-
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[IS] L. P. Huelsman and P. E. Allen. Introduction to the Theory and Design
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1191 R. Schaumman, K. Laker, and M. S . Ghausi, Design ofAnalog Filters,
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[201 M. Ismail, S. -C. Huang, and S. Sukurai, “Continous signal processing,”
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T. Fici, Eds. New York: McGraw-Hill, to be published in 1994.
[21] S. Smith, F. Liu, and M. Ismail, “Active-RC building blocks for
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Shu-Chuan Huang received the B.S degree from
National Central University, Taiwan in 1987 and
the M S Degree from the Ohio State University,
Columbus in 1990, both in electncal engineenng
She is currently a Ph.D. student of electncal
engineenng and a Research Assistant at the Ohio
State University, Columbus. Her research interests
are in the area of analog integrated circuit analysis
and de9ign. She was employed by Tatung Institute
of Technology, Taiwan as a teaching assistant, 1987-
1988, and receives d scholarship from the institute
while at Ohio State University
HUANG et a/ WIDE RANGb DlFFERtNTlAL DIFFERI-NCF AMPLIPIER 30 1

Mohammed Ismail (S’80-M’ 82-SM’ 84) received Seyed R. Zarabadi received the B.S. and M.S.
the B.S. and M.S. degrees from Cairo University and degrees in electrical engineering from the Univer-
the Ph.D. degree from the University of Manitoba sity of Nebraska-Lincoln, Lincoln, NE, in 1982
in 1983, all in electrical engineering. and 1983, respectively. He then attended the Ohio
He held several positions in industry and academia State University and received the Ph.D. degree in
in the U.S., Canada, and overseas. He is currently electrical engineering in 1992.
with the Solid-state Microelectronics Laboratory at He joined Delco Electronics Corporation in 1984
the Ohio State University as a Professor of Electrical and designed analog IC’s until 1989. He is currently
Engineering. His current interests are in the areas a senior design engineer in the IC design center of
of analog/digital VLSI design in CMOS/BiCMOS, Delco Electronics in Kokomo, IN, working on data
CAD-compatible analog IC design, statistical mod- converters and radio IC’s. He holds nine patents.
eling and simulation of device mismatches in VLSI circuits, and artificial
neural information processing.
Dr. Ismail was an Associate Editor of the IEEE TTRANSACTIONS ON
CIRCUITS AND SYSTEMS, 1989-1991, and of the IEEE Cirmir.r und De-
vices Magazine,1988-1990. He is currently the CAS Editor of the magazine
and Associate Editor of IEEE TRANS. NEURAL NETWORKS. He is the
founder and Editor-in-chief of (North American) J. A ~ d o I~itegrcrrrd
g Circuit.\
and Signal Processing. He is the Editor of the Kluwer Adbanced Book Series
on Analog Circuits and Signal Processing. He served on several technical
committees and was the chairman of IEEE Circuits and Systems (CAS)
Society’s Technical Committee on Analog Signal Processing ( 1987-1 990)
and the G‘enerdl Chairman of the 29th Midwest Symposium on Circuits
and Systems (1986). He has published about 100 technical papers, was
awarded three patents and co-edited and co-authored three books: Anu/o,q
VLSI Implemenrution of Neurul System, Introduction to A i l d o g VLSl Design
Auromurion and Statistical Modeling f o r CAD of MOS VLSI Circuits. He
is listed in American Men and Women of Science and Who’s Who in
Technology. In 1985, Dr. Imail received the Prc\idential Young Investigator
Award from the National Science Foundation, in 1985. and the Ohio State
University’s Lumley Research Award in 1993 in recognition of outstanding
reseacrh accomplishments.