Solutions – Contact Dr. Derek Molloy (Derek.Molloy@dcu.

ie) Phone: 700 5355 on any queries

SEMESTER ONE EXAMINATIONS 2002

EE101 – Digital Electronics Solutions

Question 1.

An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line
should keep moving unless any of the following conditions arise:

o If the emergency switch is pressed.

o If sensor 1 and sensor 2 are activated at the same time.
o If sensor 2 and sensor 3 are activated at the same time.
o If all three sensors are activated at the same time.

(a) Derive the truth table for this system.

A = Switch B=Sensor1 C=Sensor2 D=Sensor3

Pressed or sensor activated = 1
F=Shutdown=1

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
[4 marks for correct table]

Digital Electronics – EE101 Semester One Solutions 2002

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Solutions – Contact Dr. Derek Molloy (Derek.Molloy@dcu.ie) Phone: 700 5355 on any queries

(b) Design, using Karnaugh Map techniques, a minimum AND-OR gate network for
this system. Draw the resulting digital circuit diagram.

Calculate Karnaugh Map:

[4 marks for map]

Resulting expression is : F = A + BC + CD

[4 marks for expression & diagram]

(c) Design, a digital circuit that will implement the minimal AND-OR gate network
found in (b) using both (i) NAND gates only and (ii) NOR gates only. Assume
that each logic gate can have any number of inputs and that inverted inputs are
available.

Use DeMorgan’s theorem to convert to NAND/NOR gates. The student must use the theorem and
cannot simply substitute the gates as this does not result in the minimal solution.

(i) NAND
F = A + BC + CD
= A ? BC ? CD ? A.BC.CD

[3 marks]

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(ii) NOR
F ? A ? BC ? CD
F ? A ? BC ? CD
F ? A ? ( B ? C ) ? (C ? D)

F ? F ? A ? ( B ? C ) ? (C ? D)

[3 marks]

(d) If the time delay experienced by a NAND gate is 8ns and the time delay
experienced in a NOR gate is 10ns. Which implementation of (c) is faster? By how
long?

For the NAND gates the total delay is 2 x 8ns = 16ns

For the NOR gates the total delay is 3 x 10ns = 30ns
NAND gate implementation is faster by 14ns
[3 marks]

(e) Prove the rule of Boolean algebra: (A+B)(A+C) = A + BC

( A ? B)( A ? C ) ? AA ? AC ? AB ? BC
? A ? AC ? AB ? BC
? A(1 ? C ) ? AB ? BC
? A ? AB ? BC
? A(1 ? B) ? BC
? A ? BC
[4 marks]

Digital Electronics – EE101 Semester One Solutions 2002

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Question 2.
(a) Convert the following numbers to binary. Show each step clearly. (i) 2916
(ii)255.437510

2916 can be converted directly as 0010 1001 as it is in hex form. Conversion to base 10 and then
division by 2 will also give full marks.
[3 marks]
255.4375 do in two stages.

255/2 = 127 remainder 1

127/2 = 63 remainder 1
63/2 = 31 remainder 1
31/2 = 15 remainder 1
15/2 = 7 remainder 1
7/2 = 3 remainder 1
3/2 = 1 remainder 1
1

LHS = 11111111

.4375 * 2 = (no carry) 0

.8750 * 2 = carry of 1
.7500 * 2 = carry of 1
.5 * 2 = carry of 1
.0

RHS = .0111

ANS 1111111.01112
[3 marks]

(b) Perform the following using 9's complement Binary Coded Decimal (BCD)
subtraction. (i) 411-332 (ii) 118-555
411-332 (get 9’s complement = 667)

0100 0001 0001

0110 0110 0111
____________________
1010 0111 1000 (1st invalid)
0110
____________________
1 0000
|____________________1
_________________
0000 0111 1001 = 79
[3 marks]
118 – 555 (9’s complement of 555 = 444)
0001 0001 1000
0100 0100 0100
__________________
0101 0101 1100 (last invalid)
0110
__________________

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0101 0101 0010
0001
__________________
0101 0110 0010 (no end-around carry => negative)

get nines complement of 562 = -437

[3 marks]

(c) Explain the operation and outline the problems associated with asynchronous
counters. Draw a graph of the outputs to help explain your answer.

[4 marks]

?? If the output of one counter is connected to the clock of the next counter then all 2N states can be
used in the binary counter.
?? N flip-flops => 2N states, base 2N
?? This counter is called an asynchronous or ripple counter as the clock pulse effectively ripples
through the counter.
[3 marks]
?? The more correct waveform is shown here:

?? There is a cumulative delay which is a major disadvantage.

?? This cumulative delay of an asynchronous counter limits the rate at which a counter can be
clocked and can also create decoding problems.
?? False outputs that result are called glitches.

[6 marks]

Digital Electronics – EE101 Semester One Solutions 2002

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Question 3.

(a) Explain the operation of a right/left shift register. Draw the logic diagram to help
explain its operation.

[8 marks for diagram]

?? Shift registers can be used to transfer data from right to left, shift left by connecting the output
of a flip-flop back to the input of the flip-flop on its left.
?? A shift from left to right, shift right, can be carried out during normal operation of the shift
register
?? A shift right and shift left register can be combined by suitable gating and control signals.
?? In the operation above R / L ? 0 => shift right
?? In the operation above R / L ? 1 => shift left
?? Explain the operation of the logic gates – simply an and gate with a value of 0 has an output of
zero and an AND gate with one input of 1.A will have the output A. In effect the R/L line
turns either the Right or Left AND gate on or off. The OR gate simply combines the output of
the two AND gates to bring forward the correct output.
[5 marks for description]

(b) Design a two’s complement adder/subtractor. Draw the logic diagram and explain
how the design works in add mode and in subtract mode.

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?? This circuitry can generate the 2’s complement when we wish to do a subtraction
?? When ADD / SUB = 0 => the circuit adds
?? When ADD / SUB = 1 => the circuit subtracts
?? XOR gates act as True/complement in that they invert B when the line is set to 1 and a 1 is
added to the LSB, so that the two’s complement will be generated.
[8 marks for correct diagram]
[4 marks for the description]

Question 4.

(a) Explain the operation of a shift register with feedback. Use diagrams to explain
the operation.

?? If the serial output of a shift register is connected back to the input [Q to J], [Q\ to K] then the
sequence of numbers stored in the register will circulate.

E.g. Q3 Q2 Q1 Q0 CLK
1 0 1 1
1 1 0 1 pulse 1
1 1 1 0 pulse 2
0 1 1 1 pulse 3
1 0 1 1 pulse 4
Note that the last row is the same as the first row.
[7 marks for diagram]
[3 marks for description]

(b) Explain the operation of an n-bit ring counter with self correcting feedback.

?? An N-bit ring counter has N states each of which contains all 0’s except for a single 1
?? An ring counter is wasteful of flip-flops as we only get N states with N flip-flops.

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Solutions – Contact Dr. Derek Molloy (Derek.Molloy@dcu.ie) Phone: 700 5355 on any queries
?? We can use self correcting feedback to obtain desired sequences.
?? In this case when 0 0 0 occurs the AND gate will feed back a 1 (as the inputs to the AND gate are
connected to the Q\ values)
[Diagram 10 marks]
[Description 5 marks]

Question 5.

(a) Explain the operation of a master-slave JK flip-flop. Draw the logic diagram for
the flip-flop and describe in detail the two-stage approach of its operation, in
particular explain why a master-slave configuration is preferable to a standard JK
flip-flop.

[8 marks for diagram]

?? Two phase operation
?? When the clock pulse is high the JK inputs are applied to the master flip-flop and the slave
input is not affected [clk=0]. When the clock pulse falls to zero the data from the master is
applied to the slave inputs and the outputs Q and Q\ then get their new values. But since
CLK=0 the master flip-flop is unaffected by them and the flp-flop operates correctly.
?? Problem with standard JK flip-flops is that if the data inputs change while the clock pulse is
high then we get strange effects on the outputs. We need to insure that the Q and Q\ values do
not assume their new values until after the trailing edge of the clock pulse ie. = 0.
[7 marks for description]

(b) Explain using diagrams the modifications required to convert (a) into a JK flip-
flop with asynchronous set and reset inputs. Why are these inputs a useful addition
to the standard master-slave JK flip-flop?

?? Separate set and reset inputs can be added to the JK Flip-flop. These set and reset inputs [S\,
R\] over-ride the JK inputs and are asynchronous [i.e. override the clock].
?? When S\=R\=1 we have normal flip-flop operation.

Digital Electronics – EE101 Semester One Solutions 2002

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[6 marks for addition to diagram]

[4 marks for brief description]

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