SUMADOR Y RESTADOR DE 4 BITS (DIAGRAMA Y VHDL)

Sumador:

Restador :
SUMADOR_COMPLETO :

Sumador y restador paralelo :

library ieee;

use ieee. std_logic_1164 .all;

entity Sumador4Bits is

port ( A, B : in std_logic_vector (3 downto 0);

S : out std_logic_vector (3 downto 0);

COUT : out std_logic );

end Sumador4Bits ;

architecture structural of Sumador4Bits is

signal C : std_logic_vector (4 downto 0);

component Sumador1Bit

port (

A_i , B_i : in std_logic ;

C_i : in std_logic ;

S_i : out std_logic ;

C_i_mas_1 : out std_logic );

end component;

begin

C(0) <= '0';

COUT <= C(4);

GenSum : for i in 0 to 3 generate

Sumador1Bit_1 : Sumador1Bit

port map (

A_i => A(i),

B_i => B(i),

C_i => C(i),

S_i => S(i),

C_i_mas_1 => C(i+1));

end generate GenSum;

end structural ;