Anna University Exams Nov/Dec 2018 – Regulation 2017

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EC8392 DIGITAL ELECTRONICS

PART B & PART C Questions for all 5 Units

1. (i) Explain the common postulates and theorems used to formulate various Boolean
expressions. (ii) Convert (A+B)(A+C)(B+C’) into standard POS form
2. Reduce the following switching function using K-map and realize using logic gates. F(w ,x ,y
,z)=Σm(0,3,5,7,8,9,10,12,15).

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3. What are the advantages of Tabulation method? Solve the following using Tabulation
method: 𝐹(𝑎,𝑏,𝑐,𝑑)= Σm(0,5,7,8,9,10,12,15). List the prime implicants and essential prime
implicants.
4. Simplify 𝐹(𝐴,𝐵,𝐶,𝐷)= Σm(0,1,2,5,8,9,10) in sum of products and product of sums using K-
map. Realize the expression using NAND gate.
5. Reduce the expression using Quine- McClusky method.
F(x1,x2,x3,x4,x5)=Σm(0,2,4,5,6,7,8,10,14,17,18,21,29,31)+Σd(11,20,22)

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6. Reduce the following switching function using K-map and realize using NOR gate.
F(x1,x2,x3,x4,x5)=Σm(1,3,6,10,11,12,14,15,17,19,20,22,24,29,30).
7. Design full Subtractor and half Subtractor.
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8. Find the minimal sum of products for the Boolean expression using Quine –McCluskey
method. F = Σm(0,1,9,15,24,29,30)+ Σd(8,11,31)
9. Draw and explain carry look ahead adder
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10. Design a parallel adder/subtractor.
11. Design a circuit that performs BCD addition.
12. List the design steps involved in combinational circuits. Design the basic adders.
13. Design a 4-bit magnitude comparator.
14. Design a priority encoder.
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15. Design a 4:1 multiplexer and 1:4 Demultiplexer.

16. Explain about 2:4 decoder and 3:8 decoder.
17. Explain in detail about the operation, truth table and characteristics equation of SR and D
flipflop.
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18. Design a mod 6 counter using T flipflops.

19. Design a 4-bit synchronous counter using D flipflop.
20. Design a synchronous sequential circuit using JK flipflop for the given state diagram.
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21. i) Implement the following Boolean function using 8:1 multiplexer Y= Σm(0,1,3,4,8,9,15) ii)
Implement the following Boolean function using Demultiplexer Y1= Σm(0,3,7) Y2= Σm(1,2,5)
22. Design a negative-edge- triggered T flip-flop. The circuit has two inputs, T (toggle) and C
(clock), and one output, the output state is complemented if T = 1 and the clock C changes
from I 100 (negative-edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.
23. Design an asynchronous sequential circuit with inputs x1 and x2 and one output z. Initially
both the inputs are equal to 0. When x1 and x2 becomes 1, z becomes 1. When second input
also becomes 1, z = 0; The output stays at 0 until circuit goes back to initial state.
24. A sequential circuit that has two inputs D and G, one output Q. When G =1, Q follows D and
when G=0, Q is retained in its previous value Derive the reduced flow table for the circuit

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 25. An asynchronous sequential circuit has 2 internal states and 1 output state. The excitation
and output function describing the function are as follows
Y1 = x1x2 + x1y2 + x2y1
Y2 = x2 + x1y1y2 + x1y1
Z= x2 + y1
26. Design an Asynchronous sequential circuit which has 2 inputs x1 and x2 and one output Z.
The circuit is required to give an output whenever the input sequence (0,0) (0,1) and (1,1)
received but only in that order. Design it using T flipflops
27. For a given Boolean function obtain the hazard free circuit
F (A,B,C,D ) = ∑m ( 1,3,5,7,8,9,14,15) and F ( A,B,C,D) = ∑m( 0,2,6,7,8,10,12)

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28. Implement the following using PLA. F1 = ∑m(0,1,2,4) F2 = ∑m(0,5,6,7) F3 = ∑m(0,3,5,7)
29. Design the following using PAL.
W(A,B,C,D) = ∑m(2,12,13)
X(A,B,C,D) = ∑m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) = ∑m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) = ∑m(1,2,8,12,13)
30. Describe about CMOS inverter logic.
31. Write short notes on RTL.

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