ECE2003

VLSI System Design

Lec #02

MOS Transistor Theory

Instructor:

Dr. V. Nithish Kumar

Assistant Professor (Sr.)
Department of Micro & Nano Electronics
School of Electronics Engineering
VIT University, Vellore

Office : Room TT237

Dr. V Nithish Kumar, SENSE ECE2003 VLSI System Design WS 2017-18

Outline

 MOSFET Types
 The Big Picture
 MOS Structure
 Ideal I-V Charcteristics
 MOS Capacitance Models
 Non ideal I-V Effects
 Pass transistor circuits
 Tristate Inverter
 Switch level RC Delay Models 2
Types of MOSFET

3
Types of MOSFET

4
The Big Picture

 So far, we have treated transistors as ideal switches

 An ON transistor passes a finite amount of current
 Depends on terminal voltages
 Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
 I = C (DV/Dt)  Dt = (C/I) DV
 Capacitance and current determine speed

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MOS Transistor Symbol

6
 MOS Structure

 Gate and body form

MOS capacitor
 Operating modes
 Accumulation
 Depletion
 Inversion

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nMOS Transistor Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs V g

+ +
 Vgs = Vg – Vs V gs
V gd
- -
 Vgd = Vg – Vd V V
s - + d

 Vds = Vd – Vs = Vgs - Vgd V ds

 Source and drain are symmetric diffusion terminals

 By convention, source is terminal at lower voltage
 Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
 Cutoff
 Linear
8
 Saturation
nMOS in cutoff operation mode

 No channel
 Ids = 0

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 nMOS in linear operation mode

 Channel forms
 Current flows from D to S
 e- from S to D
 Ids increases with Vds
 Similar to linear
resistor

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 nMOS in Saturation operation mode

 Channel pinches off

 Ids independent of Vds
 We say current saturates
 Similar to current source

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pMOS Transistor

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I-V Characteristics (nMOS)
 In Linear region, Ids depends on
 How much charge is in the channel?
 How fast is the charge moving?

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 Channel Charge
 MOS structure looks like parallel
plate capacitor while operating in
inversion:
 Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = coxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt

cox = eox / tox

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Carrier velocity

 Charge is carried by e-
 Carrier velocity v proportional to lateral
E-field between source and drain
 v = mE m called mobility
 E = Vds/L
 Time for carrier to cross channel:
 t=L/v

15
 nMOS Linear I-V
 Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross
Qchannel
I ds  =
t
 mCox
WV  V  Vds V
 gs  ds
 2 
t
L

  Vgs  Vt 
Vds 
Vds
W  2 
 = mCox 16
L
nMOS Saturation I-V

 If Vgd < Vt, channel pinches off near drain

 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
 dsat
 2 

  Vt 
2
 Vgs
2
17
 nMOS I-V Summary

 first order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
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 The MOSFET as a Controlled Resistor

 When VDS is low, ID increases linearly with VDS

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 Pinch - off and Saturation

 As VDS increases, V(x) along channel increases.

 Inversion - layer charge density Qn at the drain end of
the channel is reduced; therefore, ID increases slower
than linearly with VDS.

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I-V characteristics of nMOS Transistor

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I-V characteristics of nMOS Transistor

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pMOS I-V Characteritics

 All dopings and voltages are inverted for pMOS

 Mobility mp is determined by holes
 Typically 2-3x lower than that of electrons mn
 120 cm2/V*s in AMI 0.6 mm process
 Thus pMOS must be wider to provide same
current
 In this class, assume mn / mp = 2

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I-V characteristics

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MOS capacitor
 An MOS capacitor is made of a semiconductor
body or substrate, an insulator and a metal
electrode called a gate.
 Practically the metal is a heavily doped n+ poly-
silicon layer which behaves as a metal layer.

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Capacitances of a MOS Transistor
 Gate to channel capacitor is very important
 Creates channel charge necessary for
operation (intrinsic capacitance)
 Source and drain have capacitance to body
(parasitic capacitance)
 Across reverse-biased diodes
 Called diffusion capacitance because it is
associated with source/drain diffusion

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Capacitances of a MOS Transistor
 Gate to channel capacitor is very important
 Creates channel charge necessary for
operation (intrinsic capacitance)
 Source and drain have capacitance to body
(parasitic capacitance)
 Across reverse-biased diodes
 Called diffusion capacitance because it is
associated with source/drain diffusion

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Capacitances – V Curve

The flat band voltage (Vfb) is the voltage at which there is no charge on the
capacitor plates and hence there is no static electric field across the oxide.

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Gate Capacitance

 When the transistor is off, the channel is not

inverted
Cg = Cgb = eoxWL/tox = CoxWL
 Let’s call CoxWL = C0
 When the transistor is on, the channel extends
from the source to the drain (if the transistor is
unsaturated, or to the pinchoff point otherwise)
Cg = Cgb + Cgs + Cgd
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Gate Capacitance

FIGURE 2.9 Intrinsic gate capacitance Cgc = Cgs + Cgd + Cgb as a

function of (a) Vgs and (b) Vds

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Gate Capacitance

In reality the gate overlaps source and

drain. Thus, the gate capacitance should
include not only the intrinsic capacitance
but also parasitic overlap capacitances:
Cgs(overlap) = Cox W LD
Cgd(overlap) = Cox W LD 31
Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

Source: M-S Kang, Y. Leblebici,

CMOS Digital ICs, 3/e,
2003, McGraw-Hill 32
 Diffusion Capacitance
 Csb, Cdb
 Undesired capacitance (parasitic)
 Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
 Capacitance depends on area and
perimeter
 Use small diffusion nodes
 Comparable to Cg for
contacted diffusion
 ½ Cg for uncontacted
 Varies with process
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Lumped representation of the
MOSFET capacitances

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Non-ideal I-V effects

 The saturation current increases less than quadratically with

increasing Vgs
 Velocity saturation
 Mobility degradation
 Channel length modulation
 Body Effect
 Leakage currents
 Sub-threshold conduction
 Junction leakage
 Tunneling
 Temperature Dependence

35
 Velocity saturation and
mobility degradation
 At strong lateral fields (Vds /L), resulting from high Vds, carrier velocity ceases to
increase linearly with field strength, drift velocity rolls off due to carrier scattering
and eventually saturates

 Strong vertical fields (Vgs /tox ) resulting from large Vgs cause the carriers to
scatter against the surface and also reduce the carrier mobility. This effect is
called mobility degradation

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Velocity saturation and
mobility degradation

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 Channel length modulation
 The reverse biased p-n junction
between the drain and the body
forms a depletion region with length
Ld’ that increases with Vdb. The
depletion region effectively shorten
the channel length to: Leff = L – Ld’

 Assuming the source voltage is

close to the body votage Vdb ~ Vsb.
Hence, increasing Vds decrease the
effective channel length.

 Shorter channel length results in Drain-induced barrier lowering causes Ids

higher current to increase with Vds in saturation
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Body Effect

 The potential difference between source and

body Vsb affects (increases) the threshold
voltage

 Threshold voltage depends on:

 Vsb
 Process
 Doping
 Temperature 39
Simulated and ideal I-V
characteristics

40
 Subthreshold Conduction
 The ideal transistor I-V model assumes current only flows
from source to drain when Vgs > Vt.
 In real transistors, current doesn’t abruptly cut off below
threshold, but rather drop off exponentially
 This leakage current when the transistor is nominally OFF
depends on:
 process (eox, tox)
 doping levels (NA, or ND)
 device geometry (W, L)
 temperature (T)
 Subthreshold voltage (Vt)

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Junction Leakage
 The p-n junctions between diffusion and the substrate or
well for diodes.
 The well-to-substrate is another diode
 Substrate and well are tied to GND and VDD to ensure
these diodes remain reverse biased
 But, reverse biased diodes still conduct a small amount of
current that depends on:
 Doping levels
 Area and perimeter of the diffusion region
 The diode voltage

42
 Tunneling

 There is a finite probability that

carriers will tunnel though the
gate oxide. This result in gate
leakage current flowing into
the gate
 The probability drops off
exponentially with tox
 For oxides thinner than
15-20 Å, tunneling becomes a
factor
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 Temperature dependence

 Transistor characteristics are

influenced by temperature
 m decreases with T
 Vt decreases linearly with T
 Ileakage increases with T
 ON current decreases with T
OFF current increases with T
 Thus, circuit performances are
worst at high temperature

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 Impact of non-ideal I-V effects
 Threshold is a significant fraction of the supply voltage
 Leakage is increased causing gates to
 consume power when idle
 limits the amount of time that data is retained
 Leakage increases with temperature
 Velocity saturation and mobility degradation
result in less current than expected at high voltage
 No point in trying to use high VDD to achieve fast
transistors
 Transistors in series partition the voltage across each
transistor thus experience less velocity saturation
 Tend to be a little faster than a single transistor
 Two nMOS in series deliver more than half the
current of a single nMOS transistor of the same
width 45
 Matching: same dimension and orientation
 Pass Transistors

 nMOS pass transistors pull no higher than VDD-Vtn

 Called a degraded “1”
 Approach degraded value slowly (low Ids)

 pMOS pass transistors pull no lower than |Vtp|

 Called a degraded “0”
 Approach degraded value slowly (low Ids)

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Pass transistor Circuits

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Transmission gate ON resistance

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Tri-state Inverter

If the output is tri-stated but A toggles,

charge from the internal nodes (= caps)
may disturb the floating output node

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Effective resistance of a transistor

 First-order transistor models have limited value

 Not accurate enough for modern transistors
 Too complicated for hand analysis
 Simplification: treat transistor as resistor
 Replace Ids(Vds, Vgs) with effective resistance R
 Ids = Vds/R
 R averaged across switching range of digital gate
 Too inaccurate to predict current at any given time
 But good enough to predict RC delay (propagation delay of a
logic gate)

50
RC Values
 Capacitance
 C = Cg = Cs = Cd = 2 fF/mm of gate width
 Values similar across many processes
 Resistance
 R  6 KW*mm in 0.6um process
 Improves with shorter channel lengths
 Unit transistors
 May refer to minimum contacted device (4/2 l)
 or maybe 1 mm wide device
 Doesn’t matter as long as you are consistent
51
RC Delay Models

 Use equivalent circuits for MOS transistors

 ideal switch + capacitance and ON resistance
 unit nMOS has resistance R, capacitance C
 unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width

52
Switch level RC models

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Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter

54
delay = 6RC
Resistance of a unit transmission gate
 The effective resistance of a transmission gate is the
parallel of the resistance of the two transistor
 Approximately R in both directions
 Transmission gates are commonly built using equal-sized
transistors
 Boosting the size of the pMOS only slightly improve the
effective resistance while significantly increasing the
capacitance

55
Summary
 Models are only approximations to reality, not reality itself
 Models cannot be perfectly accurate
 Little value in using excessively complicated models, particularly
for hand calculations
 To first order current is proportional to W/L
 But, in modern transistors Leff is shorter than Ldrawn
 Doubling the Ldrawn reduces current more than a factor of two
 Two series transistors in a modern process deliver more than half
the current of a single transistor
 Use Transmission gates in place of pass transistors
 Transistor speed depends on the ratio of current to capacitance
 Sources of capacitance (voltage dependents)
 Gate capacitance
 Diffusion capacitance
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60
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62
Assume all transistor W / L ratios are as shown in below figure and the following transistor
and supply voltage characteristics:

a) What Boolean logic function is implemented by the circuit?

b) Find Wp and Wn such that the worst case rise and fall times
of the circuit are equal. Be sure to minimize the total
transistor area.
c) Given your sizes from Problem (b) above, what are VOH and
VOL for the circuit ? Justify your answers
63
a)

b)

c)

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