Sci

Chapter 14 – M68HCS12 Serial I/O 14-1
Chapter 14
M68HCS12 Serial I/O
Objectives
This chapter discusses the M68HCS12 serial I/O capabilities. The

Asynchronous Serial Communications Interface, SCI, and the Synchronous
Serial Peripheral Interface, SPI, are covered. The Freescale Scalable
Controller Area Network, MSCAN, is covered in the next chapter.
14.1 Introduction
The M68HCS12 can contain a variety of serial interfaces. Among these are the following:
• The Asynchronous Serial Communications Interface – SCI. This is a universal
asynchronous receiver-transmitter (UART) designed for serial communications
to a terminal or other asynchronous serial devices such as personal computers.
• The Synchronous Serial Peripheral Interface – SPI. This is a high-speed,
synchronous serial interface used between an M68HCS12 and a serial peripheral
such as a Motorola MC68HC68A1 Serial 10-bit A/D converter or between two
M68HCS12s
• The Motorola Scalable Controller Area Network, or MSCAN. This module is
serial communications controller implementing the CAN 2.0 A/B protocol
widely used in automotive applications.
Figure 14-1(a) shows the asynchronous Serial Communications Interface – SCI. It is
frequently used to communicate with other computers, terminals and modems. In the
personal computer world, this interface is called the COM port. Usually an RS-232-C
interface standard is adopted with voltages levels that require a CMOS-to-RS-232-C
translation chip. The RS-232-C standard also defines handshaking signals such as
Request to Send – RTS and Clear to Send – CTS. These signals have not been
implemented in the SCI but Port S, bits 2 and 3 may be used for this purpose. Chapter 17
shows how to interface the SCI to RS-232-C devices
Figure 14-1(b) shows the Controller Area Network – MSCAN. This interface is
widely used in the automotive industry and is a two-wire, carrier-sense, multiple access
bus. A CAN transceiver is required to create a bus structure supporting multiple CAN
devices. Chapter 15 shows how to use the MSCAN interface.
Figure 14-1(c) is the synchronous Serial Peripheral Interface – SPI. This interface
allows a much higher data transfer between peripheral SPI devices and the
microcontroller than does the SCI. Section 14.3 shows how to use the SPI and Chapter 17
gives interfacing examples.
'PORT S'
Serial Received Data
RXD PS0 RS232
SCI CMOS to
(a) Serial Transmitted Data Serial
TXD PS1 RS232
Device
PS2
PS3
'PORT M'
RXCAN PM0 CAN CAN CAN
(b) CAN Transceiver Transceiver Device
TXCAN PM1
Master In/Slave Out
MISO PM2
SPI Master Out/Slave In
(c) MOSI PM3 SPI
Shift Clock Device
SCK PM4
Slave Select
SS* PM5
Figure 14-1 M68HCS12 (a) asynchronous, (b) CAN and (c) synchronous serial interfaces.
14.2 Asynchronous Serial Communications Interface (SCI)

The SCI is a full duplex, asynchronous, serial interface. It has an
The SCI is a Universal on-chip, independent, baud rate generator that can produce
Asynchronous Receiver- standard serial communication rates from normal M68HCS12 bus
Transmitter (UART).
clock frequencies. The receiver and transmitter are double buffered
and although they operate independently, they use the same baud
rate and data format. The SCI can send and receive 8- or 9-bit data, has a variety of
interrupts, and is fully programmable.
Using and programming each SCI can be broken into three parts. These are (1)
initialization of the device's data rate, word length, parity and interrupting capabilities, (2)
writing to the SCI data register, taking care to not exceed the data transmission rate, and
(3) reading data from the SCI data register making sure to read the incoming data before
the next serial data arrives.
The input and output transmitted data pins are in Port S. Two of the four
bidirectional Port S pins are shared with the serial communications interface (SCI). If the
SCI is enabled, bit-0 is assigned to received-data (RxD) and is configured as an input.
Bit-1 is assigned to transmitted-data (TxD) and configured as an output. Bits-2 and -3 are
not assigned and can be used to implement flow control in the serial interface.
PTS -- Base + $0248 – Port S I/O Register

Bit 7 6 5 4 3 2 1 0
Read: 0 0 0 0
PTS3 PTS2 PTS1 PTS0
Write:
Reset: 0 0 0 0 0 0 0 0
SCI - - - - - - TxD RxD
= reserved, unimplemented or cannot be written to.
SCI Data
Two data registers, SCIDRH and SCIDRL, shown in Figure 14-2,
Serial data are read from and contain the 8- or 9-bit serial data received and to be transmitted.
written to the SCIDR register. The SCIDRL register is two separate registers occupying the same
memory address. Data to be transmitted serially are written to and
serial data received are read from these registers.
SCIDRH and SCIDRL form a 9-bit data register when sending and receiving 9-bit
data. The ninth transmit bit (T8) does not have to be changed each time new serial data
are sent. The same value will be transmitted until T8 is changed. If 9-bit data are to be
used, SCIDRH bit should be written before SCIDRL to ensure the correct data are
transferred to the SCI transmit data register when SCIDRL is written. If an 8-bit data
format is being used, only SCIDRL needs to be read or written.
SCIDRL contains the 8-bit serial transmitted and received data. Reading from
SCIDRL reads the last received data and writing to it sends (transmits) the serial data.
Writing to SCIDRL does not overwrite or destroy the contents of the data that has been
received.
'SCIDRL' (READ)
Serial Received
R7 R0
Date
Receiver
R7 R0 RxD
'SCIDRH' Shift Register
R8 T8
Transmitter
T7 T0 TxD
Shift Register
Serial Transmitted
T7 T0
Data
'SCIDRL' (WRITE)
Figure 14-2 SCI data registers.
SCIDRH – Base + $00CE – SCI Data Register High

Bit 7 6 5 4 3 2 1 0
Read: R8 T8 0 0 0 0 0 0
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Anytime; reading accesses SCI receive data register Write: Anytime; write accesses SCI transmit data
register; writing to R8 has no effect.
SCIDRL – Base + $00CF – SCI Data Register Low

Bit 7 6 5 4 3 2 1 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: 0 0 0 0 0 0 0 0
Read: Anytime; reading accesses SCI receive data register Write: Anytime; write accesses SCI transmit data
register.
R8:R0, T8:T0
Serial Receive and Transmit Data
R8 and T8 are the ninth data bit received and transmitted when the SCI is in 9-bit data format (M = 1).
R7 – R0, T7 – T0 are the received and transmitted 8-bit or 9-bit data formats.
When transmitting in 9-bit data format and using 8-bit write instructions (staa etc.), write the SCIDRH
register and then SCIDRL.
If the value of T8 is the same as the previous transmission, T8 does not have to be rewritten.
In 8-bit data format, only SCIDRL has to be written and read.
SCI Initialization
Receiver and Transmitter Enable
As with any programmable device, the SCI must be initialized before use and there are a
variety of registers and bits to be programmed. First, the transmitter and receiver are
enabled by setting TE and RE in the SCICR2 - SCI Control Register 2. SCICR2 contains
bits to enable various interrupts, the SCI wake-up control, and a break generation bit. We
will discuss these in a later section.
SCICR2 – Base + $00CB – SCI Control Register 2

Bit 7 6 5 4 3 2 1 0
Read: TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Anytime. Write: Anytime.
TIE
Transmitter Interrupt Enable
0 = Transmitter Data Register Empty (TDRE) flag interrupt requests disabled (default).
1 = Data Register Empty (TDRE) flag interrupt requests enabled.
TCIE
Transmission Complete Interrupt Enable
0 = Transmission complete (TC) flag interrupt requests disabled (default).
1 = Transmission complete (TC) flag interrupt requests enabled.
RIE
Receiver Full Interrupt Enable
0 = Receive data register full (RDRF) flag interrupt requests disabled (default).
1 = Receive data register full (RDRF) flag interrupt requests enabled.
ILIE
Idle Line Interrupt Enable
0 = Idle line (IDLE) flag interrupt requests disabled (default).
1 = Idle line (IDLE) flag interrupt requests enabled.
TE
Transmitter Enable
0 = SCI transmitter disabled (default).
1 = Transmitter enabled.
RE
Receiver Enable
0 = SCI receiver disabled (default).
1 = Receiver enabled.
RWU
Receiver Wakeup
0 = SCI normal operation (default)
1 = Enables the wakeup function and disables further receiver interrupt requests.
SBK
Send Break
0 = No break characters (default).
1 = Transmit break characters.
SCI Mode Control

In addition to enabling the receiver/transmitter, the SCI operation mode must be
initialized. This is done in the SCICR1 - SCI Control Register 1.
SCICR1 – Base + $00CA – SCI Control Register 1

Bit 7 6 5 4 3 2 1 0
Read: LOOPS SCIWAI RSRC M WAKE ILT PE PT
Write:
Reset: 0 0 0 0 0 0 0 0
LOOPS
Loop Select
0 = Normal operation (default).
1 = Loop operation enabled.
In loop mode, the RxD pin is disconnected from its normal Port S input pin and connected to the
transmitter as defined by the RSRC bit. Both transmitter and receiver must be enabled (TE = 1, RE
= 1).
SCIWAI
SCI Stop in Wait Mode
0 = SCI enabled in wait mode (default).
1 = SCI disabled in wait mode.
RSRC
Receiver Source
0 = Receiver input internally connected to the transmitter output (default).
1 = Receiver input externally connected to the transmitter output.
Table 14-1 Loop Functions
LOOPS RSRC Function

0 X Normal operation.
1 0 Loop mode with RxD input internally connected to transmitter output.
1 1 Single -wire mode with RxD input connected externally to TxD output.
M
Data Format Select
0 = One start, eight data, one stop bit (default).
1 = One start, eight data, plus ninth data, one stop bit.
WAKE
Wakeup Condition
0 = Idle line wakeup (default).
1 = Address line wakeup.
ILT
Idle Line Type
0 = Idle character bit count starts after start bit (default).
1 = Idle character bit count starts after stop bit.
An idle character contains all ones with no start or stop bit. ILT determines when the bit-count starts for
detecting an idle line. The M bit determines the number of bits in an idle character.
PE
Parity Enable
0 = Parity is disabled (default).
1 = Parity is enabled.
When parity is enabled, PT determines the type of parity. The parity bit is inserted in the data word in
the most significant bit position.
PT
Parity Type
0 = Even parity (default).
1 = Odd parity.
SCI Loop Mode

The M68HCS12 offers a loop mode useful for testing serial I/O software when the
external serial device may not be available. Loop mode is enabled by setting LOOPS to
one. In the loop mode, the receiver is connected directly to the transmitter and thus
anything you send out comes straight back in. You have a choice of how the receiver is
connected to the transmitter. If the RSRC - Receiver Source bit is zero, the receiver is
connected internally to the transmitter. If RSRC is one, the SCI operates in single-wire
mode with the receiver externally connected to the transmitter. See Table 14-1.
SCI Single-Wire Mode
When LOOPS = 1 and RSRC = 1, the single-wire mode is selected. This allows a half-
duplex operation between two SCI devices. The normal RxD pins (Port S bit-0) is
disconnected from the SCI and can be used for general purpose I/O. The TxD output is
enabled or disabled by controlling TXDIR in the SCISR2 register. Thus in half-duplex or
single-wire mode the transmitter can be active (TXDIR = 1) when it is sending data and
inactive (TXDIR = 0) when it is receiving. Table 14-1 gives a summary of the TxD
activity for these modes.
8- or 9-Bit Data
The number of data bits to be sent and received is controlled by the M bit in SCICR1. M
= 0 for one start, eight data and one stop bit; M = 1 for one start, nine data, one stop bit.
Idle Line
An idle line is one in which the receive line is in a mark 1 condition (logic high) for more
than one character time. Idle line detect may be used in half-duplex, or single-wire
systems in which the line needs to be "turned around" when the remote transmitter is
done transmitting. The idle condition is detected when the RxD input remains in the mark
(1) condition for a full character time. In long idle detect mode, the idle detect logic does
not start counting logic 1-bit times until after a stop bit. In short idle detect mode, the idle
detect logic starts counting logic ones after a start bit so the stop bit time and any
contiguous one s at the end of a serial character can cause idle to be detected earlier than
expected.
Parity
The M68HCS12 can generate a parity bit in hardware. Parity generation for transmitting
and checking for receiving is enabled by setting the PE bit. The type of parity, even or
odd, is selected by the PT bit. The chosen parity bit is inserted in the most significant bit
position.
SCISR2 – Base + $00CD – SCI Status Register 2

Bit 7 6 5 4 3 2 1 0
Read: 0 0 0 0 0 BK13 TXDIR RAF
Write:
Reset: 0 0 0 0 0 0 0 0
BK13
Break Transmit Character Length
0 = Break character is 10 or 11 bits long (default).
1 = Break character is 13 or 14 bits long.
TXDIR
Transmit Data Direction in Single-Wire Mode
0 = TxD pin is used as an input (default).
1 = TxD pin is used as an output.
RAF
Receiver Active Flag
0 = No reception in progress (default).
1 = Reception in progress.
This bit is set when the receiver detects a start bit and cleared when an idle character is detected.
1
Mark and space are terms used in asynchronous serial communications to denote a logic one (mark) and
zero (space).
SCI Baud Rate Selection

The rate at which serial data bits are sent is called the Baud rate. Both the receiver and
transmitter use the same rate and a 13-bit divider derives standard Baud rates from the
bus clock. The bus clock is normally one- half the external oscillator frequency. Table
14-2 shows how the bits in the SCI Baud Rate Control Registers select standard rates.
Non-standard Baud rates can be chosen by initializing the Baud rate registers with other
BR values. The value to choose is given by the following relationship and shown in Table
14-2 for an 8 MHz bus clock.
Bus Clock
SCI Baud Rate =
(16 ∗ SCIBR [12 : 0])
SCIBDH – Base + $00C8 – SCI Baud Rate Register High

Bit 7 6 5 4 3 2 1 0
Read: 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8
Write:
Reset: 0 0 0 0 0 0 0 0
SCIBDL – Base + $00C9 – SCI Baud Rate Register Low
Bit 7 6 5 4 3 2 1 0
Read: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Write:
Reset: 0 0 0 0 0 0 0 0
SBR12:SBR0
SCI Baud Rate Select
Table 14-2 Baud Rates (8 MHz Bus Clock)
Baud Rate SBR12:SBR0 10

38,400 13
19,200 26
9,600 52
4,800 104
2,400 208
1,200 417
600 833
300 1667
150 3333
110 4545
SCI Status Flags

The SCI system has several status flags and interrupts to inform you of its progress and of
error conditions that may occur. Your program may poll the flags or make use of the
interrupts. The status flags are in the SCI Status Register 1 and 2 and the interrupt enable
bits are in the SCI Control Register 2.
SCISR1 – Base + $00CC – SCI Status Register 1

Bit 7 6 5 4 3 2 1 0
Read: TDRE TC RDRF IDLE OR NF FE PF
Write:
Reset: 1 1 0 0 0 0 0 0
TDRE
Transmitter Data Register Empty Flag
0 = No byte transferred to the transmit shift register.
1 = Byte has been transferred to the transmit shift register and the transmit data register is empty
(default).
This flag is set when the last character written to the SCI data register (SCDRL) has been transferred to
the output shift register. Normally the program should check this bit before writing the next
character to the SCIDRL. The flag is reset (cleared) by reading the SCISR1 register with TDRE set
and then writing the next byte to the SCIDRL.
TC
Transmit Complete Flag
0 = Transmission in progress.
1 = No transmission in progress (default).
This bit is different than the TDRE bit. It shows when the last character has been completely sent from
the output shift register. The flag is reset (cleared) by reading the SCISR1 register with TC set and
then writing the next byte to the SCIDRL.
RDRF
Receive Data Register Full Flag
0 = Data not available in the SCI data register (default).
1 = Received data is available.
The flag is reset (cleared) by reading the SCISR1 register with RDRF set and then reading SCIDRL
IDLE
Idle Line flag
0 = The receive line is either active now or has never been active since IDLE was last reset
(default).
1 = The receive line has become idle.
The idle flag is cleared by reading SCISR1 (while IDLE = 1) and then reading SCIDRL. After the
IDLE flag has been reset, it will not be set again until the receive line becomes active and then idle
again. When the receiver wakeup bit (RWU) is set, an idle line does not set the IDLE flag.
OR
Receiver Overrun Flag
0 = No overrun error (default).
1 = An overrun has occurred.
Overrun occurs if a new character has been received before the old data have been read by the program.
The new data are lost and the old data preserved. The flag is cleared by reading SCISR1 (with OR =
1) and then reading the SCIDRL.
NF
Noise Flag
0 = No noise was detected during the last character (default).
1 = Noise was detected.
The hardware takes three samples of the received signal near the middle of each data bit and the stop
bit. Seven samples are taken during the start bit. If the samples in each bit do not agree, the noise
flag is set. The flag may be reset by reading SCISR1 (with NF=1) followed by a read of SCIDRL.
FE
Framing Error Flag
0 = No framing error occurred (default).
1 = Framing error occurred.
A framing error occurs if the receiver detects a space during the stop bit time instead of a mark. This
kind of error can occur if the receiver misses the start bit or if the sending and receiving data rates
are not equal. It is possible to have bad framing or mismatched Baud rates but not get a framing
error indication if a mark is detected when a stop bit was expected. The flag is reset by reading
SCISR1 (with FE = 1) and then reading the SCIDRL.
PF
Parity Error Flag
0 = Parity on the last received data is correct (default).
1 = Parity incorrect.
PE is reset by reading SCISR1 with PF set and then reading SCIDRL.
SCI Flag Clearing

All SCI flags are cleared in a two-step operation. First, the status register is read followed
by a read or write to the SCI data register. If the flag has been set, it will be reset by this
operation. The two instructions may have other instructions between them but the order
of operations must be maintained.
SCI Interrupts
The SCI interrupts are enabled by setting bits in the SCICR2 SCI Control Register 2. The
interrupts are serviced by an interrupt service routine whose vector is shown in Table
14-3. There are five potential sources of interrupts shown in Table 14-3 with one
interrupt vector. When an SCI system interrupt occurs, the service routine must test the
SCISR1 status register to find out which condition caused the interrupt. As in the case of
all other interrupting sources, the flag that caused the interrupt must be cleared in the
interrupt service routine. This is done by reading the SCISR1 register and then writing
the next data byte to the SCIDRL.
Table 14-3 SCI Serial System Interrupts
Local Local HPRIO

Vector Interrupt Enable Bit Flag Value to
Priority Address Source (SCICR2) (SCISR1) Promote
20 $FFD6:FFD7 Transmit Data Register Empty TIE TDRE $D6
Transmission Complete TCIE TC
Receive Interrupt (Receive Data Register Full) RIE RDRF
Receive Interrupt (Receiver Overrun) RIE OR
Idle Line Detected ILIE IDLE
SCI Wakeup
The SCI features a sleep and wake up mode. This may be used in multi-receiver
applications in which one M68HCS12 is broadcasting data to many serial receivers in a
network. Software in each receiver puts it to sleep (by setting the RWU bit in the SCICR2
register) until the programmed wake-up sequence is received. At the start of a broadcast,
each receiver automatically wakes up and software in all receivers decodes for whom the
message is intended. Only the addressed station stays awake to receive the message. Each
of the others are put back to sleep until the start of the next broadcast. Receivers that are
asleep do not respond to received data. However, only the SCI receiver is asleep and the
CPU can continue to operate and do other chores. The CPU can wake up the SCI by
resetting the RWU bit to zero although the automatic hardware mechanism normally
wakes up sleeping receivers. The wake up mode and receiver wake up enable are
controlled by bits in SCICR1 and SCICR2.
When the program puts a receiver to sleep by writing a one to the RWU bit, all
receiver interrupts are disabled until the receiver is awakened by one of two wake up
methods. If WAKE = 0, a full character of idle line (a mark) wakes up the receiver. If
WAKE = 1, any byte with a one in the most significant bit wakes it up.
SCI Break Character

The SCI can send a break character, 10 or 11 zeros (depending on the M bit), by the
program writing a one into the SBK bit in the SCICR2 register. Break characters are used
in some systems to wake up the receiving end.
Port S SCI I/O

Port S provides the serial I/O data and control bits. For any serial function not enabled,
the bits may be used for general purpose I/O. The data direction register bits do not have
to be initialized for bit-0 and bit-1 when these bits are in service as RxD and TxD (when
TE and RE are set).
SCI Programming Example

Example 14-1 to Example 14-5 show subroutines for initializing the SCI to operate at
9600 baud, one start and stop bit, and eight data bits with no parity. The example shows
initialization, data output, receiver status check, data input, and an example data output
subroutines.
Example 14-1 SCI Initialization
Metrowerks HC12-Assembler
(c) COPYRIGHT METROWERKS 1987-2003
Rel.Loc Obj. code Source line

---------- --------- -----------
1 ;***************************************
2 ; MC68HCS12 SCI I/O Example
3 ; Initialize SCI 9600,8,N,1
4 ; Assembler routines:
5 ; init_sci, initsci
6 ; C Routines
7 ; void initsci( void);
8 ;***************************************
9 ; Initialize SCI to 1 start, 8 data and 1 stop
10 ; bit, no parity and 9600 Baud.
11 ; Inputs: None
12 ; Outputs: None
13 ; Reg Mod: CCR
14 ;***************************************
15 ; SCI port definitions
16 INCLUDE "sci.inc"
17 XDEF init_sci, initsci
18 ;***************************************
19 init_sci:
20 initsci:
21000000 3B pshd ; Save D reg
22 ; Set 1 start, 8 data and 1 stop bit
23000001 4DCA 10 bclr SCICR1,MODE
24 ; Disable parity for no parity
25000004 4DCA 02 bclr SCICR1,PE
26 ; Enable transmitter and receiver
27000007 4CCB 0C bset SCICR2,TE|RE
28 ; Set Baud rate
2900000A CC00 34 ldd #B9600
3000000D 5CC8 std SCIBDH
3100000F A7 nop
32000010 5CC8 std SCIBDH
33000012 3A puld ; Restore D
34000013 3D rts
35 ;***************************************
Example 14-2 SCI Put Character


---------- --------- -----------
1 ;***************************************
3 ; Put char to SCI 0
5 ; put_sci_0, putchar
6 ; C Routines
7 ; void putchar( char );
8 ;***************************************
9 ; Send SCI data
10 ; Inputs: B register = data to send
11 ; Outputs: None
12 ; Reg Mod: CCR
13 ;***************************************
16 XDEF put_sci, putchar
17 ;***************************************
18 put_sci:
19 putchar:
20 ; Wait until the transmit data reg is empty
21 spin_put:
22000000 4FCC 80FC brclr SCISR1,TDRE,spin_put
23 ; Output the data and reset TDRE
24000004 5BCF stab SCIDRL
25000006 3D rts
26 ;***************************************
Example 14-3 SCI Get Character


---------- --------- -----------
1 ;***************************************
3 ; Get char from SCI
5 ; get_sci, getchar
6 ; C Routines
7 ; char getchar( void );
8 ;***************************************
9 ; Get a character from SCI
10 ; Waits until character has been received
11 ; Inputs: None
12 ; Outputs: B = character
13 ; Reg Mod: B, CCR
14 ;***************************************
17 XDEF get_sci, getchar
18 XREF sci_char_ready
19 ;***************************************
20 get_sci:
21 getchar:
22000000 36 psha
23 wait:
24 ; IF a char is there waiting
25000001 16xx xx jsr sci_char_ready
26000004 24FB bcc wait ; ELSE wait
27 ; THEN get it and return
28000006 D6CF ldab SCIDRL
29000008 32 pula
30000009 3D rts
31 ;***************************************
Example 14-4 SCI Character Ready


---------- --------- -----------
1 ;***************************************
3 ; Check for char in SCI receiver
5 ; sci_char_ready, scichar_ready
6 ; C Routines
7 ; bool scichar_ready(void);
8 ;***************************************
9 ; Check the RDRF flag
10 ; If a character is ready, returns with C=1
11 ; the character in the B register, and the
12 ; status information in the A register.
13 ; Otherwise, C=0 and the A and B regs 0
14 ; Inputs: None
15 ; Outputs: B = character, Carry bit T or F
16 ; A = status information
17 ; Reg Mod: A,B CCR
18 ;***************************************
21 XDEF sci_char_ready
22 XDEF scichar_ready
23 ;***************************************
24 sci_char_ready:
25 scichar_ready:
26000000 10FE clc ; Clear carry
27000002 87 clra ; Clear A
28000003 C7 clrb ; Clear B
29 ; IF RDRF is set
30000004 4FCC 2006 brclr SCISR1,RDRF,exit_ready
31 ; THEN the character is there
32000008 D6CF ldab SCIDRL ; Get the data
3300000A 96CC ldaa SCISR1 ; Get the status
3400000C 1401 sec ; Set the carry
35 ; ENDIF
36 exit_ready:
3700000E 3D rts
38 ;***************************************
Example 14-5 SCI Put String


---------- --------- -----------
1 ;***************************************
3 ; Output null terminated string
5 ; put_str, putstr
6 ; C Routines
7 ; int putstr( char *);
8 ;***************************************
9 ; Put null terminated string to sci
10 ; Inputs: D = starting address of string
11 ; Outputs: D = number of characters printed
12 ; Reg Mod: D, CCR
13 ;***************************************
16 XDEF put_str, putstr
17 XREF putchar
18 ;***************************************
19 put_str:
20 putstr:
21000000 34 pshx
22000001 35 pshy
23000002 B745 tfr d,x ; Initialize pointer to string
24 ; Use the Y register as counter of chars printed
25000004 CD00 00 ldy #0 ; Initialize counter
26 ; WHILE character to print is not a null
27 while_do:
28000007 E600 ldab 0,x
29000009 2707 beq done
30 ; DO
31 ; Print the character
3200000B 16xx xx jsr putchar
33 ; Increment the counter and pointer
3400000E 02 iny
3500000F 08 inx
36000010 20F5 bra while_do
37 done:
38000012 31 puly
39000013 30 pulx
40000014 3D rts
41 ;***************************************
14.3 Synchronous Serial Peripheral Interface (SPI)

The SPI is designed to send high-speed serial data to peripherals and other SPI equipped
MCUs and digital signal processors.

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Chapter 14 – M68HCS12 Serial I/O 14-1

This chapter discusses the M68HCS12 serial I/O capabilities. The

14.2 Asynchronous Serial Communications Interface (SCI)

PTS -- Base + $0248 – Port S I/O Register

Figure 14-2 SCI data registers.

SCIDRH – Base + $00CE – SCI Data Register High

SCIDRL – Base + $00CF – SCI Data Register Low

SCICR2 – Base + $00CB – SCI Control Register 2

SCI Mode Control

SCICR1 – Base + $00CA – SCI Control Register 1

Table 14-1 Loop Functions

LOOPS RSRC Function

SCI Loop Mode

SCISR2 – Base + $00CD – SCI Status Register 2

SCI Baud Rate Selection

SCIBDH – Base + $00C8 – SCI Baud Rate Register High

Table 14-2 Baud Rates (8 MHz Bus Clock)

Baud Rate SBR12:SBR0 10

SCI Status Flags

SCISR1 – Base + $00CC – SCI Status Register 1

SCI Flag Clearing

Table 14-3 SCI Serial System Interrupts

Local Local HPRIO

SCI Break Character

Port S SCI I/O

SCI Programming Example

Example 14-1 SCI Initialization

Rel.Loc Obj. code Source line

Example 14-2 SCI Put Character

Rel.Loc Obj. code Source line

Example 14-3 SCI Get Character

Rel.Loc Obj. code Source line

Example 14-4 SCI Character Ready

Rel.Loc Obj. code Source line

Example 14-5 SCI Put String

Rel.Loc Obj. code Source line

14.3 Synchronous Serial Peripheral Interface (SPI)

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