Verification of Truth Tables For Logic Gates

VFSTR UNIVERSITY DEPT OF ECE
Expt. No: 1
Verification Of Truth Tables For Logic Gates
Aim: To verify the truth table of basic digital ICs of NAND, NOR, NOT, AND, OR, EX-OR
gates (7400, 7402, 7404, 7408, 7432,7486).
Apparatus:
S.No Name of the Range Quantity

Apparatus
1. Digital IC trainer kit 1
2. NAND gate IC 7400 1
3. NOR gate IC 7402 1
4. NOT gate IC 7404 1
5. AND gate IC 7408 1
6. OR gate IC 7432 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
I. NAND Gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’
if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.
a. Logic Diagram:
Fig 1.10 Logic Diagram of NAND Gate.
b. PIN DIAGRAM OF IC 7400:
Fig 1.11 Pin Diagram of IC 7400.
DIGITAL ELECTRONICS LAB Page 1 of 69

c. Circuit Diagram:
Fig 1.12 Circuit Diagram of NAND Gate.
d. TRUTH TABLE (NAND Gate): Practical Values:
INPUT OUTPUT INPUT OUTPUT

S.No S.No
A B Y = (A. B)’ A(V) B(V) Y = (A. B)’ (V)
1. 0 0 1 1.
2. 0 1 1 2.
3. 1 0 1 3.
4. 1 1 0 4.

II. NOR Gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all
the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.
a. Logic Diagram:
Fig 1.13 Logic Diagram of NOR Gate.
c. Circuit Diagram:
Fig 1.15 Circuit Diagram of NOR Gate.
d. TRUTH TABLE (NOR Gate): Practical Values:
INPUT OUTPUT S.No INPUT OUTPUT

S.No
A B Y = (A+ B)’ A(V) B(V) Y = (A+ B)’ (V)
1. 0 0 1 1.
2. 0 1 0 2.
3. 1 0 0 3.
4. 1 1 0 4.

III. AND Gate:

An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.
a. Logic Diagram:
Fig 1.1 Logic Diagram of AND Gate.
c. Circuit Diagram:
Fig 1.3 Circuit Diagram of AND Gate.
d. TRUTH TABLE (AND Gate): Practical Values:

S.No S.No
A B Y = A. B A(V) B(V) Y = A. B(V)
1. 0 0 0 1.
2. 0 1 0 2.
3. 1 0 0 3.
4. 1 1 1 4.
IV. OR Gate:

An OR gate is the physical realization of the logical addition operation. It is an

electronic circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.

a. Logic Diagram:
Fig 1.4 Logic Diagram of OR Gate.
c. Circuit Diagram:
Fig 1.6 Circuit Diagram of OR Gate.
d. TRUTH TABLE (OR Gate): Practical Values:
S.No INPUT OUTPUT INPUT OUTPUT

S.No
A B Y=A+B A(V) B(V) Y = A+B(V)
1. 0 0 0 1.
2. 0 1 1 2.
3. 1 0 1 3.
4. 1 1 1 4.

V. NOT Gate:
A NOT gate is the physical realization of the complementation operation. It is an
electronic circuit which generates an output signal which is the reverse of the input signal. A
NOT gate is also known as an inverter because it inverts the input.
a. Logic Diagram:
Fig 1.7 Logic Diagram of NOT Gate.
c. Circuit Diagram:
Fig 1.9 Circuit Diagram of NOT Gate.
d. TRUTH TABLE (NOT Gate): Practical Values:

S.No S.No
A Y=A’ A(V) Y = A’(V)
1. 0 1 1.
2. 1 0 2.

VI. EX-OR Gate:

An Ex-OR gate performs the following Boolean function,
A B = ( A . B’ ) + ( A’ . B )
It is similar to OR gate but excludes the combination of both A and B being equal to one. The
exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal
either ‘0’ or ‘1’.
a. Logic Diagram:
Fig 1.16 Logic Diagram of EX-OR Gate.
c. Circuit Diagram:
Fig 1.18 Circuit Diagram of EX-OR Gate.
d. TRUTH TABLE (NOR Gate): Practical Values:

S.No S.No
A B Y  A ⊕B A(V) B(V) Y  A ⊕B (V)
1. 0 0 0 1.
2. 0 1 1 2.
3. 1 0 1 3.
4. 1 1 0 4.

Procedure:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. To verify the truth table of basic digital ICs.
VHDL CODE :
library ieee;
use ieee.std_logic_1164.all; use
ieee.std_logic_arith.all; use
ieee.std_logic_unsigned.all;
entity gates is
port (a_in,b_in: in std_logic;
not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op:
out std_logic);
end gates;
architecture dataflow of gates is

begin
not_op<= not a_in; and_op<=
a_in and b_in; nand_op<=
a_in nand b_in; or_op<= a_in
or b_in; nor_op<= a_in nor
b_in; xor_op<= a_in xor b_in;
xnor_op<= a_in xnor b_in;
end ;
Modelsim Output

Result:
Model Review Questions:
1. Why do you call NAND and NOR gates as Universal gates?

2. Design Ex-OR Gate using only NAND Gates.
3. Explain the significance of K-Map.
4. Design Ex-NOR Gate using only NOR Gates.
5. Design an Inverter using only the Universal Gates.
6. What is the difference between logic gate and sample gate.
7. What are the applications of Logic gates.

Date:
Expt. No: 2
HALF ADDER, FULL ADDER USING LOGIC GATES

Aim: To design and verify the truth table of the Half Adder, Full Adder, circuits.
Apparatus:

Apparatus
I. HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder. The
input variables designate the augend and the addend bit, whereas the output variables produce
the sum and carry bits.
a. CIRCUIT DIAGRAM:
Fig 2.1 Logic Diagram of Half Adder.
b. TRUTH TABLE (Half Adder): Practical Values:
INPUT OUTPUT S.No INPUT OUTPUT

S.No
A B S C A (V) B (V) S (V) C (V)
1. 0 0 0 0 1.
2. 0 1 1 0 2.
3. 1 0 1 0 3.
4. 1 1 0 1 4.
c. DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as,
Sum, S = A B
Carry, C = A . B
II. FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called
full adder. The three input bits include two significant bits and a previous carry bit. A full adder
circuit can be implemented with two half adders and one OR gate.
a. CIRCUIT DIAGRAM:
Fig 2.2 Logic Diagram of Full Adder.
b. TRUTH TABLE (Full Adder): Practical Values:
INP
UT OUTPUT INPUT OUTPUT
S.No S.No
A B S C A B S (V) C (V)
1. 0 0 0 0 1. 0 0
2. 0 0 1 1 2. 0 0
3. 0 1 0 1 3. 0 1
4. 0 1 1 0 4. 0 1
5. 1 0 0 1 5. 1 0
6. 1 0 1 0 6. 1 0
7. 1 1 0 0 7. 1 1
8. 1 1 1 1 8. 1 1

c. DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained
as, SUM = A’B’C + A’BC’ + AB’C’ + ABC
CARRY = A’BC + AB’C + ABC’ +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM
SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C
CARRY
CARRY = AB + AC + BC
Procedure:
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
VHDL CODE (HALF ADDER):
library ieee;
entity halfadder is
port (a_in, b_in: in std_logic;
sum, carry: out std_logic);
end halfadder;
architecture dataflow of halfadder is
begin
sum <= a_in xor b_in;
carry<= (a_in and b_in);
end dataflow;
VHDL CODE (FULL ADDER):
library ieee;
entity fulladder is
port (a_in, b_in, c_in: in std_logic;
sum, carry: out std_logic);
end fulladder;
architecture dataflow of fulladder is
begin
sum <= a_in xor b_in xor c_in;
carry<= (a_in and b_in) or (b_in and c_in) or (a_in and
b_in);
end dataflow;
Result:


1. What is meant by half and full adder?
2. What is meant by Karnaugh map?
3. What are the ICs required for constructing adder and s circuit?
4. How many half adders are there in a full adder?
5. What is mean by SOP and POS?
6. List out the various types of k-maps.
7. What is the maximum possible grouping in a four variable k-map?
8. What are the various laws of Boolean algebra?

Date:
Expt. No: 3
HALF SUBTRACTOR
Aim: To design and verify the truth table of the Half subtractor, Full subtractor, circuits.
Apparatus:

Apparatus
Hex invertor(NOT
4. Gate) IC 7404 1
I. HALF SUBTRACTOR:
The half-subtractor is a combinational circuit which is used to perform subtraction of two
bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B
(borrow).
a. CIRCUIT DIAGRAM:
Fig 2.1 Logic Diagram of Half subtractor.
b. TRUTH TABLE (Half Subtractor): Practical Values:

S.No S.No
X Y D B X (V) Y (V) D (V) B (V)
1. 0 0 0 0 1.
2. 0 1 1 1 2.
3. 1 0 1 0 3.
4. 1 1 0 0 4.

d. DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as,
Sum, S = A B
Carry, C = A . B’
Procedure:
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
VHDL CODE:
library IEEE;
use
IEEE.STD_LOGIC_1164.A
LL; use IEEE.STD_LOG
IC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED
.ALL; entity hs is
Port ( a, b : in
std_logic;
d, br : out
std_logic)
;
end hs;
architecture dataflow of hs is
begin
d<= a xor b;
br<= (not a) and b;
end dataflow;
Result:


1. What is the expression for borrow of A, B in the half subtractor ?
2. What is the expression for the difference of full subtractor circuit?
3. What is the expression for difference of A, B in the half subtractor?
4. What is the expression for the borrow of full subtractor circuit?
5. FULL Subtractor require how many half subtractors?

Experiment: 4
ENCODER
Aim: To Design and verify the truth table of code conversion from binary to gray code (4
bit) using basic Logic Gates.
Apparatus Required:
 Designer kit
 Digital ICs:7486: Quad 2 input EXOR
 Connecting Wires
Pin Diagram:
Fig 4.1:Pin diagram of Binary to gray code converter using 7486 Ic(Exor Gate)
Theory:
Code Converters:A code converter is a circuit that makes two digital systems using different
codes for the same information. It means that a code converter is a code translator from one
code to the other. The code converter is used since to systems using two different codes but
they need to use the same information. So the code converter is the solution.
Binary-to Gray Converter: An interesting application for the exclusive-OR gate is a logic
gate to change a binary number to its equivalent in Gray Code. The logic circuit can be used to
convert a 4-bit binary number ABCD into its Gray-code equivalent, G1, G2, G3 and G4.
Circuit Diagram:
Fig 4.2: Circuit Diagram of Binary to Gray Code Converter

Truth Table:
INPUTS OUTPUTS
A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Procedure :
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. Make connections as shown in the respective circuit diagram.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the breadboard
8. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1 is
OFF Apply the various combination of inputs according to the truth tabe and obseve the
condition of Output LEDs.
Observation Table: Input Variable: A B C D
Output Variable: G3 G2 G1 G0
LED ON: RED Light:Logic 1
LED OFF: Green Light:Logic 0

INPUTS(LED) OUTPUTS(LED)
A B C D G3 G2 G1 G0
Calculation:
Kmap Simplification:
For G3
For G2
For G1
For G0
Boolean Expression: G3 =
G2 =
G1 =
G0=

VHDL CODE :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use
entity binary_gray is
port(b_in: in std_logic_vector(3 downto
0); g_op: out std_logic_vector (3 downto
0)); end binary_gray;
architecture dataflow of binary_gray
is begin
g_op(3)<= b_in(3);
g_op(2)<= b_in(3) xor b_in(2);
end;
Result:
Lab tutorial
1) Gray code is also known as
2) The Gray code for number 7 is:
3) What are the gray codes?
4) What are the properties of Gray codes?
5) What is the advantages and application of Gray codes?

6) Convert 1100 into binary code?
7) Convert 1101 into Gray Code?

Experiment: 5
DECODER
Aim: To Design and verify the truth table of code conversion from gray to binary code (4
bit) using basic Logic Gates.
Apparatus Rgequired:
 Trainer Kit
Pin Diagram:
Fig 5.1:Pin diagram of Gray to Binary code converter using 7486 Ic(Exor Gate)
Theory:
Code Converters:A code converter is a circuit that makes two digital systems using different
codes for the same information. It means that a code converter is a code translator from one
code to the other. The code converter is used since to systems using two different codes but
they need to use the same information. So the code converter is the solution.
Gray-to Binary Converter:An interesting application for the exclusive-OR gate is a logic gate
to change a gray number to its equivalent in binary Code. The logic circuit can be used to
convert a 4-bit gray number ABCD into its binary-code equivalent, B3,B2,B1 and B0.
Application: Some sensors send information in Gray code. These must be converted to
binary in order to do arithmetic with it. Occasionally, it is necessary to convert back.
Advantages: Higher speed or smaller code.

Circuit Diagram:
Fig 5.2: Circuit Diagram of Binary to Gray Code Converter
Truth Table of Binary to Gray Code Converter:

INPUTS OUTPUTS
A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Procedure :
and PIN14 = +5V.

Observation Table: Input Variable: A B C D
Output Variable: B3 B2 B1 B0
INPUTS(LED) OUTPUTS(LED)
A B C D B3 B2 B 1 B0
Calculation:
Kmap Simplification:
For B0 For B1

For B2 For B3
Boolean Expression: B3 =
B2 =
B1 =
B0=
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gray2binary is
Port ( g : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end gray2binary;
architecture Behavioral of gray2binary is

begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(3) xor g(2) xor g(1);
b(0)<= g(3) xor g(2) xor g(1) xor g(0);
end behavioral;
Result :

Lab tutorial
1) Gray code equivalent of binary 010 is:
2) Ques1: What are code converters?
3) What is the need of code converter?
4) Design 3-bit gray to binary code converter ?
5) Convert 1100 into gray code?
6) Convert 1101 into binary Code?

Experiment:
MULTIPLEXER AND DEMULTIPLEXER
Aim: a) To find the Truth Table of 4:1 Multiplexer using IC 74153
b) To find the Truth Table of 1:4 Demultiplexer using IC 74139
Apparatus Required:
 Digital IC Trainer kit

 Digital ICs:74153:Dual 4:1 MUX
74139:Dual 1:4 DEMUX
Pin Diagram:
Fig 8.1:Pin diagram of dual 4:1 Mux (IC 74153)

Fig 8.2: Pin diagram of Dual 1:4 DEMUX (IC74139)

Theory:
Multiplexer: A data selector, more commonly called a Multiplexer, shortened to "Mux" or

"MPX", is combinational logic switching devices that operate like a very fast acting multiple
position rotary switches. They connect or control, multiple input lines called "channels"
consisting of either 2, 4, 8 or 16 individual inputs, one at a time to an output. Then the job of a
multiplexer is to allow multiple signals to share a single common output. For example, a single
8-channel multiplexer would connect one of its eight inputs to the single data output.
Ref: http://www.electronics-tutorials.ws/combination/comb_3.html
The Boolean expression for this 4-to-1 Multiplexer above with inputs I0 to I3 and data select
lines S0 ,S1 is given as:
Y = S0S1I0 + S0S1I1 + S0S1I2 + S0S1I3

Multiplexer Symbol:
Truth Table of 4:1 Mux(IC 74153)( Channel A) with Active low mode:
Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
1 × × × × × × 0
0 0 × × × 0 0 0
0 1 × × × 0 0 1
0 × 0 × × 0 1 0
0 × 1 × × 0 1 1
0 × × 0 × 1 0 0
0 × × 1 × 1 0 1
0 × × × 0 1 1 0
0 × × × 1 1 1 1
Demultiplexer: The data distributor, known more commonly as a Demultiplexer or "Demux",

is the exact opposite of the Multiplexer. The demultiplexer takes one single input data line and
then switches it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel data at its output lines

1-to-4 Channel De-multiplexer
Ref: http://www.electronics-tutorials.ws/combination/comb_3.html
The Boolean expression for this 1-to-4 Demultiplexer above with outputs D0 to D3 and data
select lines S0 , S1 is given as:
E = S0S1 D0 + S0S1 D1 + S0S1 D2 + S0S1 D3
The function of the Demultiplexer is to switch one common data input line to any one of the 4
output data lines. Some standard demultiplexer IC´s also have an "enable output" input pin
which disables or prevents the input from being passed to the selected output. Also some have
latches built into their outputs to maintain the output logic level after the address inputs have
been changed. However, in standard decoder type circuits the address input will determine
which single data output will have the same value as the data input with all other data outputs
having the value of logic "0".
Truth table of 1:4 Demux(IC 74139) with Active low mode :
Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
1 × × 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Procedure:


and PIN14 = +5V.
Observation Table:
Multiplexer:: Input Variable: Ea, Ia0, Ia1, Ia2, Ia3
Selecct lines: S0, S1
Output Variable: Za
Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
Demultiplexer: Input Variable: Ea, S0, S1

Output Variable: D0, D1, D2, D3

Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
VHDL CODE(DE MUX)
entity demux is
Port ( I,en : in std_logic;
sel: in std_logic_vector(1
downto 0);
y:outstd_logic_vector(3d
ownto0));
end demux;
architecture dataflow of
demux is signal x:
std_logic_vector( 1 downto
0); begin
x<= en & a;
y <="0001" when sel="00" and x="01" else
"0010" when sel="01" and x="01" else
"0000";
end dataflow;
VHDL CODE(MUX):
entity mux4to1 is
port( A,B,C,D: in std_logic;
S: in std_logic_vector(1 downto 0);
O: out std_logic);
end mux4to1;
Architecture behavioral of mux4to1 is

begin
Process(S,A,B,C,D)
variable temp:std_logic;

Begin
case S is
when "00" => temp:=A;

when "01" => temp:=B;
when "10" => temp:=C;
when Others => temp:=D;
end case;
O<=temp;
end Process;
end behavioral;
Result:
Lab tutorial
1) The IC number of Dual 4:1 MUX is
2) IC number of Dual 1:4 DEMUX is
3) Multiplexer is also known as :
4) Demultiplexer is also known as:
5) Multiplexer converts:
6) Demultiplexer converts:
7) Differentiate between Multiplexer and demultiplexer?
8) What is the role of select lines in multiplexer?
9) How can a decoder be used as a demultiplexer?
10) What are the applications of MUX and DEMUX?

Experiment: 8
Aim: To Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity
Checker using basic Logic Gates with an even parity bit.
Apparatus Required:
 Trainer kit
Pin Diagram:
Fig 6.1:Pin diagram of 3-Bit Even Parity Generator using 7486 Ic(Exor Gate)

Fig 6.2: Pin diagram of 4-Bit Even Parity Checker using 7486 Ic(Exor Gate)
Theory:
Parity bits are extra signals which are added to binary information to enable error checking.
There are two types of Parity - even and odd. An even parity generator will produce a logic 1
at its output if the data word contains an odd number of ones. If the data word contains an even
number of ones then the output of the parity generator will be low. By concatenating the Parity
bit to the dataword, a word will be formed which always has an even number of ones i.e. has
even parity.
If a dataword is sent out with even parity, but has odd parity when it is received then
the data has been corrupted and must be resent. As its name implies the operation of an Odd
Parity generator is similar but it provides odd parity. A parity bit can be added to code either
at the beginning or at the end depending on the system design. However the total number of
1’s including parity bit is even for even parity and odd for odd parity.

The parity detector can detect a single error or an odd number of errors but cannot check
for two errors. Parity is used on communication links (e.g. Modem lines) and is often included
in memory systems. The message is transmitted and then checked at the receiving end for
errors. For this purpose a circuit is required which generates parity bit in the transmiter and
check the receiving message for errors.
Circuit Diagram:
Fig 6.3: Circuit Diagram of 3-bit parity generator(Even parity)
Fig 6.4: Circuit Diagram of 4-Bit parity checker (Even Parity)
Truth Table of 3-bit Even parity Generator:

Input Output
A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Truth Table of 4-bit Even parity Checker:

Input Output
A B C P Ch
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Procedure:
and PIN14 = +5V.
Observation Table:
Parity Generator: Input Variable: A,B,C
Output Variable: P

Input Output
A B C P
Parity checker: Input Variable: A, B, C, P

Output Variable: Ch
Input Output
A B C P Ch

Calculation:
Parity Generator:
K Map Simplification:
Parity Checker:
K Map Simplification:
Boolean Expression: Parity Generator P =
Parity Checker Ch =
VHDL CODE(PARITY GENERATOR)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity parity_gen_data is
port(
d0 : in STD_LOGIC;
d1 : in STD_LOGIC;
d2 : in STD_LOGIC;
d3 : in STD_LOGIC;
parity_even : inout STD_LOGIC;
parity_odd : out STD_LOGIC
);
end parity_gen_data;
--}} End of automatically maintained section
architecture parity_gen_data of parity_gen_data is

signal d4,d5: std_logic;

begin
d4 <= d0 xor d1;
d5 <= d4 xor d2;
parity_even <= d5 xor d3;
parity_odd <= not parity_even;
end parity_gen_data;
VHDL CODE(PARITY CHECKER)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity perity_checker is
port(
d3 : in STD_LOGIC;
d2 : in STD_LOGIC;
d1 : in STD_LOGIC;
d0 : in STD_LOGIC;
parity_even : in STD_LOGIC;
parity_even_checker : out STD_LOGIC
);
end perity_checker;
--}} End of automatically maintained section
architecture perity_checker of perity_checker is

signal d4,d5,d6: std_logic;
begin
d4 <= d3 xor d2;
d5<= d4 xor d1;
d6<= d5 xor d0;
parity_even_checker <= d6 xor parity_even;

-- enter your statements here --
end perity_checker;
Result :
Lab tutorial
1) What is the need of parity generator and parity checker ?
2) Why can’t the parity method detect even number of error in transmitted
data ?
3) Design 3-bit parity generator and 4-bit parity checker circuit for odd
parity?
4) What is the difference between odd parity and even parity?
5) Distinguish between error correcting codes and error detecting codes?

Experiment
Comparator
Aim: To Design, implement and Simulate the 4 bit comparator.
Theory:
A comparator used to compare two 4-bit words. The two 4-bit numbers are word A: A3A2A1A0, and word B:
B3 B2B1B0) So the circuit has 8 inputs and 3 binary outputs: A>B, A=B and A
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or
equal to the value at input B etc. The digital comparator accomplishes this using several logic
gates that operate on the principles of Boolean Algebra. There are two main types of Digital
Comparator available and these are.
 1. Identity Comparator – an Identity Comparator is a digital comparator that has only
one output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which
has three output terminals, one each for equality, A = B greater than, A > B and less
than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers,
for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such
as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the
result of the comparison. For example, a magnitude comparator of two 1-bits, (A and B)
inputs would produce the following three output conditions when compared to each other.
Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when any
of the above three conditions are achieved. For example, produce an output from a counter
when a certain count number is reached. Consider the simple 1-bit comparator below.
Logic diagram

WORKING:
Equality: Word A equal word B iff: A3=B3, A2=B2, A1=B1, A0=B0.
Inequality:
 If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
 If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
 If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
 If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and B0 = 0, then A > B.
 If A3 = 0 and B3 = 1, then A is less than B (A< B. Or
 If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 0, and B1 = 1, then A< B.
Procedure:
1. Check all the components for their working.
2. Insert the appropriate ICs into the IC base.
3. Make connections as shown in the circuit diagram
4. Verify the Truth Table and observe the outputs.
5. Repeat the same steps but for the circuit diagram and apply inputs in the following table, also record the
output at each:

Observation table
VHDL CODE:
VHDL CODE :
library ieee;
use
entity comparator is
port (a_in, b_in: in std_logic_vector (3 downto 0)
; g_op, e_op, L_op: out std_logic);
end comparator;
architecture behavioral of comparator

is begin
process (a_in,
b_in) begin
if (a_in<b_in)
then L_op<= '1';
else
L_op<=
'0'; end if;
if (a_in>b_in)

then g_op<= '1';

else
g_op<=
'0'; end if;
if (a_in = b_in)
then e_op<= '1';
else
e_op<=
'0'; end if;
end process;
end;
RESULT:
1. Which gate is used as a basic comparator?

2. If two numbers are not equal then binary variable will be

Expt. No: 4
Design and Implementation of JK FF, RS FF, D and T Flip-flops

Aim: To verify the characteristic table of RS, D, JK, and T Flip flops.
Apparatus:
S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit -- 1
3. NOT gate IC 7404 1
4. NAND gate IC 7400 1
5. NOR gate IC 7402 1
6. -- Connecting wires
I. RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state
with respect to the input on application of clock pulse. When the clock pulse is high the S
and R inputs reach the second level NAND gates in their complementary form. The Flip
Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input
is high and R input is low. When both the inputs are high the output is in an indeterminate
state.
a. LOGIC SYMBOL:
Fig. 3.1. Logic Symbol of RS Flip Flop.

b. CIRCUIT DIAGRAM:
Fig 3.5 Circuit Diagram of RS Flip Flop.

c. CHARACTERISTIC TABLE:
CLOCK INPUT PRESENT NEXT STATUS

PULSE S R STATE (Q) STATE(Q+1)
0 0 NC NC NO CHANGE
0 0 NC NC
0 1 0 0 RESET
0 1 1 0
1 0 0 1 SET
1 0 1 1
1 1 X X UNDEFINED
1 1 X X
Practical Values:

PULSE S (V) R (V) STATE (Q) (V) STATE(Q+1) (V)
II. D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop
when both inputs are high at the same time, in the D Flip Flop the inputs are never made
equal at the same time. This is obtained by making the two inputs complement of each
other.
a. LOGIC SYMBOL:
Fig. 3.3. Logic Symbol of D Flip Flop.
b. CIRCUIT DIAGRAM:
Fig. 3.4 Circuit Diagram of D Flip Flop.


PULSE D STATE (Q) STATE(Q+1)
0 0 0
0 1 0
1 0 1
1 1 1
Practical Values:

PULSE D (V) STATE (Q) STATE(Q+1)
III. JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K
input and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock
pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q’
output retain their previous values. When the clock pulse is high, the J and K inputs reach
the NOR gates. When both the inputs are high the output toggles continuously. This is
called Race around condition and this must be avoided.
a. LOGIC SYMBOL:
Fig. 3.5. Logic Symbol of JK Flip Flop.
b. CIRCUIT DIAGRAM:
Fig. 3.6.Circuit Diagram of JK Flip Flop.


PULSE J K STATE (Q) STATE(Q+1)
0 0 0 0 NO CHANGE
0 0 1 1
0 1 0 0 SET
0 1 1 0
1 0 0 1 RESET
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
Practical Values:

PULSE J (V) K (V) STATE (Q) (V) STATE(Q+1) (V)
IV. T FLIP FLOP:

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K
inputs together. T Flip Flop is also called Toggle Flip Flop.
a. LOGIC SYMBOL:
Fig. 3.7. Logic Symbol of T Flip Flop.

b. CIRCUIT DIAGRAM:
Fig. 3.8. Circuit Diagram of T Flip Flop.

PULSE T STATE (Q) STATE(Q+1)
1 0 0 0
2 0 1 0 TOGGLE
3 1 0 1
4 1 1 0
Practical Values:

PULSE T (V) STATE (Q) (V) STATE(Q+1) (V)
1
2
3
4
Procedure:
3. Apply the inputs and observe the status of all the flip flops.

VHDL CODE(SR-FF) :
library ieee;
use
entity srff is
port (rst, clk: in std_logic;
sr: in std_logic_vector (1 downto
0); q, qb: inout std_logic);
end srff;
architecture behavioral of srff
is begin
process
(clk) begin
if (rst=’1’) then
q<=’0’;
qb<=’1’;
elsif (rising_edge (clk))
then case (sr) is
when”00”=>q<=q; qb<=qb;
when”01”=>q<=’0’; qb<=’1’;
when”10”=>q<=’1’; qb<=’0’;
when”11”=>q<=’Z’; qb<=’Z’;
when others=>null;
end
case; end if;
end process;
end behavioral;
VHDL CODE (D-FF):
library ieee;
use

entity dff is
port (clk, rst: in std_logic;
d: in std_logic;
q, qb:out
std_logic); end dff;
architecture behavioral of dff
is begin
process
(clk) begin
if rst=’1’
then
q<=’0’;
qb
<=’1’;
elsif (rising_edge (clk))
then q<=d;
qb<=not
(d); end if;
end process;
end;
Result:
VHDL CODE (JK-FF):
library ieee;
use
entity jkff is
port (clk, rst: in bit;
jk: in bit_vector (1 downto
0); q, qb: inout bit);

end jkff;
architecture behavioral of jkff is
signal div: std_logic_vector(22 downto
0); signal clkdiv:std_logic;
begin
process(clk)
is begin
if rising_edge (clk)
then
div<=div+’1’;
end if;
end process;
clkdiv<=div(22);
process (clkdiv,
rst) begin
if (rst='1')
then
q<='0';
qb<=’1’;
elsif (rising_edge (clkdiv))
then case (jk) is
when”00”=>q<=q; qb<=qb;
when”01”=>q<=’0’; qb<=’1’;
when”10”=>q<=’1’; qb<=’0’;
when”11”=>q<=not(q);
qb<=not(qb); when others=>null;
end
case; end if;
end
process;
end ;
VHDL CODE(T-FF) :
library ieee;
use
entity tff is
port (t: in std_logic;
clk, rst: in std_logic;
q, qb: inout
std_logic);
end tff;
architecture behavioral of tff is
signal div:std_logic_vector(22 downto
0); signal clkdiv:std_logic;
begin
process
(clk) begin
if (rising_edge(clk))
then div<=div+’1’;
end if;
end process;
clkdiv<=div(22)
; process
(clkdiv) begin
if (rst=’1’) then
q<=’0’;
qb<=’1’;
elsif (rising_edge(clkdiv))
then case (t )is
when ’0’=>q<=q; qb<=qb;
when ’1’=>q<=not(q);
qb<=not(qb); when others=>null;
end
case;
end if;
end
process; end ;
RESULT:

1. What are the basic logic gates?
2. What is mean by universal logic gates?
3. How many bits a flip flop can store?
4. What is mean by RS flip flop?
5. What is the different between RS and JK flip flop?

6. What will be the output of D-Flip flop if the input is zero?

7. NAND gate is a combination of _____________________
8. What is the use of flip-flops?
9. How many OR gate and NOT gate needed for constructing a NOR gate?
10. What is the different between a truth table and a characteristics table?
11. Why are the gates used in manufacturing ICs?
12. Why the digital circuit always represents 1s and 0s?

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35
THEORY:
A register is capable of shifting its binary information in one or both
directions is known as shift register. The logical configuration of shift register
consist of a D-Flip flop cascaded with output of one flip flop connected to input
of next flip flop. All flip flops receive common clock pulses which causes the shift
in the output of the flip flop. The simplest possible shift register is one that
uses only flip flop.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN

COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35
THEORY:
A counter is a register capable of counting number of clock pulse arriving
at its clock input. Counter represents the number of clock pulses arrived. An
up/down counter is one that is capable of progressing in increasing order or
decreasing order through a certain sequence. An up/down counter is also called
bidirectional counter. Usually up/down operation of the counter is controlled by
up/down signal. When this signal is high counter goes through up sequence and
when up/down signal is low counter follows reverse sequence.
K MAP:

STATE DIAGRAM:
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:
TRUTH TABLE:
Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the 3 bit synchronous up/down counter was designed and
implemented using the IC7476.

ASYNCHRONOUS COUNTER DESIGN AND MOD-N COUNTER
Aim: - Realization of 3-bit Asynchronous counter and Mod-N counter

design .
.
Apparatus Required: -
IC 7408, IC 7476, IC 7400, IC 7432 etc.
Procedure: -
1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is
observed at QA, QB & QC for IC 7476.
3. Verify the Truth table .
Circuit Diagram:



Result:-

Verification of Truth Tables For Logic Gates

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VFSTR UNIVERSITY DEPT OF ECE

Verification Of Truth Tables For Logic Gates

S.No Name of the Range Quantity

Fig 1.10 Logic Diagram of NAND Gate.

b. PIN DIAGRAM OF IC 7400:

Fig 1.11 Pin Diagram of IC 7400.

DIGITAL ELECTRONICS LAB Page 1 of 69

Fig 1.12 Circuit Diagram of NAND Gate.

d. TRUTH TABLE (NAND Gate): Practical Values:

INPUT OUTPUT INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 2 of 69

II. NOR Gate:

Fig 1.13 Logic Diagram of NOR Gate.

b. PIN DIAGRAM OF IC 7402:

Fig 1.14 Pin Diagram of IC 7402.

Fig 1.15 Circuit Diagram of NOR Gate.

d. TRUTH TABLE (NOR Gate): Practical Values:

INPUT OUTPUT S.No INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 3 of 69

III. AND Gate:

Fig 1.1 Logic Diagram of AND Gate.

b. PIN DIAGRAM OF IC 7408:

Fig 1.2 Pin Diagram of IC 7408.

Fig 1.3 Circuit Diagram of AND Gate.

d. TRUTH TABLE (AND Gate): Practical Values:

INPUT OUTPUT INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 4 of 69

An OR gate is the physical realization of the logical addition operation. It is an

DIGITAL ELECTRONICS LAB Page 5 of 69

Fig 1.4 Logic Diagram of OR Gate.

b. PIN DIAGRAM OF IC 7432:

Fig 1.5 Pin Diagram of IC 7432.

Fig 1.6 Circuit Diagram of OR Gate.

d. TRUTH TABLE (OR Gate): Practical Values:

S.No INPUT OUTPUT INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 6 of 69

Fig 1.7 Logic Diagram of NOT Gate.

b. PIN DIAGRAM OF IC 7404:

Fig 1.8 Pin Diagram of IC 7404.

Fig 1.9 Circuit Diagram of NOT Gate.

d. TRUTH TABLE (NOT Gate): Practical Values:

INPUT OUTPUT INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 7 of 69

VI. EX-OR Gate:

Fig 1.16 Logic Diagram of EX-OR Gate.

b. PIN DIAGRAM OF IC 7486:

Fig 1.17 Pin Diagram of IC 7486.

Fig 1.18 Circuit Diagram of EX-OR Gate.

d. TRUTH TABLE (NOR Gate): Practical Values:

INPUT OUTPUT INPUT OUTPUT

DIGITAL ELECTRONICS LAB Page 8 of 69

architecture dataflow of gates is

DIGITAL ELECTRONICS LAB Page 9 of 69

Model Review Questions:

1. Why do you call NAND and NOR gates as Universal gates?

DIGITAL ELECTRONICS LAB Page 10 of 69

HALF ADDER, FULL ADDER USING LOGIC GATES

S.No Name of the Range Quantity

Fig 2.1 Logic Diagram of Half Adder.

b. TRUTH TABLE (Half Adder): Practical Values:

INPUT OUTPUT S.No INPUT OUTPUT

II. FULL ADDER:

Fig 2.2 Logic Diagram of Full Adder.