UNIT-I

Sequential Logic
A Sequential logic circuits is a form of binary circuit; its design employs one or
more inputs and one or more outputs, whose states are related to some definite rules that
depend on previous states. Both the inputs and outputs can reach either of the two states:
logic 0 (low) or logic 1 (high). In these circuits their output depends, not only on the
combination of the logic states at its inputs, but moreover on the logic states that existed
previously. In other words their output depends on a SEQUENCE of the events occurring
at the circuit inputs. Examples of such circuits include clocks, flip-flops, bi-stables,
counters, memories, and registers. The actions of the circuits depend on the range of
basic sub-circuits

The combinational circuit does not use any memory. Hence the previous state of input
does not have any effect on the present state of the circuit. But sequential circuit has
memory so output can vary based on input. This type of circuits uses previous input,
output, clock and a memory element.

Block diagram of Sequential circuit

Observations about sequential circuits from the above diagram:

 The "state" of the sequential circuit is stored in the memory elements. There are a finite number of states
the circuit can be in.

 The next state of the memory elements is a function of the current state and current inputs.

 Output of the circuit is a function of the current state and current inputs.

1
Classification of Sequential Logic
As standard logic gates are the building blocks of combinational circuits, bistable latches
and flip-flops are the basic building blocks of sequential logic circuits. Sequential logic
circuits can be constructed to produce either simple edge-triggered flip-flops or more
complex sequential circuits such as storage registers, shift registers, memory devices or
counters. Either way sequential logic circuits can be divided into the following three main
categories:

 1. Event Driven – asynchronous circuits that change state immediately when

enabled.
 2. Clock Driven – synchronous circuits that are synchronised to a specific clock
signal.
 3. Pulse Driven – which is a combination of the two that responds to triggering
pulses?

Circuit Properties of Bistable latch

Sequential logic circuits are generally termed as two state or Bistable devices which can have their output
or outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain “latched”
(hence the name latch) indefinitely in this current state or condition until some other input trigger pulse or
signal is applied which will cause the bistable to change its state once again.

Simple sequential logic circuits can be constructed from standard Bistable circuits such as: Flip-
flops, Latches and Counters and which themselves can be made by simply connecting together
universal NAND Gates and/or NOR Gates in a particular combinational way to produce the required
sequential circuit.

As well as the two logic states mentioned above logic level “1” and logic level “0”, a third element is
introduced that separates sequential logic circuits from their combinational logic counterparts,
namely TIME. Sequential logic circuits return back to their original steady state once reset and sequential
circuits with loops or feedback paths are said to be “cyclic” in nature.

We now know that in sequential circuits changes occur only on the application of a clock signal making
it synchronous, otherwise the circuit is asynchronous and depends upon an external input.

2
Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its
outputs only at particular instants of time and not continuously. Flip flop is said to be
edge sensitive or edge triggered rather than being level triggered like latches.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also
called as level triggered SR-FF. For this, circuit in output will take place if and only if
the enable input (E) is made active. In short this circuit will operate as an S-R latch if E
= 1 but there is no change in the output if E = 0.

Block Diagram

Circuit Diagram

3
Truth Table

Operation
S.N. Condition Operation

1 S = R = 0 : No change If S = R = 0 then output of NAND gates 3 and 4 are

forced to become 1.

Hence R' and S' both will be equal to 1. Since S' and R'
are the input of the basic S-R latch using NAND gates,
there will be no change in the state of outputs.

2 S = 0, R = 1, E = 1 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the

output of NAND-4 i.e. S' = 0.

Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

3 S = 1, R = 0, E = 1 Output of NAND-3 i.e. R' = 0 and output of NAND-4

i.e. S' = 1.

Hence output of S-R NAND latch is Qn+1 = 1 and

Qn+1 bar = 0. This is the reset condition.

4 S = 1, R = 1, E = 1 As S = 1, R = 1 and E = 1, the output of NAND gates 3

and 4 both are 0 i.e. S' = R' = 0.

Hence the Race condition will occur in the basic NAND

latch.

4
JK flip Flop :

JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated
letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous
letters chosen by its inventor Jack Kirby to distinguish the flip-flop design from other types.

The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop
with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no
invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as the addition of a clock input.

The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.

The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This
cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” andR = “1”
state to be used to produce a “toggle action” as the two inputs are now interlocked.

5
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower
NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the
upper NAND gate. As Q and Q are always different we can use them to control the input. When
both inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in the following truth
table.

The Truth Table for the JK Function

Input Output

Description

J K Q Q

0 0 0 0

Memory

same as no change

for the 0 0 0 1
SR Latch

0 1 1 0

Reset Q » 0

0 1 0 1

1 0 0 1 Set Q » 1

6
 1 0 1 0

1 1 0 1

toggle
Toggle
action

1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the invalid
condition seen previously in the SR flip flop circuit.

Also when both the J and the K inputs are at logic level “1” at the same time, and the clock input
is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-versa.
This result in the JK flip flop acting more like a T-type toggle flip-flop when both terminals are
“HIGH”.

Although this circuit is an improvement on the clocked SR flip-flop it still suffers from
timing problems called “race” if the output Q changes state before the timing pulse of the clock
input has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much
improved Master-Slave JK Flip-flop was developed.

Race around condition of JK Flip Flop

In JK flip flop as long as clock is high for the input conditions J&K equals to the output
changes or complements its output from 1–>0 and 0–>1. This is called toggling output or
uncontrolled changing or racing condition. Consider above J&K circuit diagram as long as clock
is high and J&K=11 then two upper and lower AND gates are only triggered by the
complementary outputs Q and Q(bar). I.e. in any condition according to the propagation delay
one gate will be enabled and another gate is disabled. If upper gate is disabled then it sets the
output and in the next lower gate will be enabled which resets the flipflop output.

7
Steps to avoid racing condition in JK Flip flop:
1. If the Clock On or High time is less than the propagation delay of the flip flop then racing
can be avoided. This is done by using edge triggering rather than level triggering.
2. If the flip flop is made to toggle over one clock period then racing can be avoided. This
introduced the concept of Master Slave JK flip flop.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second
to input of first. Master is a positive level triggered. But due to the presence of the
inverter in the clock line, the slave will respond to the negative level. Hence when the
clock = 1 (positive level) the master is active and the slave is inactive. Whereas when
clock = 0 (low level) the slave is active and master is inactive.

Circuit Diagram

Truth Table

8
Operation
S.N. Condition Operation

1 J = K = 0 (No change) When clock = 0, the slave becomes active and master is
inactive. But since the S and R inputs have not changed,
the slave outputs will also remain unchanged. Therefore
outputs will not change if J = K =0.

2 J = 0 and K = 1 (Reset) Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 0 and Q1 bar = 1.
That means S = 0 and R =1.

Clock = 0 − Slave active, master inactive. Therefore

outputs of the slave become Q = 0 and Q bar = 1.

Again clock = 1 − Master active, slave inactive.

Therefore even with the changed outputs Q = 0 and Q
bar = 1 fed back to master, its output will be Q1 = 0 and
Q1 bar = 1. That means S = 0 and R = 1.

Hence with clock = 0 and slave becoming active the

outputs of slave will remain Q = 0 and Q bar = 1. Thus
we get a stable output from the Master slave.

3 J = 1 and K = 0 (Set) Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 1 and Q1 bar = 0.
That means S = 1 and R =0.

Clock = 0 − Slave active, master inactive. Therefore

outputs of the slave become Q = 1 and Q bar = 0.

Again clock = 1 − then it can be shown that the outputs

of the slave are stabilized to Q = 1 and Q bar = 0.

4 J = K = 1 (Toggle) Clock = 1 − Master active, slave inactive. Outputs of

master will toggle. So S and R also will be inverted.

Clock = 0 − Slave active, master inactive. Outputs of

9
 slave will toggle.

These changed output are returned back to the master

inputs. But since clock = 0, the master is still inactive.
So it does not respond to these changed outputs. This
avoids the multiple toggling which leads to the race
around condition. The master slave flip flop will avoid
the race around condition.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data is appearing at
the output after some time. Due to this data delay between i/p and o/p, it is called delay
flip flop. S and R will be the complements of each other due to NAND inverter. Hence S
= R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by
SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

10
Truth Table

Operation
S.N. Condition Operation

1 E=0 Latch is disabled. Hence no change in output.

2 E = 1 and D = 0 If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of

the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1.
This is the reset condition.

3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch

and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol
for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

11
Block Diagram

Truth Table

Operation
S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock

signal.

Flip Flop Conversion

The main purpose of the flip flop conversion is to convert a flip flop into a desired type-B flip
flop using some conversion logic. The flip flop conversions are classified into different types that
are

 SR-FF to JK-FF Conversion

 JK-FF to SR-FF Conversion
 SR-FF to D-FF Conversion
 D-FF to SR-FF Conversion
 JK-FF to T-FF Conversion
 JK-FF to D-FF Conversion
12
 D-FF to JK-FF Conversion

SR-Flip Flop to JK-Flip Flop Conversion

In JK-flipflop, j and k are given as external i/ps to S and R in SR-flip flop. Here, both S & R are
o/ps of the combinational circuit. The truth tables of flip flop conversions are shown below. The
current state is denoted with Qp & Qp+1 is the next state to be found when the J &K i/ps are
applied.

SR-FF to JK-FF Conversion

There are eight possible combinations for two i/ps J and K. For every combination of J, K & Qp,
the equivalent Qp+1 states are found. Qp+1 simply recommends the future values to be found by
the JK-flip flop after the importance of Qp. Then the table is finished by writing the values of S &
R compulsory to get each Qp+1 from the equivalent Qp. That is, the S and R values are
compulsory to change the state of the flip flop from Qp to Qp+1 are written

JK-Flip Flop to SR-Flip Flop Conversion

The conversion of the JK-FF to SR-FF is opposite to the SR-FF to JK-FF. Here S & R will be the
external i/ps to J & K, that is shown in the below logic diagram, J & K will be the o/ps of the
combinational circuit. So, the J and K values have to be acquired in terms of S, R & Qp. The
13
logic diagram is shown below. The conversion table for flip flop to be written in terms of S, R,
Qp, Qp+1, J & K. There are eight possible combinations for two i/ps S and R.

SR-Flip Flop to D-Flip Flop Conversion

As shown in the below figure, actual inputs of the flip flop are S & R where D is the external i/p.
The four combinations of the S & R in terms of D and Qp, conversion table, logic diagram and
the Karnaugh map are given below.

SR-FF to D-FF Conversion

D-Flip Flop to SR-Flip Flop Conversion

In this type of conversion, D is the actual i/p of the flip flop where S & R are the external
i/ps.There are Eight possible combinations are obtained from the external i/ps S, R & Qp.

14
Nevertheless, since the combination of S=R=1 is unacceptable, the values of D and Qp+1 are
taken as “don’t care”. The logic diagram of D-FF to SR-FF is showing the conversion from D-FF
to SR-FF, and the Karnaugh map for D in terms of S, R & Qp are given below.

JK-Flip Flop to T-Flip Flop Conversion

In this type of conversion, J & k are the actual i/ps of the flip flop where K is considered as the
external i/p. Four combinations are created by T, Qp, J & K that are expressed in terms of T &
Qp. The Karnaugh map, the logic diagram and conversion table, are given below.

JK-Flip Flop to D-Flip Flop Conversion

In this type of flip flop conversion, J&K are the actual inputs where D is the external input of the
flip flop. The four combinations of the flip flop will be done by using D & Qp, and in terms of
these two J&K are expressed. The conversion table with four combinations, JK-FF to D-FF
conversion logic diagram and Karnaugh map for J & K in terms of D & are shown below.

15
D-Flip Flop to JK-Flip Flop Conversion

In this type of flip flop conversion, J & K are the external i/ps of the flip flop where D is the
actual input. The eight combinations can make by using J, K and Qp that is shown in the
conversion table below. D is stated in terms of J, K & Qp. The Karnaugh map D in terms of J, K
& Qp, conversion table and the logic diagram of the D-FF to JK-FF is shown below.

State Table:

A state table looks similar to a truth table, except that in addition to the inputs, the left part of
the table also contains the values of the outputs. The right part of the table does not contain
the values of the outputs, but the values of the outputs after the next clock transition. To
distinguish between the output values before and after the clock transition, we call them x, y,
etc before the transition and x', y', etc after the transition.
Here is an example of a state table:

16
 x a b c | a' b' c'
-----------------
0000|0 0 0
0001|0 0 1
0010|0 1 0
0011|0 1 1
0100|1 0 0
0101|1 0 1
0110|1 1 0
0111|1 1 1
1000|0 0 1
1001|0 1 0
1010|0 1 1
1011|1 0 0
1100|1 0 1
1101|1 1 0
1110|1 1 1
1111|0 0 0

As you can see, when the x input is 0, the values of the outputs do not change as a
result of a clock pulse. When the value of the x input is 1, however, the values of the outputs
(interpreted as a binary number) is one plus the values of the inputs (also interpreted as a
binary number). This state table describes a counter with an extra input that lets you control
whether it counts or not.

State Tables and State Diagrams

We have examined a general model for sequential circuits. In this model the effect of all previous
inputs on the outputs is represented by a state of the circuit. Thus, the output of the circuit at any
time depends upon its current state and the input. These also determine the next state of the
circuit. The relationship that exists among the inputs, outputs, present states and next states can be
specified by either the state table or the state diagram.

State Table

The state table representation of a sequential circuit consists of three sections labeled present
state, next state and output. The present state designates the state of flip-flops before the
occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and
the output section lists the value of the output variables during the present state.

State Diagram

In addition to graphical symbols, tables or equations, flip-flops can also be represented

graphically by a state diagram. In this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the circles. An example of a
state diagram is shown in Figure below.

17
 Figure: State Diagram

The binary number inside each circle identifies the state the circle represents. The directed lines
are labeled with two binary numbers separated by a slash (/). The input value that causes the state
transition is labeled first. The number after the slash symbol / gives the value of the output. For
example, the directed line from state 00 to 01 is labeled 1/0, meaning that, if the sequential circuit
is in a present state and the input is 1, then the next state is 01 and the output is 0. If it is in a
present state 00 and the input is 0, it will remain in that state. A directed line connecting a circle
with itself indicates that no change of state occurs. The state diagram provides exactly the same
information as the state table and is obtained directly from the state table.

Example: Consider a sequential circuit shown in Figure. It has one input x, one output Z and two
state variables Q1Q2 (thus having four possible present states 00, 01, 10, 11).

18
 Figure. A Sequential Circuit

The behavior of the circuit is determined by the following Boolean expressions:

Z = x * Q1
D1 = x' + Q1
D2 = x * Q2' + x' * Q1'

These equations can be used to form the state table. Suppose the present state (i.e. Q1Q2) = 00 and
input x = 0. Under these conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state of the
circuit D1D2 = 11, and this will be the present state after the clock pulse has been applied. The
output of the circuit corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This data is
entered into the state table as shown in Table.

Present State Next State Output

Q1Q2 x=0 x=1 x=0 x=1

00 11 01 0 0
01 11 00 0 0
10 10 11 0 1
11 10 10 0 1

Table State table for the sequential circuit in Figure.

The state diagram for the sequential circuit is shown in Figure

19
 State Diagram of circuit in above Table

State Diagrams of Various Flip-flops

Table shows the state diagrams of the four types of flip-flops.

NAME STATE DIAGRAM

SR

JK

Table. State diagrams of the four types of flip-flops.

20
You can see from the table that all four flip-flops have the same number of states and transitions.
Each flip-flop is in the set state when Q=1 and in the reset state when Q=0. Also, each flip-flop
can move from one state to another, or it can re-enter the same state. The only difference between
the four types lies in the values of input signals that cause these transitions.

A state diagram is a very convenient way to visualize the operation of a flip-flop or even of large
sequential components.

Flip Flop Excitation Table:

An excitation table shows the minimum inputs that are necessary to generate a particular next
state (in other words, to "excite" it to the next state) when the current state is known. They
are similar to truth tables and state tables, but rearrange the data so that the current state and
next state are next to each other on the left-hand side of the table, and the inputs needed to
make that state change happen are shown on the right side of the table.

21
 Unit 2
SEQUENTIAL CIRCUITS

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used for the storage or the
transfer of binary data

This sequential device loads the data present on its inputs and then moves or “shifts” it to its
output once every clock cycle, hence the name Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that
the output from one data latch becomes the input of the next latch and so on.

Data bits may be fed in or out of a shift register serially, that is one after the other from either the
left or the right direction, or all together at the same time in a parallel configuration.

The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches.

Shift Registers are used for data storage or for the movement of data and are therefore commonly
used inside calculators or computers to store data such as two binary numbers before they are
added together, or to convert the data from either a serial to parallel or parallel to serial format.
The individual data latches that make up a single shift register are all driven by a common clock
( Clk ) signal making them synchronous devices.

22
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:

 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form.

 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.

 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.

 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can be presented
graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left
shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting
within the same register thereby making it bidirectional. it is assumed that all the data shifts to the
right, (right shifting).

23
Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FF0 to FF3 ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.

If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still
remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW
again to logic “0” giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic “0” and the output
of FFB andQB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic
“1” has now moved or been “shifted” one place along the register to the right as it is now at QA.

When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so
on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic
level “0” because the input to FFA has remained constant at logic level “0”.

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and
this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA toQD.

24
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.

Basic Data Movement Through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow straight
through the register and out of the other end. Since there is only one output, theDATA leaves the
shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift
Register or SISO.

25
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.

4-bit Serial-in to Serial-out Shift Register

You may think what’s the point of a SISO shift register if the output data is exactly the same as
the input data. Well this type of Shift Register also acts as a temporary storage device or it can
act as a time delay device for the data, with the amount of time delay being controlled by the
number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses.
Commonly available IC’s include the 74HC595 8-bit Serial-in to Serial-out Shift Register all with
3-state outputs.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read
out sequentially in the normal shift-right mode from the register at Q representing the data present
at PA to PD.

This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this type of data register a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.

26
4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it
can be used to multiplex many different input lines into a single serial DATA stream which can
be sent directly to a computer or transmitted over a communications line. Commonly available
IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output pins QA toQD by the
same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for
parallel loading and unloading is shown below.

27
4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections between
the individual flip-flops since no serial shifting of the data is required.

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available such
as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function
devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel,
parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence their name
“Universal”.

These universal shift registers can perform any combination of parallel and serial input to output
operations but require additional inputs to specify desired function and to pre-load and reset the
device. A commonly used universal shift register is the TTL 74LS194 as shown below.

28
4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond
to operations that require some form of temporary memory storage or for the delay of information
such as the SISO or PIPO configuration modes or transfer data from one point to another in either
a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to
shift data to the left or right for multiplication or division.

29
 Counters

A counter is a sequential machine that produces a specified count sequence. The

count changes whenever the input clock is asserted.

There is a great variety of counter based on its construction.

1. Clock: Synchronous or Asynchronous

2. Clock Trigger: Positive edged or Negative edged
3. Counts: Binary, Decade
4. Count Direction: Up, Down, or Up/Down
5. Flip-flops: JK or T or D

A counter can be constructed by a synchronous circuit or by an asynchronous circuit.

With a synchronous circuit, all the bits in the count change synchronously with the
assertion of the clock. With an asynchronous circuit, all the bits in the count do not all
change at the same time.

A counter may count up or count down or count up and down depending on the input
control.

Because of limited word length, the count sequence is limited. For an n-bit counter,
the range of the count is [0, 2n-1]. The count sequence usually repeats itself. When
counting up, the count sequence goes in this manner: 0, 1, 2, … 2n-2, 2n-1, 0, 1, …etc.
When counting down the count sequence goes in the same manner: 2n-1, 2n-2, … 2, 1,
0, 2n- 1, 2n-2, … etc.

Example:

3-bit Up Counter 3-bit Down Counter

000 000
001 111
010 110
011 101
100 100
101 011
110 010
111 001

30
 The complement of the count sequence counts in reverse direction. If the
uncomplemented output counts up, the complemented output counts down. If the
uncomplemented output counts down, the complemented output counts up.

Example:

3-bit Up Counter Complement of the

Count
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000

The natural count sequence is to run through all possible combinations of the bit
patterns before repeating itself. External logic can be used to arbitrary cause the
counter to start at any count and terminate at any count.
A binary counter produces a count sequence similar to the binary numbers. A decade
counter counts from 0 to 9, thus making it suitable for human interface. Other
counters count to 12 making them suitable for clocks.

Uses of Counters

The most typical uses of counters are

 To count the number of times that a certain event takes place; the occurrence of event
to be counted is represented by the input signal to the counter

 To control a fixed sequence of actions in a digital system

 To generate timing signals

 To generate clocks of different

31
32
Figure

33
 Two Classes of Counters

Counters are classified into two categories:

 Asynchronous Counters (Ripple counters)

 Synchronous Counters

Asynchronous & Synchronous

Asynchronous: The events do not have a fixed time relationship with each other and do not
occur at the same time.

Synchronous: The events have a fixed time relationship with each other and do occur
at the same time.

Counters are classified according to the way they are clocked. In asynchronous
counters, the first flip-flop is clocked by the external clock pulse and then each
successive flip-flop is by clocked the output of the preceding flip-flop. In
synchronous counters, the clock input is connected to all of the flip-flop so that they
are clocked simultaneously.

Asynchronous Counters

An asynchronous counter is one in which the flip-flop within the counter do not change states
at exactly the same time because they do not have a common clock pulse.

 2 Bit asynchronous binary counter

 3 Bit asynchronous binary counter

 4 Bit asynchronous binary counter

The main characteristic of an asynchronous counter is each flip-flop derives its own clock
from other flip-flops and is therefore independent of the input clock. Consequently, the output of
each flip-flop may change at different time, hence the term asynchronous. From the
asynchronous counter diagram above, we observed that the output of the first flip-flop becomes
the clock input for the second flip-flop, and the output of the second flip-flop becomes the clock
input for the third flip-flop etc.

For the first flip-flop, the output changes whenever there is a negative transition in the
clock input. This means that the output of the first flip- flop produces a series of square waves
that is half the frequency of the clock input. Since the output of the first flip-flop becomes the
clock of the second flip-flop, the output of the second flip-flop is half the frequency of its
clock, i.e. the output of the first flip-flop that in turn is half the frequency of the clock input.
This behaviour, in essence is captured by the binary bit pattern in the counting sequence.

34
2-Bit Asynchronous Binary Counter

Example 1:

Figure: two-bit asynchronous counter

A two-bit asynchronous counter is shown on the left. The external clock is

connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at
the falling edge of each clock pulse, but FF1 changes only when triggered by the
falling edge of the Q output of FF0. Because of the inherent propagation delay
through a flip-flop, the transition of the input clock pulse and a transition of the Q
output of FF0 can never occur at exactly the same time. Therefore, the flip-flops
cannot be triggered simultaneously, producing an asynchronous operation.

Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram
above are shown as simultaneous even though this is an asynchronous counter.
Actually, there is some small delay between the CLK, Q0 and Q1 transitions.

Usually, all the CLEAR inputs are connected together, so that a single pulse can clear
all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled
through the other counters after propagation delays, like a ripple on water, hence the
name Ripple Counter.

35
 The 2-bit ripple counter circuit above has four different states, each one
corresponding to a count value. Similarly, a counter with n flip-flops can have 2 to
the power n states. The number of states in a counter is known as its mod (modulo)
number. Thus a 2-bit counter is a mod-4 counter

A mod-n counter may also be described as a divide-by-n counter. This is because

the most significant flip-flop (the furthest flip-flop from the original clock pulse)
produces one pulse for every n pulses at the clock input of the least significant flip-
flop (the one triggers by the clock pulse). Thus, the above counter is an example of a
divide-by-4 counter.

Example 2:

Figure: Two-bit asynchronous binary counter, timing diagram, binary state sequence

36
 3-Bit Asynchronous Binary Counter

The following is a three-bit asynchronous binary counter and its timing diagram for one cycle.
It works exactly the same way as a two-bit asynchronous binary counter mentioned above,
except it has eight states due to the third flip-flop.

37
Figure Three-bit asynchronous binary counter, timing diagram, binary state sequence

38
Propagation Delay:

Figure: Propagation Delay in a 3-bit asynchronous binary counter

39
Asynchronous counters are commonly referred to as ripple counters for the following reason:
The effect of the input clock pulse is first “felt” by FFO. This effect cannot get to FF1
immediately because of the propagation delay through FF0. Then there is the propagation
delay through FF1 before FF2 can be triggered. Thus, the effect of an input clock pulse
“ripples” through the counter, taking some time, due to propagation delays, to reach the last
flip-flop.

4 Bit Asynchronous Binary Counter

The following is a 4-bit asynchronous binary counter and its timing diagram for one cycle. It
works exactly the same way as a 2-bit or 3 bit asynchronous binary counter mentioned above,
except it has 16 states due to the fourth flip-flop.

Figure Four-bit asynchronous binary counter, timing diagram

40
Asynchronous Decade Counters

The binary counters previously introduced have two to the power n states. But
counters with states less than this number are also possible. They are designed to have
the number of states in their sequences, which are called truncated sequences. These
sequences are achieved by forcing the counter to recycle before going through all of
its normal states.

A common modulus for counters with truncated sequences is ten. A counter with ten
states in its sequence is called a decade counter.

The circuit below is an implementation of a decade counter.

Figure Asynchronous decade counter, timing diagram

41
 Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that
only Q1 and Q3 are used to decode the count of ten. This is called partial decoding, as
none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.

The sequence of the decade counter is shown in the table below

Recycles
1 1 0 0 (normal next state)

Glitch: Notice that there is a glitch on the Q1 waveform. The reason for this glitch is that Q1
must first go HIGH before the count of ten can be decoded. Not until several nanoseconds
after the counter goes to the count of ten does the output of the decoding gate go LOW (both
inputs are HIGH). Therefore, the counter is in the 1010 state for a short time before it is reset
to 0000, thus producing the glitch on Q1 and the resulting glitch on the CLR line that resets the
counter.

42
Example: Modulus Twelve Asynchronous Counter

An Asynchronous counter can be implemented having a modulus of 12 with a straight

binary sequence from 0000 through 1011.

Figure Asynchronous modulus-12 counter & timing diagram.

43
 Asynchronous Up-Down Counters

In certain applications a counter must be able to count both up and down. The circuit below is
a 3-bit up-down counter. It counts up or down depending on the status of the control signals
UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network
between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of
FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input
of FF2. Thus the counter will count up.

Figure -bit up-down counter

When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and
FF1 are gated into the clock inputs of FF1 and FF2 respectively. If the flip-flops are
initially reset to 0's, then the counter will go through the following sequence as input
pulses are applied.

Notice that an asynchronous up-down counter is slower than an up counter or a down

counter because of the additional propagation delay introduced by the NAND
networks.

44
 Commercially Available Asynchronous Counters

Example 1: The 74LS93 Asynchronous Binary Counter

[Floyd]

Figure The 74LS93A 4-bit asynchronous binary counter logic diagram

Three configurations of the 74LS293 asynchronous counter:

[Floyd]

RO(1), R0(2) are the gated reset inputs. If both of these inputs are HIGH, the counter is reset to
the 0000 state by CLR .
45
Synchronous Counters

In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).

2-Bit Synchronous Binary Counter

Figure : Two-bit synchronous binary counter, timing diagram

46
Propagation Delay:

Figure

3-Bit Synchronous Binary Counter

The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to
HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of
FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.

Figure A 3-bit synchronous binary counter

47
 Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are
HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the
AND gate.

Figure: Timing diagram

(recycles)
Figure: Binary state sequence
The count sequence for the 3-bit counter is shown in Figure.

The most important advantage of synchronous counters is that there is no cumulative time
delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency
for this counter will be significantly higher than for the corresponding ripple counter.

4-Bit Synchronous Binary Counter

Figure shows a 4-bit synchronous binary counter and reveals its timing diagram.

48
Figure: Four-bit synchronous binary counter, timing diagram

49
 Synchronous Decade Counters

Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9

and then recycles to 0 again. This is done by forcing the 1010 state back to the 0000 state.
This so called truncated sequence can be constructed by the following circuit.

Figure: A synchronous BCD decade counter

Figure : States of a BCD decade

Figure: Timing diagram for the BCD decade counter (Q0 is the LSB)

50
 From the sequence in the Figure ,we notice that:

 Q0 toggles on each clock pulse.

 Q1 changes on the next clock pulse each time Q0=1 and Q3=0.
 Q2 changes on thenext clock pulse each time Q0=Q1=1.
 Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1 (count 7), or then
Q0=1 and Q3=1 (count 9).

Flip-flop 2 (Q2) changes on the next clock pulse each time both Q0=1 and Q1=1. Thus we
must have
J2 = K2 = Q0Q1
Flip-flop 3 (Q3) changes to the opposite state on the next clock pulse each time Q0=1,
Q1=1, and Q2=1 (state 7), or when Q0=1 and Q3=1 (state 9). Thus we must have
J3 = K3 = Q0Q1Q2 + Q0Q3

These characteristics are implemented with the AND/OR logic connected as shown in the logic
diagram.
Modulus Counter (MOD-N Counter)
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8
counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD
number = 2n.

Type of modulus

 2-bit up or down (MOD-4)

 3-bit up or down (MOD-8)
 4-bit up or down (MOD-16)
Application of counters

 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.

51
Up-Down Synchronous Counters

A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown in
Figure 3.6. Similar to an asynchronous up-down counter, a synchronous up-down counter also
has an up-down control input. It is used to control the direction of the counter through a
certain sequence.

Figure A basic 3-bit up/down synchronous counter and its up/down sequence

52
 An examination of the sequence table shows:

 for both the UP and DOWN sequences, Q0 toggles on each clock pulse.
 for the UP sequence, Q1 changes state on the next clock pulse when Q0=1.
 for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0.
 for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1.
 for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as shown in
the Figure
Example: 4-bit synchronous up-down counter

53
 UNIT III

MEMORY & I/O DEVICES

A memory is just like a human brain. It is used to store data and instruction. Computer memory is the
storage space in computer where data is to be processed and instructions required for processing are
stored.

The memory is divided into large number of small parts. Each part is called a cell. Each location or cell
has a unique address which varies from zero to memory size minus one.

For example if computer has 64k words, then this memory unit has 64 * 1024 = 65536 memory location.
The address of these locations varies from 0 to 65535.

Memory is primarily of two types

 Internal Memory − cache memory and primary/main memory

 External Memory − magnetic disk / optical disk etc.

Basic types and parameters of memory devices in computers

54
Memory devices in computers are used for storing different forms of information such as
data, programs, addresses, textual files and status information on processor and other
computer devices. Information stored in memory devices can be divided into bits, bytes,
words, blocks, segments, pages and other larger data structures, which have their own
identifiers. In main memory, information is stored in memory cells or memory locations.
Memory locations contain information to which an access can take place. To read or write
information in a memory location, a single memory access operation has to be executed,
which requires independent control signals to be supplied to the memory.

Based on information addressing method, memory devices can be divided into two groups:

a. memories in which access to locations is controlled by using addresses,

b. memories with access to locations controlled by the contents of the memory.

To the first group such memories belong in which each accessible location has its address
that can be used to select a location in the memory and perform a required operation.
These are memories addressed by addresses. Such memories are based on hardware
circuits, which do address decoding and select the requested location for a memory access
operation. The set of all addresses available in a given memory is called an address
space of this memory.

To the second group, associative memories belong. In these memories, the selection of a
requested location takes place as a result of a comparison of this memory contents with a
requested information pattern. For the selection operation, a part of the information stored
in a location is used. The positive result of comparison with a pattern, activates the readout
of the remaining information in the location. During a write operation, besides the basic
data, which will be accessed in the future, an additional information is stored in each
location, which will be used for searching the basic data using a comparative method.
Associative memories are also called content addressable memories. Such memories do
not have address decoders.

Memories addressed by addresses can be sub-divided into the following types according to
the access freedom to a location at a given address:

 random access memories

 sequential access memories
 cyclic access memories.

A random access memory enables unrestricted in space and time access to any location
at any address in the address space. The access is possible independently on the order of all
previous accesses. The access can take place to an addresses in any order. Each location in
a random access memory has independent hardware circuits that provide the access. These
circuits are activated as a result of address decoding. To such memories belong
semiconductor memories of the RAM and ROM types.

55
A sequential access memory enables access restricted to locations which have
consecutive addresses in the memory address space. In such memories, information is
stored sequentially on a data carrier, e.g. a magnetic tape or surface of an optical disk -
on a spiral track. Access to data takes place while the carrier moves in respect to the writing
or reading device, under control of a control unit, which counts addresses of neighboring
locations. Such memory type includes, among others, magnetic tape memories and optical
disk memories.

A cyclic access memory is a memory in which access is limited to locations that have
consecutive addresses in the address space computed modulo certain subspace of that
address space. Information is stored on a carrier that constitutes a loop or a set of loops.
This feature makes that in some place on the carrier there is an abrupt change of the
address- from the largest to the smallest one. In such memories, access to data takes place
while the carrier moves in respect to the writing or reading device, under control of a
control unit, which counts addresses of neighboring locations. Usually, many reading-writing
devices (heads) appear. An example of such a memory is a magnetic disk memory.

We can distinguish different parameters which determine properties of different kinds of

memories. The most important parameters will be discussed below.

Memory capacity or memory volume is the number of locations that exist in a given
memory. Memory capacity is measured in bits, byte or words. When words are used, the
length of a word in bits or bytes has to be given.

Memory access time is the time that separates sending a memory access request and the
reception of the requested information. The access time determines unitary speed of a
memory (the reception time of unitary data). The access time is small for fast memories.

Memory cycle time is the shortest time that has to elapse between consecutive access
requests to the same memory location. The memory cycle time is another parameter that
characterizes the overall speed of the memory. The speed is big when the cycle time is
small.

Memory transfer rate is the speed of reading or writing data in the given memory,
measured in bits/sec or bytes/sec.

It is easy to see that the following rules, concerning memory parameters, hold:

 growing memory volume makes the memory cost per bit of stored information
decreased,
 lower access time makes the memory cost per bit increased,
 growing memory volume frequently corresponds to larger access time.

56
RAM
A RAM constitutes the internal memory of the CPU for storing data, program and program result. It is
read/write memory. It is called random access memory (RAM).

Since access time in RAM is independent of the address to the word that is, each storage location inside
the memory is as easy to reach as other location & takes the same amount of time. We can reach into the
memory at random & extremely fast but can also be quite expensive.

RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a power
failure. Hence, a backup uninterruptible power system (UPS) is often used with computers. RAM is
small, both in terms of its physical size and in the amount of data it can hold.

RAM is of two types

 Static RAM (SRAM)

 Dynamic RAM (DRAM)
Static RAM (SRAM)
The word static indicates that the memory retains its contents as long as power remains applied.
However, data is lost when the power gets down due to volatile nature. SRAM chips use a matrix of 6-
transistors and no capacitors. Transistors do not require power to prevent leakage, so SRAM need not
have to be refreshed on a regular basis.

Because of the extra space in the matrix, SRAM uses more chips than DRAM for the same amount of
storage space, thus making the manufacturing costs higher.

Static RAM is used as cache memory needs to be very fast and small.

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data. This is done
by placing the memory on a refresh circuit that rewrites the data several hundred times per second.
DRAM is used for most system memory because it is cheap and small. All DRAMs are made up of
memory cells. These cells are composed of one capacitor and one transistor.

57
ROM
ROM stands for Read Only Memory. The memory from which we can only read but cannot write on it.
This type of memory is non-volatile. The information is stored permanently in such memories during
manufacture.

A ROM, stores such instruction as are required to start computer when electricity is first turned on, this
operation is referred to as bootstrap. ROM chip are not only used in the computer but also in other
electronic items like washing machine and microwave oven.

Following are the various types of ROM −

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data or
instructions. These kind of ROMs are known as masked ROMs. It is inexpensive ROM.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank PROM and
enters the desired contents using a PROM programmer. Inside the PROM chip there are small fuses
which are burnt open during programming. It can be programmed only once and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

The EPROM can be erased by exposing it to ultra-violet light for a duration of upto 40 minutes. Usually,
an EPROM eraser achieves this function. During programming an electrical charge is trapped in an
insulated gate region. The charge is retained for more than ten years because the charge has no leakage
path. For erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). This
exposure to ultra-violet light dissipates the charge. During normal use the quartz lid is sealed with a
sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

The EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten
thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM, any
location can be selectively erased and programmed. EEPROMs can be erased one byte at a time, rather
than erasing the entire chip. Hence, the process of re-programming is flexible but slow.

Serial Access Memory

Sequential access means the system must search the storage device from the beginning of the memory
address until it finds the required piece of data. Memory device which supports such access is called a
Sequential Access Memory or Serial Access Memory. Magnetic tape is an example of serial access
memory.

58
Direct Access Memory
Direct access memory or Random Access Memory, refers to conditions in which a system can go
directly to the information that the user wants. Memory device which supports such access is called a
Direct Access Memory. Magnetic disks, optical disks are examples of direct access memory.

Cache Memory
Cache memory is a very high speed semiconductor memory which can speed up CPU. It acts as a buffer
between the CPU and main memory. It is used to hold those parts of data and program which are most
frequently used by CPU. The parts of data and programs, are transferred from disk to cache memory by
operating system, from where CPU can access them.

Advantages

 Cache memory is faster than main memory.

 It consumes less access time as compared to main memory.
 It stores the program that can be executed within a short period of time.
 It stores data for temporary use.
Disadvantages

 Cache memory has limited capacity.

 It is very expensive.
Virtual memory is a technique that allows the execution of processes which are not completely
available in memory. The main visible advantage of this scheme is that programs can be larger than
physical memory. Virtual memory is the separation of user logical memory from physical memory.

This separation allows an extremely large virtual memory to be provided for programmers when only a
smaller physical memory is available. Following are the situations, when entire program is not required
to be loaded fully in main memory.

 User written error handling routines are used only when an error occurred in the data or
computation.

 Certain options and features of a program may be used rarely.

 Many tables are assigned a fixed amount of address space even though only a small amount of
the table is actually used.

 The ability to execute a program that is only partially in memory would counter many benefits.

59
  Less number of I/O would be needed to load or swap each user program into memory.

 A program would no longer be constrained by the amount of physical memory that is available.

 Each user program could take less physical memory, more programs could be run the same time,
with a corresponding increase in CPU utilization and throughput.

Auxiliary Memory
Auxiliary memory is much larger in size than main memory but is slower. It normally stores system
programs, instruction and data files. It is also known as secondary memory. It can also be used as an
overflow/virtual memory in case the main memory capacity has been exceeded. Secondary memories
cannot be accessed directly by a processor. First the data/information of auxiliary memory is transferred
to the main memory and then that information can be accessed by the CPU. Characteristics of Auxiliary
Memory are following −

 Non-volatile memory − Data is not lost when power is cut off.

 Reusable − The data stays in the secondary storage on permanent basis until it is not overwritten
or deleted by the user.

 Reliable − Data in secondary storage is safe because of high physical stability of secondary
storage device.

 Convenience − With the help of a computer software, authorised people can locate and access
the data quickly.

 Capacity − Secondary storage can store large volumes of data in sets of multiple disks.

 Cost − It is much lesser expensive to store data on a tape or disk than primary memory.

Magnetic memories

Magnetic memory is based on residual effect that appears in magnetic materials that allows
preserving their magnetization state (hysteresis loops). A magnetization state in a magnetic
material is obtained due to alignment of elementary magnetic domains (dipoles) with an applied
external magnetic field. A magnetization state remains in these materials when, after application
of an external magnetic field (strong enough), the field is removed. A magnetization state can be
easily changed into a reverse one by applying a sufficiently strong magnetic field with reverse
polarization. In contemporary magnetic memories, ferrites are applied as fundamental materials.
Ferrites are sintered finely powdered mixtures of ferrozinc oxide, manganese and strontium, in
which the contents of the first one is 60-85 %. By assigning logical values to magnetization
directions in magnetic materials, we obtain the information storage effect. Magnetic memories
based on magnetizing miniature ferrite cores have been used for long years as basic type of

60
 computer main memory, before they were replaced by semiconductor memories. Currently,
magnetic memories are based on magnetization of magnetic carriers such as magnetic tapes and
disks. They are memories that have sequential or cyclic access methods Such memories have very
large capacities and belong to the mass storage class.

Magnetic memory head functioning on write

Writing and reading of information is done by the use of writing/reading heads. Such a head is a ring
(core) made of ferritic steel, which well conveys and encloses magnetic flux. The core has an air gap
under which a magnetic carrier is moved (a tape or disk). There is a winding (a coil) on the core.
On data write, electric pulses are supplied to the coil. The pulses induce magnetic flux of a given
direction in the core. The flux spreads out of the core in the air gap as an external magnetic field,
which encompasses the carrier material and causes its magnetization in a respective direction. The
electric current direction changes accordingly to the stored information, thus creating regions on the
carrier with respective magnetization direction. During readout, the magnetic carrier is moved under
the reading head. This time, an electric current is taken out from the coil, induced in the coil as a
result of changes of the magnetic field created by the magnetized carrier, which encompasses the
core. The carrier magnetization direction decides on the direction current pulses read from the coil.

 The most popular type of magnetic memory is currently a magnetic disk memory. Magnetic disks
are designed by placing a magnetic material layer on an elastic base (plastic) or a hard base
(metal). As a result, we distinguish floppy disks and hard disks. The disks are mounted inside
disk drives, which contain motors that generate disk movement, moving write/read heads with
positioning mechanisms and control units. Information on a disk is organized in concentric tracks,
which are divided into sectors - see the figure below.

61
Basic mechanism of a disk memory

 Elastic (floppy) disks are exchangeable and have currently the 3.5-inch diameter, up to 2MB
capacity and data transmission rate up to 1 Mbit/s. On each side of a standard 1.44 MB floppy
disk, there are 80 tracks, divided into 18 sectors, each with a capacity of 512 bytes. A sector
contains a control field (including the track number, the sector number, the sector length,
correction control bits) and a data field. The heads are moving on both sides of the disk surface.
The access time to the floppy disk memory is 200 ms.
 Hard disks have many concentric disks, placed permanently inside an isolated housing that
contains also the heads. The number of heads is from several to several dozens, one head on each
side of a disk. The hard disk drive heads move synchronously during work and spontaneously
position themselves above the disk surface on an air cushion - this requires complete isolation
from the impurities of the surrounding environment. A disk surface is divided into concentric
tracks, which are divided into sectors. The sectors contain a control field (the contents is similar
as in floppy disks) and a data field. A group of all tracks placed at a given distance from the disk
center constitutes a so-called cylinder, see the figure below.

62
Simplified structure of a hard disk drive

The number of cylinders is from several hundred to a dozen or so thousand. The rotation speed is
currently very high, up to 10 000 revolutions/min (standard - 7200 revolutions/min). The maximal
capacity of hard disk drives is higher than 100 Gbytes. The data transmission rate in hard disk drives
comes up to several dozen Mbytes/s. A medium access time is currently several ms.

Magnetic tape memories are currently used as a lower level peripheral storage of computers, first of all
for archivizing purposes. Information read and write on the tape is done in blocks of the fixed
length, called records. A write of a record is done in 9-bit rows. Information addressing is done by
specifying the record number from the beginning of the tape. Magnetic tapes are used as tape
cartridges, for which special drives are designed. A tape cartridge has capacity of several Gbytes.
Transmission rates are up to several hundred Kbytes/s.

Optical memories

Basic optical memories are designed with the use of permanent storage of information on the surface
of a disk, which reflects the laser light. These memories are of the "read-only" type. The dimensions
of the used standard disks are small (5.25 inches), which is the reason for their name - CDROM
(Compact Disk ROM). Information is stored on a disk at a spiral track, which goes all over the entire
disk. A write takes place by extruding on tracks small regions (pits) that are 0.25 of the light wave
length deep. The configuration of pits and unextruded regions represents zeros and ones of data,
according to an established convention. The extruded disk surface is covered by a metallic light-
reflecting layer and next with a hard transparent plastic layer, which prevents from mechanical
corruption of data.

63
Information stored on a compact disk CDROM

 Data reads are done by enlightening disk surface with laser light and examining the reflected
light. Light reflection from a pit region causes fading of the reflected light beam due to negative
interference of the falling light with a reflected one. When the light is reflected from an
unextruded region, the light is enforced due to positive interference. A schematic of the CDROM
data read system is shown in the figure below.

64
  Data read system in a CDROM drive
 A low power laser diode generates light with the light wave length of 700 nm. The laser light first
obtains planar polarization by a calcite polarizing prism with an air gap. The air gap lets pass only
the light, which has been polarized, in one of its characteristic planes. The light is next directed
through the collimator (light parallelizing lenses) to the surface of a mica plate, which is a quarter
of the light wave length thick. The plate polarizes the light elliptically. Next, the light is directed
as a condensed beam to the surface of the optical disk. After reflection, the light returns to the
mica plate, which converts it into a form, which is polarized in the plane perpendicular to the
plane of the falling light. The air beam of the polarizing prism reflects the light towards a
photodiode, which inspects the light intensity after interference with the falling light. The
photodiode converts light pulses into electric pulses.
 On an optical disk, data are written on a spiral track. The track is divided into sectors, counted
from the middle of the disk. A sector contains 3234 bytes and is composed of a control field (882
bytes) and a data field (2352 bytes). The control field stores an identification of the sector and
data correctness control bits. The structure of a header and byte use in data fields is determined
according to different standards (yellow, red books). In sectors, data are written in frames
composed of 584 bits. Encoding of data bits is done with the use of 14 bits, which together with 3
extra control bits gives 17 bits per byte of data. In a frame, there are 33 bytes of data encoded.
Data reading is done with a constant linear speed, which with a spiral track requires controlling
the revolution speed of the disk in dependence on the head position on the track (the revolution
speed is up to several thousand revolutions/min). The access time of a contemporary CDROM
disk is 100 ms. CDROM disk capacities are usually 650-750 Mbytes.
 Besides optical disks of the "read-only" type, there are disk drives with a single write capability -
WORM (Write-Once-Read-Many), which co-operate with CD-R disks (CD- Recordable) and

65
 disk drives with multiple write capability, which co-operate with CD-RW (CD- Read-Write)
disks.
 Single write disk drives are built based on the use of two lasers: write laser and read laser with
different powers: high power laser for write and lower power - for read. Data write is done on
special disks, on which a laser can superficially burn the metallic disk surface or it can make
turbid the surface layer of the disk made of a special chemical agent (cyanine), which is
equivalent to a pit on a CDROM disk track.
 In optical disk drives with multiple writes, the stored information can be cancelled. For this,
special disks are used, which are covered with special chemical materials. In these materials
placed as an superficial layer on a disk, the laser light, which has a respective intensity or the
wave length, can make a reversible structure transformation from a light transparent phase
(enabling the light to pass) to a dense colloidal phase that absorbs the light. Multiple write disk
drives are based on the use of multiple lasers with different powers or wave lengths, that are used
to write, read and cancel information on a disk.
 As a parameter of an optical disk, the multiplicity of write and read speed is given (currently
maximally over 50), in respect to the speed that appeared in first CDROM disk drive designs (150
Kbytes/s).
 The latest type of optical memories is DVD (Digital-Video Disk) memory. It uses special DVD
disks that have increased information density. The DVD drives have twice-smaller distances
between tracks and twice smaller sizes of elementary regions that are used for bit recording.
Besides that, they apply a double-sided data write, which is additionally implemented using two
layers on a disk.

The capacity of a double layer double-sided optical DVD disk is 17 Gbs. Drives for DVD memory work
according to similar principles as CDROM, based on the use of lasers. For a two layer memory, the
read heads can focus light beam on consecutive reflecting layers, separated by light transparent
layers.

Recently, recordable optical DVD drives have become popular DVD-R (DVD - Recordable) that
enable writes to be done at users place. CDROM and DVD disks are used as data and program large
capacity carriers. CD-R, CD-RW and DVD-R memories are used as auxiliary memories for
archivization purposes.

Magneto-optical memories

Magneto-optical memory (WREM - Write Read Erase Memory) belongs to the group of writeable
memories with sequential or cyclic access to data. Such memories are used as relatively small
memories for archivizing data in personal computers.

 Magneto-optical memory is based on a magnetic technique for writing/storing of data and an

optical technique for reading and erasing data. Data carriers in such memories are disks covered
with a magneto-optical material that is separated from the protective upper disk layer and the
bottom base layer by layers of aluminum nitrate.

66
 Such constructed carrier has magnetization ability with external magnetic field and also
demagnetization ability in high temperature. Additionally, this material enables changing
polarization direction of the light reflected from it, in dependence on the magnetization direction.
It is shown in the figure below.

Section through an magneto-optical disk and the read principle

 To write data, a polarized beam of light is directed onto a track on the disk surface that had been
magnetized accordingly to some data values. The beam is reflected from the disk surface,
obtaining respective directions of elliptical polarization. The reflected light is then directed
through a prism onto a filter that passes the light only if it has a defined polarization direction.
The transmitted light falls onto a photodiode, which converts the light intensity into electric
voltage. The functioning principle of the magneto-optical memory is illustrated in the figures
below.

67
 Magneto-optical memory functioning on read

To write down data, a disk surface is exposed to magnetic field, which makes the surface magnetized
(for example corresponding to writing "ones" on the track). Next, to consecutive selected places on
the track (where "zeros" are to be stored) a strong beam of laser light is directed, which causes point
overheating of the disk. Heating above the Curie point (temperature of 150-200 degrees C), causes
demagnetizing of the disk, and so, writing down zeros on the track.

68
 Magneto-optical memory functioning on write

Data transmission rate in magnetic-optical memories is 1 Mbyte/s. Access time is 50 ms.The capacity
of this memory is 300 Mbytes on each side of a disk.

FLASH MEMORY

Flash memory of a form of semiconductor memory is widely used for many electronics data storage
applications.
Although first developed in the 1980s, the use of flash memory has grown rapidly in recent years as forms
the basis of many memory products.
Flash memory can be seen in many forms today including flash memory USB memory sticks, digital
camera memory cards in the form of compact flash or secure digital, SD memory. In addition to this flash
memory storage is used in many other items from MP3 players to mobile phones, and in many other
applications
There are also different flash memory types and these different types are each suited to their own
applications.

Flash memory storage is a form of non-volatile memory that was born out of a combination of the
traditional EPROM and E2PROM.

69
In essence it uses the same method of programming as the standard EPROM and the erasure method of
the E2PROM.
One of the main advantages that flash memory has when compared to EPROM is its ability to be erased
electrically. However it is not possible to erase each cell in a flash memory individually unless a large
amount of additional circuitry is added into the chip. This would add significantly to the cost and
accordingly most manufacturers dropped this approach in favour of a system whereby the whole chip, or
a large part of it is block or flash erased - hence the name.

Today most flash memory chips have selective erasure, allowing parts or sectors of the flash memory to
be erased. However any erasure still means that a significant section of the chip has to be erased.

Flash memory history

Flash memory dates back to around 1980 when the concept was developed at Toshiba by
Dr.FujioMasuoka. It was then later presented at the 1984 IEEE International Electron Devices Meeting,
IEDM held in San Francisco, California.
The basic laboratory concept took a few years to develop into a product that could be launched
commercially. Intel introduced the first commercial chips onto the market in 1988 - these were NOR
based types.
The NOR flash memories had relatively long erase and write times. Toshiba again developed their
technology further and were able to announce NAND technology at the 1987 IEDM. This technology,
though, still needed further development to take it through to commercial launch.
The advantage of NAND flash was that it had reduced erase and write times and it had a greater storage
density.

Flash memory advantages & disadvantages

As with any technology there are various advantages and disadvantages. It is necessary to consider all of
these when determining the optimum type of memory to be used.

70
 FLASH MEMORY FLASH MEMORY
ADVANTAGES DISADVANTAGES
 Non-volatile memory  Higher cost per bit than hard drives
 Easily portable (e.g. USB  Slower than other forms of memory
memory sticks)
 Limited number of write / erase
 Mechanically robust cycles
 Data must be erased before new data
can be written
 Data typically erased and written in
blocks

Flash memory types

There are two basic types of Flash memory. Although they use the same basic technology, the way they
are addressed for reading and writing is slightly different. They two flash memory types are:

1. NAND Flash memory: NAND Flash memories have a different structure to NOR memories.
This type of flash memory is accessed much like block devices such as hard disks. When NAND
Flash memories are to be read, the contents must first be paged into memory-mapped RAM. This
makes the presence of a memory management unit essential.

2. NOR Flash memory: NOR Flash memory is able to read individual flash memory cells, and as
such it behaves like a traditional ROM in this mode. For the erase and write functions, commands
are written to the first page of the mapped memory, as defined in "common flash interface"
created by Intel.

NAND / NOR tradeoff: NAND Flash memories and NOR Flash memories can be used for different
applications. However some systems will use a combination of both types of Flash memory. The NOR
memory type is used as ROM and the NAND memory is partitioned with a file system and used as a
random access storage area.

Flash memory is a particularly important form of semiconductor memory. It is now widely used and is
possibly one of the most important forms of medium term storage. As mentioned earlier Flash memory
can be seen in a variety of forms and uses ranging from Flash memory USB sticks to Compact Flash
cards used for cameras. In addition to this many other items of electronics can be seen using Flash
memory ranging from mobile phones to MP3 players and many more. In view of its current importance,
Flash memory will be seen in widespread use for many years to come.

71
I/O DEVICES:

In computing, input/output or I/O (or, informally, io or IO) is the communication between

an information processing system, such as a computer, and the outside world, possibly a human or
another information processing system. Inputs are the signals or data received by the system and outputs
are the signals or data sent from it. The term can also be used as part of an action; to "perform I/O" is to
perform an input or output operation.
I/O devices are the pieces of hardware used by a human (or other system) to communicate with a
computer. For instance, a keyboard or computer mouse is an input device for a computer,
while monitors and printers are output devices. Devices for communication between computers, such
as modems and network cards, typically perform both input and output operations.
The designation of a device as either input or output depends on perspective. Mouse and keyboards take
physical movements that the human user outputs and convert them into input signals that a computer can
understand; the output from these devices is the computer's input. Similarly, printers and monitors take
signals that a computer outputs as input, and they convert these signals into a representation that human
users can understand. From the human user's perspective, the process of reading or seeing these
representations is receiving output; this type of interaction between computers and humans is studied in
the field of human–computer interaction.
In computer architecture, the combination of the CPU and main memory, to which the CPU can read or
write directly using individual instructions, is considered the brain of a computer. Any transfer of
information to or from the CPU/memory combo, for example by reading data from a disk drive, is
considered I/O.[1] The CPU and its supporting circuitry may provide memory-mapped I/O that is used in
low-level computer programming, such as in the implementation of device drivers, or may provide access
to I/O channels. An I/O algorithm is one designed to exploit locality and perform efficiently when
exchanging data with a secondary storage device, such as a disk drive.

Some of the I/O devices are explained below:

(1) Keyboard : Keyboard is used in the input phase of a computer-based information system. Keyboard
is most common input device is used today. The data and instructions are input by typing on the
keyboard. The message typed on the keyboard reaches the memory unit of a computer. It’s connected to a
computer via a cable. Apart from alphabet and numeral keys, it has other function keys for performing
different functions.

(2) Mouse : It’s a pointing device. The mouse is rolled over the mouse pad, which in turn controls the
movement of the cursor in the screen. We can click, double click or drag the mouse. Most of the mouse’s
have a ball beneath them, which rotates when the mouse in moved. The ball has 2 wheels of the sides,
which in turn mousse with the movement of the ball. The sensor notifies the speed of its movements to
the computer, which in turn moves the cursor/pointer on the screen.
(3) Scanner : Scanners are used to enter information directly in to the computers memory. This device
works like a Xerox machine. The scanner converts any type of printed or written information including
photographs into digital pulses, which can be manipulated by the computer.
(4) Track Ball : Track ball is similar to the upside- down design of the mouse. The user moves the ball
directly, while the device itself remains stationary. The user spins the ball in various directions to effect
the screen movements

72
(5) Light Pen : This is an input device which is used to draw lines or figures on a computer screen. It’s
touched to the CRT screen where it can detect raster on the screen as it passes.
(6) Optical Character Rader : It’s a device which detects alpha numeric characters printed or written on
a paper. The text which is to be scanned is illuminated by a low frequency light source. The light is
absorbed by the dark areas but reflected from the bright areas. The reflected light is received by the
photocells
(7) Bar Code Reader : This device reads bar codes and coverts them into electric pulses to be processed
by a computer. A bar code is nothing but data coded in form of light and dark bars.

(8) Voice Input Systems : This devices converts spoken words to M/C language form. A micro phone is
used to convert human speech into electric signals. The signal pattern is then transmitted to a computer
when it’s compared to a dictionary of patterns that have been previously placed in a storage unit of
computer. When a close match is found, the word is recognized.

(9) Plotter : Plotter is an O/P device that is used to produce graphical O/P on papers. It uses single color
or multi color pens to draw pictures as blue print etc.

(10) Digital Camera : It converts graphics directly into digital form. It looks like an ordinary camera, but
no film is used therein, instead a CCD (changed coupled Divide) Electronic chip in used. When light falls,
on the chip though the lens, it converts light waves into electrical waves.

73
 UNIT –IV

Instruction Design & I/O Organization

Machine Instruction

A binary code used for specifying micro operations for computer.

Instruction Code

Group of bits used to instruct the CPU to perform specific operation.

 Instructions are encoded as binary instruction codes.

 Each instruction code contains of a operation code, or opcode, which designates the
overall purpose of the instruction.
 The number of bits allocated for the opcode determined how many different instructions
the architecture supports.

Instruction Set

Collection of instructions.

Instruction Representation

Each instruction has a unique bit pattern, but for human beings a corresponding symbolic
representation has been defined.

Instruction Cycles

Instruction cycle consists of following phases

 Fetching an instruction from memory.

 Decoding the instruction.

74
 Reading the effective address from memory in case of the instruction having an indirect
address.
 Execution of the instruction.
 Writing the results back to the memo

75
Instruction Format

An instruction consists of bits and these bits are grouped up to make fields.

Some fields in instruction format are as follows

1. Opcode which tells about the operation to be performed.

2. Address field designating a memory address or a processor register.
3. Mode field specifying the way the operand or effective address is determined.

Different types of Instruction formats

Some common types are as: Three address instruction format, Two address instruction format,
One address instruction format, and Zero address instruction format.

 Three Address Instruction Format: This system contains three address fields (address of
operand1, address of operand2 and address where result needs to be put). The address of
next instruction is held in a CPU register called Program Counter (PC).

Here, the number of bytes required to encode an instruction is 10 bytes.

Each address requires 24 bit = 3 bytes.

Since, there are three addresses and one opcode field.

Therefore 3 × 3 + 1 = 10 bytes.

The number of memory access required is 7 words.

4 words for instruction fetch, 2 words for operand fetch and 1 word for result to be placed back
in memory.

 Two Address Instruction Format: In this format, two addresses and an operation field is
there. The result is stored in either of the operand address i.e., either in address of first

76
 operand or in the address of second operand. CPU register called Program Counter (PC)
contains the address of next instruction.

 One Address Instruction Format: One address field and an operation field. This address is
of the first operand. The second operand and the result are stored in a CPU register called
Accumulator Register (AR). Since, a machine has only one accumulator, it needs not be
explicitly mentioned in the instruction. A CPU register (i.e., Program Counter (PC) holds
the address of next instruction. In this scenario, two extra instructions are required to
load and store the accumulator contents.

Number of bits required to encode an instruction is 4 bytes. i.e., each address requires 24 bits = 3
bytes. Since, there are one address and one operation code field, 1* 3 + 1= 4 bytes.

The number of memory access required is 3 words i.e., 2 words for instruction fetch +1 word for
code for operand fetch.

 Zero Address Instruction Format: Stack is included in the CPU for performing arithmetic
and logic instructions with no addresses. The operands are pushed onto the stack from
memory and ALU operations are implicitly performed on the top elements of the stack.
The address of the next instruction is held in a CPU register called program counter.

77
e.g., Add

Top of stack ← Top of stack + second top of stack.

Addressing Modes:

The different ways in which the location of an operand is specified in an instruction are referred
to as addressing modes.

Types of Addressing Modes

Memory Based Addressing Modes:

 Implied Addressing Mode: In this mode the operands are specified implicitly in the
definition of an instruction.
 Immediate Addressing Mode: In this mode the operand is specified in the instruction
itself or we can say that, an immediate mode instruction has an operand rather than an
address.
 Direct Register Addressing Mode: In this mode, One of the operand is in registers and
other is taken from mempry.
 Direct Addressing Mode: It this mode, the address of the memory location that holds the
operand is included in the instruction. The effective address is the address part of the
instruction.
 Indirect Addressing Mode: In this mode the address field of the instruction gives the
address where the effective address is stored in memory.
 Relative Addressing Mode: In this mode the content of program counter is added to the
address part of the instruction to calculate the effective address.
 Indexed Addressing Mode: In this mode, the effective address will be calculated as the
addition of the content of index register and the address part of the instruction.

78
Transfer Of Control Addressing Modes:

PC Relative Addressing Mode: This addressing mode is used to access the instruction within the
segment, therefore only one offset address is required.

Base register Addressing Mode: This addressing mode is used to access the instructions between two
segments. therfore, base address as well as offset is required.

Types of Instructions

 Data Transfer Instructions: Data transfer instructions cause transfer of data from one
location to another without changing the information content. The common transfers may
be between memory and processor registers, between processor registers and
input/output.

Typical Data Transfer Instructions

 Data Manipulation Instructions: Data manipulation instructions perform operations on

data and provide the computational capabilities for the computer. There are three types of
data manipulation instructions: Arithmetic instructions, Logical and bit manipulation
instructions, and Shift instructions.

Typical Arithmetic Instructions

79
Typical Logical and Bit Manipulation Instructions

Typical Shift Instructions

80
Program Control Instructions

Program control instructions specify conditions for altering the content of the program counter,
while data transfer and manipulation instructions specify conditions for data processing
operations. The change in value of a program counter as a result of the execution of a program
control instruction causes a break in the sequence of instruction execution.

Typical Program Control Instructions

81
Program Interrupt

The program interrupts are used to handle a variety of problems that arise out of normal program
sequence.

 Program interrupts are used to transfer the program control from a currently running
program to another service program as a result of an external or internal generated
request. Control returns to the original program after the service program is executed.

Types of Interrupts

Interrupts can be classified into two categories:

On the basis of Masking

1. Maskable Interrupts: It may be a hardware or a software interrupt which can be masked

for future.
2. Non-Maskable Interrupts: A non-maskable interrupt (NMI) is a hardware interrupt that
standard interrupt-masking techniques in the system cannot ignore. It typically occurs to
signal attention for non-recoverable hardware errors.

On the basis of devices

1. External interrupt: External interrupts come from Input-Output (I/O) devices or from a
timing device.
2. Internal interrupt: Internal interrupts arise from illegal or erroneous use of an instruction
or data. External and internal interrupts from signals that occur in the hardware of the
CPU.
3. Software interrupt: A Software interrupt is initiated by executing an instruction.

Complex Instruction Set Computer (CISC)

 Computer architecture is described as the design of the instruction set for the processor.

82
  The computer with a large number of instructions is classified as a complex instruction
set computer. The CISC processors typically have the 100 to 250 instructions.
 The instructions in a typical CISC processor provide direct manipulation of operands
residing in memory.
 As more instructions and addressing modes are incorporated into a computer, the more
hardware logic is needed to implement and support them and this may caus e the
computations to slow down.

Reduced Instruction Set Computer (RISC)

 RISC architecture is used to reduce the execution time by simplifying the instruction set
of the computer.
 In the RISC processors, there are relatively few instructions and few addressing modes.
In RISC processors, all operations are done within the registers of the CPU.

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three types of modes
which are given below:

1. Programmed I/O

2. Interrupt Initiated I/O

3. Direct Memory Access

Programmed I/O

Programmed I/O instructions are the result of I/O instructions written in computer program. Each data
item transfer is initiated by the instruction in the program.

83
Usually the program controls data transfer to and from CPU and peripheral. Transferring data under
programmed I/O requires constant monitoring of the peripherals by the CPU.

Interrupt Initiated I/O

In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that it is
ready for data transfer. This is time consuming process because it keeps the processor busy needlessly.

This problem can be overcome by using interrupt initiated I/O. In this when the interface determines
that the peripheral is ready for data transfer, it generates an interrupt. After receiving the interrupt signal,
the CPU stops the task which it is processing and service the I/O transfer and then returns back to its
previous processing task.

Direct Memory Access

Removing the CPU from the path and letting the peripheral device manage the memory buses directly
would improve the speed of transfer. This technique is known as DMA.

In this, the interface transfer data to and from the memory through memory bus. A DMA controller
manages to transfer data between peripherals and memory unit.

Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound
cards etc. It is also used for intra chip data transfer in multicore processors. In DMA, CPU would initiate
the transfer, do other operations while the transfer is in progress and receive an interrupt from the DMA
controller when the transfer has been completed.

84
 Above figure shows block diagram of DMA

I/O Processor:

The DMA mode of data transfer reduces CPU’s overhead in handling I/O operations. It also allows
parallelism in CPU and I/O operations. Such parallelism is necessary to avoid wastage of valuable CPU
time while handling I/O devices whose speeds are much slower as compared to CPU. The concept of
DMA operation can be extended to relieve the CPU further from getting involved with the execution of
I/O operations. This gives rises to the development of special purpose processor called Input-Output
Processor (IOP) or IO channel.
The Input Output Processor (IOP) is just like a CPU that handles the details of I/O operations. It is more
equipped with facilities than those are available in typical DMA controller. The IOP can fetch and
execute its own instructions that are specifically designed to characterize I/O transfers. In addition to the
I/O – related tasks, it can perform other processing tasks like arithmetic, logic, branching and code
translation. The main memory unit takes the pivotal role. It communicates with processor by the means of
DMA.

85
The block diagram –

The Input Output Processor is a specialized processor which loads and stores data into memory along
with the execution of I/O instructions. It acts as an interface between system and devices. It involves a
sequence of events to executing I/O operations and then store the results into the memory.

Advantages –
 The I/O devices can directly access the main memory without the intervention by the processor in
I/O processor based systems.
 It is used to address the problems that are arises in Direct memory access method.

86