VLSI Training Center

Setting standards in VLSI Design

System Verilog

1. Predict the output of the following program.

module test();

class AB;
int i = 1;
endclass

AB a1;

initial
begin
repeat(2)
begin
AB a2 = new();
a1 = new();

a1.i++;
a2.i++;
$display("disp_1 -- a1.i = %0d, a2.i
= %0d", a1.i, a2.i);
a1.i++;
a2.i++;
$display("disp_2 -- a1.i = %0d, a2.i
= %0d", a1.i, a2.i);
end
end
endmodule

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Setting standards in VLSI Design

2. Predict the output of the below program.

module test();

class AB;
int i;
pure virtual function void disp();
endclass

class BC extends AB;

int j;
function void disp(int z);
j = z;
$display("%0d", j);
endfunction
endclass

class CD extends AB;

int k;
function void display(int z);
k = z;
$display("%0d", k);
endfunction
endclass

AB a_h = new();
BC b_h = new();
CD c_h = new();

initial
begin
a_h.disp();
b_h.disp(2);
c_h.display(3);
end
endmodule

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 VLSI Training Center
Setting standards in VLSI Design

3. Predict the output of the below program.

module test();

class AB;
rand int i;
task xyz(string s);
fork
begin
#(i);
end
begin
#(20);
$display("in object of %s, 20ns delay is
completed", s);
end
join_any
disable fork;
endtask
endclass

AB a1 = new();
AB a2 = new();

initial
begin
a1.i = 5;
a2.i = 30;
fork
a1.xyz("a1");
a2.xyz("a2");
join
end
endmodule

4. Can we do the object assignment with the three given objects.

class AB #(type T= int, int width = 8);

T i;
bit[width-1:0] b;

endclass

AB #(int, 8) a_h1;
AB #(real, 16) a_h2;
AB a_h3;

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