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Synchronization of a single-phase photovoltaic generator with the grid

Conference Paper · March 2011

Source: dx.doi.org

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 Synchronization of a single-phase photovoltaic
generator with the grid

N. Anani, O. Al-Kharji Al-Ali and P. Ponnapalli S. R. Al-Araji and M. A. Al-Qutayri

School of Engineering College of Engineering
Manchester Metropolitan University Khalifa University of Sci, Tech, and Research
Manchester, UK Sharjah Campus, UAE
n.anani@mmu.ac.uk; oalkharji@yahoo.com alarajis@kustar.ac.ae; mqutayri@kustar.ac.ae

Abstract—this paper presents the architecture of a hybrid phase grid is necessary not only for improved efficiency, but also to
lock loop circuit topology for synchronizing a single-phase comply with relevant national and international standards [4,5].
inverter fed from a renewable energy source such as a
photovoltaic (PV) generator to the low voltage utility grid. The In addition, the inverter must be cable of re-gaining
system uses a digital phase lock loop (DPLL) architecture, which synchronization following a sudden change in the grid
is based on the arctan phase detector, driving a phase lock loop waveform such as a step change in the phase.
(PLL) to synchronize a PV generator with the grid. The proposed
Various methods for synchronization have been presented
system has been tested by simulation using Simulink/Matlab. The
in the literature [6-9].
test results, which are also presented, demonstrate the ability of
the system to synchronize a PV inverter with the grid and to re-
gain synchronization following a sudden change in the phase of
the grid voltage.

Keywords- PV generator, grid synchronization, phase lock loop,

time-delay tanlock loop.

I. INTRODUCTION
Growing concerns over the environment coupled with
uncertainty about the stability of supplies and prices of fossil
fuels led to renewed interests amongst governments and
researchers in renewable energy sources (RES) [1-3]. These Fig. 1(a)
include solar, wind, geothermal, hydro and tidal. Due to their
abundance and ease of utilization with current power
electronics technology, solar and wind energy have gained
particular interest. Solar energy is harnessed by means of
photovoltaic (PV) systems, which use arrays of PV panels that
convert solar energy into electrical energy. PV generating
systems may be categorized as standalone, Fig. 1(a), or grid-
tied. In a standalone system, the energy harvested by the PV
panel is conditioned via a dc-dc converter with an MPPT
(maximum power point tracking) algorithm so that the PV is
operated at its maximum power point at all times [3,4].
Standalone PV systems are suitable for applications such
battery charging, lighting and water pumping in remote areas. Fig. 1(b)
The dc voltage is used to charger a battery which is connected
to a dc-ac inverter that finally feeds an ac load such as a water Figure 1. (a) Standalone and (b) grid-tie in inverter.
pump. An efficient method of utilizing the energy harvested by
a renewable energy source such as a PV generator is by In this paper a new circuit topology for synchronizing the
connecting the PV generator to the low voltage utility grid. inverter voltage to the grid is presented. The proposed circuit is
This is done using a voltage source inverter (VSI) known as a based on the digital phase lock loop (DPLL) which has been
grid-tie inverter in a system similar to that depicted in Fig. 1(b). used extensively in communications and signal processing
The inverter must convert the RE stored in the battery bank systems that require phase tracking and synchronization
into grid-quality sinusoidal voltage that tracks the grid voltage [10,11]. In particular, the proposed system makes use of a
in amplitude, frequency and phase. That is the inverter must be variant of the DPLL known as the time-delay digital tanlock
synchronized with the grid. Better synchronization with the loop (TDTL) [12]. Essentially, the system is a TDTL circuit
driving a phase lock loop for which the input is the grid As both the incoming input signal and its phase-shifted
voltage, henceforth, referred to as TDTL-PL and is shown in version pass through a sample and hold blocks, as illustrated in
Fig. 2. The system has been tested by simulation using Fig. 1, sampled versions of these continuous signals (1) and
Simulink/Matlab software. (2) can be expressed as in (3) and (4) respectively.
The TDTL-PL performed as expected in synchronizing the y k Asin ω t k θ k 3
inverter with the grid and managed to re-gain synchronization
following single and multi-step changes in the phase of the grid and
voltage. The paper presents the mathematical analysis of the x k Asin ω t k θ k ψ 4
proposed system in section II, whilst the testing results of the
system are presented in section III. Section IV summarizes the where θ k θt k
paper and proposes future work. The sampling interval between the sampling instants
t k and t k 1 is given by
II. SYSTEM ANALYSIS
The block diagram of the proposed systems is shown in T k T c k 1 5
Fig. 2. The system consists of two loops; the main ‘or upper’ where T 2π⁄ω is the nominal period of the DCO and
loop, which is based on the TDTL architecture, and this is used c i is the output of the digital loop filter at the ith sampling
to correct the phase-error produced by the lower loop whenever instant. By assuming t 0 0, the time up to the Kth sampling
there is a phase difference between the grid and the output of instant is given by
the digital controlled oscillator (DCO).

t k T i kT c i 6

As a result both y k and x k are written as

y k A sin θ k ω c i 7

and

x k A sin θ k ω c i ψ 8

Therefore, the phase error difference between the incoming

input signal and the DCO can be defined as

Figure. 2: Block diagram of the TDTL-PL. k θ k ω c i ψ 9

Both (7) and (8) can be expressed in term of phase error as

A continuous sinusoidal input signal y t with a frequency
offset Δω ω ω is received by the proposed design, y k A sin k ψ 10
which is also translated as a phase shift, from the free running
frequency ω of the digital controlled oscillator (DCO), as and
follows x k A sin k 11
y t Asin ω t θ t 1 Therefore, the loop error signal e k produced by the phase
where A is the amplitude of the incoming input signal whilst detector can be expressed as

θ t Δωt θ sin k
e k f tan 12
sin k ψ
is its phase process and θ is constant.
where f γ π γ π mod 2π . This error signal
The incoming signal is passed through a time delay τ that e k represent the non-linear phase error version that have a
introduces a variable phase shift ‘lag’ of ψ ωτ whose value major effect as the phase shift ψ moves away from π⁄2 value.
depends on the frequency of the incoming signal. The digital loop filter with a transfer function D k receives the
Consequently, a phase shifted signal x t of the incoming input error signal e k and produces the signal c k that drives the
signal is generated due to the delay which may be expressed as DCO to the required frequency. Consequently, the system
x t Asin ω t θ t ψ 2 difference equation can be derived from (6) and (9) as
k 1 k ωc k Λ 13
where Λ 2π Δω⁄ω . Due to the nonlinearity produced by III. RESULTS
the variation in the phase shift ψ affected by the incoming The system of Fig. 2 was tested by applying a single phase
signal changes, the system difference equation can’t be solved step and multiple phase steps as shown in Fig. 3 and Fig. 4
by Z transform to find the locking range as the case for the respectively. Fig. 3 shows the phase error response and the
DTL [13]. Therefore, the difference equation can be solved phase plan which proves that the phase error goes to zero.
numerically using the fixed point theorem [14-16]. Another test was performed by applying consecutive phase
The second order loop utilizes a proportional plus steps, as shown in Fig. 4. Both phase error Fig. (4a) and phase
accumulation digital filter transfer function D z which is plan Fig. (4b) indicate that the system was successful in
given by achieving synchronization between the grid and the PV
generator.
D z G G ⁄ 1 z 14
where G and G are positive constants. From (13) and (14), the
difference equation of the second order TDTL system can be
obtained as
k 2 2 k 1 k rK h k 1
K h k 15
where r 1 G ⁄G and K K ω. Following the same
procedure as in [14,16] with a fixed point analysis as in [15,16]
the second order TDTL locking range is given by
4 ψ
0 K W sin 16
1 r W
where ψ is the nominal phase lag induced into the incoming
signal by the time delay unit.
Figure 3(a). Input phase step.
There will be error produced by the multiplication of both
DCO and the grid signal if they are out of phase. This error is
added to the main loop to be corrected. Therefore, the mixer
only produces zero error only when both signals are in phase.
Assuming that the signal coming from both the grid and the
DCO, respectively, are
G t Asin ω t θ t ψ 17
D t Acos ω t θ t 18
where ψ is the nominal phase difference between the grid and
the DCO.
Therefore the output of the multiplier is S t D t G t .
Figure 3(b). Phase error for phase step input.
Hence,
A
S t sin ψ sin 2ω t 2θ t ψ 19
2
The output of the multiplier as given by (19) consists of
two parts, the first one is function of only the phase difference
between the two signals and the second term is at a frequency,
which is twice the signal frequency plus the sum of the two
phases.
A low pass filter (LPF) is attached to the output of the
multiplier signal S(t). If initially, there is no phase shift, then
the phase difference will be zero and consequently the dc
output of the LPF will also be zero. On the other hand, when a
phase step is applied to the input, a phase error will be
generated, resulting in a nonzero dc output which will be
corrected by the TDTL loop, therefore, D(t) will be
Figure 3(c) Phase plan for phase step
synchronized with the grid.
 difference between the grid and the digital controlled oscillator
(DCO) output. Synchronization between the grid and PV
source was achieved by the proposed system. The system was
tested by applying a single and consecutive phase steps to the
grid. Future work will include more extensive evaluations of
the proposed loop under dynamic environment such as Noise
and glitches effect.
REFERENCES

[1] D. Jinxu and A. Somani, "A Long-Term Investment Planning Model for
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[2] UK Government White Paper on Energy, “Meeting the Challenge,” 23rd
May2007. UK.
[3] Directive 2009/28/EC OF the European Parliament and of the Council
Figure 4(a). Consecutive Input Phase Step.
of 23 April 2009 on the promotion of the use of energy from renewable
sources and amending and subsequently repealing Directives
2001/77/EC and 2003/30/EC.
[4] D. P. Kothari, "Renewable energy scenario in India," IEEE Power
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Figure 4(b). Phase error for Consecutive Input Phase Step. 1409.
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Figure 4(c). Phase plan for consecutive phase steps.
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IV. CONCLUSIONS
A hybrid phase lock loop with dual input sources (TDTL-
PL) topology that consists of an ‘upper’ and a ‘lower’ loop
were designed and simulated using Matlab/Simulink. The main
upper loop which is based on TDTL and is used to correct the
phase-error produced by the lower loop when there is a phase

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