CMOS Logic Circuit Design

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Combinational and Sequential CMOS Circuits

• Combinational CMOS Circuits
– Definition of a Combinational CMOS Circuit
– Logic Depth of a Combinational CMOS Circuit
• Sequential CMOS Circuits
– Definition of a Sequential CMOS Circuit
– Conventional Sequential Circuit Structure
– Finite-State Machine (FSM): Sequential Circuit with Feedback
• Methods for Increasing the Throughput of CMOS Circuits
– Combinational Circuits: Parallel Processing
– Sequential Circuits: Pipeline Processing
– Comparison of the Quality of Parallel and Pipeline Processing

Mattausch, CMOS Design, H20/5/16 1

Combinational CMOS Circuits
- Definition of a Combinational Circuit
- Logic Depth of a Combinational Circuit

Mattausch, CMOS Design, H20/5/16 2

 Definition of a Combinational CMOS Circuit

1) Output signals Outcj(Inci) of a combinational CMOS circuit are only a

function of its input signals Inci

2) Output signals of a combinational CMOS circuit are valid a delay

time tdc after the input signals become valid

3) Combinational CMOS circuits do not contain any kind of information-

storing elements [necessary for 1)]

4) Combinational CMOS circuits do not contain any kind of feedback

[necessary for 1)]

The simplest type of a logic CMOS circuit is a

combinational CMOS circuit.
Mattausch, CMOS Design, H20/5/16 3
Logic Depth of a Combinational CMOS Circuit

Example of a combinational circuit with logic depth 3

(red lines show the signals which pass through 3 logic gates)

In1
Out1
In2

In3
In4

In5 Out2

The logic depth N of a combinational circuit is given by the

signal path with the largest number N of logic gates.
Mattausch, CMOS Design, H20/5/16 4
Sequential CMOS Circuits
- Definition of a Sequential CMOS Circuit
- Conventional Sequential Circuit Structure
- Finite-State Machine (FSM): Sequential
Circuit with Feedback

Mattausch, CMOS Design, H20/5/16 5

 Definition of a Sequential CMOS Circuit
1) Sequential CMOS circuits are constructed with combinational CMOS
circuits and information-storing elements.

2) Output signals Outsj(Insi, Stsk) of a sequential CMOS circuit are a

function of its input signals Insi and of its stored signals Stsk.

3) The information-storing elements in a sequential CMOS circuit are

normally edge-triggered D flip-flops (registers) or latches and are
controlled by a clock signal.

4) The validity time of the output signals of a sequential CMOS circuit is

determined by the clock signal and the type of the storing elements.

5) If edge-sensitive registers are used, the outputs are valid a

delay time tds after the sensitive edge of the clock signal.

Most digital CMOS logic circuits are complicated

sequential CMOS circuits.
Mattausch, CMOS Design, H20/5/16 6
 Sequential CMOS Circuit with Registers

Structure of a sequential CMOS Circuit

with a sequential depth of 3 registers

N1 N1’ N2 N2’ N3 N3’

D Q D Q D Q
tqr Combinational tsr tqr Combinational tsr
N1-Bit Circuit 1 N2-Bit Circuit 2 N3-Bit
Register Register Register
td1 td2

clock

tc

The sequential depth of CMOS circuits is the number of

sequential registers in the longest signal path of the circuit.
Mattausch, CMOS Design, H20/5/16 7
 Timing of Sequential Circuits with Registers

Timing diagram of a sequential Timing requirement for a

CMOS Circuit with registers sequential CMOS Circuit
tc
clock with registers
N1 tc ≥ td1+tqr+tsr
tsr
thr
td1 = delay time of the
N1’
tqr combinational logic
N2 tqr = clock-to-Q delay time
td1 of the register
N2’ tsr = set-up time
tqr of the register

The timing of a sequential CMOS circuit with registers is

simple because it is based on a clock edge.
Mattausch, CMOS Design, H20/5/16 8
 Sequential CMOS Circuit with Latches

Structure of a sequential CMOS Circuit with a sequential

depth of 3 latches (level-sensitive D flip-flops)

N1 N1’ N2 N2’ N3 N3’

D Q D Q D Q
tql+ Combinational tsl- tql- Combinational tsl+
N1-Bit N2-Bit N3-Bit
Circuit 1 Circuit 2
Latch Latch Latch
td1 td2

clock

tc

A sequential CMOS circuit with latches requires alternating

usage of positive and negative level-sensitive latches.
Mattausch, CMOS Design, H20/5/16 9
 Timing of Sequential Circuits with Latches
Timing diagram of a sequential Timing requirement for a
CMOS Circuit with latches sequential CMOS Circuit
tc
clock with latches
N1 tc ≥ td1+td2+tql++tql-
tsl
+ thl+ +tsl++tsl-
N1’
tql+ td1 ,td2 = delay times of the
N2 combinational logic
td1 tql = clock-to-Q delay time
tsl-
N2’ of the latch
tql- tsl = set-up time
N3 of the latch
td2
tsl+

A sequential CMOS circuit with latches requires a clock-cycle

time, which is about twice as long as in the case of registers.
Mattausch, CMOS Design, H20/5/16 10
 Structure of a State Machine with Registers
A state machine needs at least a Operation:
combinational circuit and a N-bit The bits of the next state are
register for storing the state bits determined by the bits of the
current state and the input bits.
Inputs Outputs

Combinational Moore Machine:

Circuit
Only the bits of the current state are
used to determine the output bits.
Current Next
state bits state bits
(N) (N)
Q D Mealy Machine:
N-Bit The bits of the current state and the
Register input bits are used to determine the
clock output bits.

The finite-state machine (FSM) is mainly used for the control

functions in CMOS logic circuits.
Mattausch, CMOS Design, H20/5/16 11
Methods for Increasing the
Throughput of CMOS Circuits
- Combinational Circuits: Physical
Parallel Processing
- Sequential Circuits: Pipeline
Processing or Time-Overlapped
Parallel Processing
- Comparison of the Efficiency of
Physical Parallel Processing and
Pipeline Processing

Mattausch, CMOS Design, H20/5/16 12

 Throughput, Efficiency and Latency of Circuits

Throughput = R
= (Circuit Operations)/(Time)
Efficiency = E
= Throughput/(Silicon Area)

Latency =L
= Time from beginning to end
of one operation

Throughput, efficiency and latency are important quantities

for judging the quality of a CMOS logic circuit.
Mattausch, CMOS Design, H20/5/16 13
 Throughput of a Combinational Circuit

The shortest operation time is the delay

time tdc of the combinational circuit.
Parameters of a
Combinational Circuit
The maximum throughput in time T is
R(T) = T ·(tdc)-1.
In Combinational Out
Circuit In1 tdc Out1
Out=F(In)
In2 tdc Out2
Delay = tdc
In3 tdc Out3
In4 tdc Out4

Time

The maximum throughput of a combinational circuit is limited

by its physical delay time.
Mattausch, CMOS Design, H20/5/16 14
Throughput Increase through Physical Parallelism
The shortest operation time is still the
2 identical combinational delay time tdc of the combinational
circuits used in parallel circuit, but 2 circuits operate in parallel.
In(odd) Out(odd)
Combinational
Circuit The maximum throughput in time T is
Out=F(In) doubled to R(T) = 2T ·(tdc)-1.
Delay = tdc
In1 tdc Out1
In2 tdc Out2
In(even) Out(even)
Combinational In3 tdc Out3
Circuit
Out=F(In) In4 tdc Out4

Delay = tdc
Time

The throughput of combinational circuits can be increased by

a factor N through parallel operation of N identical circuits.
Mattausch, CMOS Design, H20/5/16 15
 Higher Throughput by Pipelining (Structure)

In Combinational Out
Circuit
Out=F(In) If tsr and tqr are negligible, the
Delay = tdc 2-stage pipeline achieves a 2-
fold larger throughput by
time-overlapped processing.
Int Int’
In Combinational Combinational Out
D Q
Part 1 tsr tqr Part 2
Out1=F1(In) N-Bit Out=F2(Int’)
Register F(In)=F2(F1(In))
Delay ≈ tdc/2 Delay ≈ tdc/2
clock

Partitioning of combinational CMOS circuits into N parts and

operation as a sequential circuit is called N-stage pipelining.
Mattausch, CMOS Design, H20/5/16 16
 Higher Throughput by Pipelining (Time View)

Combinational Circuit 2-Stage Pipeline Circuit

(Processing of 1 Input per Time) (Processing of 2 Inputs per Time)

F(In1) F1(In1) F2(Int1)

tsr ~ tqr ~ 0
F(In2) F1(In2) F2(Int2) assumed

F(In3) F1(In3) F2(Int3)

F1(In4) F2(Int4)

F1(In5) F2(Int5)
Latency tL Latency tL
tdc tdc tdc tdc tdc tdc
Time Time

N-stage pipelines achieve higher throughput by simultaneous

processing of N input data, but increase latency (tsr,tqr>0!).
Mattausch, CMOS Design, H20/5/16 17
Circuit-Quality Improvement by N-fold Parallelism
Definitions:
• A1, R1=1/L1 and E1=R1/A1 are area, throughput and efficiency of the non-parallel
combinational circuit.
• (N-1)Az is the additional area for input-data distribution and output data
gathering by N-fold parallelism. (N-1)Lz is the corresponding latency increase.
Latency: Throughput:
−1
L N, parallel = L 1 + (N − 1) ⋅ L z  L 
R N, parallel = N⋅ R 1 ⋅ 1 + (N − 1) z
 L 1 
 L
= L 1 ⋅ 1 + (N − 1) z
 L1

Silicon Area: Efficiency:

R N, parallel
A N, parallel = N ⋅ A 1 + (N − 1) ⋅ A z E N, parallel =
A N, parallel
 1 A −1 −1
= N ⋅ A 1 ⋅ 1 + (1 − ) z  1 A   L 
 = E 1 ⋅ 1 + (1 − ) z ⋅ 1 + (N − 1) z
N A1  N A 1   L 1 

N-fold parallelism improves throughput nearly by a factor N.

Since area increases also by N, efficiency gets slightly worse.
Mattausch, CMOS Design, H20/5/16 18
Circuit-Quality Improvement by N-Stage Pipeline
Definitions:
• A1, R1=1/L1 and E1=R1/A1 are area, throughput and efficiency of the non-
pipelined combinational circuit.
• Areg and Lreg= tsr+ tqr are additional area and latency of pipelining register.

Latency: Throughput:
−1
L N, pipeline = L 1 + (N − 1) ⋅ L reg  L 
R N, pipeline = N ⋅ R 1 ⋅ 1 + (N − 1) reg
 L 1 
 L
= L 1 ⋅ 1 + (N − 1) reg
 L1
Silicon Area: Efficiency:
R N, pipeline
A N, pipeline = A 1 + (N − 1) ⋅ A reg E N, pipeline =
A N, pipeline
 A  −1 −1
= A 1 ⋅ 1 + (N − 1) reg  A   L 
 A 1  = N ⋅ E 1 ⋅ 1 + (N − 1) reg ⋅ 1 + (N − 1) reg
 A 1   L 1 

N-fold pipelining improves throughput and efficiency, if area

and latency of the additional registers are small enough.
Mattausch, CMOS Design, H20/5/16 19