Professional Documents
Culture Documents
Bo Wang
Division of Information & Computing Technology
Hamad Bin Khalifa University
bwang@hbku.edu.qa
• Higher value is a logic “1”; lower value is a logic “0”; may have don’t care
values (represented by shaded grey area)
• Clocked RS latch
CLK R S Q (n)
0 X X Q (n-1)
1 0 0 Q (n-1)
1 0 1 1
1 1 0 0 CLK
1 1 1 X
R
Output only changes at the rising Reset Take effect
S
edge of the clock When clk=1
Set
Q Keep state
Keep state
• When the clock is low, the memory remembers the data, no matter how
the input changes, the output will not change
In Clk R S Out
0 0 0 0 Q (n)=Q (n-1)
1 0 0 0 Q (n)=Q (n-1)
0 1 1 0 Q=0
1 1 0 1 Q=1
• Transparent D Flip-flop
In Clk Out
0 0 Q (n)=Q (n-1)
1 0 Q (n)=Q (n-1)
0 1 Q=0
1 1 Q=1
D flip-flop symbol Truth table
• This means that the preceding logic circuits cannot start computing the
next operation while clock =1
• We call the first flip-flop a MASTER and the second one a SLAVE, and
hence we call this new memory element a MASTER-SLAVE D flip-flop
• The frequency at the output of the circuit becomes half of that of the input
• Each flip-flop divides the clock frequency of the input from the previous
flip-flop/ clock
Combinational Logic
Input Output
Combinational Logic
Memory
Clock