PROBLEMA 1

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY problema1 IS
PORT(
x1,x2,x3,x4 : IN STD_LOGIC;
f1,f2 : OUT STD_LOGIC);
END problema1;

ARCHITECTURE solucion OF problema1 IS

BEGIN
f1 <= (x1 AND NOT(x3)) OR (x2 AND NOT(x3)) OR (NOT(x3) AND NOT(x4)) OR (x1 AND x2) OR (x1
AND NOT(x4));
f2 <= (x1 OR NOT(x3)) AND (x1 OR x2 OR NOT(x4)) AND (x2 OR NOT(x3) OR NOT(x4));

END solucion;

PROBLEMA 2

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY problema2 IS
PORT(
x1,x2,x3,x4 : IN STD_LOGIC;
f1,f2 : OUT STD_LOGIC);
END problema2;

ARCHITECTURE solucion OF problema2 IS

BEGIN
f1 <= ((x1 AND x3) OR (NOT(x1) AND NOT(x3)) OR (x2 AND x4) OR (NOT(x2) AND NOT(x4));

f2 <= (x1 AND x2 AND NOT(x3) AND NOT(x4) OR (NOT(x1) AND NOT(x2) AND x3 AND x4) OR (x1
AND NOT(x2) AND NOT(x3) AND x4) OR (NOT(x1) AND x2 AND x3 AND NOT(x4));
END solucion;

PROBLEMA 3
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY problema3 IS
PORT(
X : IN STD_LOGIC_VECTOR(4 DOWNTO 1);
F : OUT STD_LOGIC);
END problema3;

ARCHITECTURE solucion OF problema3 IS

BEGIN

with X select

F <= ‘1’ when “0000”,

‘1’ when “0001”,
‘1’ when “0010”,
‘1’ when “0100”,
‘1’ when “0101”,
‘1’ when “0111”,
‘1’ when “1000”,
‘1’ when “1001”,
‘1’ when “1011”,
‘1’ when “1100”,
‘1’ when “1110”,
‘1’ when “1111”,
‘0’ when others;

END solucion;

PROBLEMA 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY test4 IS

PORT(
X : IN STD_LOGIC_VECTOR(4 DOWNTO 1);
F : OUT STD_LOGIC);
END test4;

ARCHITECTURE solucion OF test4 IS

BEGIN
with X select

F <= '0' when "0110",

'0' when "1000",
'0' when "1001",
'0' when "1100",
'0' when "1101",
'1' when others;

END solucion;