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UCC27282
SNVSAQ5 – NOVEMBER 2018
LI HS
0 …F
VSS LO
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27282
SNVSAQ5 – NOVEMBER 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 14
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 16
3 Description ............................................................. 1 8 Application and Implementation ........................ 17
4 Revision History..................................................... 2 8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 18
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 25
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 26
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 26
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 26
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 27
6.5 Electrical Characteristics........................................... 5 11.1 Receiving Notification of Documentation Updates 27
6.6 Switching Characteristics .......................................... 6 11.2 Community Resources.......................................... 27
6.7 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 27
7 Detailed Description ............................................ 13 11.4 Electrostatic Discharge Caution ............................ 27
7.1 Overview ................................................................. 13 11.5 Glossary ................................................................ 27
7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
DATE REVISION NOTES
November 2018 * Initial release.
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
VDD 1 10 LO
NC 2 9 VSS
HB 3 Thermal 8 LI
Pad
HO 4 7 HI
HS 5 6 EN
Not to scale
Pin Functions
PIN
I/O (1) DESCRIPTION
NAME DRC
Enable input. When this pin is pulled high, it will enable the driver. If left floating or
EN 6 I pulled low, it will disable the driver. 1 nF filter capacitor is recommended for high-
noise systems.
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin.
HB 3 P Typical recommended value of HB bypass capacitor is 0.1 μF, This value primarily
depends on the gate charge of the high-side MOSFET. When using external boot
diode, connect cathode of the diode to this pin.
HI 7 I High-side input.
High-side output. Connect to the gate of the high-side power MOSFET or one end of
HO 4 O
external gate resistor, when used.
High-side source connection. Connect to source of high-side power MOSFET.
HS 5 P
Connect negative side of bootstrap capacitor to this pin.
LI 8 I Low-side input
Low-side output. Connect to the gate of the low-side power MOSFET or one end of
LO 10 O
external gate resistor, when used.
NC 2 — Not connected internally.
Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical
VDD 1 P decoupling capacitor value is 1 μF. When using an external boot diode, connect the
anode to this pin.
VSS 9 G Negative supply terminal for the device which is generally the system ground.
Connect to a large thermal mass trace (generally IC ground plane) to improve
Thermal pad —
thermal performance. This can only be electrically connected to VSS.
6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to Vss (1) (2)
MIN MAX UNIT
VDD Supply voltage –0.3 20 V
VEN, VHI, VLI Input voltages on EN, HI and LI –5 20 V
DC –0.3 VDD + 0.3
VLO Output voltage on LO V
Pulses < 100 ns (3) –2 VDD + 0.3
DC VHS – 0.3 VHB + 0.3
VHO Output voltage on HO V
Pulses < 100 ns (3) VHS – 2 VHB + 0.3
DC –10 100
VHS Voltage on HS (3)
V
Pulses < 100 ns –14 100
VHB Voltage on HB –0.3 120 V
VHB-HS Voltage on HB with respect to HS –0.3 20 V
TJ Operating junction temperature –40 150 °C
Lead temperature (soldering, 10 sec.) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization only.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Pins HS, HB and HO are rated at 500V HBM
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) VHB-HS < 16V (Voltage on HB with respect to HS must be less than 16V)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
LI
HI
Voltage (V)
Input
Voltage (V)
(HI, LI)
LO
TDLRR, TDHRR
Output
(HO, LO) HO
TDLFF,
TDHFF
Time (s) Time (s)
TMON TMOFF
0.3 0.22
0.28
VDD Quiescent Current (mA)
0.26 0.18
HB Quiescent Current (mA)
0.24
0.22 0.14
0.2
0.18 0.1
0.16
0.14 5.5V 0.06 5.5V
0.12 12V 12V
16V 16V
0.1 0.02
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) IDDQ
Temperature (°C) IHBQ
VHI = VLI = 0 V VHI = VLI = 0 V
4 3
IDDO (mA)
IHBO (mA)
2.5
3
2
2 1.5
1
1
0.5
0 0
1 2 3 4 5 67 10 20 30 50 70100 200 500 1000 1 2 3 4 5 67 10 20 30 50 70100 200 500 1000
Frequency (kHz) IDDO
Frequency (kHz) IHBO
CL = 0 F VDD =VHB= 12V CL = 0 F VDD =VHB= 12V
12
IHBS (PA)
8
10
6
8
4 6
4
2
2
0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) IDD_ Temperature (°C) IHBS
CL = 0 F VEN = 0 V VHB=VHS=100V
2.205 1.135
2.2 1.13
2.195
1.125
2.19
2.185 1.12
2.18 1.115
2.175 5.5V 5.5V
12V 1.11 12V
2.17
16V 16V
2.165 1.105
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) IN_R
Temperature (°C) IN_F
1.6
55
Enable Delay (Ps)
1.2
50
1.15 45
1.1 40
35
1.05
30
1
25
0.95 20
0.9 15
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Dis_
Temperature (°C) T_EN
2
VDD UVLO (V)
1.95 4.8
1.9
1.85 4.6
1.8
1.75
4.4
1.7
Rise
1.65
Fall
1.6 4.2
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) T_Di Temperature (°C) VDDU
3.6 0.7
0.65
0.6
3.4 0.55
0.5
0.45
3.2 0.4
Rise 0.35
Fall 0.3
3 0.25
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) HBUV
Temperature (°C) Vf
Figure 16. HB UVLO Threshold Figure 17. Boot Diode Forward Voltage Drop
1.8 0.135
1.75 0.13
0.125
Diode Dynamic Resistance (:)
1.7
0.12
1.65
0.115
Output Voltage (V)
1.6 0.11
1.55 0.105
1.5 0.1
1.45 0.095
0.09
1.4
0.085
1.35
0.08
1.3 5.5V
0.075 12V
1.25 0.07 16V
1.2 0.065
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C) V_LO
R_Dy
IO=100mA
Figure 18. Boot Diode Dynamic Resistance Figure 19. LO Low Output Voltage (VLOL)
0.21 0.155
0.2 0.15
0.145
0.19
0.14
0.18 0.135
Output Voltage (V)
Output Voltage (V)
0.17 0.13
0.125
0.16
0.12
0.15 0.115
0.14 0.11
0.13 0.105
0.1
0.12 5.5V 5.5V
12V 0.095 12V
0.11 0.09
16V 16V
0.1 0.085
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) V_LO
Temperature (°C) UCC2
V_HO
IO=-100mA IO=100mA
Figure 20. LO High Output Voltage (VLOH) Figure 21. HO Low Output Voltage (VHOL)
Figure 22. HO High Output Voltage (VHOH) Figure 23. LO Rise Time
10.2 18
5.5V 5.5V
10
12V 12V
9.8 16V 16V
9.6 15
HO Rise Time (ns)
LO Fall Time (ns)
9.4
9.2
12
9
8.8
8.6 9
8.4
8.2
8 6
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) LO_F
Temperature (°C) HO_R
CL=1800pF CL=1800pF
8.4
0.32
Time (Ps)
8.2
0.3
8
0.28
7.8
0.26
7.6 0.24
7.4 0.22 Rise
Fall
7.2 0.2
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) HO_F
Temperature (°C) LO_R
CL=1800pF CL=100nF
Figure 26. HO Fall Time Figure 27. LO Rise & Fall Time
Time (ns)
0.325 17.5
0.3 17
0.275 16.5
0.25 16
0.225 15.5 5.5V
Rise 12V
0.2 15
Fall 16V
0.175 14.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) HO_R Temperature (°C) TDHR
CL=100nF CL=No Load
Figure 28. HO Rise & Fall Time Figure 29. HO Rising Propagation Delay (TDHRR)
20.5 20
20 19.5
19.5
19
19
18.5 18.5
18 18
Time (ns)
Time (ns)
17.5
17.5
17
16.5 17
16 16.5
15.5
5.5V 16 5.5V
15
12V 15.5 12V
14.5 16V 16V
14 15
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) TDHF
Temperature (°C) TDLR
CL= No Load CL= No Load
Figure 30. HO Falling Propagation Delay (TDHFF) Figure 31. LO Rising Propagation Delay (TDLRR)
19
18.5
18
17.5
Time (ns)
17
16.5
16
15.5
5.5V
15 12V
16V
14.5
-40 -20 0 20 40 60 80 100 120 140
Temperature (°C) TDLF
CL= No Load
7 Detailed Description
7.1 Overview
The UCC27282 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel
FETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with
two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long
as signals meet turn-on and turn-off threshold specifications of the UCC27282. The floating high-side driver is
capable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the
UCC27282 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and provides clean level transitions from the control logic to the high-side gate
driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is
provided (in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality,
which shuts off both the outputs when the two inputs overlap.
HB
UVLO
DRIVER HO
LEVEL STAGE
SHIFT
HS
HI
VDD
UVLO
EN
DRIVER
LO
STAGE
Interlock Logic
LI VSS
filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,
they can be connected to outputs of either digital controller or analog controller. Inputs can accept wide slew rate
signals and input can withstand negative voltage to increase the robustness. Small filter at the inputs of the driver
further improves system robustness in noise prone applications. The inputs have internal pull down resistors with
typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.
HI
LI
LO
Interlock
HO
Time
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7V
75 V
VDD EN
HB SECONDARY
SIDE
CIRCUIT
HI DRIVE HO
HI
CONTROL
PWM HS
CONTROLLER
LI DRIVE LO
LO
UCC27282
ISOLATION
AND
FEEDBACK
In this example the allowed voltage drop across bootstrap capacitor is 1.97 V.
It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
DMAX IHB
Q TOTAL = Q G + IHBS × l p+l p
fSW fSW
= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC
where
• QG is the total MOSFET gate charge
• IHBS is the HB to VSS leakage current from datasheet
• DMax is the converter maximum duty cycle
• IHB is the HB quiescent current from the datasheet (2)
The caculated total charge is 53.41 nC.
Next, use Equation 3 to estimate the minimum bootstrap capacitor value.
QTOTAL 53.41 nC
CBOOT :min ; = = = 27.11 nF
¿VHB 1.97 V (3)
The calculated value of minimum bootstrap capacitor is 27.11 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a CVDD capacitor with the following
specifications: 1 µF , 25 V, X7R
CVDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
3. Equation 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG.
R GD _R
PQG = 2 × VDD × Q G × fSW ×
R GD _R + R GATE + R GFET :int ;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
where
• QG is the total MOSFET gate charge
• fSW is the switching frequency
• RGD_R is the average value of pullup and pulldown resistor
• RGATE is the external gate drive resistor
• RGFET(int) is the power MOSFETs internal gate resistor (6)
Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull
down resistance of the driver output section is approximately 4 Ω. Substitute the application values to
calculate the dynamic loss due to gate charge, which is 160 mW here.
4. Equation 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses,
(PLS) during high-side switching.
PLS = VHB × QP × fSW (7)
For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.
kTJ F TA o
PMAX =
REJA
where
• PMAX is the maximum allowed power dissipation in the gate driver device
• TJ is the recommended maximum operating junction temperature
• TA is hte ambient temperature of the gate driver device
• RθJA is the junction-to-ambient thermal resistance (8)
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external
gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to estimate how
these changes affect junction temperature of the gate driver device.
The Thermal Information table summarizes the thermal metrics for the driver package. For detailed information
regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics
application report.
VDD F VDH
IOHH =
R HOH + RGATE + RGFET:int;
where
• IOHH is the high-side, peak pull-up current
• VDH is the bootstrap diode forward voltage drop
• RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO)
• RGATE is the external gate resistance connected between driver output and power MOSFET gate
• RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet (9)
Use Equation 10 to calculate the driver high-side sink current.
VDD F VDH
IOLH =
R HOL + RGATE + RGFET:int;
where
• RHOL is the gate driver internal high-side pull-down resistance (10)
Use Equation 11 to calculate the driver low-side source current.
VDD
IOHL =
R LOH + RGATE + RGFET:int;
where
• RLOH is the gate driver internal low-side pull-up resistance (11)
Use Equation 12 to calculate the driver low-side sink current.
VDD
IOLL =
R LOL + RGATE + RGFET:int;
where
• RLOL is the gate driver internal low-side pull-down resistance (12)
Typical peak pull up and pull down current of the device is 2.5 A and 3.5 A respectively. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 34. Generally selecting an
optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers
These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
Figure 35 shows that the UCC27282 device produces reliable output pulse even when the input pulses are very
narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when the
input pulse width is very narrow.
HI (2V/div)
BW=1GHz
LI (2V/div)
BW=1GHz
HO (5V/div) LO (5V/div)
BW=1GHz BW=1GHz
VDD=6 V CLOAD=2 nF Ch1=HI Ch2=LI Ch3=HO Ch4=LO VDD=6 V CLOAD=2 nF Ch1=HI Ch2=LI Ch3=HO Ch4=LO
Figure 40. Propagation Delay and Delay Matching Figure 41. Propagation Delay and Delay Matching
HI (2V/div)
LI (2V/div)
HO (5V/div)
LO (5V/div)
10 Layout
Input PWMs
Boot Diode & Capacitor
(Bottom Layer)
11.3 Trademarks
E2E is a trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 8-Dec-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
UCC27282DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U27282
& no Sb/Br)
UCC27282DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U27282
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Nov-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Nov-2018
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD
5 6
2X 11 SYMM
2
2.4 0.1
10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
SYMM (2.4)
(3.4)
(0.95)
8X (0.5)
5 6
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP
10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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