Sampada A Deshpande Email:sampadadeshpande1234@gmail.

com
Senior Analog layout Engineer Ph.:7353443959

Current job profile:

• Developing mixed signal CMOS IC layout design at block & module level, including floor
planning and integration, deriving block layout constraints from design requirements.
• Good understanding of the analog layout techniques such as device matching, shielding etc.
Designing an area efficient & parasitic aware block layout.
• Running checkers like DRC, LVS, ERC, Antenna, Lightning ESD on block as well as top level
design and post layout extraction. Finally signing off a physically verified layout
• Having expertise in ESD related blocks. Validating ESD path resistances. Have a good experience
in Calibre -PERC analysis for advanced nodes.
• Have worked on various Foundries like TSMC, UMC, SMIC, Global Foundries, Samsung, in latest
technology nodes including 7nm,10nm, 16nm, 28nm,65nm and 180nm. Having better
understanding of FINFET & Double Patterning.
• Provided guidance and training on Analog layout designing to junior layout designers.
• Having excellent communication skills and ability to work independently.

Summary of qualifications:
• Working as Analog Layout Engineer for Cadence Design Systems from Jan 2015 to till date.
• Internship in Analog Layout in Cadence Design Systems from June 2014 to Dec 2014.

Work experience:
Cadence Design Systems, Inc. July 2018-till date
Design Engineer II
• CDNS internal flow development automations-shell scripting
• Full module ownership in advanced node projects
• ESD simulations, resolving customer issues related to ESD resistance for IPs and Test chip level

Cadence Design Systems, Inc. Jan 2015-June 2018

Design Engineer I
• Delivering quality layout for the blocks/modules handled with a good understanding of design. Quality
assured for the modules with DRC, LVS, BA, EM,IR
• Layout for core custom blocks in 16nm and 28nm projects
• Developed a flow for Point to Point ESD resistance analysis using Cadence internal tool.
• Mentor PERC analysis at Test chip level for advanced nodes
• Work with cross functional teams to enable timely, smooth and qualified delivery
Sampada A Deshpande Email:sampadadeshpande1234@gmail.com
Senior Analog layout Engineer Ph.:7353443959

Cadence Design Systems, Inc. June 2014-Dec 2014

Intern Design Engineering
• 7 months training in Analog layout design.
• Full custom layout design for Band gap reference circuit in 28nm with post layout simulations
• 28nm TSMC IP ported to SMIC with all PVS verifications.

Additional Responsibilities:
• Mentoring interns for Analog Layout Internship program at Cadence Design Systems, Inc.
• Active member of Cadence recruitment panel

Technical Skill Set:

Tools Cadence Virtuoso layout and schematic Editor, Cadence Lightning, PVS
verification tool, ADEXL

Academic Background:
• Masters in Microelectronics March 2017-Feb 2019
Birla Institute of Technology and Science, Pilani, Rajasthan
CGPA: 9.2
• Bachelor of Engineering, Electronics and communication June 2011-June 2014
B V B college of Engineering and Technology, Hubli, Karnataka
CGPA: 9.3
• Diploma in Electronics and communication June 2008- May 2011
K.H. Kabbur Institute of Engineering, Dharwad, Karnataka
CGPA: 8.7
Accomplishments:
• Secured 22nd rank in Karnataka state level CET entrance exam
• Received IDrive award at Cadence for Custom PCELL development in 28nm
• Poster presentation at TECCI conference India on Point to point resistance calculation
• Participated in 2nd and 3rd India ESD workshop from IEEE in IISC Bengaluru
• Best Outgoing student award in graduation
• State level throw ball player
• Actively participated in various cultural and sports activities at Cadence
Personal Details:
Name Sampada A Deshpande
DOB: 7th April 1992
Languages known Kannada, English, and Hindi
I hereby declare that the above information is true as per best of my knowledge.
Date: 03/04/2019
Place:Bangalore Sampada A Deshpande