1 With neat sketches, explain the transfer characteristic of a CMOS inverter.

2 Design an inverter using (i) NMOS; (ii) CMOS

Compare and explain the characteristics of above designs.
3 Describe with neat diagram P well fabrication process.

4 Describe with neat diagram n well fabrication process.

5 Describe with neat diagram twin tub fabrication process.

6 Explain DC transfer characteristics of CMOS inverter and mark all the regions
of operations with necessary expression of Vout in each region.

7 Explain Transmission Gate inverter operation with neat diagram.

8 Define sheet resistance and standard unit of capacitance Cg?

9 Find the sheet resistance of CMOS inverter and NMoS inverter .

10 Describe in detail step by step procedure involved in the fabrication of n Mos.

11 With the truth table draw the schematic of 2:1 mux and XOR gate using
transmission gate.
12 Discuss the origin of latch up problems in CMOS circuits with necessary
diagrams. Explain the remedial measures.

13 Explain the importance of static timing analysis in the VLSI Design? What
do you mean by pre layout and post layout static timing analysis?

14 Design 4:1 mux using transmission gates.

15 Explain advantages and disadvantages of stick diagram? Draw the stick

diagram for y=AB+E+CD.

16 List out Lambda based design rules.

17 Explain the effect of scaling on gate capacitance and transistor delay and power
dissipation.

18 What are the types of scaling? Draw MOSFET scaling model. When the device
dimensions are scaled down how does the depletion regions around the source
and drain affected.

19 Write a short note on Drain Induced Barrier Lowering.

20 What is the difference between positive and negative mask in photolithography.

21 Explain the process of Photolithography in detail.

22 What do you understand by positive and negative mask?

23 Explain with expression the channel length modulation in MoSFET.

24 What is the latch up problem that arises in bulk CMOS technology? How the
latch up problem can be overcome?

25 What is transconductance, figure of merit of a MOS transistor?

26 Justify the reason for not recommending more than 4 pass transistors to
use in series in realizing logic circuits.

27 Give the schematic diagram of a Bi-CMOS inverter. Explain its operation.

. Compare the switching characteristics of a BiCMOS inverter with respect
to that for static CMOS for different fan out conditions.
Ans 24 : The latch-up is an inherent problem in both n-well as well as pwell based CMOS
circuits. The phenomenon is caused by the parasitic bipolar transistors formed in the bulk of
silicon as shown in the figure for the n-well process. Latch-up can be defined as the formation of
a low-impedance path between the power supply and ground rails through the parasitic npn and
pnp bipolar transistors. As shown the BJTs are cross-coupled to form the structure of a silicon-
controlled-rectifier (SCR) providing a short-circuit path between the power rail and ground.
Leakage current through the parasitic resistors can cause one transistor to turn on, which in turn
turns on the other transistor due to positive feedback and leading to heavy current flow and
consequent device failure.

There are several approaches to reduce the tendency of Latch-up. Some of the important
techniques are mentioned below:
1. Use guard ring around p- and/or n-well with frequent contacts to the rings
2. To reduce the gain product B1XB2
3. Moving the n-well and the n+ source/drain further apart
4. Buried n+ layer in well to reduce gain of Q1
5. Higher substrate doping level to reduce R-sub
6. Reduce R-well by making low resistance contact to GND

Ans: Photolithography: The purpose of this is to open windows whenever diffusion is to be done and
retaining Sio2 remaining areas. During manufacturing, this step (photographic printing) process is used
to transfer the layout patterns from the masks to the Wafer. The pattern left by the mask are used to
selectively change the wafer: Impurities are added at selected locations in the wafer, done by diffusion
and insulating materials by Oxidation (Sio2 ), the conducting materials are added at the top of the wafer
as well ( Metallization).