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A B C D E

Compal Confidential
Model Name : V5WE2/T2/C2 (EA/EG/BA50_HW)
File Name : LA-9531P
1 1

Compal Confidential
2 2

EA50_HW M/B Schematics Document


Intel Shark Bay ULT (Hasswell + Lynx Point-LP)

AMD MARS / SUN

3 2013-04-11 3

REV:1.0

4 4

ZZZ
Part Number Description

DAZ0VR00100 PCB V5WE2 LA-9531P LS-9531P/9532P


V5WE2_PCB
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 11, 2013 Sheet 1 of 52
A B C D E
A B C D E

CRT Conn.
Fan Control
page 28 page 36

DP to VGA HDMI Conn. eDP Conn.


1 1
ITE IT6511FN page 26 page 25
204pin DDR3L-SO-DIMM X1
page 27
eDP
Intel Haswell ULT BANK 0, 1, 2, 3 page 15
DP x 2 lanes HDMI x 4 lanes Memory BUS
2.7GT/s 2.97GT/s Dual Channel
DDI
Haswell ULT
Processor 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16

MINI Card AMD SUN/MARS OPI


WLAN with DDR3 x4 or 8
USB port 4 page 31 page 17~23

PCIe 2.0 PCIe 2.0 x4 USB 3.0 USB 2.0 CMOS Finger
5GT/s 5GT/s conn x1 conn x2 Camera Print
2

port 4 port 5
Lynx Point - LP USB port 0 USB/B (port 1,2) USB port 7 USB (port 5)
2

Flexible IO
page 33 page 33 page 25 page 26
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 2 HD Audio 3.3V 24MHz
Touch
LAN(GbE) SATA HDD SATA CDROM Screen
Boardcom USB (port 6)
Conn. Conn. 1168pin BGA HDA Codec
57786Xpage ALC3225 page 25
29 page 32 page 32
page 04~14 page 36
SPI

3
Card Reader LPC BUS 3
2 in 1 SPI ROM x2
(SD) CLK=24MHz Int. Speaker Int. MIC Combo Jack
page 30 page 7
ENE page 36 page 36 page 36

KB9012
page 34

RTC CKT. Sub Board


page 6
Touch Pad Int.KBD
LS-9531P page 35 page 35

Power On/Off CKT. PWR/B


page 33
page 35

LS-9532P EC ROM x1
4
DC/DC Interface CKT. USB/B (port 1,2) (reserved) 4

page 34
page 38 page 33

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 39~49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 2 of 52
A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VS_VTT +1.05V power rail for CPU ON OFF OFF Vcc 3.3V +/- 5%
+0.95VSDGPU +0.95VSDGPU switched power rail for GPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.35V +1.35V power rail for DDR3L ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V power rail for CPU ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.8VSDGPU +1.8VSDGPU power rail for GPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW +3VALW always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VSDGPU +3VS to +3VSDGPU power rail for GPU ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VS +3VALW to +5VS power rail ON OFF OFF
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
2
BTO Item BOM Structure 2

Board ID PCB Revision Unpop @


0 0.1 Connector CONN@
1 0.2 EC 932 940@
2 0.3 EC 9012 9012@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 0.4 UMA Component UMA@
4 0.5 AMD GPU VGA@
EC SM Bus1 address EC SM Bus2 address 5 1.0 1 SPI ROM 1ROM@
Device Address Device Address
6 2 SPI ROM 2ROM@
Smart Battery 0001 011X On Board Thermal Senser 0100 110x
7 Assembly Level 45@
VGA Internal Thermal Senser 0100 000x
Cable for Power 45PWR@
USB Port Table KB Backlight BL@
G Senser 0011 000x
3 External Debug Only DEG@
PCH SM Bus address USB 2.0 Port
USB Port EMC Component EMC@
Device Address
0 USB Port(Left 3.0) Reservec for EMC XEMC@
ChannelA DIMM0 1001 000x JDIMM1
1 USB Port(Right 2.0) eDP to LVDS TL@
3
ChannelB DIMM1 1001 010x JDIMM2
2 USB Port(Right 2.0) TPM Module TPM@ 3

3 G-Sensor GSEN@
EHCI1
4 Mini Card (WLAN+BT) V5WE2/T2/C2 EA50@
5 Reserved BA51@
6 Touch Screen TS@
7 Camera For IOAC IOAC@
For EDP panel EDP@

Mars component MARS@


SUN component SUN@
VRAM x 8pcs 128@

USB 3.0 Port VRAM Selection X76@


0 USB Port(Left 3.0) Micron 4G x 8 X7601@
1 Hynix 2G x 4 X7603@
XHCI
4
2 Hynix 2G x 8 X7604@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 11, 2013 Sheet 3 of 52
A B C D E
5 4 3 2 1

HASWELL_MCP_E
U1A

C54 C45
27 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 25
C55 B46
27 CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 25
B58 A47
27 CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 25
DP to CRT 27 CPU_DP1_P1
C58
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1
B47
EDP_TXP1 25
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
26 CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN 25
26 CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP 25
26 CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
HDMI 26
26
CPU_DP2_P1
CPU_DP2_N2
B54
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
26 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
26 CPU_DP2_N3 DDI2_TXN3
B53
26 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 25

1 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

Reserved for ESD


HASWELL_MCP_E
U1B

C94 1 2 6.8P_0402_50V8C
XEMC@ T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R @ T157
+1.35V 34 H_PECI PECI PRDY K62 XDP_PREQ#_R @ T158
2 1 R68 R8 JTAG
PREQ E60 XDP_TCK_R @ T159
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS_R @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R @ T161
34,39,40 H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_R @ T162
PROC_TDI
1

C C95 1 2 6.8P_0402_50V8C F62 XDP_TDO_R @ T163 C


PROC_TDO
R184 Reserved for ESD XEMC@
470_0603_5% R6 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
C60 1 2 6.8P_0402_50V8C J60 XDP_BPM#0_R @ T164
2

XEMC@ BPM#0 H60 XDP_BPM#1_R @ T165


DIMM_DRAMRST# 15,16 BPM#1
Reserved for ESD BPM#2
H61 @ T148
2 H62 @ T149
R11 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 @ T150
SM_RCOMP0 BPM#4
C96 Close to AV15 R13 1 2 120_0402_1% SM_RCOMP1 AV60
SM_RCOMP1
DDR3
BPM#5
H63 @ T151
6.8P_0402_50V8C R41 1 2 100_0402_1% SM_RCOMP2 AU61 K60 @ T152
1 DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 @ T153
XEMC@ SM_DRAMRST BPM#7
DDR_PG_CTRL AV61
15 DDR_PG_CTRL SM_PG_CNTL1
DDR3 Compensation Signals
Reserved for ESD 1120 2 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

B B

U1 U1

CPU_SR16Q_C1 CPU_SR170_C1
SR16Q@ SR170@
A SA00006SX70 SA00006SMB0 A

U1 U1 U1 U1

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
CPU_QEK2_C0 CPU_QEK4_C0 CPU_QEVG_C0 CPU_QEVE_C0
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
QEK2@ QEK4@ QEVG@ QEVE@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA00006SJ40 SA00006NM50 SA00006SX30 SA00006SM30 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 08, 2013 Sheet 4 of 52
5 4 3 2 1
5 4 3 2 1

U1C HASWELL_MCP_E
U1D HASWELL_MCP_E

DDR_A_D0 AH63 AU37


SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 15
DDR_A_D1 AH62 AV37
SA_DQ1 SA_CLK0 SA_CLK_DDR0 15
DDR_A_D2 AK63 AW36 DDR_B_D0 AY31 AM38
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 15 SB_DQ0 SB_CK#0 SB_CLK_DDR#0 16
DDR_A_D3 AK62 AY36 DDR_B_D1 AW31 AN38
SA_DQ3 SA_CLK1 SA_CLK_DDR1 15 SB_DQ1 SB_CK0 SB_CLK_DDR0 16
DDR_A_D4 AH61 DDR_B_D2 AY29 AK38
SA_DQ4 SB_DQ2 SB_CK#1 SB_CLK_DDR#1 16
DDR_A_D5 AH60 AU43 DDR_B_D3 AW29 AL38
SA_DQ5 SA_CKE0 DDRA_CKE0_DIMMA 15 SB_DQ3 SB_CK1 SB_CLK_DDR1 16
DDR_A_D6 AK61 AW43 DDR_B_D4 AV31
SA_DQ6 SA_CKE1 DDRA_CKE1_DIMMA 15 SB_DQ4
DDR_A_D7 AK60 AY42 DDR_B_D5 AU31 AY49
SA_DQ7 SA_CKE2 SB_DQ5 SB_CKE0 DDRB_CKE0_DIMMB 16
DDR_A_D8 AM63 AY43 DDR_B_D6 AV29 AU50
SA_DQ8 SA_CKE3 SB_DQ6 SB_CKE1 DDRB_CKE1_DIMMB 16
D DDR_A_D9 AM62 DDR_B_D7 AU29 AW49 D
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
SA_DQ10 SA_CS#0 DDRA_CS0_DIMMA# 15 SB_DQ8 SB_CKE3
DDR_A_D11 AP62 AR32 DDR_B_D9 AW27
SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# 15 SB_DQ9
DDR_A_D12 AM61 DDR_B_D10 AY25 AM32
SA_DQ12 SB_DQ10 SB_CS#0 DDRB_CS0_DIMMB# 16
DDR_A_D13 AM60 AP32 DDRA_ODT0 @ T4 DDR_B_D11 AW25 AK32
SA_DQ13 SA_ODT0 SB_DQ11 SB_CS#1 DDRB_CS1_DIMMB# 16
DDR_A_D14 AP61 DDR_B_D12 AV27
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D13 AU27 SB_DQ12 AL32 DDRB_ODT0 @ T5
SA_DQ15 SA_RAS DDR_A_RAS# 15 SB_DQ13 SB_ODT0
DDR_A_D16 AP58 AW34 DDR_B_D14 AV25
SA_DQ16 SA_WE DDR_A_WE# 15 SB_DQ14
DDR_A_D17 AR58 AU34 DDR_B_D15 AU25 AM35
SA_DQ17 SA_CAS DDR_A_CAS# 15 SB_DQ15 SB_RAS DDR_B_RAS# 16
DDR_A_D18 AM57 DDR_B_D16 AM29 AK35
SA_DQ18 SB_DQ16 SB_WE DDR_B_WE# 16
DDR_A_D19 AK57 AU35 DDR_B_D17 AK29 AM33
SA_DQ19 SA_BA0 DDR_A_BS0 15 SB_DQ17 SB_CAS DDR_B_CAS# 16
DDR_A_D20 AL58 AV35 DDR_B_D18 AL28
SA_DQ20 SA_BA1 DDR_A_BS1 15 SB_DQ18
DDR_A_D21 AK58 AY41 DDR_B_D19 AK28 AL35
SA_DQ21 SA_BA2 DDR_A_BS2 15 SB_DQ19 SB_BA0 DDR_B_BS0 16
DDR_A_D22 AR57 DDR_B_D20 AR29 AM36
SA_DQ22 SB_DQ20 SB_BA1 DDR_B_BS1 16
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D21 AN29 AU49
SA_DQ23 SA_MA0 SB_DQ21 SB_BA2 DDR_B_BS2 16
DDR_A_D24 AP55 AY37 DDR_A_MA1 DDR_B_D22 AR28
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D23 AP28 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39DDR_A_MA7 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46DDR_B_MA6
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41DDR_A_MA11 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
C DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13 C
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D40 AY54 SA_DQ39 AJ61 DDR_A_DQS#0 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D41 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D39 AU21 SB_DQ38 SB_MA15
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D40 AY19 SB_DQ39 AW30DDR_B_DQS#0
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
SA_DQ43 SA_DQSN3 15 DDR_A_D[0..63] SB_DQ41 SB_DQSN1
DDR_A_D44 AV54 AV57 DDR_A_DQS#4 DDR_B_D42 AY17 AN28 DDR_B_DQS#2
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
SA_DQ45 SA_DQSN5 15 DDR_A_MA[0..15] SB_DQ43 SB_DQSN3
DDR_A_D46 AV52 AL43 DDR_A_DQS#6 DDR_B_D44 AV19 AW22DDR_B_DQS#4
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
SA_DQ47 SA_DQSN7 15 DDR_A_DQS#[0..7] SB_DQ45 SB_DQSN5
DDR_A_D48 AK40 DDR_B_D46 AV17 AN21 DDR_B_DQS#6
DDR_A_D49 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
SA_DQ49 SA_DQSP0 15 DDR_A_DQS[0..7] SB_DQ47 SB_DQSN7
DDR_A_D50 AM43 AN61 DDR_A_DQS1 DDR_B_D48 AR21
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_B_DQS0
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26DDR_B_DQS1
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57DDR_A_DQS4 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53DDR_A_DQS5 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18DDR_B_DQS5
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
SA_DQ58 SM_VREF_CA SM_DIMM_VREFCA 15 SB_DQ56 SB_DQSP7
DDR_A_D59 AK49 AR51 DDR_B_D57 AR20
SA_DQ59 SM_VREF_DQ0 SA_DIMM_VREFDQ 15 SB_DQ57
DDR_A_D60 AM48 AP51 DDR_B_D58 AK18
SA_DQ60 SM_VREF_DQ1 SB_DIMM_VREFDQ 16 SB_DQ58
DDR_A_D61 AK48 DDR_B_D59 AL18
DDR_A_D62 AM51 SA_DQ61 DDR_B_D60 AK20 SB_DQ59
SA_DQ62 SB_DQ60 16 DDR_B_D[0..63]
DDR_A_D63 AK51 DDR_B_D61 AM20
SA_DQ63 DDR_B_D62 AR18 SB_DQ61
SB_DQ62 16 DDR_B_MA[0..15]
DDR_B_D63 AP18
SB_DQ63
B 16 DDR_B_DQS#[0..7] B

16 DDR_B_DQS[0..7]

3 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 4 OF 19 Rev1p2
@ HASWELL-MCP-E-ULT_BGA1168
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(2/11) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 5 of 52
5 4 3 2 1
5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2 U1E HASWELL_MCP_E


R101 10M_0402_5% +RTCVCC
1
C149
Y1 +RTCVCC 1U_0402_10V6K ME CMOS PCH_RTCX1 AW5
32.768KHZ_12.5PF_Q13FC135000040 PCH_RTCX2 AY5 RTCX1
2 1 R69 2 R72 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
INTRUDER RTC SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 32
20K_0402_1% PCH_INTVRMEN AV7 H5 SATA_PRX_DTX_P0 32
INTVRMEN SATA_RP0/PERP6_L3
1 2 PCH_SRTCRST# AV6
SRTCRST SATA_TN0/PETN6_L3
B15
SATA_PTX_DRX_N0 32 HDD
1 2 PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 32
1 1 R70

1
D 20K_0402_1% 1 J8 SATA_PRX_DTX_N1 32 D
C153 C154 C150 R71 SATA_RN1/PERN6_L2 H8
15P_0402_50V8J 15P_0402_50V8J 1U_0402_10V6K @ 0_0603_5% SATA_RP1/PERP6_L2 A17
SATA_PRX_DTX_P1 32 ODD
2 2 SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 32
B17
2 CMOS SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 32

2
HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
HDA_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
36 HDA_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
T6 @ AU12
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
+RTCVCC RTCRST close RAM door T7 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
T8 @ AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 R937
T9 @ AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 0_0402_5%
PCH_INTVRMEN R73 1 2 330K_0402_5% I2S1_SCLK SATA_TP3/PETP6_L0 1 @ 2 EC_SCI# 34,9
R74 1 @ 2 330K_0402_5%
V1 PCH_GPIO34 PCH_GPIO34 9
SATA0GP/GPIO34
INTVRMEN U1 PCH_GPIO35
* H:Integrated VRM enable
L:Integrated VRM disable
SATA1GP/GPIO35
SATA2GP/GPIO36
V6
AC1
PCH_GPIO36
PCH_GPIO37
PCH_GPIO35 9
PCH_GPIO36 9
+1.05VS_ASATA3PLL

SATA3GP/GPIO37 PCH_GPIO37 9
T95 @
PCH_JTAG_RST# AU62
51_0402_5% 1 @ 2 R97 PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF R75 1 @ 2 0_0603_5%
T21 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 @ T13
T19 @ PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 @ T14
PCH_TDO RSVD within 500 mils
T15 @ PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
T10 @ AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED#
RSVD SATALED PCH_SATALED# 35
T11 @ AC4
T22 @ PCH_TCK_JTAGX AE63 RSVD R10 1 2
HDA for AUDIO T12 @ AV2 JTAGX 10K_0402_5%
+3VS
C RP14 EMC@ RSVD C

36 HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK
36 HDA_SYNC_AUDIO 2 7 HDA_SYNC
36 HDA_RST_AUDIO# 3 6 HDA_RST#
36 HDA_SDOUT_AUDIO 4 5 HDA_SDOUT 5 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
33_0804_8P4R_5% @

34 HDA_SDO R163 1 9012@ 2 0_0402_5%

32,34,7 SPI_WP1#_R R161 1 940@ 2 4.7K_0402_5%

ME Debug

W=20mils trace width 10mil W=20mils


+RTCBATT +CHGRTC +RTCVCC
B B
D23
2

BAS40-04_SOT23-3 1
C151
0.1U_0402_16V4Z
2

+RTCBATT
+RTCBATT
2

+CHGRTC
R446
+

1K_0402_5%
@
3 1

+RTCBATT_R
2

A 20mil A
20mil
+RTCVCC

D32
1

CHN202UPT_SC70-3 JBATT1
-

1 @ LOTES_AAA-BAT-054-K01 Security Classification Compal Secret Data Compal Electronics, Inc.


2

C168 CONN@ 2012/07/10 2013/07/10 Title


0.1U_0402_16V4Z SP07000H700
Issued Date Deciphered Date HSW MCP(3/11) RTC,SATA,XDP
@
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 18, 2013 Sheet 6 of 52
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E
U1F

XTAL24_IN C43 A25 XTAL24_IN


C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
2 1 XTAL24_OUT PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT
9 PCH_GPIO18 PCIECLKRQ0/GPIO18
1M_0402_5% R48 K21 @ T16
B41 RSVD M21 @ T17
Y2 A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF R78 1 2 3.01K_0402_1%
D +1.05VS_AXCK_LCPLL D
24MHZ_12PF_X3G024000DC1H PCH_GPIO19 Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
9 PCH_GPIO19 PCIECLKRQ1/GPIO19
1 3 C35 R140 1 2 10K_0402_5%
2 4 CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 R141 1 2 10K_0402_5%
29 CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
PCIE LAN 29 CLK_PCIE_LAN
CLK_PCIE_LAN B42
CLKOUT_PCIE_P2 TESTLOW_AK8
AK8 R142 1 2 10K_0402_5%
1

1
R52 1 2 10K_0402_5% AD1 SIGNALS AL8 R148 1 2 10K_0402_5%
+3VS PCIECLKRQ2/GPIO20 TESTLOW_AL8
C2 C3 29 LAN_CLKREQ#
10P_0402_50V8J 10P_0402_50V8J CLK_PCIE_MINI1# B38 AN15 CLKOUT_LPC0 R390 2 EMC@ 1 22_0402_5%
31 CLK_PCIE_MINI1# CLK_PCI_LPC 34
2

CLK_PCIE_MINI1 C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLKOUT_LPC1 R395 2 TPM@ 1 22_0402_5%


31 CLK_PCIE_MINI1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM 35
WLAN 31,8 MINI1_CLKREQ# MINI1_CLKREQ# N1
PCIECLKRQ3/GPIO21 B35 CLK_BCLK_ITP# @ T184
CLK_PEG_VGA# A39 CLKOUT_ITPXDP_N A35 CLK_BCLK_ITP @ T183
17 CLK_PEG_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
CLK_PEG_VGA B39
17 CLK_PEG_VGA CLKOUT_PCIE_P4
VGA_CLKREQ# U5
+3VS PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
1

PCH_GPIO23 T2
9 PCH_GPIO23 PCIECLKRQ5/GPIO23
R216
10K_0402_5%
@ 6 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
2

VGA_CLKREQ# @
1

U1G HASWELL_MCP_E
R221
10K_0402_5% LPC_AD0 AU14 AN2 PCH_GPIO11
34,35 LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 9
LPC_AD1 AW12 AP2 PCH_SMBCLK
34,35 LPC_AD1 LAD1 LPC SMBCLK PCH_SMBCLK 31
LPC_AD2 AY12 AH1 PCH_SMBDATA
34,35 LPC_AD2 PCH_SMBDATA 31
2

C LPC_AD3 AW11 LAD2 SMBDATA AL2 PCH_GPIO60 C


34,35 LPC_AD3 LAD3 SMBUS SML0ALERT/GPIO60 PCH_GPIO60 9
LPC_FRAME# AV12 AN1 SML0CLK
34,35 LPC_FRAME# LFRAME SML0CLK AK1 SML0DATA
SML0DATA AU4 PCH_GPIO73
SML1ALERT/PCHHOT/GPIO73 PCH_GPIO73 9
AU3 SML1CLK
SML1CLK/GPIO75 AH3 SML1DATA +3VALW_PCH
PCH_SPI_CLK AA3 SML1DATA/GPIO74
PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T23
PCH_SPI_CS1# Y4 SPI_CS0 CL_CLK AD2 @ T24 SML0CLK RP8 1 8 2.2K_0804_8P4R_5%
AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T25 SML0DATA 2 7
PCH_SPI_MOSI AA2 SPI_CS2 CL_RST PCH_SMBDATA 3 6
PCH_SPI_MISO AA4 SPI_MOSI PCH_SMBCLK 4 5
PCH_SPI_WP1# Y6 SPI_MISO
PCH_SPI_HOLD1# AF1 SPI_IO2 SML1CLK R114 1 2 2.2K_0402_5%
R572 1 DEG@ 2 0_0402_5% PCH_SPI_CLK_1 SPI_IO3 SML1DATA R113 1 2 2.2K_0402_5%
32 PCH_SPI_CLK_1_R
32 PCH_SPI_CS0#_1_R R599 1 DEG@ 2 0_0402_5% PCH_SPI_CS0#
32 PCH_SPI_MOSI_1_R R603 1 DEG@ 2 0_0402_5% PCH_SPI_MOSI_1
32 PCH_SPI_MISO_1_R R602 1 DEG@ 2 0_0402_5% PCH_SPI_MISO_1
32 SPI_HOLD1#_R R604 1 DEG@ 2 0_0402_5% PCH_SPI_HOLD1# 7 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
D29 design for Debug
+3VS
+BIOS_SPI
board flash SPI ROM +3VS
(can be short after MP)
+3VS

2
R305 1 9012@ 2 0_0402_5%
R116 R119

SPI ROM ( 8MByte )


D29 1 2 940@ RB751V40_SC76-2 Q7A 4.7K_0402_5% 4.7K_0402_5%

2
B DMN66D0LDW-7_SOT363-6 B
C66 1 2 0.1U_0402_16V7K

1
U6 PCH_SMBDATA 6 1 D_CK_SDATA D_CK_SDATA 15,16,37
R108 PCH_SPI_CS0# 1 8 RP19
CS# VCC

5
15_0402_5% PCH_SPI_MISO_1 2 7 PCH_SPI_IO3_1 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI
PCH_SPI_WP1# 2 1ROM@ 1 PCH_SPI_IO2_1 3 DO(IO1) HOLD#(IO3) 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 2 7 PCH_SPI_CLK
4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 PCH_SPI_IO3_1 3 6 PCH_SPI_HOLD1# PCH_SMBCLK 3 4 D_CK_SCLK
GND DI(IO0) D_CK_SCLK 15,16,37
PCH_SPI_MISO_1 4 5 PCH_SPI_MISO
+BIOS_SPI EN25QH64-104HIP_SO8 1ROM@ Q7B
1ROM@ 15_0804_8P4R_5% DMN66D0LDW-7_SOT363-6
R105 1 1ROM@ 2 1K_0402_5% PCH_SPI_IO2_1 Reserve for EMI(Near SPI ROM)
R106 1 1ROM@ 2 1K_0402_5% PCH_SPI_IO3_1 C152
10P_0402_50V8J
R103 1 2ROM@ 2 1K_0402_5% PCH_SPI_HOLD1# 1 2 2 1 PCH_SPI_CLK_1 +3VS
R102 1 2ROM@ 2 1K_0402_5% PCH_SPI_WP1# R104 XEMC@ 33_0402_5%
32,34,6 SPI_WP1#_R R564 1 940@ 2 1K_0402_5% XEMC@
Q8A

2
SPI ROM ( 4MByte )
+3VS DMN66D0LDW-7_SOT363-6
PU 2.2K at EC side (+3VS)
C67 1 2 0.1U_0402_16V7K SML1CLK 6 1 EC_SMB_CK2 18,24,34
U7 2ROM@

5
PCH_SPI_CS1# 1 8 RP20
PCH_SPI_MISO_2 2 CS# VCC 7 PCH_SPI_IO3_2 PCH_SPI_MOSI_2 1 8 PCH_SPI_MOSI
PCH_SPI_WP1# 33_0402_5% 2 2ROM@ 1 R109 PCH_SPI_IO2_2 3 DO HOLD# 6 PCH_SPI_CLK_2 PCH_SPI_CLK_2 2 7 PCH_SPI_CLK SML1DATA 3 4
WP# CLK EC_SMB_DA2 18,24,34
4 5 PCH_SPI_MOSI_2 PCH_SPI_IO3_2 3 6 PCH_SPI_HOLD1#
GND DI PCH_SPI_MISO_2 4 5 PCH_SPI_MISO Q8B
EN25QH32-104HIP_SO8 33_0804_8P4R_5% DMN66D0LDW-7_SOT363-6
2ROM@ 2ROM@
A
SPI ROM ( 8MByte for Chrome) C453
Reserve for EMI(Near SPI ROM)
10P_0402_50V8J
A

U6 2ROM is SPI ROM 2M + 4M Byte 1 2 2 1 PCH_SPI_CLK_2


R402 XEMC@ 33_0402_5%
RP19 U6 XEMC@
R108
33_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2ROM@ 2012/07/10 2013/07/10 Title
MX25L6406EM2I-12G_SO8 2 1
Issued Date Deciphered Date HSW MCP(4/11) CLK,SPI,SMBUS
940@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA00004G600 33_0804_8P4R_5% EN25QH16-104HIP_SO8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2ROM@ 2ROM@ Custom 1.0
SD309330A80 SA00004UG00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 7 of 52
5 4 3 2 1
5 4 3 2 1

+3VS

1
R227
10K_0402_5% DSWODVREN - On Die DSW VR Enable
* L:Disable
H:Enable(DEFAULT)

2
R59 1 DEG@ 2 0_0402_5% SYS_RESET# +RTCVCC
32 XDP_DBRESET#
HASWELL_MCP_E
U1H
D R124 1 2 330K_0402_5% D
R125 1 @ 2 330K_0402_5%
R206 SYSTEM POWER MANAGEMENT
SUSWARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#_R
SYS_PWROK R61 1 @ 2 0_0402_5% SYS_PWROK_R AG2 SYS_RESET DPWROK AJ5 PCH_PCIE_WAKE#
SYS_PWROK WAKE PCH_PCIE_WAKE# 29
34 PCH_PWROK R62 1 2 0_0402_5% PCH_PWROK_R AY7 1K_0402_5% 1 2 R120 +3VALW_PCH
R63 1 @ 2 0_0402_5% PM_APWROK AB5 PCH_PWROK 8.2K_0402_5% 1 2 R157
11,34 VCCST_PG_EC APWROK +3VS
AG7 V5 CLKRUN# CLKRUN# 35
PCH_PWROK_R 2 1 R64 0_0402_5% PLTRST CLKRUN/GPIO32 AG4 LPCPD#
SUS_STAT/GPIO61 LPCPD# 35
PLT_RST# AE6 SUSCLK
34,35 PLT_RST# SUSCLK/GPIO62 SUSCLK 34
AP5 PM_SLP_S5#
SLP_S5/GPIO63 PM_SLP_S5# 34
34 PCH_RSMRST# R79 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6 @ T27
PCH_RSMRST# R117 1 2 10K_0402_5% SUSWARN# AV4 RSMRST @ T28 @ T29
9 SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
34 PBTN_OUT# R110 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#
PWRBTN SLP_S4 PM_SLP_S4# 34
Note: EC is +3VL change to @ PCH_ACIN AJ8
ACPRESENT/GPIO31 SLP_S3
AT4 PM_SLP_S3#
PM_SLP_S3# 34
+3VALW_PCH R156 1 2 8.2K_0402_5% PCH_BATLOW# AN4 AL5 @ T30
T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
SLP_WLAN/GPIO29 SLP_LAN +3VALW_PCH
10K_0402_5%
+3VALW_PCH

not support Deep S4,S5 can NC


1

8 OF 19 Rev1p2
R245 Note: Deep Sx need use EC GPIO for HASWELL-MCP-E-ULT_BGA1168
100K_0402_5% ACPRESENT function @
@ DDPB_CTRLDATA: Port B Detected
@ D21
2

34,39,41 ACIN 1 2 PCH_ACIN DDPC_CTRLDATA: Port C Detected


C C
RB751V40_SC76-2
1: Port B or C is detected
+3VS * 0: Port B or C is not detected
(Have internal PD)
5

R65
2 HASWELL_MCP_E
PCH_PWROK 0_0402_5% U1I
P

B 4 SYS_PWROK 1 2 PCH_PWROK
VGATE_3V 1 Y +3VS
A
G
1

U43
3

R208 MC74VHC1G08DFT2G_SC70-5 R207 B8 B9


24,25 PCH_INV_PWM EDP_BKLCTL DDPB_CTRLCLK
10K_0402_5% @ 10K_0402_5% A9 C9 R271 1 2 2.2K_0402_5%
34 ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA
@ C6 D9 DDI2_CTRL_CK
25 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK DDI2_CTRL_CK 26
D11 DDI2_CTRL_DATA
DDI2_CTRL_DATA 26
2

DDPC_CTRLDATA

EC_SMI# U6
34 EC_SMI# PIRQA/GPIO77
VGA_ON P4 C5 DDI1_AUX_DN
+3VS 38,9 VGA_ON PIRQB/GPIO78 DISPLAY DDPB_AUXN DDI1_AUX_DN 27
DGPU_HOLD_RST# N4 B6
9 DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN
PCH_GPIO80 N2 B5 DDI1_AUX_DP
PIRQD/GPIO80 DDPB_AUXP DDI1_AUX_DP 27
+1.05VS_VTT T26 @ AD4 A6
PME DDPC_AUXP
1

GPIO
U17 R310 PCH_GPIO55 U7
9 PCH_GPIO55 GPIO55
1 5 10K_0402_5% 37 G_SEN_INT G_SEN_INT L1
NC VCC @ Project_ID1 L3 GPIO52 C8
GPIO54 DDPB_HPD CPU_DP_HPD 27
11,46 VGATE 2 PCH_GPIO51 R5 A8 CPU_HDMI_HPD 26
9 PCH_GPIO51
2

B A 4 VGATE_3V Project_ID0 L4 GPIO51 DDPC_HPD D6 B


Y VGATE_3V 34 GPIO53 EDP_HPD CPU_EDP_HPD 25
3
GND
74AUP1G07GW_TSSOP5
@
9 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
+3VS R405
0_0402_5% R403
2 @ 1 0_0402_5%
RP27 1 8 G_SEN_INT 2 @ 1
2 7 PCH_GPIO80 +3VS
3 6 MINI1_CLKREQ# MINI1_CLKREQ# 31,7
4 5 DEVSLP0 +3VS
DEVSLP0 32,9
10K_0804_8P4R_5%
5

5
VCC

PLT_RST# 1

VCC
IN1 4 PLT_RST# 1
OUT PLTRST_VGA# 17 IN1
DGPU_HOLD_RST# 2 4
GND

IN2 OUT PLT_RST_BUF# 29,31


2

GND
IN2
1

1
R391 R416
3

U37 100K_0402_5% 100K_0402_5%

3
+3VS +3VS MC74VHC1G08DFT2G_SC70-5 VGA@ U30
VGA@ MC74VHC1G08DFT2G_SC70-5
2

2
1

A A
R205 R204
10K_0402_5% 10K_0402_5% Project_ID1 Project_ID0
@ @ Project ID
GPIO54 GPIO53
2

Project_ID1 Project_ID0
*V5WE2/T2 0 0
Security Classification Compal Secret Data Compal Electronics, Inc.
2

R214 R215 Reserved 0 1 2012/07/10 2013/07/10 Title


10K_0402_5% 10K_0402_5%
Reserved 1 0
Issued Date Deciphered Date HSW MCP(5/11) PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Reserved 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 8 of 52
5 4 3 2 1
5 4 3 2 1

+3VS

+3VS
RP23 1 8 PCH_GPIO51 PCH_GPIO51 8
2 7 PCH_GPIO83
3 6 PCH_GPIO55 PCH_GPIO55 8 RP36 1 8 PCH_GPIO88
4 5 SERIRQ 2 7 PCH_GPIO92 +1.05VS_VTT
10K_0804_8P4R_5% 3 6 PCH_GPIO85
RP24 1 8 EC_IN_RW 4 5 PCH_GPIO39

1
2 7 PCH_GPIO69 10K_0804_8P4R_5% U1J HASWELL_MCP_E
3 6 PCH_GPIO4 R144
4 5 PCH_GPIO7 1K_0402_5%
D 10K_0804_8P4R_5% D
RP25 1 8 PCH_GPIO5

2
2 7 PCH_GPIO1 PCH_GPIO76 P1 D60 H_THERMTRIP#
3 6 PCH_GPIO94 PCH_GPIO8 AU2 BMBUSY/GPIO76 THERMTRIP V4
GPIO8 RCIN/GPIO82 EC_KBRST# 34
4 5 PCH_GPIO93 AM7 T4 SERIRQ SERIRQ 34,35
10K_0804_8P4R_5% EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 1 2 R145
34 EC_LID_OUT# GPIO15 MISC PCH_OPI_RCOMP
RP26 1 8 PCH_GPIO2 PCH_GPIO16 Y1 AF20 @ T106 49.9_0402_1%
2 7 PCH_GPIO91 PCH_GPIO17 T3 GPIO16 RSVD AB21 @ T32
3 6 PCH_GPIO90 PCH_GPIO24 AD5 GPIO17 RSVD
4 5 PCH_GPIO38 PCH_GPIO27 AN5 GPIO24
10K_0804_8P4R_5% PCH_GPIO28 AD7 GPIO27
RP16 1 8 PCH_GPIO19 PCH_GPIO26 AN3 GPIO28
PCH_GPIO19 7 GPIO26
2 7 PCH_GPIO36 PCH_GPIO36 6 R6 PCH_GPIO83
3 6 VGA_ON PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
VGA_ON 38,8 GPIO56 GSPI0_CLK/GPIO84
4 5 EC_KBRST# PCH_GPIO57 AP1 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
RP28 1 8 PCH_GPIO18 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT#
PCH_GPIO18 7 GPIO59 GSPI1_CS/GPIO87
2 7 PCH_GPIO35 PCH_GPIO35 6 PCH_GPIO44 AK4 L5 PCH_GPIO88
3 6 PCH_GPIO48 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89
4 5 PCH_GPIO34 PCH_GPIO48 U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
PCH_GPIO34 6 GPIO48 GSPI_MOSI/GPIO90
10K_0804_8P4R_5% PCH_GPIO49 Y3 J1 PCH_GPIO91
RP29 1 8 PCH_GPIO71 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
2 7 PCH_GPIO49 PCH_GPIO71 Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93
3 6 PCH_GPIO16 PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PCH_GPIO94
4 5 PCH_GPIO37 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
PCH_GPIO37 6 GPIO14 UART1_RXD/GPIO0
10K_0804_8P4R_5% PCH_GPIO25 AM4 G2 PCH_GPIO1
PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
RP30 8 1 PCH_GPIO67 PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
7 2 PCH_GPIO65 R66 GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
C 6 3 PCH_GPIO6 0_0402_5% PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5 C
5 4 PCH_GPIO64 EC_SCI# 1 @ 2 PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
34,6 EC_SCI# GPIO10 I2C1_SDA/GPIO6
10K_0804_8P4R_5% DEVSLP0 P2 F1 PCH_GPIO7
32,8 DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
RP31 8 1 PCH_GPIO84 PCH_GPIO70 C4 E3 PCH_GPIO64
7 2 PCH_GPIO0 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
6 3 PCH_GPIO3 PCH_GPIO39 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
5 4 PCH_GPIO89 PCH_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
36 PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
10K_0804_8P4R_5% C3 EC_IN_RW EC_IN_RW 35
RP32 8 1 PCH_GPIO17 SDIO_D2/GPIO68 E2 PCH_GPIO69
7 2 PCH_GPIO23 SDIO_D3/GPIO69
PCH_GPIO23 7
6 3 PCH_GPIO76 10 OF 19 Rev1p2
5 4 PCH_GPIO50 HASWELL-MCP-E-ULT_BGA1168
10K_0804_8P4R_5% @
R311 1 2 PCH_GPIO70
10K_0402_5%

+3VALW_PCH

RP34 1 8 PCH_GPIO10
2 7 PCH_GPIO11
PCH_GPIO11 7
3 6 SUSWARN#
SUSWARN# 8
4 5 USB_OC3#
USB_OC3# 10 +3VALW_PCH
10K_0804_8P4R_5%
RP35 8 1 PCH_GPIO8 +3VALW_PCH
7 2 USB_OC1#
USB_OC1# 10
6 3 PCH_GPIO13 +3VS

1
5 4 PCH_GPIO26
10K_0804_8P4R_5% R301 R303 R269 1 @ 2 1K_0402_1% PCH_SPKR
B RP37 1 8 PCH_GPIO45 10K_0402_5% 10K_0402_5% B
+3VS 2 7 PCH_GPIO14
3 6 PCH_GPIO44

2
4 5 PCH_GPIO46 PCH_GPIO56 PCH_GPIO57
10K_0804_8P4R_5% SPKR / GPIO81 : NO REBOOT
RP38 1 8 DGPU_HOLD_RST# DGPU_HOLD_RST# 8
2 7 PCH_GPIO47
3 6 PCH_GPIO24 1: ENABLED
4 5 PCH_GPIO28
10K_0804_8P4R_5% 0: DISABLED (Have internal PD)
RP39 1
2
8
7
PCH_GPIO58
PCH_GPIO59 *
3 6 PCH_GPIO27
4 5 PCH_GPIO25
10K_0804_8P4R_5%
RP40 1 8 USB_OC2# USB_OC2# 10
2 7 PCH_GPIO60 PCH_GPIO60 7
3 6 USB_OC0# +3VALW_PCH +3VS
USB_OC0# 10,33
4 5 PCH_GPIO9 PCH_GPIO66 R270 1 @ 2 1K_0402_1%
10K_0804_8P4R_5% PCH_GPIO86 R272 1 @ 2 1K_0402_1%
R248 1 2 PCH_GPIO73 R247 1 @ 2 10K_0402_5% EC_LID_OUT# R273 1 2 1K_0402_5%
PCH_GPIO73 7
10K_0402_5%

GPIO15 : TLS Confidentiality GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
+3VS
1: Intel ME TLS with confidentiality 1: ENABLED 1: ENABLED
1

R306 0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
A
10K_0402_5%
UMA@ * (Have internal PD) * * A
2

DGPU_PRSNT#
GPIO87
DGPU_PRSNT# Security Classification Compal Secret Data Compal Electronics, Inc.
2

R219
10K_0402_5%
DIS,Optimus 0 Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title
HSW MCP(6/11) GPIO,LPIO
VGA@
UMA 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 9 of 52
5 4 3 2 1
5 4 3 2 1

U1K HASWELL_MCP_E

PEG_GTX_HRX_N0 C76 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N0 F10 AN8 USB20_N0


PERN5_L0 USB2N0 USB20_N0 33
PEG_GTX_HRX_P0 C77 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P0 E10 AM8 USB20_P0 USB2 Port 0 (USB3.0 P0)
PERP5_L0 USB2P0 USB20_P0 33
PEG_HTX_C_GRX_N0 C78 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_N0 C23 AR7 USB20_N1
PETN5_L0 USB2N1 USB20_N1 33
PEG_HTX_C_GRX_P0 C79 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_P0 C22 AT7 USB20_P1 USB2 Port 1
PETP5_L0 USB2P1 USB20_P1 33
PEG_GTX_HRX_N[0..3] 17
PEG_GTX_HRX_N1 C80 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N1 F8 AR8 USB20_N2
PEG_GTX_HRX_P[0..3] 17 PERN5_L1 USB2N2 USB20_N2 33
PEG_GTX_HRX_P1 C81 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P1 E8 AP8 USB20_P2 USB2 Port 2
PERP5_L1 USB2P2 USB20_P2 33
PEG_HTX_C_GRX_N[0..3] 17
D PEG_HTX_C_GRX_N1 C82 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_N1 B23 AR10 D
PEG_HTX_C_GRX_P[0..3] 17 PETN5_L1 USB2N3
PEG_HTX_C_GRX_P1 C83 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_P1 A23 AT10
PETP5_L1 USB2P3
PEG_GTX_HRX_N2 C84 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N2 H10 AM15 USB20_N4
PERN5_L2 USB2N4 USB20_N4 31
PEG_GTX_HRX_P2 C85 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P2 G10 AL15 USB20_P4 Mini Card(WLAN+BT)
PERP5_L2 USB2P4 USB20_P4 31
PEG_HTX_C_GRX_N2 C86 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_N2 B21 AM13 USB20_N5
PETN5_L2 USB2N5 USB20_N5 33
PEG_HTX_C_GRX_P2 C87 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_P2 C21 AN13 USB20_P5 Finger Print
PETP5_L2 USB2P5 USB20_P5 33
PEG_GTX_HRX_N3 C88 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_N3 E6 AP11 USB20_N6
PERN5_L3 USB2N6 USB20_N6 25
PEG_GTX_HRX_P3 C89 1 2 VGA@ 0.1U_0402_16V7K PEG_GTX_C_HRX_P3 F6 AN11 USB20_P6 Touch Screen
PERP5_L3 USB2P6 USB20_P6 25
PEG_HTX_C_GRX_N3 C90 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_N3 B22 AR13 USB20_N7
PETN5_L3 USB2N7 USB20_N7 25
PEG_HTX_C_GRX_P3 C91 1 2 VGA@ 0.1U_0402_16V7K PEG_HTX_GRX_P3 A21 AP13 USB20_P7 Camera
PETP5_L3 USB2P7 USB20_P7 25

29 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11


PCIE_PRX_DTX_P3 F11 PERN3 G20
29 PCIE_PRX_DTX_P3 PERP3 USB3RN1 PCH_USB3_RX0_N 33
PCIE LAN USB3.0 P1 USB3RP1
H20 PCH_USB3_RX0_P 33
C155 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3 Port 0
29 PCIE_PTX_C_DRX_N3 PETN3 USB
C160 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PCIe C33
29 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 PCH_USB3_TX0_N 33
B34
USB3TP1 PCH_USB3_TX0_P 33
31 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 F13
PCIE_PRX_DTX_P4 G13 PERN4 E18
31 PCIE_PRX_DTX_P4 PERP4 USB3RN2
WLAN USB3.0 P2 USB3RP2
F18
C156 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N4 B29
31 PCIE_PTX_C_DRX_N4 PETN4
C157 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P4 A29 B33
31 PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 A33
G17 USB3TP2
F17 PERN1/USB3RN3
C
PERP1/USB3RP3 C
C30 USB3.0 P3 / PCIE P1
C31 PETN1/USB3TN3 AJ10 USBRBIAS R154 1 2 22.6_0402_1%
PETP1/USB3TP3 USBRBIAS CAD note: 
AJ11
F15 USBRBIAS AN10 @ T35 Route single‐end 50‐ohms and max 450‐mils length.
G15 PERN2/USB3RN4 RSVD AM10@ T36 Avoid routing next to clock pins or under stitching capacitors. 
PERP2/USB3RP4 USB3.0 P4 / PCIE P2 RSVD
Recommended minimum spacing to other signal traces is 15 mils
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 USB_OC0# 33,9
AT1 USB_OC1#
+1.05VS_AUSB3PLL OC1/GPIO41 USB_OC1# 9
AH2 USB_OC2#
OC2/GPIO42 USB_OC2# 9
T33 @ E15 AV3 USB_OC3#
RSVD OC3/GPIO43 USB_OC3# 9
T34 @ E13
R232 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
PCIE_RCOMP 1
R155 1 @ 2 0_0603_5% PCIE_IREF B27 C612
PCIE_IREF 0.1U_0402_16V4Z
@
2
11 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(7/11) PCIE,USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 10 of 52
5 4 3 2 1
5 4 3 2 1

Shark Bay ULT have internal gate for VDDQ +CPU_CORE


HASWELL_MCP_E
U1L
+1.35V +1.35V_CPU
T37 @ L59 C36
@ J2 +1.35V_CPU T38 @ J58 RSVD VCC C40
1 2 RSVD VCC C44
AH26 VCC C48
JUMP_43X118 AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
Q5 @ AJ37 VDDQ VCC E23
AO4304L_SO8 AN33 VDDQ VCC E25
8 1 AP43 VDDQ VCC E27
7 2 AR48 VDDQ VCC E29
D D
6 3 AY35 VDDQ VCC E31
5 AY40 VDDQ VCC E33
AY44 VDDQ VCC E35
+CPU_CORE AY50 VDDQ VCC E37

4
VDDQ VCC E39
1 @ 2 F59 VCC E41
38 3VS_GATE VCC VCC
T39 @ N58 E43
R182 +VCCIO_OUT T40 @ AC58 RSVD VCC E45
1 RSVD VCC
0_0402_5% C5 +1.05VS_VTT E47
0.1U_0603_25V7K VCC_SENSE_R E63 VCC E49
@ R164 T41 @ AB23 VCC_SENSE VCC E51
2 2 @ 1 0_1206_5% A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
T42 @ AD23 E57
T43 @ AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
0_0402_5% 1 @ 2 R165 H_CPU_SVIDCLK N63 VIDALERT VCC F40
46 VR_SVID_CLK VIDSCLK VCC
VIDSOUT L63 F44
+3VS VCCST_PG_EC_R B59 VIDSOUT HSW ULT POWER VCC F48
+1.05VS_VTT 0_0402_5% 1 2 R167 PCH_VR_EN F60 VCCST_PWRGD VCC F52
46 VR_ON VR_EN VCC
46,8 VGATE 0_0402_5% 1 2 R168 VR_READY C59 F56
VR_READY VCC
1

+3VALW_PCH @ C167 G23


VCC

1
R422 1 2 0.1U_0402_16V7K D63 G25
100K_0402_5% U16 R309 CPU_PWR_DEBUG H59 VSS VCC G27
PWR_DEBUG VCC
@ 1
NC VCC
5 10K_0402_5% Reserved Only P62
VSS VCC
G29
R166 T45 @ P60 G31
2

C 2 0_0402_5% T46 @ P61 RSVD_TP VCC G33 C


34,8 VCCST_PG_EC
2
A 4 VCCST_PG_EC_R 1 @ 2 T47 @ N59 RSVD_TP VCC G35
Y VCCST_PWRGD 34,45 RSVD_TP VCC
3 T48 @ N61 G37
GND T98 @ T59 RSVD_TP VCC G39
74AUP1G07GW_TSSOP5 T142 @ AD60 RSVD VCC G41
T143 @ AD59 RSVD VCC G43
+1.05VS_VTT T144 @ AA59 RSVD VCC G45
T141 @ AE60 RSVD VCC G47
T140 @ AC59 RSVD VCC G49
T147 @ AG58 RSVD VCC G51
RSVD VCC

2
+1.05VS_VTT T145 @ U59 G53
RSVD VCC
SVID ALERT R169
150_0402_1%
T146 @ V59
RSVD VCC
VCC
G55
G57
@ AC22 H23
1 +CPU_CORE AE22 VCCST VCC J23
+1.05VS_VTT AE23 VCCST VCC K23
VCCST VCC
Place the PU CPU_PWR_DEBUG
VCC
K57
AB57 L22
resistors close to CPU VCC VCC
1

AD57 M23
VCC VCC
2

R171 AG57 M57


R170 C24 VCC VCC P57
75_0402_1% VCC VCC
10K_0402_5% C28 U57
R172 C32 VCC VCC W57
@
2

43_0402_1% VCC VCC


1

2 1 H_CPU_SVIDALRT# 12 OF 19 Rev1p2
46 VR_ALERT#
HASWELL-MCP-E-ULT_BGA1168
@

+1.35V_CPU
SVID DATA
B B
VDDQ DECOUPLING
+1.05VS_VTT
Place the PU
resistors close to CPU

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
EMC@ EMC@ 1
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
+

C8

C9

C10

C11
R173 @ C18

C12

C13

C14

C15

C16

C17
130_0402_1% 330U_2.5V_M

R174 2 2 2 2 2 2 2 2 2 2 2
2

0_0402_5%
2 @ 1 VIDSOUT +1.05VS_VTT
46 VR_SVID_DATA

+CPU_CORE For ESD


1U_0402_6.3V6K
22U_0805_6.3V6M

@ 1 1
1

C7
C6

R177
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU @
2 2
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2

VCC_SENSE_R 2 @ 1 R178
VCC_SENSE 46
0_0402_5% 2.2UF/6.3V/0402 * 4
A A

13 VSS_SENSE_R 2 @ 1 R235
VSS_SENSE 46
0_0402_5%
1

R233 Security Classification Compal Secret Data Compal Electronics, Inc.


100_0402_1% 2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(8/11) Power
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 11 of 52
5 4 3 2 1
5 4 3 2 1

+1.05VS_VTT +1.05VS_VTT U1M HASWELL_MCP_E

K9 +3VALW_PCH +RTCVCC
VCCHSIO

1U_0402_6.3V6K
L10
VCCHSIO

1U_0402_6.3V6K
1 M9 C30 1 2 1U_0402_6.3V6K
N8 VCCHSIO mPHY AH11
+ VCC1_05 VCCSUS3_3

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
C408 P9 RTC AG10
1 1 1 VCC1_05 VCCRTC +RTCVCC
+1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2 1 1 1
VCCUSB3PLL DCPRTC

C21

C20
220U_6.3V_M C31 +1.05VS_ASATA3PLL B11 C54 0.1U_0402_16V7K @ @
2 VCCSATA3PLL +3VS

C52

C51

C50
1U_0402_6.3V6K
2 2 2
EMC@ SPI 2 2 2
Y20 Y8 C58 2 1 0.1U_0402_16V7K
RSVD VCCSPI
D Near PJ602 +1.05VS_APLLOPI AA21
VCCAPLL
OPI @ D
Near K9 Near L10 Near M9 W21
VCCAPLL AG14 +1.05VS_VTT
VCCASW AG13
+3VALW_PCH VCCASW
+1.05VS_VTT
HDA --> 3.3V or 1.5V T105 @ J13 USB3
+1.05VS_VTT +1.05VS_AUSB3PLL I2C --> 1.8V DCPSUS3 J11 C27 1 2 10U_0603_6.3V6M
VCC1_05
Near B18 VCC1_05
H11 C33 1 2 1U_0402_6.3V6K
C42 1 2 1U_0402_6.3V6K 2 1 C38 AH14 AXALIA/HDA H15 C40 1 2 10U_0603_6.3V6M
L1 1 2 C32 1 2 100U_1206_6.3V6M 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 EMC@ C41
2.2UH_LQM2MPN2R2NG0L_30% VCC1_05 AF22 1U_0402_6.3V6K
Idc 1.2A Rdc 0.11ohm +/-30% T116 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW_R 1 2
DCPSUS2 CORE DCPSUSBYP AG20 R209 0_0402_5%
+1.05VS_ASATA3PLL +3VALW_PCH DCPSUSBYP AE9
VCCASW +1.05VS_VTT
C28 AF9 C36 1 2 22U_0805_6.3V6M
VCCASW
Near B11 Near AC9 2 1 22U_0805_6.3V6M AC9
VCCSUS3_3 VCCASW
AG8 C37 1 2 1U_0402_6.3V6K
C46 1 2 1U_0402_6.3V6K C59 @ AA9 AD10 C43 @1 2 1U_0402_6.3V6K
VCCSUS3_3 DCPSUS1
L2 1 2 C61 1 2 100U_1206_6.3V6M Near AH10 2 1 0.1U_0402_16V7K AH10
VCCDSW3_3 DCPSUS1
AD8
2.2UH_LQM2MPN2R2NG0L_30% C29 V8 GPIO/LCC
Idc 1.2A Rdc 0.11ohm +/-30% VCC3_3
Near V8 2 1 22U_0805_6.3V6M W9
VCC3_3 J15 +1.5VS
R210 +1.05VS_APLLOPI THERMAL SENSOR VCCTS1_5 K14
+3VS VCC3_3 +3VS
0_0805_5% K16 C55 1 2 0.1U_0402_16V7K
VCC3_3
1 @ 2 Near AA21
C47 1 2 1U_0402_6.3V6K
L3 1 2 C22 1 2 100U_1206_6.3V6M +1.05VS_AXCK_DCB J18
2.2UH_LQM2MPN2R2NG0L_30% K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
Idc 1.2A Rdc 0.11ohm +/-30% A20 T9 C44 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
+1.05VS_VTT J17
C C57 R21 VCCCLK C
VCCCLK
Near J17 2 1 1U_0402_6.3V6K T21
VCCCLK
LPT LP POWER C53 @1 2 1U_0402_6.3V6K
+1.05VS_VTT +1.05VS_AXCK_DCB C56 T100 @ K18 SUS OSCILLATOR AB8 C25 @1 2 100U_1206_6.3V6M
RSVD DCPSUS4
Near R21 2 1 1U_0402_6.3V6K T101 @ M20
RSVD
Near J18 T102 @ V21
RSVD
C48 1 2 1U_0402_6.3V6K +3VALW_PCH AE20 AC20 @ T103
L4 1 2 C23 1 2 100U_1206_6.3V6M AE21 VCCSUS3_3 RSVD AG16
VCCSUS3_3 USB2 VCC1_05 +1.05VS_VTT
2.2UH_LQM2MPN2R2NG0L_30% AG17
Idc 1.2A Rdc 0.11ohm +/-30% VCC1_05 C45 1 2 1U_0402_6.3V6K

+1.05VS_AXCK_LCPLL
Near A20 13 OF 19 Rev1p2
C49 1 2 1U_0402_6.3V6K HASWELL-MCP-E-ULT_BGA1168
L5 1 2 C24 1 2 100U_1206_6.3V6M @
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

+3VALW TO +3VALW(PCH AUX Power)


Short J5 for PCH VCCSUS3.3
+3VALW J5 @ +3VALW_PCH
B JUMP_43X39 B
1 2
1 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(9/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 12 of 52
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E HASWELL_MCP_E
U1N U1O U1P HASWELL_MCP_E
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R 11
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 HASWELL-MCP-E-ULT_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS @
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
HASWELL-MCP-E-ULT_BGA1168
@
14 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(10/11) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 13 of 52
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E HASWELL_MCP_E
U1Q U1R

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 T51 @ AT2 N23 @ T64


DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 @ T58 T52 @ AU44 RSVD RSVD R23 @ T65
T49 @ AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 T53 @ AV44 RSVD RSVD T23 @ T66
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T59 T54 @ D15 RSVD RSVD U10 @ T67
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 RSVD RSVD
T50 @ B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 @ T60
D D
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 @ T61 T55 @ F22 AL1 @ T68
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 @ T62 T56 @ H22 RSVD RSVD AM11 @ T69
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 T57 @ J21 RSVD RSVD AP7 @ T70
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD RSVD AU10 @ T71
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 RSVD AU15 @ T72
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 RSVD AW14 @ T73
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T63 RSVD AY14 @ T74
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2 RSVD
HASWELL-MCP-E-ULT_BGA1168
@ 18 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

U1S HASWELL_MCP_E

T104 @ CFG0 AC60 AV63 @ T75


CFG0 RSVD_TP
T107
T108
T166
@
@
@
CFG1
CFG2
CFG3
AC62
AC63
AA63
CFG1
CFG2
RSVD_TP
AU63 @ T76
CFG Straps for Processor
T167 @ CFG4 AA60 CFG3 C63 @ T77
T168 @ CFG5 Y62 CFG4 RSVD_TP C62 @ T78
C T169 @ CFG6 Y61 CFG5 RSVD_TP B43 @ T79 C
T170 @ CFG7 Y60 CFG6 RSVD CFG3
T171 @ CFG8 V62 CFG7 A51 @ T80
CFG8 RSVD_TP

1
T172 @ CFG9 V61 B51 @ T81
T182 @ CFG10 V60 CFG9 RSVD_TP R224
T181 @ CFG11 U60 CFG10 L60 @ T82 1K_0402_1%
T180 @ CFG12 T63 CFG11 RESERVED RSVD_TP @
T179 @ CFG13 T62 CFG12 N60 @ T83

2
T178 @ CFG14 T61 CFG13 RSVD
T177 @ CFG15 T60 CFG14 W23 @ T84
CFG15 RSVD Y22 @ T85
T176 @ CFG16 AA62 RSVD AY15 OPI_COMP
T175 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T174 @ CFG17 AA61 CFG18 AV62 @ T86
CFG17 RSVD
T173 @ CFG19 U62
CFG19 RSVD
D58 @ T87 Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS
VSS
N21 1: DISABLED
T90 @ A5
RSVD CFG3
RSVD
P20 @ T88 0: ENABLED; SET DFX ENABLED BIT
T91 @ E1 R20 @ T89
T92 @ D1 RSVD RSVD IN DEBUG INTERFACE MSR
T93 @ J20 RSVD
T94 @ H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF

1
19 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 R225
@ 1K_0402_5%
B B

2
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1%
2 1 TD_IREF Display Port Presence Strap
R226 8.2K_0402_5%

1 : Disabled; No Physical Display Port


CFG4 attached to Embedded Display Port

0 : Enabled; An external Display Port device is


connected to the Embedded Display Port

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(11/11) RSVD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 14 of 52
5 4 3 2 1
A B C D E

+1.35V
+1.35V +1.35V +1.35V
JDIMM1

1
+V_DDR_REFA 1 2
VREF_DQ VSS1 +5VALW +5VS

0.1U_0402_16V7K
3 4 DDR_A_D9
VSS2 DQ4

C34
R54 DDR_A_D13 5 6 DDR_A_D12 1
R293 1.8K_0402_1% DDR_A_D8 7 DQ0 DQ5 8 @
2_0402_1% 9 DQ1 VSS3 10 DDR_A_DQS#1 R187 1 2 SA_ODT0

2
1 2 11 VSS4 DQS#0 12 DDR_A_DQS1 66.5_0402_1%
5 SA_DIMM_VREFDQ DM0 DQS0 2

2.2U_0402_6.3V6M
1 13 14
VSS5 VSS6

2
@ 1 1 DDR_A_D14 15 16 DDR_A_D15
DQ2 DQ6 +1.35V

C105

0.1U_0402_16V7K
C106
C158 @ DDR_A_D10 17 18 DDR_A_D11 R186 R191 R188 1 2 SA_ODT1
0.022U_0402_25V7K R185 19 DQ3 DQ7 20 U45 66.5_0402_1%
VSS7 VSS8 100K_0402_5% 100K_0402_5%
2 1.8K_0402_1% DDR_A_D29 21 22 DDR_A_D25 1 5 Q18
DQ8 DQ12 NC VCC @

1
2 2 DDR_A_D28 23 24 DDR_A_D24 LBSS138LT1G_SOT-23-3
D

1
DQ9 DQ13

1
25 26 4 DDR_PG_CTRL 2 R189 1 2 SB_ODT0
1 VSS9 VSS10 A SB_ODT0 16 1
R176 DDR_A_DQS#3 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_A_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# 16,4 GND
@ 31 32 S
2

3
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT R190 1 2 SB_ODT1
DQ10 DQ14 SB_ODT1 16
DDR_A_D31 35 36 DDR_A_D26 66.5_0402_1%
37 DQ11 DQ15 38
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DQ16 DQ20 DDR_VTT_PG_CTRL 43
DDR_A_D41 41 42 DDR_A_D40
43 DQ17 DQ21 44
VSS15 VSS16 DDR_A_DQS#[0..7] 5
DDR_A_DQS#5 45 46
DDR_A_DQS5 47 DQS#2 DM2 48
DQS2 VSS17 DDR_A_DQS[0..7] 5
49 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
DQ18 DQ23 DDR_A_D[0..63] 5
DDR_A_D47 53 54
55 DQ19 VSS19 56 DDR_A_D52
All VREF traces should DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53
DDR_A_MA[0..15] 5
Layout Note: have 10 mil trace width DDR_A_D50 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_A_DQS#6
+1.35V 63 VSS22 DQS#3 64 DDR_A_DQS6
65 DM3 DQS3 66
DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
DQ27 DQ31
1U_0402_6.3V6K
C107

1U_0402_6.3V6K
C108

1U_0402_6.3V6K
C109

1U_0402_6.3V6K
C110

71 72
VSS25 VSS26
1 1 1 1
@ @

5 DDRA_CKE0_DIMMA DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA DDRA_CKE1_DIMMA 5


2 2 2 2 75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
5 DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
2 87 A9 A7 88 2
+1.35V DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
A3 A2
10U_0603_6.3V6M
C111

10U_0603_6.3V6M
C112

10U_0603_6.3V6M
C113

10U_0603_6.3V6M
C114

DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SA_CLK_DDR0 SA_CLK_DDR0 101 102 SA_CLK_DDR1 SA_CLK_DDR1 5
SA_CLK_DDR#0 103 CK0 CK1 104 SA_CLK_DDR#1
5 SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 5
105 106
2 2 2 2 DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 5 +1.35V
5 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# 5
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# 5

1
5 DDR_A_CAS# DDR_A_CAS# 115 116 SA_ODT0
117 CAS# ODT0 118 R56
DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
+1.35V 5 DDRA_CS1_DIMMA# S1# NC2
123 124 R296

2
125 VDD17 VDD18 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA 5
127 128 2_0402_1% 1
VSS27 VSS28

1
EMC@ EMC@ DDR_A_D0 129 130 DDR_A_D5 @
DQ32 DQ36
10U_0603_6.3V6M
C115

10U_0603_6.3V6M
C116

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C161

2.2U_0402_6.3V6M

0.1U_0402_16V7K
1 DDR_A_D1 131 132 DDR_A_D4 C162
@ 133 DQ33 DQ37 134 R295 0.022U_0402_25V7K
1 1 1 1 VSS29 VSS30 1 1
+ 2

C119

C120
C118 DDR_A_DQS#0 135 136 @ 1.8K_0402_1%
DQS#4 DM4

1
330U_2.5V_M DDR_A_DQS0 137 138

2
139 DQS4 VSS31 140 DDR_A_D3
2 2 2 2 2 DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2 2 @ R294
SF000002Z00 DDR_A_D6 143 DQ34 DQ39 144 24.9_0402_1%
330U 2.5V H4.2 145 DQ35 VSS33 146 DDR_A_D18

2
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
17mohm OSCON DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
3 153 VSS36 DQS#5 154 DDR_A_DQS2 3
155 DM5 DQS5 156
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
+0.675VS DQ43 DQ47 +VREF_CA 16
161 162
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C121

1U_0402_6.3V6K
C122

1U_0402_6.3V6K
C123

1U_0402_6.3V6K
C124

DDR_A_DQS#4 169 170


DDR_A_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43
@ @ 173 174 DDR_A_D35
DDR_A_D34 175 VSS44 DQ54 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_A_D63
DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
Layout Note: 195 DQ59 DQ63 196
Place near JDIMM1.203,204 197 VSS51 VSS52 198
199 SA0 EVENT# 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 16,37,7
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 16,37,7
+0.675VS 203 204 +0.675VS
VTT1 VTT2
2.2U_0402_6.3V6M

205 206
G1 G2
2

1 1
Channel A
0.1U_0402_16V7K
C125

C126

0_0402_5%
R211

0_0402_5%
R212

@
@ @ TYCO_2-2013022-1
CONN@
2 2
SP07000JN10
1

4 4

<Address: SA1:SA0=00>

DIMM_1 STD H:4mm


Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date DDRIII DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0

A
http://sualaptop365.edu.vn B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Date:
V5WE2 M/B LA-9531P Schematic
Tuesday, March 26, 2013
E
Sheet 15 of 52
A B C D E

+1.35V
+1.35V +1.35V
JDIMM2
DDR_B_DQS#[0..7] 5

1
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4 DDR_B_DQS[0..7] 5
R57 DDR_B_D8 5 6 DDR_B_D9
R297 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8
DQ1 VSS3 DDR_B_D[0..63] 5
2_0402_1% 9 10 DDR_B_DQS#1

2
1 2 11 VSS4 DQS#0 12 DDR_B_DQS1
5 SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] 5

2.2U_0402_6.3V6M
1 13 14
VSS5 VSS6

1
@ 1 1 DDR_B_D10 15 16 DDR_B_D13
DQ2 DQ6

C127

0.1U_0402_16V7K
C128
C159 @ DDR_B_D11 17 18 DDR_B_D15
0.022U_0402_25V7K R213 19 DQ3 DQ7 20
2 1.8K_0402_1% DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
DQ8 DQ12

1
2 2 DDR_B_D29 23 24 DDR_B_D24

2
25 DQ9 DQ13 26
1 VSS9 VSS10 1
R179 DDR_B_DQS#3 27 28
24.9_0402_1% DDR_B_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# 15,4
@ 31 32
2

DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30


DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
All VREF traces should DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60
Layout Note: have 10 mil trace width DDR_B_D57 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_B_DQS#7
+1.35V 63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
DQ27 DQ31
1U_0402_6.3V6K
C129

1U_0402_6.3V6K
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

71 72
VSS25 VSS26
1 1 1 1
@ @

5 DDRB_CKE0_DIMMB DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB DDRB_CKE1_DIMMB 5


2 2 2 2 75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
5 DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
2 87 A9 A7 88 2
+1.35V DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
A3 A2
10U_0603_6.3V6M
C133

10U_0603_6.3V6M
C134

10U_0603_6.3V6M
C135

10U_0603_6.3V6M
C136

DDR_B_MA1 97 98 DDR_B_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SB_CLK_DDR0 SB_CLK_DDR0 101 102 SB_CLK_DDR1 SB_CLK_DDR1 5
SB_CLK_DDR#0 103 CK0 CK1 104 SB_CLK_DDR#1
5 SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 5
105 106
2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 5
5 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# 5
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# 5
5 DDR_B_CAS# DDR_B_CAS# 115 116 SB_ODT0 SB_ODT0 15
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1
A13 ODT1 SB_ODT1 15
5 DDRB_CS1_DIMMB# DDRB_CS1_DIMMB# 121 122
+1.35V 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CA 15
127 128
DDR_B_D4 129 VSS27 VSS28 130 DDR_B_D5
DQ32 DQ36
10U_0603_6.3V6M
C137

10U_0603_6.3V6M
C138

10U_0603_6.3V6M
C139

2.2U_0402_6.3V6M
DDR_B_D1 131 132 DDR_B_D0
133 DQ33 DQ37 134
1 1 1 VSS29 VSS30 1 1

C141

0.1U_0402_16V7K
C142
DDR_B_DQS#0 135 136 @
DDR_B_DQS0 137 DQS#4 DM4 138
@ 139 DQS4 VSS31 140 DDR_B_D2
2 2 2 DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
3 153 VSS36 DQS#5 154 DDR_B_DQS2 3
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
+0.675VS 161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C143

1U_0402_6.3V6K
C144

1U_0402_6.3V6K
C145

1U_0402_6.3V6K
C146

DDR_B_DQS#4 169 170


DDR_B_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43
@ @ 173 174 DDR_B_D34
DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_B_D51
DDR_B_D52 181 VSS46 DQ60 182 DDR_B_D55
+3VS DDR_B_D49 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#6
187 VSS48 DQS#7 188 DDR_B_DQS6
DM7 DQS7
2

189 190
R229 DDR_B_D48 191 VSS49 VSS50 192 DDR_B_D54
10K_0402_5% DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
Layout Note: 195 DQ59 DQ63 196
Place near JDIMM1.203,204 197 VSS51 VSS52 198
1

199 SA0 EVENT# 200 D_CK_SDATA


+3VS VDDSPD SDA D_CK_SDATA 15,37,7
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 15,37,7
+0.675VS 203 204 +0.675VS
VTT1 VTT2
2.2U_0402_6.3V6M

205 206
G1 G2
2

1 1
Channel B
0.1U_0402_16V7K
C147

C148

0_0402_5%
R231

@
@ TYCO_2-2013022-1
CONN@
2 2
SP07000JN10
1

4 4

<Address: SA1:SA0=10>

DIMM_2 STD H:4mm


Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date DDRIII DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0

A
http://sualaptop365.edu.vn B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Date:
V5WE2 M/B LA-9531P Schematic
Tuesday, March 26, 2013
E
Sheet 16 of 52
A B C D E

GFX PCIE LANE REVERSAL


U51A
PEG_HTX_C_GRX_P[0..3]
10 PEG_HTX_C_GRX_P[0..3] PART 1 0F 9 PEG_GTX_HRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] PEG_GTX_HRX_P[0..3] 10
10 PEG_HTX_C_GRX_N[0..3] PEG_GTX_HRX_N[0..3]
PEG_GTX_HRX_N[0..3] 10
U51G
PEG_HTX_C_GRX_P0 AA38 Y33 PEG_GTX_HRX_P0
PEG_HTX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PEG_GTX_HRX_N0 PART 7 0F 9
1 1
PCIE_RX0N PCIE_TX0N
AK27
PEG_HTX_C_GRX_P1 Y35 W33 PEG_GTX_HRX_P1 RSVD/VARY_BL AJ27
PEG_HTX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PEG_GTX_HRX_N1 RSVD/DIGON
PCIE_RX1N PCIE_TX1N LVDS CONTROL

PEG_HTX_C_GRX_P2 W38 U33 PEG_GTX_HRX_P2


PEG_HTX_C_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PEG_GTX_HRX_N2 AK35
PCIE_RX2N PCIE_TX2N TXCBP_DPB3P AL36
TXCBM_DPB3N
PEG_HTX_C_GRX_P3 V35 U30 PEG_GTX_HRX_P3 AJ38
PEG_HTX_C_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PEG_GTX_HRX_N3 TX3P_DPB2P AK37
PCIE_RX3N PCIE_TX3N TX3M_DPB2N
AH35
U38 T33 TX4P_DPB1P AJ36
T37 PCIE_RX4P PCIE_TX4P T32 TX4M_DPB1N
PCIE_RX4N PCIE_TX4N AG38
TX5P_DPB0P AH37
T35 T30 TX5M_DPB0N
R36 PCIE_RX5P PCIE_TX5P T29 AF35

LVTMDP
PCIE_RX5N PCIE_TX5N NC#AF35 AG36
NC#AG36
R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N
AP34
P35 P30 TXCAP_DPA3P AR34
N36 PCIE_RX7P PCIE_TX7P P29 TXCAM_DPA3N
2
PCIE_RX7N PCIE_TX7N AW37 2
TX0P_DPA2P AU35
N38 N33 TX0M_DPA2N
M37 NC#N38 NC#N33 N32 AR37
NC#M37 NC#N32 TX1P_DPA1P AU39
TX1M_DPA1N
PCI EXPRESS INTERFACE

M35 N30 AP35


L36 NC#M35 NC#N30 N29 TX2P_DPA0P AR35
NC#L36 NC#N29 TX2M_DPA0N
AN36
L38 L33 NC#AN36 AP37
K37 NC#L38 NC#L33 L32 NC#AP37
NC#K37 NC#L32

K35 L30
J36 NC#K35 NC#L30 L29 2160842006A0MARSXT_FCBGA962
NC#J36 NC#L29 @

J38 K33
H37 NC#J38 NC#K33 K32
NC#H37 NC#K32

H35 J33
G36 NC#H35 NC#J33 J32
NC#G36 NC#J32

G38 K30
F37 NC#G38 NC#K30 K29
NC#F37 NC#K29
3 3
F35 H33
E37 NC#F35 NC#H33 H32
NC#E37 NC#H32

CLOCK
AB35
7 CLK_PEG_VGA PCIE_REFCLKP
AA36
7 CLK_PEG_VGA# PCIE_REFCLKN

CALIBRATION
Y30 VGA_PCIE_CALRP R794 1 VGA@ 2 1.69K_0402_1% +0.95VSDGPU
PCIE_CALR_TX
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN R796 1 VGA@ 2 1K_0402_1% +0.95VSDGPU
R795 1K_0402_5% TEST_PG PCIE_CALR_RX
3.3-V tolerant
PLTRST_VGA# AA30
8 PLTRST_VGA# PERSTB

2160842006A0MARSXT_FCBGA962
@

4 4

U51 U51

Security Classification Compal Secret Data Compal Electronics, Inc.


SUN_XT_M2_962P MARS_XT_M2_962P 2012/07/10 2013/07/10 Title
SUN@ MARS@
Issued Date Deciphered Date MARS-Pro_PCIE
SA00006G610 SA000061J20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 11, 2013 Sheet 17 of 52
A B C D E
A B C D E

U51B U51I 130mA L64


BLM18AG121SN1D_2P
+3VSDGPU External VGA Thermal Sensor PART 2 0F 9

PART 9 0F 9
+MPLL_PVDD 2 1 +1.8VSDGPU
U52 @ MUTI GFX VGA@
1 8 VGA_SMB_CK2 T109 AD29 AU24
VDD SCLK AC29 GENLK_CLK NC#AU24 AV23 VGA@ 1 VGA@ 1
1 T110 GENLK_VSYNC NC#AV23 SM010030010 200ma
0.1U_0402_16V4Z
C823

1U_0402_6.3V6K
C825

10U_0603_6.3V6M
C826
@ GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA AT25
120ohm@100mhz DCR 0.2
C827 1 2 3 6 THM_ALERT# AJ21 NC#AT25 AR24 AV33 XTALIN
2 @ D- ALERT# AK21 SWAPLOCKA DPA NC#AR24 XTALIN 2 2
GPU_THERM_D- 4 5 1 @ 2 SWAPLOCKB AU26
THERM# GND +3VSDGPU NC#AU26
R798 4.7K_0402_5% AV25
NC#AV25 L65
ADM1032ARMZ-2REEL_MSOP8 AR8 AT27
75mA BLM18AG121SN1D_2P
AU8 NC#AR8 NC#AT27 AR26 +SPLL_PVDD 2 1
NC#AU8 NC#AR26 +1.8VSDGPU
T111 AP8 AU34 XTALOUT VGA@
+3VSDGPU AW8 DBG_CNTL0 AR30 XTALOUT
1 AR3 NC#AW8 NC#AR30 AT29 VGA@ 1 VGA@ 1 1
+3VSDGPU NC#AR3 NC#AT29

1U_0402_6.3V6K
C829

10U_0603_6.3V6M
C830
AR1
AU1 NC#AR1 AV31 +MPLL_PVDD H7
T112 DBG_DATA0 NC#AV31 MPLL_PVDD

2
T113 AU3 AU30 H8
R800 R801 AW3 DBG_DATA1 DPB NC#AU30 MPLL_PVDD 2 2
T114 DBG_DATA2
4.7K_0402_5% 4.7K_0402_5% Q54B VGA@ T115 AP6 AR32 AW34 XO_IN 1 @ 2
DBG_DATA3 NC#AR32 XO_IN

5
VGA@ VGA@ DMN66D0LDW-7_SOT363-6 T118 AW5 AT31 0_0402_5% R799
AU5 DBG_DATA4 NC#AT31 +SPLL_PVDD AM10

PLLS/XTAL
T117
1

1
VGA_SMB_CK2 4 3 EC_SMB_CK2 AR6 DBG_DATA5 AT33 SPLL_PVDD L66
EC_SMB_CK2 24,34,7 T119
AW6 DBG_DATA6 NC#AT33 AU32
100mA BLM18AG121SN1D_2P
T121 DBG_DATA7 NC#AU32
T120 AU6 +SPLL_VDDC 2 1 +0.95VSDGPU
DBG_DATA8

2
Q54A VGA@ T122 AT7 AU14 +SPLL_VDDC AN9 AW35 XO_IN2 2 @ 1 VGA@
DMN66D0LDW-7_SOT363-6 AV7 DBG_DATA9 NC#AU14 AV13 SPLL_VDDC XO_IN2 0_0402_5% R802
T124 DBG_DATA10 NC#AV13
VGA_SMB_DA2 1 6 EC_SMB_DA2 T123 AN7 VGA@ 1 VGA@ 1
EC_SMB_DA2 24,34,7 DBG_DATA11

1U_0402_6.3V6K
C832

10U_0603_6.3V6M
C833
T125 AV9 AT15
AT9 DBG_DATA12 NC#AT15 AR14 SPLL_PVSS AN10
T127 DBG_DATA13 NC#AR14 SPLL_PVSS
T126 AR10
AW10 DBG_DATA14 DPC AU16 SPLL_PVSS 2 2
T128 DBG_DATA15 NC#AU16
T130 AU10 AV15
AP10 DBG_DATA16 NC#AV15 AK10
T129 DBG_DATA17 CLKTESTA T137
T131 AV11 AT17 AF30 AL10 T138
AT11 DBG_DATA18 NC#AT17 AR16 AF31 NC_XTAL_PVDD CLKTESTB
T133 DBG_DATA19 NC#AR16 NC_XTAL_PVSS

0.1U_0402_16V4Z 51.1_0402_1%

0.1U_0402_16V4Z 51.1_0402_1%
T132 AR12 1 1
DBG_DATA20

C892

C891
T134 AW12
DBG_DATA21 NC#AU20
AU20 @ @ Mars MLPS configuration
T136 AU12 AT19
AP12 DBG_DATA22 NC#AT19
T135 DBG_DATA23 AT21 2 2 Bits[5:1] PU(1%) PD(1%) Cap
NC#AT21 AR20
R898 0_0402_5% NC#AR20 2160842006A0MARSXT_FCBGA962
xx000 NC 4.75k

1
VGA_SMB_CK2 1 @ 2VGA_SMB_CK2_R AJ23 DPD AU22 @
SMBCLK SMBus NC#AU22 xx001 8.45k 2.00k

R904

R841
VGA_SMB_DA2 1 @ 2VGA_SMB_DA2_R AH23 AV21 @ @
R899 0_0402_5% SMBDATA NC#AV21
AT23
xx010 4.53k 2.00k
NC#AT23
+3VSDGPU Slave ID: 0x41 AR22
xx011 6.98k 4.99k

2
AK26 NC#AR22
AJ26 SCL I2C
2 SDA xx100 4.53k 4.99k 2
2

R409 AD39
100K_0402_5% R AD37
T154 xx101 3.24k 5.62k
GENERAL PURPOSE I/O
D22 VGA@ GPU_DPRSLPVR AH20 AVSSN
RB751V40_SC76-2
47 GPU_DPRSLPVR
AH18 GPIO_0 AE36
xx110 3.40k 10.0k
GPIO_1 G T156
VGA@ AN16 AD35
xx111 4.75k NC
1

GPIO_2 AVSSN
34 GPU_ACIN
1 2 GPU_ACIN_D AUD[1:0]:
AF37 00 - No audio function
GPU_ACIN_D AH17 B AE38
T155 00xxx 680nF
GPU_VID_4 AJ17 GPIO_5_AC_BATT AVSSN
47 GPU_VID_4
AK17 GPIO_6_TACH DAC1 AC36 AUD_1 R803 1 @ 2 10K_0402_5%
01xxx 82nF
AJ13 GPIO_7_BLON HSYNC AC38 AUD_0 R804 1 2 10K_0402_5%
AH15 GPIO_8_ROMSO VSYNC @
10xxx 10nF
GPU_VID_5 AJ16 GPIO_9_ROMSI
47 GPU_VID_5
AK16 GPIO_10_ROMSCK AB34 RSET R805 1 MARS@ 2 499_0402_1%
10mil 11xxx NC
AL16 GPIO_11 RSET (SUN NC) L67
AM16 GPIO_12 AD34 +AVDD 2 1
70mA
GPIO_13 AVDD +1.8VSDGPU
AM14 AE34 (SUN NC) MARS@
GPIO_14_HPD2 AVSSQ

1U_0402_6.3V6K
C834

0.1U_0402_16V4Z
C835
GPU_VID_1 AM13 1 1 0_0603_5%
47 GPU_VID_1 GPIO_15_PWRCNTL_0
47 GPU_VID_3
GPU_VID_3 AK14
GPIO_16 VDD1DI
AC33 +VDD1DI PS0_[1]=1 : same as GPIO_11 Since the frame buffer size is 512 MB
THM_ALERT# AG30 AC34 PS0_[2]=0 : same as GPIO_12 the aperture size is set to 256 MB.
AN14 GPIO_17_THERMAL_INT VSS1DI @ @
R806 10K_0402_5%1 @ 2 GPIO_19_CTF AM17 GPIO_18_HPD3 (SUN NC) 2 2 PS0_[3]=0 : same as GPIO_13
GPU_VID_2 AL13 GPIO_19_CTF V13 PS0_[4]=1 : Reserved for internal use only. Must be 1
47 GPU_VID_2 GPIO_20_PWRCNTL_1 NC#V13
AJ14
GPIO_21 NC#U13
U13 PS0_[5]=1 : AUD_PORT_CONN_PINSTRAP[0]
AK13 AF33 10mil
GPIO_22_ROMCSB NC#AF33
AN13
CLKREQB NC#AF32
AF32 L68 100 - 512Kbit M25P05A (ST)
(GPIO1, 2, 7, 11, 12, 13, 18, 21 is NC at SUN) AA29 0_0603_5% 101 - 1Mbit M25P10A (ST)
NC#AA29 AG21
117mA 2 1
AG32 NC#AG21 AC32 MARS@
+1.8VSDGPU 101 - 2Mbit M25P20 (ST)
AG33 GPIO_29 NC#AC32
1 1 @ 101 - 4Mbit M25P40 (ST)
GPIO_30
101 - 8Mbit M25P80 (ST)

0.1U_0402_16V4Z
C837

1U_0402_6.3V6K
C838
AC31 @
AJ19 NC_SVI2#AC31 AD30
GENERICA NC_SVI2#AD30 100 - 512Kbit Pm25LV512 (Chingis)
AK19 AD32
AJ20 GENERICB NC_SVI2#AD32 2 2 101 - 1Mbit Pm25LV010 (Chingis)
AK20 GENERICC
3 3
AJ24 GENERICD
GENERICE_HPD4
AH26
GENERICF_HPD5
PS_1[1] = 0 : PCIeR GEN3 is not supported.
VREFG:Use a voltage divider to set AH24
GENERICG_HPD6 PS_1[2] = 0 : Reserved for internal use only
VREFG = 1.80 V / 3 (or 0.60-V nominal). PS_1[3] = 0 : Reserved for internal use only
AM34 PS_0
PS_0 PS_1[4] = 1 : TX_PWRS_ENB: Full Tx output swing.
AC30
CEC_1
PS_1[5] = 1 : TX_DEEMPH_EN: Tx deemphasis enabled.

+1.8VSDGPU R810 1 MARS@ 2 499_0402_1% AK24 AD31 PS_1


HPD1 PS_1
20mil
MLPS
PS_2[1] = 0 : Reserved.
R811 1 MARS@ 2 249_0402_1% PS_2[2] = 0 : Reserved.
C841 1 2 0.1U_0402_16V4Z +VGA_VREF AH13 AG31 PS_2 PS_2[3] = 0 : BIOS_ROM_EN :Disable the external BIOS ROM device.
MARS@ (SUN NC) DBG_VREFG PS_2 PS_2[4] = 0 : VGA_DIS : 0=VGA controller capacity enabled.
PS_2[5] = 1 : Reserved.
Place VREFG divider and cap close to ASIC BACO
AL21 AD33 PS_3
PX_EN PS_3
2

Pull high @ VGA side


R813
R814 0_0402_5% +VDDC_CT +VDDC_CT +VDDC_CT +VDDC_CT PS_3[1] = x :
+3VSDGPU 5.11K_0402_1%
@ DEBUG DDC/AUX
PS_3[2] = x : VRAM ID
2 @ 1 AM26
PS_3[3] = x :
1

DDC1CLK

1
AN26
2 VGA@ 1 TESTEN AD28 DDC1DATA X76@ @ @ VGA@ PS_3[4] = 1 : AUD_PORT_CONN_PINSTRAP[1]
+3VSDGPU TESTEN
VGA@ R817 1K_0402_5%
AUX1P
AM27 R812 R821 R816 R808 PS_3[5] = 1 : AUD_PORT_CONN_PINSTRAP[2]
R822 AL27 10K_0402_5% 10K_0402_5% 10K_0402_5% 8.45K_0402_1%
1M_0402_5% RP21 AUX1N

2
XTALOUT 2 1 XTALIN 1 8 JTAG_TRSTB AM23
JTAG_TRSTB DDC2CLK
AM19 PS_0 ======= VRAM ID for Mars =======
2 7 JTAG_TDI AN23 AL19 PS_1
X2 3 6 JTAG_TCK AK23 JTAG_TDI DDC2DATA PS_2
VGA@ 4 5 JTAG_TMS AL24 JTAG_TCK AN20 PS_3 001 Micron MT41K256M16HA-107G:E x 8
Crystal AM24 JTAG_TMS AUX2P AM20 010 Hynix H5TQ2G63DFR-11C x 4
JTAG_TDO AUX2N
3
OUT GND
4 T18
10K_0804_8P4R_5% @ @ @ @ @ 011 Hynix H5TQ2G63DFR-11C x 8

1
@ AL30 1 1 1 1
NC#AL30
0.1U_0402_16V7K
C842

0.01U_0402_16V7K
C847

0.1U_0402_16V7K
C843

0.1U_0402_16V7K
C840
2 1 AM30 X76@
4 GND IN NC#AM30 R815 R823 R818 R809 4
2 2 THERMAL AL29 10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
C848 27MHZ_10PF_X3G027000BA1H-U C849 +3VSDGPU GPU_THERM_D+ AF29 NC#AL29 AM29 2 2 2 2 VGA@ VGA@ VGA@

2
12P_0402_50V8J GPU_THERM_D- AG29 DPLUS NC#AM29
12P_0402_50V8J DMINUS
VGA@ 1 1 1 @ 2 AN21
VGA@ NC#AN21
R819 10K_0402_5% AM21
1 VGA@ 2 MLPS_EN# AK32 NC#AM21
R820 10K_0402_5% GPIO_28_FDO AK30
AL31 NC#AK30 AK29
+1.8VSDGPU TS_A NC#AK29
Crystals must have a max ESR of 80 ohm
L69 @ 13mA 10mil AJ30 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 0_0603_5% +TSVDD AJ32 DDCVGACLK AJ31 2012/07/10 2013/07/10 Title
AJ33 TSVDD
TSVSS
DDCVGADATA Issued Date Deciphered Date MARS-Pro_STRAP
10U_0603_6.3V6M 2 1 @ C844
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1U_0402_6.3V6K 2 1 @ C845 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z 2 1 VGA@ C846 2160842006A0MARSXT_FCBGA962 Custom 1.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 18 of 52
A B C D E

http://sualaptop365.edu.vn
A B C D E

U51D MAA[0..15]
MAA[0..15] 22
U51C
PART 4 0F 9 DQMA#[0..7]
PART 3 0F 9 MDB[0..63] DQMA#[0..7] 22
MDA[0..63] 23 MDB[0..63] GDDR5/DDR3 QSA[0..7]
GDDR5/DDR3 MDB0 C5 P8 MAB0
22 MDA[0..63] DQB0_0 MAB0_0/MAB_0 QSA[0..7] 22
MDA0 C37 G24 MAA0 MDB1 C3 T9 MAB1
MDA1 C35 DQA0_0 MAA0_0/MAA_0 J23 MAA1 MDB2 E3 DQB0_1 MAB0_1/MAB_1 P9 MAB2 QSA#[0..7]
(SUN 64 bin on at Channel B) DQA0_1 MAA0_1/MAA_1 DQB0_2 MAB0_2/MAB_2 QSA#[0..7] 22
MDA2 A35 H24 MAA2 MDB3 E1 N7 MAB3
MDA3 E34 DQA0_2 MAA0_2/MAA_2 J24 MAA3 MDB4 F1 DQB0_3 MAB0_3/MAB_3 N8 MAB4
MDA4 G32 DQA0_3 MAA0_3/MAA_3 H26 MAA4 MDB5 F3 DQB0_4 MAB0_4/MAB_4 N9 MAB5
DQA0_4 MAA0_4/MAA_4 DQB0_5 MAB0_5/MAB_5

MEMORY INTERFACE A
MDA5 D33 J26 MAA5 MDB6 F5 U9 MAB6
MDA6 F32 DQA0_5 MAA0_5/MAA_5 H21 MAA6 MDB7 G4 DQB0_6 MAB0_6/MAB_6 U8 MAB7 MAB[0..15]
DQA0_6 MAA0_6/MAA_6 DQB0_7 MAB0_7/MAB_7 MAB[0..15] 23
MDA7 E32 G21 MAA7 MDB8 H5 Y9 MAB8
1
MDA8 D31 DQA0_7 MAA0_7/MAA_7 H19 MAA8 MDB9 H6 DQB0_8 MAB1_0/MAB_8 W9 MAB9 DQMB#[0..7] 1
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9 DQMB#[0..7] 23
MDA9 F30 H20 MAA9 MDB10 J4 AC8 MAB10
MDA10 C30 DQA0_9 MAA1_1/MAA_9 L13 MAA10 MDB11 K6 DQB0_10 MAB1_2/MAB_10 AC9 MAB11 QSB[0..7]
DQA0_10 MAA1_2/MAA_10 DQB0_11 MAB1_3/MAB_11 QSB[0..7] 23
MDA11 A30 G16 MAA11 MDB12 K5 AA7 MAB12
MDA12 F28 DQA0_11 MAA1_3/MAA_11 J16 MAA12 MDB13 L4 DQB0_12 MAB1_4/MAB_12 AA8 B_BA2 QSB#[0..7]

MEMORY INTERFACE B
DQA0_12 MAA1_4/MAA_12 DQB0_13 MAB1_5/BA2 B_BA2 23 QSB#[0..7] 23
MDA13 C28 H16 A_BA2 MDB14 M6 Y8 B_BA0
+1.5VSDGPU DQA0_13 MAA1_5/MAA_BA2 A_BA2 22 DQB0_14 MAB1_6/BA0 B_BA0 23
MDA14 A28 J17 A_BA0 MDB15 M1 AA9 B_BA1
DQA0_14 MAA1_6/MAA_BA0 A_BA0 22 DQB0_15 MAB1_7/BA1 B_BA1 23
MDA15 E28 H17 A_BA1 MDB16 M3
DQA0_15 MAA1_7/MAA_BA1 A_BA1 22 DQB0_16
MDA16 D27 MDB17 M5 H3 DQMB#0
MDA17 F26 DQA0_16 A32 DQMA#0 MDB18 N4 DQB0_17 WCKB0_0/DQMB_0 H1 DQMB#1
DQA0_17 WCKA0_0/DQMA_0 DQB0_18 WCKB0B_0/DQMB_1
1

MDA18 C26 C32 DQMA#1 MDB19 P6 T3 DQMB#2


R825 MDA19 A26 DQA0_18 WCKA0B_0/DQMA_1 D23 DQMA#2 MDB20 P5 DQB0_19 WCKB0_1/DQMB_2 T5 DQMB#3
MDA20 F24 DQA0_19 WCKA0_1/DQMA_2 E22 DQMA#3 MDB21 R4 DQB0_20 WCKB0B_1/DQMB_3 AE4 DQMB#4
40.2_0402_1% MDA21 C24 DQA0_20 WCKA0B_1/DQMA_3 C14 DQMA#4 MDB22 T6 DQB0_21 WCKB1_0/DQMB_4 AF5 DQMB#5
MARS@
15mil MDA22 A24 DQA0_21 WCKA1_0/DQMA_4 A14 DQMA#5 MDB23 T1 DQB0_22 WCKB1B_0/DQMB_5 AK6 DQMB#6 +1.5VSDGPU
2

MVREFDA MDA23 E24 DQA0_22 WCKA1B_0/DQMA_5 E10 DQMA#6 MDB24 U4 DQB0_23 WCKB1_1/DQMB_6 AK5 DQMB#7
MDA24 C22 DQA0_23 WCKA1_1/DQMA_6 D9 DQMA#7 MDB25 V6 DQB0_24 WCKB1B_1/DQMB_7
DQA0_24 WCKA1B_1/DQMA_7 DQB0_25
1

1 MARS@ MDA25 A22 MDB26 V1 F6 QSB0


DQA0_25 DQB0_26 EDCB0_0/QSB_0

1
1U_0402_6.3V6K
C850

R826 MDA26 F22 C34 QSA0 MDB27 V3 K3 QSB1


MDA27 D21 DQA0_26 EDCA0_0/QSA_0 D29 QSA1 MDB28 Y6 DQB0_27 EDCB0_1/QSB_1 P3 QSB2 R824
100_0402_1% MDA28 A20 DQA0_27 EDCA0_1/QSA_1 D25 QSA2 MDB29 Y1 DQB0_28 EDCB0_2/QSB_2 V5 QSB3 VGA@
MARS@ 2 MDA29 F20 DQA0_28 EDCA0_2/QSA_2 E20 QSA3 MDB30 Y3 DQB0_29 EDCB0_3/QSB_3 AB5 QSB4 40.2_0402_1% 15mil
2

MDA30 D19 DQA0_29 EDCA0_3/QSA_3 E16 QSA4 MDB31 Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB5

2
MDA31 E18 DQA0_30 EDCA1_0/QSA_4 E12 QSA5 MDB32 AA4 DQB0_31 EDCB1_1/QSB_5 AJ9 QSB6 MVREFDB
MDA32 C18 DQA0_31 EDCA1_1/QSA_5 J10 QSA6 MDB33 AB6 DQB1_0 EDCB1_2/QSB_6 AM5 QSB7
DQA1_0 EDCA1_2/QSA_6 DQB1_1 EDCB1_3/QSB_7

1
MDA33 A18 D7 QSA7 MDB34 AB1
DQA1_1 EDCA1_3/QSA_7 DQB1_2
1

MDA34 F18 MDB35 AB3 G7 QSB#0 1 VGA@


+1.5VSDGPU DQA1_2 DQB1_3 DDBIB0_0/QSB_0B

1U_0402_6.3V6K
C851
R900 MDA35 D17 A34 QSA#0 MDB36 AD6 K1 QSB#1 R827 VGA@
0_0402_5% MDA36 A16 DQA1_3 DDBIA0_0/QSA_0B E30 QSA#1 MDB37 AD1 DQB1_4 DDBIB0_1/QSB_1B P1 QSB#2 100_0402_1%
@ MDA37 F16 DQA1_4 DDBIA0_1/QSA_1B E26 QSA#2 MDB38 AD3 DQB1_5 DDBIB0_2/QSB_2B W4 QSB#3
2 2

2
MDA38 D15 DQA1_5 DDBIA0_2/QSA_2B C20 QSA#3 MDB39 AD5 DQB1_6 DDBIB0_3/QSB_3B AC4 QSB#4 2
2

DQA1_6 DDBIA0_3/QSA_3B DQB1_7 DDBIB1_0/QSB_4B


1

MDA39 E14 C16 QSA#4 MDB40 AF1 AH3 QSB#5


R828 MDA40 F14 DQA1_7 DDBIA1_0/QSA_4B C12 QSA#5 MDB41 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#6
MDA41 D13 DQA1_8 DDBIA1_1/QSA_5B J11 QSA#6 MDB42 AF6 DQB1_9 DDBIB1_2/QSB_6B AM3 QSB#7
DQA1_9 DDBIA1_2/QSA_6B DQB1_10 DDBIB1_3/QSB_7B

1
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 MDB43 AG4
MARS@ MDA43 A12 DQA1_10 DDBIA1_3/QSA_7B MDB44 AH5 DQB1_11 T7 ODTB0 R901
ODTB0 23
2

MVREFSA MDA44 D11 DQA1_11 J21 ODTA0 MDB45 AH6 DQB1_12 ADBIB0/ODTB0 W7 ODTB1 0_0402_5%
DQA1_12 ADBIA0/ODTA0 ODTA0 22 DQB1_13 ADBIB1/ODTB1 ODTB1 23 +1.5VSDGPU
MDA45 F10 G19 ODTA1 MDB46 AJ4 @
DQA1_13 ADBIA1/ODTA1 ODTA1 22 DQB1_14
1

1 MARS@ MDA46 A10 MDB47 AK3 L9 CLKB0


CLKB0 23

2
DQA1_14 DQB1_15 CLKB0
1U_0402_6.3V6K
C852

R830 MDA47 C10 H27 CLKA0 MDB48 AF8 L8 CLKB0#


DQA1_15 CLKA0 CLKA0 22 DQB1_16 CLKB0B CLKB0# 23
MDA48 G13 G27 CLKA0# MDB49 AF9
DQA1_16 CLKA0B CLKA0# 22 DQB1_17

1
100_0402_1% MDA49 H13 MDB50 AG8 AD8 CLKB1
2 DQA1_17 DQB1_18 CLKB1 CLKB1 23
MARS@ MDA50 J13 J14 CLKA1 MDB51 AG7 AD7 CLKB1# R829
CLKA1 22 CLKB1# 23
2

MDA51 H11 DQA1_18 CLKA1 H14 CLKA1# MDB52 AK9 DQB1_19 CLKB1B VGA@
DQA1_19 CLKA1B CLKA1# 22 DQB1_20
MDA52 G10 MDB53 AL7 T10 RASB0# 40.2_0402_1% 15mil
DQA1_20 DQB1_21 RASB0B RASB0# 23
MDA53 G8 K23 RASA0# MDB54 AM8 Y10 RASB1#
RASA0# 22 RASB1# 23

2
MDA54 K9 DQA1_21 RASA0B K19 RASA1# MDB55 AM7 DQB1_22 RASB1B MVREFSB
DQA1_22 RASA1B RASA1# 22 DQB1_23
MDA55 K10 MDB56 AK1 W10 CASB0#
DQA1_23 DQB1_24 CASB0B CASB0# 23

1
MDA56 G9 K20 CASA0# MDB57 AL4 AA10 CASB1# 1 VGA@
DQA1_24 CASA0B CASA0# 22 DQB1_25 CASB1B CASB1# 23

1U_0402_6.3V6K
C853
MDA57 A8 K17 CASA1# MDB58 AM6 R831
DQA1_25 CASA1B CASA1# 22 DQB1_26
MDA58 C8 MDB59 AM1 P10 CSB0# VGA@
DQA1_26 DQB1_27 CSB0B_0 CSB0# 23
MDA59 E8 K24 CSA0# MDB60 AN4 L10 100_0402_1%
DQA1_27 CSA0B_0 CSA0# 22 DQB1_28 CSB0B_1 2
MDA60 A6 K27 MDB61 AP3

2
MDA61 C6 DQA1_28 CSA0B_1 MDB62 AP1 DQB1_29 AD10 CSB1#
DQA1_29 DQB1_30 CSB1B_0 CSB1# 23
MDA62 E6 M13 CSA1# MDB63 AP5 AC10
DQA1_30 CSA1B_0 CSA1# 22 DQB1_31 CSB1B_1
MDA63 A5 K16
DQA1_31 CSA1B_1 U10 CKEB0
CKEB0 CKEB0 23
MVREFDA L18 K21 CKEA0 MVREFDB Y12 AA11 CKEB1
MVREFDA CKEA0 CKEA0 22 MVREFDB CKEB1 CKEB1 23
MVREFSA L20 J20 CKEA1 MVREFSB AA12
3 MVREFSA CKEA1 CKEA1 22 MVREFSB 3
N10 WEB0#
WEB0B WEB0# 23
L27 K26 WEA0# AB11 WEB1#
NC#L27 WEA0B WEA0# 22 WEB1B WEB1# 23
N12 L15 WEA1#
NC#N12 WEA1B WEA1# 22
AG12
NC#AG12 T8 MAB13
H23 MAA13 MAB0_8/MAB_13 W8 MAB14
R835 1 VGA@ 2 MEM_CALRP0 M27 MAA0_8/MAA_13 J19 MAA14 MAB1_8/MAB_14 U12 MAB15
120_0402_1% MEM_CALRP0 MAA1_8/MAA_14 M21 MAA15 MAB0_9/MAB_15 V12
M12 MAA0_9/MAA_15 M20 MAB1_9/RSVD
AH12 NC#M12 MAA1_9/RSVD AH11 1 2 1 2
NC#AH12 DRAM_RST VRAM_RST# 22,23
VGA@ VGA@
R838 R839

2
10_0402_5% 1 VGA@ 51.1_0402_1%
2160842006A0MARSXT_FCBGA962 VGA@ C854
@ R840 120P_0402_50V8
2160842006A0MARSXT_FCBGA962 4.99K_0402_1%
@ 2

1
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2

The suggested components are tested on the AMD


reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
4 4
the DRAM specification.

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date MARS-Pro_MEMORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
Date: Tuesday, March 26, 2013 Sheet 19 of 52
A B C D E
A B C D E

U51E
PART 5 0F 9

1.5A AC7
MEM I/O
AA31
+1.5VSDGPU
VGA@ @ VGA@ @ VGA@ AD11 VDDR1 NC#AA31 AA32
20mil
VDDR1 NC#AA32 +1.8VSDGPU

0.01U_0402_16V7K
C856

0.01U_0402_16V7K
C857

0.01U_0402_16V7K
C858

0.01U_0402_16V7K
C859

0.01U_0402_16V7K
C860
1 1 1 1 1 AF7 AA33 VGA@ @ @
AG10 VDDR1 NC#AA33 AA34
VDDR1 NC#AA34 1 1 1
NC For Mars

1U_0402_6.3V6K
C861

1U_0402_6.3V6K
C862

10U_0603_6.3V6M
C863
AJ7 W30
AK8 VDDR1 NC#W30 Y31
2 2 2 2 2 AL9 VDDR1 NC#Y31 V28
G11 VDDR1 NC_BIF_VDDC W29 2 2 2
G14 VDDR1 NC_BIF_VDDC AB37
100mA

PCIE
G17 VDDR1 PCIE_PVDD
G20 VDDR1 G30
1 1
VGA@ @ VGA@ @ VGA@ G23 VDDR1 PCIE_VDDC G31
VDDR1 PCIE_VDDC +0.95VSDGPU

0.1U_0402_16V4Z
C864

0.1U_0402_16V4Z
C865

0.1U_0402_16V4Z
C866

0.1U_0402_16V4Z
C867

0.1U_0402_16V4Z
C868
1 1 1 1 1 G26 H29 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
G29 VDDR1 PCIE_VDDC H30
VDDR1 PCIE_VDDC 2.5A 100mil 1 1 1 1 1 1

1U_0402_6.3V6K
C869

1U_0402_6.3V6K
C872

1U_0402_6.3V6K
C873

1U_0402_6.3V6K
C874

1U_0402_6.3V6K
C875

10U_0603_6.3V6M
C876
H10 J29
J7 VDDR1 PCIE_VDDC J30
2 2 2 2 2 J9 VDDR1 PCIE_VDDC L28
K11 VDDR1 PCIE_VDDC M28 2 2 2 2 2 2
K13 VDDR1 PCIE_VDDC N28
K8 VDDR1 PCIE_VDDC R28
L12 VDDR1 PCIE_VDDC T28
VGA@ VGA@ VGA@ @ @ VGA@ VGA@ VGA@ L16 VDDR1 PCIE_VDDC U28
VDDR1 PCIE_VDDC

2.2U_0402_6.3V6M
C880

2.2U_0402_6.3V6M
C881

2.2U_0402_6.3V6M
C882

2.2U_0402_6.3V6M
C883

2.2U_0402_6.3V6M
C884
1 1 1 1 1 1 1 1 L21
VDDR1

10U_0603_6.3V6M
C877

10U_0603_6.3V6M
C878

10U_0603_6.3V6M
C879
L23
L26 VDDR1 N27
L7 VDDR1 BACO BIF_VDDC T27
1.4A 60mil
2 2 2 2 2 2 2 2 VDDR1 BIF_VDDC +0.95VSDGPU
M11 VGA@ VGA@ VGA@
N11 VDDR1
VDDR1 1 1 1

1U_0402_6.3V6K
C890

1U_0402_6.3V6K
C889

10U_0603_6.3V6M
C888
P7 AA15 +VGA_CORE
R11 VDDR1 CORE VDDC AA17
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
30A (TBD) 2 2 2
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDR1 VDDC AB16
VDDC AB18
VDDC AB21
VDDC AB23
+VDDC_CT VDDC
20mil 13mA LEVEL VDDC
AB26 Must always be connected to PCIE_VDDC.
TRANSLATION AB28 0.95 V for "Mars" and
2 1 +VDDC_CT AF26 VDDC AC17
+1.8VSDGPU
L70 VGA@ VGA@ AF27 VDD_CT VDDC AC20 "Heathrow"/"Chelsea" on both BACO and
VDD_CT VDDC non-BACO designs.

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
BLM18AG121SN1D_2P 1 1 1 AG26 AC22
@ AG27 VDD_CT VDDC AC24
VGA@ VDD_CT VDDC

C885

C886

C887
AC27
2 VDDC AD18 2
2 2 2 10mil 25mA VDDC AD21
I/O
+VDDR3 AF23 VDDC AD23
AF24 VDDR3 VDDC AD26
AG23 VDDR3 VDDC AF17
2 1 AG24 VDDR3 VDDC AF20
+3VSDGPU VDDR3 VDDC
L71 @ VGA@ VGA@ AF22
VDDC

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z
BLM18AG121SN1D_2P 1 1 1 300mA DVP AG16
VDDC

C896

C897

C898
VGA@ AD12 AG18
AF11 VDDR4 VDDC
AF12 VDDR4 AH22
2 2 2 AF13 VDDR4 VDDC AH27
VDDR4 VDDC AH28
VDDC M26
AF15 VDDC N24
AG11 VDDR4 VDDC R18
20mil AG13 VDDR4 VDDC R21
2 1 +VDDR4 AG15 VDDR4 VDDC R23
+1.8VSDGPU VDDR4 VDDC
L72 MARS@ MARS@ R26
(SUN NC) VDDC
0.1U_0402_16V4Z

BLM18AG121SN1D_2P 1 1 1 T17
VDDC
10U_0603_6.3V6M
C907

1U_0402_6.3V6K
C908

C899

MARS@ @ T20
VDDC T22
VDDC T24
2 2 2 VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
3 3
VDDC Y21
VDDC Y23
VDDC Y26
VDDC Y28
VDDC
AA13 360mil
VDDCI AB13
VDDCI +VGA_CORE
AC12
VDDCI AC15 VGA@ VGA@ VGA@
VDDCI AD13
3.5A (DDR3)
VDDCI

0.1U_0402_16V4Z
C917

0.1U_0402_16V4Z
C918

0.1U_0402_16V4Z
C919
AD16 1 1 1
VDDCI M15
VDDCI M16
VDDCI M18
VOLTAGE VDDCI 2 2 2
ISOLATED

10mil M23
VDDCI
CORE I/O

SENESE N13
VCC_GPU_SENSE AF28 VDDCI N15
47 VCC_GPU_SENSE FB_VDDC VDDCI N17
VDDCI N20
AG28 VDDCI N22
T139 FB_VDDCI VDDCI R12
VDDCI R13
VSS_GPU_SENSE AH29 VDDCI R16
47 VSS_GPU_SENSE FB_GND VDDCI T12
VDDCI T15
VDDCI V15
VDDCI
1

Y13
@ VDDCI
R842
0_0402_5% 2160842006A0MARSXT_FCBGA962
@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2012/07/10 2013/07/10 Title
Issued Date Deciphered Date MARS-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
Date: Tuesday, March 26, 2013 Sheet 20 of 52
A B C D E
A B C D E

U51F
PART 6 0F 9

AB39 A3
E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
H34 PCIE_VSS GND AA26
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
1 J34 PCIE_VSS GND AB12 1
K31 PCIE_VSS GND AB15
K34 PCIE_VSS GND AB17
K39 PCIE_VSS GND AB20
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
P34 PCIE_VSS GND AC2
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
T34 PCIE_VSS GND AC28
T39 PCIE_VSS GND AC6 U51H
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17 PART 8 0F 9
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22 DP_VDDR DP_VDDC
W31 PCIE_VSS GND AD24 AP31
20mil
W34 PCIE_VSS GND AD27 DP_VDDC AP32
PCIE_VSS GND DP_VDDC +0.95VSDGPU
Y34 AD9 AN33
Y39 PCIE_VSS GND AE2 DP_VDDC AP33
PCIE_VSS GND AE6 AN24 DP_VDDC AL33
280mA
GND NC#AN24 DP_VDDC 1 VGA@ 1 VGA@ 1 VGA@

0.1U_0402_16V4Z
C927

1U_0402_6.3V6K
C928

10U_0603_6.3V6M
C929
AF10 AP24 AM33
GND AF16 AP25 NC#AP24 DP_VDDC AK33
GND AF18 AP26 NC#AP25 DP_VDDC AK34
GND AF21 AU28 NC#AP26 DP_VDDC AN31 2 2 2
GND GND NC#AU28 DP_VDDC
AG17 AV29
F15 GND AG2 NC#AV29
2 F17 GND GND AG20 2
F19 GND GND AP20 AP13
F21 GND AG6 AP21 NC#AP20 NC#AP13 AT13
F23 GND GND AG9 AP22 NC#AP21 NC#AT13 AP14
F25 GND GND AH21 AP23 NC#AP22 NC#AP14 AP15
F27 GND GND AJ10 AU18 NC#AP23 NC#AP15
F29 GND GND AJ11 AV19 NC#AU18
F31 GND GND AJ2 NC#AV19 DP GND
F33 GND GND AJ28 AN27
F7 GND GND AJ6 AH34 DP_VSSR AP27
F9 GND GND AK11 AJ34 DP_VDDR DP_VSSR AP28
G2 GND GND AK31 AF34 DP_VDDR DP_VSSR AW24
G6 GND GND AK7 AG34 DP_VDDR DP_VSSR AW26
H9 GND GND AL11 AM37 DP_VDDR DP_VSSR AN29
J2 GND GND AL14
237mA AL38 DP_VDDR DP_VSSR AP29
J27 GND GND AL17 AM32 DP_VDDR DP_VSSR AP30
GND GND +1.8VSDGPU DP_VDDR DP_VSSR
J6 AL2 @ VGA@ VGA@ AW30
GND GND DP_VSSR

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
J8 AL20 1 1 1 AW32
GND GND DP_VSSR

C936

C937

C938
K14 AN17
K7 GND AL23 DP_VSSR AP16
L11 GND GND AL26 DP_VSSR AP17
L17 GND GND AL32 2 2 2 DP_VSSR AW14
L2 GND GND AL6 DP_VSSR AW16
L22 GND GND AL8 DP_VSSR AN19
L24 GND GND AM11 DP_VSSR AP18
L6 GND GND AM31 DP_VSSR AP19
M17 GND GND AM9 DP_VSSR AW20
M22 GND GND AN11 CALIBRATION DP_VSSR AW22
M24 GND GND AN2 DP_VSSR AN34
N16 GND GND AN30 DP_VSSR AP39
N18 GND GND AN6 AW28 DP_VSSR AR39
N2 GND GND AN8 NC#AW28 DP_VSSR AU37
3 N21 GND GND AP11 DP_VSSR AF39 3
N23 GND GND AP7 DP_VSSR AH39
N26 GND GND AP9 AW18 DP_VSSR AK39
N6 GND GND AR5 NC#AW18 DP_VSSR AL34
R15 GND GND B11 R845 DP_VSSR AV27
R17 GND GND B13 150_0402_1% DP_VSSR AR28
R2 GND GND B15 2 MARS@ 1 AM39 DP_VSSR AV17
R20 GND GND B17 DP_CALR DP_VSSR AR18
R22 GND GND B19 DP_VSSR AN38
R24 GND GND B21 DP_VSSR AM35
R27 GND GND B23 DP_VSSR AN32
R6 GND GND B25 DP_VSSR
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9 2160842006A0MARSXT_FCBGA962
T26 GND GND C1 @
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND
U6 GND
V11 GND AG22
V16 GND NC#AG22
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39 Security Classification Compal Secret Data Compal Electronics, Inc.
GND VSS_MECH
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date MARS-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2160842006A0MARSXT_FCBGA962 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 21 of 52
A B C D E
A B C D E

U54 U55 U56 U57

VREFCA_A1 M8 E3 MDA23 VREFDA_Q1 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFDA_Q3 M8 E3 MDA48


VREFDA_Q1 H1 VREFCA DQL0 F7 MDA19 VREFCA_A1 H1 VREFCA DQL0 F7 MDA30 VREFDA_Q3 H1 VREFCA DQL0 F7 MDA32 VREFCA_A3 H1 VREFCA DQL0 F7 MDA51
VREFDQ DQL1 F2 MDA22 VREFDQ DQL1 F2 MDA24 VREFDQ DQL1 F2 MDA38 VREFDQ DQL1 F2 MDA55
MAA0 N3 DQL2 F8 MDA18 MAA0 N3 DQL2 F8 MDA29 MAA0 N3 DQL2 F8 MDA34 MAA0 N3 DQL2 F8 MDA54 X76
MAA1 P7 A0 DQL3 H3 MDA21 MAA1 P7 A0 DQL3 H3 MDA26 MAA1 P7 A0 DQL3 H3 MDA37 MAA1 P7 A0 DQL3 H3 MDA50 ZZZ1
MAA2 P3 A1 DQL4 H8 MDA16 MAA2 P3 A1 DQL4 H8 MDA31 MAA2 P3 A1 DQL4 H8 MDA36 MAA2 P3 A1 DQL4 H8 MDA52
MAA3 N2 A2 DQL5 G2 MDA20 MAA3 N2 A2 DQL5 G2 MDA27 MAA3 N2 A2 DQL5 G2 MDA39 MAA3 N2 A2 DQL5 G2 MDA49
MAA4 P8 A3 DQL6 H7 MDA17 MAA4 P8 A3 DQL6 H7 MDA28 MAA4 P8 A3 DQL6 H7 MDA33 MAA4 P8 A3 DQL6 H7 MDA53 X7601@
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
MAA[0..15] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA14 MAA7 R2 A6 D7 MDA43 MAA7 R2 A6 D7 MDA63
19 MAA[0..15] A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0 X76402BOL01
MAA8 T8 C3 MDA5 MAA8 T8 C3 MDA11 MAA8 T8 C3 MDA44 MAA8 T8 C3 MDA58 4Gbx8 Micron 256M16
MDA[0..63] MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA12 MAA9 R3 A8 DQU1 C8 MDA40 MAA9 R3 A8 DQU1 C8 MDA60
1 19 MDA[0..63] A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2 1
MAA10 L7 C2 MDA7 MAA10 L7 C2 MDA10 MAA10 L7 C2 MDA45 MAA10 L7 C2 MDA59
DQMA#[0..7] MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA42 MAA11 R7 A10/AP DQU3 A7 MDA61
19 DQMA#[0..7] A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
MAA12 N7 A2 MDA4 MAA12 N7 A2 MDA9 MAA12 N7 A2 MDA46 MAA12 N7 A2 MDA56 ZZZ3
QSA[0..7] MAA13 T3 A12 DQU5 B8 MDA2 MAA13 T3 A12 DQU5 B8 MDA15 MAA13 T3 A12 DQU5 B8 MDA41 MAA13 T3 A12 DQU5 B8 MDA62
19 QSA[0..7] A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
MAA14 T7 A3 MDA6 MAA14 T7 A3 MDA8 MAA14 T7 A3 MDA47 MAA14 T7 A3 MDA57
QSA#[0..7] MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 X7603@
19 QSA#[0..7] A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 X76402BOL03


19 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 2Gbx4 HYN 128M16
19 A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
19 A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1 ZZZ4
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9 CLKA1 J7 VDD N9 CLKA1 J7 VDD N9
CLKA0# K7 CK VDD R1 CLKA0# K7 CK VDD R1 CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
K9 CK VDD R9 CKEA0 K9 CK VDD R9 K9 CK VDD R9 CKEA1 K9 CK VDD R9 X7604@
19 CKEA0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU 19 CKEA1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU

ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1 ODTA1 K1 A1 X76402BOL04


19 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 19 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0# L2 A8 L2 A8 CSA1# L2 A8 2Gbx8 HYN 128M16
19 CSA0# CS/CS0 VDDQ CS/CS0 VDDQ 19 CSA1# CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
19 RASA0# RAS VDDQ RAS VDDQ 19 RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
19 CASA0# CAS VDDQ CAS VDDQ 19 CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
19 WEA0# WE VDDQ WE VDDQ 19 WEA1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 VDDQ H2 QSA3 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9


DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3
2 DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 2
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 VSS J2 QSA#3 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9
19,23 VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R846 L1 NC/ODT1 VSSQ B9 R847 L1 NC/ODT1 VSSQ B9 R848 L1 NC/ODT1 VSSQ B9 R849 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
1

1
R850 R851 R854 R855
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
3 128@ 128@ 128@ 128@ 3

15mil 15mil 15mil 15mil


2

2
VREFCA_A1 VREFDA_Q1 VREFCA_A3 VREFDA_Q3
1

1
1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R858 C939 R859 R862 C943 R863 C944
4.99K_0402_1% 4.99K_0402_1% C940 4.99K_0402_1% 4.99K_0402_1% 128@
128@ 128@ 128@ 128@ 128@ 128@ 128@
2 2 2 2
2

2
+1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU

128@ 128@ 128@ 128@ 128@


128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 1 1 1 1 1

1U_0402_6.3V6K
C962

1U_0402_6.3V6K
C963

1U_0402_6.3V6K
C964

1U_0402_6.3V6K
C965

1U_0402_6.3V6K
C966
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C947

1U_0402_6.3V6K
C948

1U_0402_6.3V6K
C949

1U_0402_6.3V6K
C950

1U_0402_6.3V6K
C951

1U_0402_6.3V6K
C952

1U_0402_6.3V6K
C953

1U_0402_6.3V6K
C954

1U_0402_6.3V6K
C955

1U_0402_6.3V6K
C956

1U_0402_6.3V6K
C957

1U_0402_6.3V6K
C958

1U_0402_6.3V6K
C959

1U_0402_6.3V6K
C960

1U_0402_6.3V6K
C961
128@
1 2
19 CLKA0 2 2 2 2 2
R866 40.2_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
128@
1 2
19 CLKA0#
R867 40.2_0402_1%
+1.5VSDGPU +1.5VSDGPU
1
+1.5VSDGPU +1.5VSDGPU
C395
0.01U_0402_16V7K 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
2 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
128@ 1 10U_0603_6.3V6M 1 1 1 1 1 1 1
C972

10U_0603_6.3V6M
C973

10U_0603_6.3V6M
C974

10U_0603_6.3V6M
C975

10U_0603_6.3V6M
C1029

10U_0603_6.3V6M
C1028

10U_0603_6.3V6M
C1027

10U_0603_6.3V6M
C1030
1 1 1 1 1 1 1 1
4 128@ 4
10U_0603_6.3V6M
C968

10U_0603_6.3V6M
C969

10U_0603_6.3V6M
C970

10U_0603_6.3V6M
C971

10U_0603_6.3V6M
C1024

10U_0603_6.3V6M
C1026

10U_0603_6.3V6M
C1023

10U_0603_6.3V6M
C1025

1 2
19 CLKA1 2 2 2 2 2 2 2 2
R868 40.2_0402_1%
2 2 2 2 2 2 2 2
128@
1 2
19 CLKA1#
R869 40.2_0402_1%
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C406 2012/07/10 2013/07/10 Title
Issued Date Deciphered Date
2
0.01U_0402_16V7K
128@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9531P Schematic 1.0

http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 22 of 52
A B C D E
A B C D E

U58 U59 U60 U61

VREFCB_A1 M8 E3 MDB31 VREFDB_Q1 M8 E3 MDB23 VREFCB_A3 M8 E3 MDB35 VREFDB_Q3 M8 E3 MDB55


VREFDB_Q1 H1 VREFCA DQL0 F7 MDB26 VREFCB_A1 H1 VREFCA DQL0 F7 MDB16 VREFDB_Q3 H1 VREFCA DQL0 F7 MDB37 VREFCB_A3 H1 VREFCA DQL0 F7 MDB49
VREFDQ DQL1 F2 MDB25 VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB34 VREFDQ DQL1 F2 MDB52
MAB0 N3 DQL2 F8 MDB29 MAB0 N3 DQL2 F8 MDB18 MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB50
MAB1 P7 A0 DQL3 H3 MDB28 MAB1 P7 A0 DQL3 H3 MDB21 MAB1 P7 A0 DQL3 H3 MDB33 MAB1 P7 A0 DQL3 H3 MDB53
MAB2 P3 A1 DQL4 H8 MDB30 MAB2 P3 A1 DQL4 H8 MDB19 MAB2 P3 A1 DQL4 H8 MDB38 MAB2 P3 A1 DQL4 H8 MDB48
MAB[0..15] MAB3 N2 A2 DQL5 G2 MDB24 MAB3 N2 A2 DQL5 G2 MDB20 MAB3 N2 A2 DQL5 G2 MDB32 MAB3 N2 A2 DQL5 G2 MDB54
19 MAB[0..15] A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
MAB4 P8 H7 MDB27 MAB4 P8 H7 MDB17 MAB4 P8 H7 MDB36 MAB4 P8 H7 MDB51
MDB[0..63] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
19 MDB[0..63] A5 A5 A5 A5
MAB6 R8 MAB6 R8 MAB6 R8 MAB6 R8
DQMB#[0..7] MAB7 R2 A6 D7 MDB12 MAB7 R2 A6 D7 MDB2 MAB7 R2 A6 D7 MDB46 MAB7 R2 A6 D7 MDB59
19 DQMB#[0..7] A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
MAB8 T8 C3 MDB11 MAB8 T8 C3 MDB4 MAB8 T8 C3 MDB43 MAB8 T8 C3 MDB62
QSB[0..7] MAB9 R3 A8 DQU1 C8 MDB15 MAB9 R3 A8 DQU1 C8 MDB0 MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB58
1 19 QSB[0..7] A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2 1
MAB10 L7 C2 MDB9 MAB10 L7 C2 MDB6 MAB10 L7 C2 MDB41 MAB10 L7 C2 MDB63
QSB#[0..7] MAB11 R7 A10/AP DQU3 A7 MDB13 MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB44 MAB11 R7 A10/AP DQU3 A7 MDB56
19 QSB#[0..7] A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB8 MAB12 N7 A2 MDB7 MAB12 N7 A2 MDB42 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB14 MAB13 T3 A12 DQU5 B8 MDB1 MAB13 T3 A12 DQU5 B8 MDB45 MAB13 T3 A12 DQU5 B8 MDB57
MAB14 T7 A13 DQU6 A3 MDB10 MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB40 MAB14 T7 A13 DQU6 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2


19 B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
19 B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
19 B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
CLKB0 J7 VDD N9 CLKB0 J7 VDD N9 CLKB1 J7 VDD N9 CLKB1 J7 VDD N9
CLKB0# K7 CK VDD R1 CLKB0# K7 CK VDD R1 CLKB1# K7 CK VDD R1 CLKB1# K7 CK VDD R1
K9 CK VDD R9 CKEB0 K9 CK VDD R9 K9 CK VDD R9 CKEB1 K9 CK VDD R9
19 CKEB0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU 19 CKEB1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU

ODTB0 K1 A1 ODTB0 K1 A1 ODTB1 K1 A1 ODTB1 K1 A1


19 ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 19 ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0# L2 A8 L2 A8 CSB1# L2 A8
19 CSB0# CS/CS0 VDDQ CS/CS0 VDDQ 19 CSB1# CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
19 RASB0# RAS VDDQ RAS VDDQ 19 RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
19 CASB0# CAS VDDQ CAS VDDQ 19 CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
19 WEB0# WE VDDQ WE VDDQ 19 WEB1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB1 C7 DQSL VDDQ H9 QSB0 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9


DQMB#1 D3 DML VSS B3 DQMB#0 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3
2 DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 2
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 VSS J2 QSB#2 G3 VSS J2 QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
QSB#1 B7 DQSL VSS J8 QSB#0 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9
19,22 VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R870 L1 NC/ODT1 VSSQ B9 R871 L1 NC/ODT1 VSSQ B9 R872 L1 NC/ODT1 VSSQ B9 R873 L1 NC/ODT1 VSSQ B9
VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU
1

1
R874 R875
4.99K_0402_1% 4.99K_0402_1% R878 R879
3 VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 3
VGA@ VGA@
2

2
VREFCB_A1 VREFDB_Q1
VREFCB_A3 VREFDB_Q3
1

1 1 +1.5VSDGPU

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

R882 C977 R883 C978 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.99K_0402_1% 4.99K_0402_1% R886 C981 R887 C982
VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@
2 2 VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1
2

2 2

1U_0402_6.3V6K
C1001

1U_0402_6.3V6K
C1002

1U_0402_6.3V6K
C1003

1U_0402_6.3V6K
C1004

1U_0402_6.3V6K
C1005
2

2
R890 40.2_0402_1% 2 2 2 2 2
1 VGA@ 2 +1.5VSDGPU +1.5VSDGPU
19 CLKB0
+1.5VSDGPU

R891 40.2_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 VGA@ 2 1 1 1 1 1 1 1 1 1 1 VGA@ VGA@ VGA@ VGA@ VGA@
19 CLKB0#
1U_0402_6.3V6K
C987

1U_0402_6.3V6K
C988

1U_0402_6.3V6K
C989

1U_0402_6.3V6K
C990

1U_0402_6.3V6K
C985

1U_0402_6.3V6K
C991

1U_0402_6.3V6K
C992

1U_0402_6.3V6K
C993

1U_0402_6.3V6K
C994

1U_0402_6.3V6K
C995

1 1 1 1 1

1U_0402_6.3V6K
C996

1U_0402_6.3V6K
C997

1U_0402_6.3V6K
C998

1U_0402_6.3V6K
C999

1U_0402_6.3V6K
C1000
1
C409 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU 2 2 2 2 2 +1.5VSDGPU
0.01U_0402_16V7K
2 +1.5VSDGPU
VGA@
R892
40.2_0402_1%
1 VGA@ 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 1 1 1
19 CLKB1
10U_0603_6.3V6M
C1009

10U_0603_6.3V6M
C1006

10U_0603_6.3V6M
C1007

10U_0603_6.3V6M
C1008

1 1 1 1 VGA@ VGA@ VGA@ VGA@

10U_0603_6.3V6M
C1038

10U_0603_6.3V6M
C1036

10U_0603_6.3V6M
C1035

10U_0603_6.3V6M
C1037
R893 VGA@ VGA@ VGA@ VGA@

10U_0603_6.3V6M
C1010

10U_0603_6.3V6M
C1011

10U_0603_6.3V6M
C1012

10U_0603_6.3V6M
C1013
40.2_0402_1%
1 VGA@ 2 +1.5VSDGPU 2 2 2 2 2 2 2 2
4 19 CLKB1# 2 2 2 2 4

1
C410 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C1031

10U_0603_6.3V6M
C1032

10U_0603_6.3V6M
C1033

10U_0603_6.3V6M
C1034

0.01U_0402_16V7K
2
VGA@
2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9531P Schematic 1.0

http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 23 of 52
A B C D E
5 4 3 2 1

+3VS_TL
+3VS +3VS_TL U50 TL@
TL@ 19 TXOUT_CLK+ TXOUT_CLK+ 25
TXEC+
30mil 30mil L63 2 1 DP_V33 40mil 3 DP_V33 TXEC-
20 TXOUT_CLK- TXOUT_CLK- 25
2 1 HCB2012KF-221T30_0805
R928 TL@ 0_0603_5% 60mil TL@ 60mil13 SWR_VDD TXE2+
21 TXOUT2+ TXOUT2+ 25
+1.2V_TL

Power
L73 2 1 SWR_VDD 18 22 TXOUT2-

LVDS
D PVCC TXE2- TXOUT2- 25 D
HCB2012KF-221T30_0805
TL@ L6 1 2 +1.2V_TL_OUT 60mil12 SWR_LX TXE1+
23 TXOUT1+ TXOUT1+ 25
4.7UH_PG031B-4R7MS_1.1A_20% 11 24 TXOUT1- TXOUT1- 25
27 SWR_VCCK TXE1-
+1.2V_TL VCCK
7 25 TXOUT0+ TXOUT0+ 25
DP_V12 TXE0+
60mil TXE0-
26 TXOUT0- TXOUT0- 25
Close to Pin3
DP_V33
2
RTD2132S
25 EDP_AUXP_C_TL AUX_P
10U_0603_6.3V6M
C1016

0.1U_0402_16V4Z
C1015

0.1U_0402_16V4Z
C983

DP-IN
1 14 R932 1 TL@ 2 0_0402_5%

GPIO
25 EDP_AUXN_C_TL AUX_N GPIO(PWM OUT) TL_INVT_PWM 25
1 1 1 15 R948 1 TL@ 2 0_0402_5%
GPIO(Panel_VCC) TL_ENVDD 25
5 16 R934 1 TL@ 2 0_0402_5%
25 EDP_TXP0_C_TL LANE0P GPIO(PWM IN) PCH_INV_PWM 25,8
6 17
25 EDP_TXN0_C_TL LANE0N GPIO(BL_EN) TL_BKOFF# 25
TL@

TL@

TL@

2 2 2
CSCL 9
CIICSCL1 LVDS MIICSCL1
29 I2CC_SCL I2CC_SCL 25
CSDA 10 28 I2CC_SDA
CIICSDA1 EDID MIICDA1 I2CC_SDA 25

Other
25 EDP_HPD 1 2 TL_HPD 32
HPD ROM MIICSCL0
31 MODE_CFG1
30 MODE_CFG0
R936 8 MIICSDA0
C DP_REXT C
1K_0402_5% 4 33
DP_GND GND

2
Close to L64 Close to Pin13 Close to P18 TL@
TL@
SWR_VDD R938 RTD2132R-CG_QFN32_5X5
12K_0402_1% Part Number = SA000069200 TL@ +3VS_TL
10U_0603_6.3V6M
C984

0.1U_0402_16V4Z
C1020

22U_0805_6.3V6M
C986

0.1U_0402_16V4Z
C1019

0.1U_0402_16V4Z
C1018

RP41

1
I2CC_SCL 1 8
1 1 1 1 1 use 2132S symbol I2CC_SDA 2 7
CSCL 3 6
TL@

TL@

TL@

TL@

TL@

CSDA 4 5
2 2 2 2 2
4.7K_8P4R_5%

Close to Close to Close to +3VS_TL


L6 Pin27 Pin7
+1.2V_TL +3VS_TL
10U_0603_6.3V6M
C1014

2
0.1U_0402_16V4Z
C1022

0.1U_0402_16V4Z
C1017

0.1U_0402_16V4Z
C1021

1 @
R943 R944
B 1 1 1 B
4.7K_0402_5% 4.7K_0402_5%
TL@

TL@
2
TL@

TL@

TL@

1
2 2 2 @

2
MODE_CFG0 Q53A
MODE_CFG1
CSDA 1 6
EC_SMB_DA2 18,34,7
2

@
R945 R946 DMN66D0LDW-7_SOT363-6 @

5
4.7K_0402_5% 4.7K_0402_5% Q53B
TL@
CSCL 4 3
EC_SMB_CK2 18,34,7
1

DMN66D0LDW-7_SOT363-6

MODE_CFG0(PIN30)
0 1
0 X EP MODE
MODE_CFG1(PIN31)
A
1 ROM ONLY MODE* EEPROM MODE A

Security Classification Compal Secret Data


Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132R
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9532P Schematic
Date: Tuesday, March 26, 2013 Sheet 24 of 52
5 4 3 2 1

http://sualaptop365.edu.vn
A B C D E

Place closed to JLVDS1


+LCDVDD
+3VS
LCD POWER CIRCUIT
1 1
C375 @ C419
+3VS +LCDVDD +INVPWR_B+ B+
1 U8 W=60mils W=60mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
1 2 2
5 OUT L11
W=60mils
IN HCB2012KF-221T30_0805
1 1
2 C368 2 1
GND
1U_0402_6.3V6K
C140

4 0.1U_0402_16V4Z XEMC@ EMC@


IN

1000P_0402_50V7K
C364
1 @ 1 1 XEMC@
3 C367 2 2 C365 SM01000EJ00 3000ma
EN 4.7U_0603_6.3V6K 68P_0402_50V8J
G5243T11U_SOT23-5
220ohm@100mhz
2 2 2 DCR 0.04
R947 1 @ 2 0_0402_5%
8 PCH_ENVDD

24 TL_ENVDD

+3VS
XEMC@

5
INVTPWM C549 1 2 220P_0402_50V7K
BKOFF# 2 XEMC@

P
+3VS +3VS 34 BKOFF# B
U20 @ 4 DISPOFF# C528 1 2 220P_0402_50V7K
M74VHC1GT125DF2G_SC70-5
24 TL_BKOFF#
TL_BKOFF# 1
A
Y
LCD/ LED PANEL Conn.

G
1 @ 2 1 5
OE Vcc
1
2 2
R362 U22 TL@

3
100K_0402_5% R401 NC7SZ08P5X_NL_SC70-5
2 1K_0402_5%
IN A @
@
R949 1 @ 2 0_0402_5% 1 R959 2
2

3 4 INVTPWM 100K_0402_5%
GND OUT Y R280 1 @ 2 10K_0402_5%
W=60mils JLVDS1
R951 1 TL@ 2 100K_0402_5% +INVPWR_B+ 1
R363 1 @ 2 0_0402_5% 2 1 41
24,8 PCH_INV_PWM 2 G1
3 42
3 G2
1

R404 1 @ 2 0_0402_5% W=60mils 4 43


4 EDP_DISP_UTIL 4 G3
R393 +LCDVDD 5 44
@ 10K_0402_5% 6 5 G4 45
24 TL_INVT_PWM 6 G5
+3VS 7 46
INVTPWM 8 7 G6
2

DISPOFF# 9 8
I2CC_SCL 10 9
24 I2CC_SCL 10
I2CC_SDA 11
24 I2CC_SDA 11
+5VS_TS 12
TXOUT0- 13 12

eDP 24 TXOUT0-
24 TXOUT0+
TXOUT0+
TS_EN_1
14
15
13
14
TXOUT1- 16 15
24 TXOUT1- 16
C372 1 2 EDP@ 0.1U_0402_16V7K EDP_TXN0_C TXOUT1+ 17
4 EDP_TXN0 24 TXOUT1+ 17
C371 1 2 EDP@ 0.1U_0402_16V7K EDP_TXP0_C TS_EN_2 18
4 EDP_TXP0 +5VS +5VS_TS 18
3 C377 1 2 TL@ 0.1U_0402_16V7K EDP_TXN0_C_TL EDP_TXN0_C_TL 24 TXOUT2- 19 3
24 TXOUT2- 19
C376 1 2 TL@ 0.1U_0402_16V7K EDP_TXP0_C_TL EDP_TXP0_C_TL 24 TXOUT2+ 20
24 TXOUT2+ 20
21
R81 TXOUT_CLK- 22 21
24 TXOUT_CLK- 22
C374 1 2 0.1U_0402_16V7K EDP_TXN1_C 0_0603_5% TXOUT_CLK+ 23
4 EDP_TXN1 24 TXOUT_CLK+ 23
C373 1 2 0.1U_0402_16V7K EDP_TXP1_C 1 TS@ 2 24
4 EDP_TXP1 24
EDP_TXN0_C 25
EDP_TXP0_C 26 25
+3VS 27 26
EDP@ EDP_TXN1_C 28 27
C369 1 2 0.1U_0402_16V7K EDP_AUXN_C R613 2 @ 1 100K_0402_1% EDP_TXP1_C 29 28
4 EDP_AUXN 29
4 EDP_AUXP C370 1 2 0.1U_0402_16V7K EDP_AUXP_C R614 2 @ 1 100K_0402_1% 30
EDP@ R414 1 TS@ 2 0_0402_5% TS_EN_1 EDP_AUXN_C 31 30
34 TS_EN 31
C388 1 2 TL@ 0.1U_0402_16V7K EDP_AUXN_C_TL 24 R424 1 @ 2 0_0402_5% EDP_AUXP_C 32
C389 1 2 TL@ 0.1U_0402_16V7K 33 32
EDP_AUXP_C_TL 24 33
R425 1 @ 2 0_0402_5% TS_EN_2 EDP_HPD 34
R426 1 TS@ 2 0_0402_5% USB20_P6 35 34
10 USB20_P6 35
Touch Screen 10 USB20_N6
USB20_N6 36
36
+3VS TS_INT_1 for TS one chip solution 37
+3VS 37
TS_INT_2 for TS two chip solution USB20_P7 38
+5VS 10 USB20_P7 38
For Camera 10 USB20_N7
USB20_N7 39
39
1

40
R383 40
10K_0402_5% Q13 ACES_50203-04001-001
2
G

@ L2N7002LT1G_SOT23-3 SP010014B00
@ CONN@
2

8 CPU_EDP_HPD 3 1 EDP_HPD EDP_HPD 24


4 4
S

1 @ 2
R406
0_0402_5% R364 Security Classification Compal Secret Data Compal Electronics, Inc.
100K_0402_5% 2012/07/10 2013/07/10 Title
Issued Date Deciphered Date
eDP Connector
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 25 of 52
A B C D E
A B C D E

RP17 SM070001310 400ma 90ohm@100mhz DCR 0.3


680_8P4R_5%
4 CPU_DP2_N1 C381 2 1 0.1U_0402_16V7K HDMI_TX1- 4 5 HDMI_CLK- R368 1 XEMC@ 2 0_0402_5% HDMI_R_CK-
4 CPU_DP2_P1 C382 2 1 0.1U_0402_16V7K HDMI_TX1+ 3 6
4 CPU_DP2_N0 C379 2 1 0.1U_0402_16V7K HDMI_TX2- 2 7 HDMI_CLK+ R369 1 XEMC@ 2 0_0402_5% HDMI_R_CK+
4 CPU_DP2_P0 C380 2 1 0.1U_0402_16V7K HDMI_TX2+ 1 8

HDMI_GND
4 CPU_DP2_N2 C383 2 1 0.1U_0402_16V7K HDMI_TX0- 4 5
4 CPU_DP2_P2 C384 2 1 0.1U_0402_16V7K HDMI_TX0+ 3 6 HDMI_TX0- R370 1 XEMC@ 2 0_0402_5% HDMI_R_D0-
+HDMI_5V_OUT C385 2 1 0.1U_0402_16V7K HDMI_CLK- 2 7
+5VS 4 CPU_DP2_N3
U3 4 CPU_DP2_P3 C386 2 1 0.1U_0402_16V7K HDMI_CLK+ 1 8 HDMI_TX0+ R371 1 XEMC@ 2 0_0402_5% HDMI_R_D0+
1
3
W=40mils RP18
1
OUT 680_8P4R_5%
1

3
1 HDMI_TX1- R372 1 XEMC@ 2 0_0402_5% HDMI_R_D1-
IN C378
1 1
2 0.1U_0402_16V4Z HDMI_TX1+ R373 1 XEMC@ 2 0_0402_5% HDMI_R_D1+
C398 C396 GND 2 EMC@ 5
+3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z Q14B
EMC@ 2 EMC@ 2 AP2330W-7_SC59-3 DMN66D0LDW-7_SOT363-6

4
HDMI_TX2- R374 1 XEMC@ 2 0_0402_5% HDMI_R_D2-

Reserved for ESD HDMI_TX2+ R375 1 XEMC@ 2 0_0402_5% HDMI_R_D2+


+3VS

+3VS

1
R376
1M_0402_5% Q14A

2
DMN66D0LDW-7_SOT363-6

2
8 CPU_HDMI_HPD 1 6 HDMI_HPD

1
1
R121 C387
2 100K_0402_5% 220P_0402_50V7K 2
2 EMC@

2
RP15
2.2K_0804_8P4R_5%
1 8 HDMI_SCLK
3
+HDMI_5V_OUT 2 7 HDMI_SDATA HDMI connector 3

3 6 DDI2_CTRL_CK JHDMI1
+3VS 4 5 DDI2_CTRL_DATA 32 HDMI_HPD HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
+3VS 14 SCL
13 Reserved
CEC

2
HDMI_R_CK- 12
Q15A 11 CK-
CK_shield
2

DMN66D0LDW-7_SOT363-6 HDMI_R_CK+ 10
HDMI_R_D0- 9 CK+
1 6 HDMI_SCLK 8 D0-
8 DDI2_CTRL_CK D0_shield
HDMI_R_D0+ 7
4 3 HDMI_SDATA D2 HDMI_R_D1- 6 D0+
8 DDI2_CTRL_DATA D1-
Q15B XEMC@ 5
DMN66D0LDW-7_SOT363-6 HDMI_R_D1+ 4 D1_shield 20
YSLC05CH_SOT23-3

1
HDMI_R_D2- 3 D1+ GND 21
5

2 D2- GND 22
+3VS D2_shield GND
Place closed to JHDMI1 HDMI_R_D2+ 1 23
D2+ GND
Reserved for ESD
ACON_HMR2U-AK120C
ZZZ CONN@
4 DC232002700 4

HDMI_ROYALTY Security Classification Compal Secret Data Compal Electronics, Inc.


ROYALTY HDMI W/LOGO+HDCP 2012/07/10 2013/07/10 Title
Issued Date Deciphered Date
RO0000003HM HDMI Conn
45@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
A
http://sualaptop365.edu.vn B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Date: Tuesday, March 26, 2013 Sheet
E
26 of 52
5 4 3 2 1

+1.8VS_6511 +1.8VS_RXVDD +1.8VS_6511 +1.8VS_DAC


+3VS_6511

L30 1 @ 2 0_0603_5% L48 1 @ 2 0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
10U_0603_6.3V6M

1U_0402_6.3V6K
0.1U_0402_16V4Z
1 1 1 1 1

C473 @

@
1 1

C476

C472

C579
@

C455

C457

C75
2 2 2 2 2
2 2

D +1.8VS_6511 +1.8VS_RXVCC D

R399 1 @ 2 0_0402_5% L47 1 @ 2 0_0603_5%


Can be remove after MP

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
ISPSCL_R
ISPSDA_R
+5VS
1 1

1
1
+3VS +HDMI_5V_OUT

@
22_0402_5%

C519

C498
R407
2

+3VS_6511 +1.8VS_RXVDD 2 2 +3VS


G

2.2K_0402_5%
R408
22_0402_5%

1
R240

2
2
8 CPU_DP_HPD 3 1 DP_HPD 4.7K_0402_5% R234 R230 R123
1 @ 2 4.7K_0402_5%
S

+3VS 4.7K_0402_5% 2.2K_0402_5%


1

R127
1 @ 2
Q24 R418 R241

2
2
L2N7002LT1G_SOT23-3 4.7K_0402_5% 4.7K_0402_5%
@ +3VS

55
56

16
46
54

17
15
49
52
U42 CRT_DATA_1 1 6
CRT_DATA 28
2

1.52mA C477

OVDD
OVDD
OVDD

IVDD
IVDD
IVDD
IVDD
DDCSDA
DDCSCL
DP_HPD 44 51 1 2 0.1U_0402_16V4Z
HPD MCUVDDH Q27A

5
4.2mA 100.5mA C496 1 2 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6
C68 2 1 0.1U_0402_16V7K CPU_DP1_C_P0 30 50 1 2 1 2 CRT_CLK_1 4 3 CRT_CLK 28
4 CPU_DP1_P0 RX0P MCUVDD
C69 2 1 0.1U_0402_16V7K CPU_DP1_C_N0 31 R133
4 CPU_DP1_N0 RX0N 4.7K_0402_5% C614
C70 2 1 0.1U_0402_16V7K CPU_DP1_C_P1 33 53 MCURSTN 0.1U_0402_16V4Z Q27B
4 CPU_DP1_P1 RX1P MCURSTN DMN66D0LDW-7_SOT363-6
C71 2 1 0.1U_0402_16V7K CPU_DP1_C_N1 34
4 CPU_DP1_N1 RX1N
32 @ T97 1 @ 2 R413 22_0402_5%
URDBG ISPSCL 28
+3VS R50 2 @ 1 1M_0402_5% 1 @ 2 R412 22_0402_5%
ISPSDA 28
R421 2 @ 1 100K_0402_5% C72 19 ISPSCL_R 1 2 R411 22_0402_5%
0.1U_0402_16V7K ISPSCL 20 ISPSDA_R 1 2 R410 22_0402_5%
C R400 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DP 24 ISPSDA C
8 DDI1_AUX_DP RXAUXP
R415 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DN 23 27 R397 2 1 22_0402_5% CRT_CLK_1
8 DDI1_AUX_DN RXAUXN VGADDCCLK CRT_CLK_1 28
C73 25 R398 2 1 22_0402_5% CRT_DATA_1 CRT_DATA_1 28
0.1U_0402_16V7K VGADDCSDA
+3VS R420 2 @ 1 100K_0402_5% DDI1_AUX_DP_R 22 1
DCAUXP VSYNC VSYNC 28
R51 2 @ 1 1M_0402_5% DDI1_AUX_DN_R 21 2
DCAUXN HSYNC HSYNC 28
R80
For EMI +3VS 0_0603_5%
45 1 @ 2 +3VS_6511
OSCOUT C35 EMC@
+1.8VS_RXVCC 35
AVCC
56.95mA 65.5mA VDDC 8 +1.8VS_DAC 470P_0402_50V7K

D
29 11 1 2 3 1
AVCC VDDC 14

IT6511FN VDDC Q25


DMG2301U-7_SOT23-3

G
2
+1.8VS_RXVCC 26
PVCC
41.6mA IOBN
13 R53 1 2 37.4_0402_1% R396
@
38 12 CRT_B 1K_0402_5%
PVCC IOBP CRT_B 28
6511_PWR_EN# 2@ 1
10 R76 1 2 37.4_0402_1%
IOGN 9 CRT_G
IOGP CRT_G 28 1

+1.8VS_RXVDD 28 47.3mA 7 R147 1 2 37.4_0402_1% C411


37 DVDD18 IORN 6 CRT_R
DVDD18 IORP CRT_R 28 0.1U_0402_16V7K
36 2
DVSS18 @

1
18
VGADETECT VGADETECT 28
3 R196 1 2 100_0402_1%
RSET
+1.8VS_RXVCC 39
ASPVCC
6.158mA

75_0402_1% 2

75_0402_1% 2

75_0402_1% 2
0.293mA 5 +1.8VS_DAC
VDDA

+3VS R134 1 @ 2 10K_0402_5% 42


B INT# 4 1 2 C500 B
COMP

R197

R199

R201
R193 1 2 10K_0402_5% 48 0.1U_0402_16V4Z
R194 1 2 10K_0402_5% 47 PCSDA
PCSCL
Note: need external PU to 2K ~ 10K XTALIN
41 XTALIN_6511
40 XTALOUT_6511 +3VS
6511_PWR_EN 43 XTALOUT
SYSRSTN
GND

2
@
R584
IT6511FN_QFN56_7X7 R419 100K_0402_5%
57

1M_0402_5%
XTALOUT_6511 XTALIN_6511

1
6511_PWR_EN#
38 6511_PWR_EN#
X4
27MHZ_10PF_X3G027000BA1H-U
Crystal
D

1
3 4
OUT GND 6511_PWR_EN 2
45 6511_PWR_EN
2 1 G
GND IN
18P_0402_50V8J

1 Q52 S

3
18P_0402_50V8J
1 L2N7002LT1G_SOT23-3
@
C65
2 C74
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ITE IT6511FN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0

http://sualaptop365.edu.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 27 of 52
5 4 3 2 1
A B C D E

W=40mils

1 1
+HDMI_5V_OUT
CRB1.0 use 47ohm@100Mhz Bead

L42 EMC@
27 ISPSDA
27 ISPSCL CRT Connector
BLM18BA470SN1D_2P
1 2 CRT_R_2 JCRT1
27 CRT_R
L45 EMC@ 6
BLM18BA470SN1D_2P 11
1 2 CRT_G_2 1
27 CRT_G
L46 EMC@ 7
BLM18BA470SN1D_2P 12
1 2 CRT_B_2 2
27 CRT_B
8

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
13
1 1 1 1 1 1 3
9

C648

C615

C611

C647

C618

C616
14
4
2 2 2 2 2 2 10 16
G
15 G 17
5

C-H_13-12201560CP
CONN@
DC060006E00
2 R175 2
+HDMI_5V_OUT 1 XEMC@ 2 0_0603_5% CRT_HSYNC_2
U24 @
1 5 0.1U_0402_16V4Z 2 1 C447 R180 CRT_CLK 27
R439 OE Vcc 1 XEMC@ 2 0_0603_5% CRT_VSYNC_2
CRT_DATA 27
0_0402_5% 1 1
2 @ 1 CRT_HSYNC 2 @ @
27 HSYNC IN A C448 C449
10P_0402_50V8J 10P_0402_50V8J
3 4 CRT_HSYNC_1 2 2
GND OUT Y VGADETECT 27

1
M74VHC1GT125DF2G_SC70-5 R312
0_0402_5%
R239 +HDMI_5V_OUT
@
0_0402_5% U23

2
2 @ 1 1 5
OE Vcc

2 @ 1 CRT_VSYNC 2
27 VSYNC IN A
R441
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y

M74VHC1GT125DF2G_SC70-5
3 3

+HDMI_5V_OUT
C451 @ +3VS
1 2 0.1U_0402_16V4Z
1 2
C452 @
0.1U_0402_16V4Z
1
2
7

U10
VCC_VIDEO
VCC_SYNC

VCC_DDC

3 CRT_R_2
HSYNC 13 VIDEO_1 4 CRT_G_2
VSYNC 15 SYNC_IN1 VIDEO_2 5 CRT_B_2
SYNC_IN2 VIDEO_3
CRT_CLK_1 10 14 CRT_HSYNC_1
27 CRT_CLK_1 DDC_IN1 SYNC_OUT1
27 CRT_DATA_1 CRT_DATA_1 11 16 CRT_VSYNC_1
DDC_IN2 SYNC_OUT2
9 CRT_CLK
1 2 8 DDC_OUT1 12 CRT_DATA
4 BYP DDC_OUT2 4
C454
0.1U_0402_16V4Z DDC_CLK/DAT reserved PU Resistor
GND

For contact discharge ESD +/-8kV CM2009-00QR_QSOP16


6

@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 28 of 52
A B C D E
5 4 3 2 1

+1.2V_LAN
+VDDO_CR
U48 R759 L74
+3VALW BLM31PG601SN1_2P +3V_LAN
4.7U_0603_6.3V6K

37 +LAN_BIASVDDH 0_0805_5%
BIASVDDH +3V_LAN
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 20 EMC@
VDDO_CR
C771

C772

C773

C774
@ @ EMC@ 1 @ 2 1 2 60mil
+1.2V_LAN

1U_0402_6.3V6K
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
1 1 35 17 +LAN_XTALVDDH 1 1 1
VDDC XTALVDDH

C820
C777

C803

C779

C780
61 DMG2301U-7_SOT23-3 @
2 2 2 2 VDDC

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
Q6

D
48 +LAN_AVDDH 3 1 1 1
2 2 AVDDH 2 2 2

C784
42 EMC@ @
+3V_LAN AVDDH

C783
7

G
1

2
56 VDDO C815 2 2
D 62 VDDO 0.1U_0402_16V4Z D
VDDO 49 LAN_MIDI3-
TRD3_N LAN_MIDI3- 30 2 R781
50 LAN_MIDI3+
TRD3_P LAN_MIDI3+ 30
10K_0402_5%
47 LAN_MIDI2- 1 2
TRD2_N LAN_MIDI2- 30 LAN_PWR_EN# 34
46 LAN_MIDI2+
TRD2_P LAN_MIDI2+ 30
1
+LAN_AVDDL 39 43 LAN_MIDI1- C792 20mil
AVDDL TRD1_N LAN_MIDI1- 30
45 44 LAN_MIDI1+ 0.1U_0402_16V4Z L56
AVDDL TRD1_P LAN_MIDI1+ 30
51 +LAN_XTALVDDH 1 1 2 +3V_LAN
AVDDL 41 LAN_MIDI0- 2 C785 BLM18AG601SN1D_2P
TRD0_N LAN_MIDI0- 30
+LAN_GPHYPLLVDDL 36 40 LAN_MIDI0+ 0.1U_0402_16V4Z
GPHY_PLLVDDL TRD0_P LAN_MIDI0+ 30
R02 modify for ESD +LAN_PCIEPLLVDD 32
20mil 2 L57
PCIE_PLLVDDL +LAN_BIASVDDH 1 2
1
29 C787 BLM18AG601SN1D_2P
C786 1 2 0.1U_0402_16V4Z PLT_RST_BUF# PCIE_PLLVDDL 65 0.1U_0402_16V4Z
EMC@ SO_LINKLED# LAN_LINK# 30
66 2
SCLK_SPD1000LED# 20mil L58
2 +LAN_AVDDH 1 2
SPD100LED#_SERIALDO BLM18AG601SN1D_2P
1 1
C789 C790
10 PCIE_PRX_DTX_P3 0.1U_0402_16V7K 1 2 C788 PCIE_PRX_C_DTX_P3 28 67 R760 2 @ 1 0_0402_5% @
0.1U_0402_16V7K 1 2 C791 PCIE_PRX_C_DTX_N3 27 PCIE_TXD_P TRAFFICLED#_SERIALDI LAN_ACTIVITY# 30 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 PCIE_PRX_DTX_N3 PCIE_TXD_N 2 2
33
10 PCIE_PTX_C_DRX_P3 PCIE_RXD_P
34 8 +VDDO_CR_R R761 1 @ 2 0_0603_5% +VDDO_CR +VDDO_CR
10 PCIE_PTX_C_DRX_N3 PCIE_RXD_N GPIO1_LR_OUT
5 5IN1_LED_R# R762 2 @ 1 0_0402_5%
R763 1 @ 2 0_0402_5% GPIO_0 5IN1_LED# 35
34 EC_PME#

+3V_LAN R764 1 2 4.7K_0402_5% 64 SPROM_DOUT


C SI_EEDATA 63 SPROM_CLK C
R765 1 @ 2 0_0402_5% LAN_PME# 3 CS#_EECLK
8 PCH_PCIE_WAKE# WAKE#
11
31,8 PLT_RST_BUF# PREST#
31
7 CLK_PCIE_LAN PCIE_REFCLK_P
30
7 CLK_PCIE_LAN# PCIE_REFCLK_N 1 CR_XD_WE#_SD_DETECT_R R767 2 @ 1 0_0402_5% CR_XD_WE#_SD_DETECT
SD_DETECT/XD_WE# CR_XD_WE#_SD_DETECT 30,32
68
CR_DATA0 R768 1 EMC@ 2 33_0402_5% CR_DATA0_R 25 SR_DISABLE/XD_DETECT#
30 CR_DATA0 CR_DATA0
CR_DATA1 R769 1 EMC@ 2 33_0402_5% CR_DATA1_R 24 59
30 CR_DATA1 CR_DATA1 MS_INS#/XD_CE#
CR_DATA2 R770 1 EMC@ 2 33_0402_5% CR_DATA2_R 23
30 CR_DATA2 CR_DATA2
CR_DATA3 R771 1 EMC@ 2 33_0402_5% CR_DATA3_R 22 9
30 CR_DATA3 CR_DATA3 GPIO2_MEDIA_SENSE/XD_RE#
52
53 CR_DATA4 57 CR_WP#_XD_WP#_R R772 2 @ 1 0_0402_5% CR_WP#_XD_WP#
54 CR_DATA5 CR_WP#/XD_WP# CR_WP#_XD_WP# 30
CR_DATA6
55
CR_DATA7 CR_LED_CR_BUS_PWR/XD_ALE
60 CR_PWR_EN_R R773 2 @ 1 0_0402_5% CR_PWR_EN
CR_PWR_EN 30 For EMI request
21 CR_CLK_XD_RY_BY#_R R774 1 EMC@ 2 56_0402_5%
CR_CLK/XD_RY_BY# CR_CLK_XD_RY_BY# 30
+3VS 26 CR_CMD_XD_CLE_R R775 1 2 22_0402_5%
CR_CMD_XD_CLE CR_CMD_XD_CLE 30
R776 1 2 1K_0402_5% 58
VMAIN_PRSNT
+3V_LAN
R777 1 2 4.7K_0402_5% 6
TEST1
1 2 10
40mil L59
R778 4.7K_0402_5% TEST2 16 +1.2V_LAN_OUT 1 2
40mil
SR_LX +1.2V_LAN
4.7UH_PG031B-4R7MS_1.1A_20%
4 13 1 1
LOW_PWR SR_VFB
EMI Request...2010/07/27
C793 C794
B LAN_XTALO_R 19 0.1U_0402_16V4Z 10U_0603_6.3V6M B
LAN_XTALI 18 XTALO 2 2
XTALI SM010005500 500ma 600ohm@100mhz DCR 0.38
R02 Modify
20mil L60
Reserved for leakage current 15
40mil +LAN_PCIEPLLVDD 1 2
GND PLANE

SR_VDDP +3V_LAN +1.2V_LAN


15mil38 14 BLM18AG601SN1D_2P
1 2 LAN_RDAC SR_VDD
RDAC 1 0.1U_0402_16V4Z 1 4.7U_0603_6.3V6K 1 1
R780 1.24K_0402_1% C795 C796 C797 C798
2 @ 1 12
7 LAN_CLKREQ# CLK_REQ# 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
R896 BCM57786XA1KMLG_QFN68_8X8 2 2 2 2
69

0_0402_5%
PLACE NEXT P14
20mil L61
+LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
+3V_LAN BLM18AG601SN1D_2P
1 1
C801 C802
2

1K_0402_5%

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
R783

LAN_XTALI
LAN_XTALO_R
1

20mil
1

R779 SPROM_CLK L62


Y6 200_0402_1% SPROM_DOUT +LAN_AVDDL 1 2 +1.2V_LAN
25MHZ 10PF X3G025000DA1H-X BLM18AG601SN1D_2P
2

1K_0402_5%

1 1
2

R784

C804 C805
1 3LAN_XTALO SPROM_CLK SPROM_DOUT
1 3 (EECLK) (EEDATA) 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
A GND GND 2 2 A
1 1
1

On chip 1 0
C799 2 4 C800
15P_0402_50V8J 15P_0402_50V8J
2 2 AT24C02 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM57786X
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9531P Schematic 1.0

http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 29 of 52
5 4 3 2 1
5 4 3 2 1

+3V_LAN

T1

1
1 24 R786 R787

D
29 LAN_MIDI3+
29 LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI3-
2
3
TCT1
TD1+
MCT1
MX1+
23
22
RJ45_MIDI3+
RJ45_MIDI3-
LAN Connector 1K_0402_5% 1K_0402_5%
D
TD1- MX1-

2
4 21
LAN_MIDI2- 5 TCT2 MCT2 20 RJ45_MIDI2- C806 1 2 220P_0402_50V7K
29 LAN_MIDI2- TD2+ MX2+
29 LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+ XEMC@
TD2- MX2- C807 1 2 220P_0402_50V7K
7 18 JRJ45 XEMC@
LAN_MIDI1+ 8 TCT3 MCT3 17 RJ45_MIDI1+ RJ45_MIDI0+ 1
29 LAN_MIDI1+ TD3+ MX3+ PR1+
29 LAN_MIDI1- LAN_MIDI1- 9 16 RJ45_MIDI1- 9 LAN_ACTIVITY#
TD3- MX3- RJ45_MIDI0- 2 LED_YELLOW_A1 LAN_ACTIVITY# 29
10 15 PR1- 10 C808 1 2 68P_0402_50V8J
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- RJ45_MIDI1+ 3 LED_YELLOW_A2 XEMC@
29 LAN_MIDI0- TD4+ MX4+ PR2+
29 LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+
TD4- MX4- RJ45_MIDI2+ 4
PR3+ 11 LAN_LINK#
LED_GREEN_B1 LAN_LINK# 29

75_0402_1%

75_0402_1%
RJ45_MIDI2- 5
PR3-

1
GST5009-E 12 C809 1 2 68P_0402_50V8J
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
SP050006B10 RJ45_MIDI1- 6 LED_GREEN_B2 XEMC@
PR2-

R788

R789
1 1 1 1
C810

C811

C812

C813
RJ45_MIDI3+ 7 13
PR4+ GND

75_0402_1%

75_0402_1%
14

2
GND

1
RJ45_MIDI3- 8 40mil
2 2 2 2 PR4-

R790

R791
SANTA_130451-F
CARD READER_2in1 SP07000TF00 CONN@
DC234005300

2
RJ45_GND

C
Place close to TCT pin C

BOTHHAND: S X'FORM_ GST5009-E LF LAN, SP050006B10


TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 JP1 XEMC@
MHPC:S X'FORM_ NS892403 LAN , SP050008500 B88069X9231T203_4P5X3P2-2
2 1

RJ45_GND C814 1 2 LANGND


EMC@

B88069X9231T203_4P5X3P2-2
10P_0402_50V8J

XEMC@
J15

1
40mil JUMP_43X118

D39 EMC@
L30ESDL5V0C3-2
@

2
Card Reader Connector

JP2
2
+XDPWR_SDPWR_MSPWR

1
JREAD1

CR_CMD_XD_CLE 3
B 29 CR_CMD_XD_CLE CMD B
4
5 VSS
R897 2 EMC@ 1 CR_CLK 6 VDD
29 CR_CLK_XD_RY_BY# CLK +XDPWR_SDPWR_MSPWR
For EMI change to 22 ohm Bead BLM15BA220SN1D_0402 7
VSS L75
SM01000LU00 300ma 22ohm@100mhz DCR 0.3 CR_DATA0 8 +3VALW BLM31PG601SN1_2P
29 CR_DATA0
CR_DATA1 9 DAT0 EMC@
40mil
29 CR_DATA1 DAT1

D
CR_DATA2 1 3 1 1 2
29 CR_DATA2 DAT2
CR_DATA3 2
29 CR_DATA3 CD/DAT3

1
1 EMC@

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1

1U_0402_6.3V6K
C821

C817

C818

C819
R793 Q9 @ @

G
2
CR_WP#_XD_WP# 10 10K_0402_5% DMG2301U-7_SOT23-3
29 CR_WP#_XD_WP# WP SW
CR_XD_WE#_SD_DETECT 11 R782
29,32 CR_XD_WE#_SD_DETECT CD SW 2 2 2 2
12 10K_0402_5%

2
13 GND SW 1 2
GND SW Q23
L2N7002LT1G_SOT23-3 D

1
1
T-SOL_156-1000302601_NR 2
29 CR_PWR_EN
G

C822
CONN@

0.1U_0402_16V4Z
SP07000TF00 S

3
2

C26
R26
CR_CLK 1 XEMC@ 2 1 2
XEMC@
22_0402_5%
6.8P_0402_50V8C
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 30 of 52
5 4 3 2 1
A B C D E

For Wireless LAN


+1.5VS J13 +1.5VS_WLAN
+3VS 60mil +3VS_WLAN JUMP_43X39
@ J3 1 2
1 2 1 2
1 1 1 @ 1
JUMP_43X118 C458 C459 C460 @ C463
@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2 2 2 2

1 1
+3VS_WLAN
Mini Card Power Rating
+3VS_WLAN
+1.5VS_WLAN
R429 1 2 4.7K_0402_5%
JMINI1
WLAN_PME# 1 2
34 WLAN_PME# 1 2
R423 3 4
0_0402_5% 5 3 4 6
+3VS_WLAN 1 @ 2 7 5 6 8
+3VALW 7,8 MINI1_CLKREQ# 7 8
9 10
U9 11 9 10 12
1
W=60mils 7 CLK_PCIE_MINI1#
13 11 12 14
OUT 7 CLK_PCIE_MINI1 13 14
5 15 16
IOAC@ IN 17 15 16 18
2 19 17 18 20 WL_OFF#
GND 19 20 WL_OFF# 34
1U_0402_6.3V6K
C165

4 21 22 PLT_RST_BUF#
IN 21 22 PLT_RST_BUF# 29,8
1 10 PCIE_PRX_DTX_N4 23 24
3 25 23 24 26
EN 10 PCIE_PRX_DTX_P4 25 26
27 28
G5243T11U_SOT23-5 29 27 28 30 MINI1_SMBCLK R432 1 @ 2 0_0402_5%
2 29 30 PCH_SMBCLK 7
IOAC@ 31 32 MINI1_SMBDATA R434 1 @ 2 0_0402_5% PCH_SMBDATA 7
10 PCIE_PTX_C_DRX_N4 31 32
33 34
10 PCIE_PTX_C_DRX_P4 33 34
35 36
34 WLAN_ON 35 36 USB20_N4 10
37 38
37 38 USB20_P4 10
39 40
41 39 40 42 R443 1 2 100K_0402_5%
+3VS_WLAN 41 42 +3VS_WLAN
43 44 MINI1_LED# 34
2 R435 45 43 44 46 2
0_0402_5% 47 45 46 48
1 @ 2 E51TXD_P80DATA_R 49 47 48 50
34 E51TXD_P80DATA 49 50
1 @ 2 E51RXD_P80CLK_R 51 52
34 E51RXD_P80CLK 51 52

1
R436 53 54
0_0402_5% GNDGND
R437 R438 BELLW_80053-1021
100K_0402_5% 1K_0402_5% CONN@
@ DC040009P00

2
D

1
2 Q20
34 BT_ON#
G L2N7002LT1G_SOT23-3
S @

3
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 31 of 52
A B C D E
A B C D E

SATA HDD1 Conn.


CL 4.0 mm
JHDD2 SATA HDD1 Conn.
1 1
1 JHDD1
C534 1 2 BA51@ 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 1
6 SATA_PTX_DRX_P0 2
6 SATA_PTX_DRX_N0 C535 1 2 BA51@ 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 1
4 3 SATA_PTX_DRX_P0 EA50@ C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0_1 2 GND
C536 1 2 BA51@ 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 4 SATA_PTX_DRX_N0 EA50@ C393 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0_1 3 A+
6 SATA_PRX_DTX_N0 C537 1 2 BA51@ 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 5 4 A-
6 SATA_PRX_DTX_P0 7 6 SATA_PRX_DTX_N0 EA50@ C391 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0_1 5 GND
8 7 SATA_PRX_DTX_P0 EA50@ C394 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0_1 6 B-
+3VS 8 B+
9 7
10 9 GND
11 10
12 11 R308 8
12 +3VS V33
13 0_0402_5% 9
14 13 1 @ 2 +3VS_HDD 10 V33
+5VS 14 V33
15 11
16 15 R307 1 @ 2 0_0402_5% 12 GND
16 8,9 DEVSLP0 GND
17 13
18 17 R49 1 @ 2 0_0805_5% +5VS_HDD 14 GND
18 +5VS V5
19 15
20 19 16 V5
21 20 17 V5
22 G1 18 GND
23 G2 19 Reserved 23
24 G3 +3VS +5VS 20 GND GND 24
G4 21 V12 GND 25
ACES_50406-02071-001 22 V12 GND 26
CONN@
100mils V12 GND

10U_0603_6.3V6M
C420

0.1U_0402_16V4Z
C397
2 1 1 CCM_C127043HR022M27FZR_22P-T 2

1
0.1U_0402_16V4Z
C390
@
CONN@

DC231211190

2
2 2

Debug Board
JDB1
1 2
7 PCH_SPI_CS0#_1_R
3
5
1
3
2
4
4
6
PCH_SPI_CLK_1_R 7
PCH_SPI_MOSI_1_R 7 SATA ODD Conn.
7 PCH_SPI_MISO_1_R 5 6 +BIOS_SPI
7 8 JODD1
7 SPI_HOLD1#_R 7 8
9 10
34 EC_SPICLK 9 10 EC_SPICS#/FSEL#_R 34
11 12 EC_SI_SPI_SO_R1 34 1
34 EC_SO_SPI_SI_R1 11 12 GND
+EC_SPI 13 14 6 SATA_PTX_DRX_P1 C401 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2
13 14 EC_RST# 34,35 A+
15 16 6 SATA_PTX_DRX_N1 C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
17 15 16 18 4 A-
19 17 18 20 C403 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND
29,30 CR_XD_WE#_SD_DETECT 19 20 6 SATA_PRX_DTX_N1 B-
21 22 C405 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6
3 21 22 ON/OFFBTN# 33,35 6 SATA_PRX_DTX_P1 B+ 3
23 24 7
25 23 24 26 GND
27 25 26 28 +5VS R593
29 27 28 30 0_0805_5% 8
31 29 30 32
REC_MODE_L 34
1 @ 2
80mils +5VS_ODD 9 DP
31 32 EC UART_RXD 34 +5V

10U_0603_6.3V6M
C404

0.1U_0402_16V4Z
C407
33 34 +3VALW_EC 1 10
34 EC UART_TXD 33 34 +5V

1
35 36 ODD_MD 11
37 35 36 38 12 MD 14
39 37 38 40 T185 @ 13 GND GND 15
26 HDMI_HPD SPI_WP1#_R 34,6,7

2
41 39 40 42 2 GND GND
43 41 42 44
43 44 LID_SW# 33,34
45 46 SANTA_201902-1_13P-T
8 XDP_DBRESET# 45 46 KSI2 34,35
47 48 CONN@
34,35 KSI0 47 48 KSO3 34,35
49 50
34,35 KSO2 49 50 KSO4 34,35 LTCX004HZ00
51 52
G1 G2
E&T_1001K-F50C-05R
CONN@

Ctrl (L, 58) C03, R04 (KSI2, KSO3)


Ctrl (R, 64) C01, R04 (KSI0, KSO3)
D (33) C01, R03 (KSI0, KSO2)
F3 (114)
Enter (43)
C03,
C01,
R03
R05
(KSI2,
(KSI0,
KSO2)
KSO4)
Kill SW
4
Space (61) C03, R05 (KSI2, KSO4) 4

SPI_WP1#_R 34,6,7

R569
1K_0402_1% JP5
1 940@ 2 1
1 G1
3 Security Classification Compal Secret Data Compal Electronics, Inc.
2 4 2012/07/10 2013/07/10 Title
+3VALW 2 G2 Issued Date Deciphered Date
ACES_87212-02G0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/Debug Board
CONN@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 32 of 52
A B C D E
A B C D E

For ESD request +5VALW +USB3_VCCA

D15 U25
L24 XEMC@ C483 EMC@ W=60mils
10 PCH_USB3_TX0_P 2 1 PCH_USB3_TX0_P_C 2 1 U3TXDP0 U3RXDN0 1 1 109 U3RXDN0 0.1U_0402_16V4Z 1 8
C484 0.1U_0402_16V7K 2 1 1 2 2 GND OUT 7 R454
U3RXDP0 2 2 98 U3RXDP0 3 IN OUT 6 0_0402_5%
2 1 PCH_USB3_TX0_N_C 3 4 U3TXDN0 4 IN OUT 5 1 @ 2
10 PCH_USB3_TX0_N 3 4 34 USB_CHARGE_2A# EN/ENB OCB USB_OC0# 10,9
C482 0.1U_0402_16V7K U3TXDN0 4 4 77 U3TXDN0
DLW21SN900HQ2L-0805_4P SY6288D10CAC_MSOP8
EMC@ U3TXDP0 5 5 66 U3TXDP0

3 3
L25
1 PCH_USB3_RX0_P 2 1 U3RXDP0 8 1
10 PCH_USB3_RX0_P 2 1
L05ESDL5V0NA-4 SLP2510P8
PCH_USB3_RX0_N 3 4 U3RXDN0
10 PCH_USB3_RX0_N 3 4 +USB3_VCCA
DLW21SN900HQ2L-0805_4P
EMC@ W=100mils SF000002Y00
EMC@
R458 1 @ 2 0_0402_5% 1 1 220U 6.3V OSCON
R461 1 @ 2 0_0402_5% C487
+ ESR 17mohm@100Khz

0.1U_0402_16V4Z
L26 C486
USB20_P0 3 4 U2DP0_L
10 USB20_P0 3 4 2
220U_6.3V_M

USB20_N0 2 1 U2DN0_L
2
USB3.0 Conn.
10 USB20_N0 2 1
WCM2012F2SF-670T04_0805 JUSB1
XEMC@ 1
U2DN0_L 2 VBUS
U2DP0_L 3 D-
4 D+
U3RXDN0 5 GND
U3RXDP0 6 StdA-SSRX- 10
7 StdA-SSRX+ GND 11
U3TXDN0 8 GND-DRAIN GND 12
U3TXDP0 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
OCTEK_USB-09EAAB
CONN@
2 DC233008O20 2

3 3

USB/B
(USB Port 1, Port2)
+5VALW
PWR/B Finger Print /B 1
JUSB2

JPWR1 2 1
1 +3VS 3 2
1 +3VALW 3
2 +3VLP JFP1 4
2 3 LID_SW# 4 6 USB_EN# 5 4
3 LID_SW# 32,34 4 G2 34 USB_EN# 5
4 PWR_LED# PWR_LED# 35 USB20_P5 3 5 6
4 10 USB20_P5 3 G1 6
5 ON/OFFBTN# ON/OFFBTN# 32,35 USB20_N5 2 USB20_N1 7
5 10 USB20_N5 2 10 USB20_N1 7
6 1 USB20_P1 8
6 1 10 USB20_P1 8
9
9
2

7 ACES_50504-0040N-001 USB20_N2 10
GND 10 USB20_N2 10
8 CONN@ USB20_P2 11
GND 10 USB20_P2 11
SP01000Z300 12
ACES_88514-00601-071 13 12
CONN@ D38 14 13
YSLC05CH_SOT23-3 14
SP010014M00
XEMC@ ACES_88514-01201-071
CONN@
SP01001BF00
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB_B/PWR_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 33 of 52
A B C D E
A B C D E

C501 +3VALW R24 +3VALW_EC L31 SM010030010 200ma 120ohm@100mhz DCR 0.2 +3VALW_EC
22P_0402_50V8J 0_0805_5% BLM18AG121SN1D_2P
2 1 2 XEMC@ 1 CLK_PCI_LPC 1 @ 2 1 2 +EC_VCCA +EC_VCCA LID_SW# R476 1 2 100K_0402_5%
XEMC@ R477 33_0402_5% XEMC@ XEMC@ 1
+3VLP
1 1 1 1 2 2

0.1U_0402_16V4Z
C502

0.1U_0402_16V4Z
C503

0.1U_0402_16V4Z
C504

0.1U_0402_16V4Z
C505

1000P_0402_50V7K
C506

1000P_0402_50V7K
C507
@ @ +EC_VCC C508
1 @ 2 0.1U_0402_16V4Z
2

ECAGND
+3VALW_EC R485 1 9012@ 2 4.7K_0402_5% +5VS
R480 2 1 47K_0402_5% EC_RST#_R R236 2 2 2 2 1 1 R483 1 9012@ 2 4.7K_0402_5%
0_0805_5%
C509 2 1 0.1U_0402_16V4Z
ECAGND 40

111
125
TP_CLK R478 1 940@ 2 4.7K_0402_5%

22
33
96

67
U28 +3VS

9
TP_DATA R479 1 940@ 2 4.7K_0402_5%
1 2

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
32,35 EC_RST#
R591 DEG@ 0_0402_5% EC_MUTE# R481 1 @ 2 10K_0402_5%
1 1

KBL_EN# 1 21 BT_ON# EC_ENTERING_RW R588 1 @ 2 10K_0402_5%


+3VALW_EC 35 KBL_EN# GATEA20/GPIO00 GPIO0F BT_ON# 31
EC_KBRST# 2 23 BEEP#
9 EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 36
SERIRQ 3 26 USB_EN#
35,9 SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 USB_EN# 33 R482
35,7 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
R484 1 @ 2 100K_0402_5% EC_PME# LPC_AD3 5 0_0402_5%
35,7 LPC_AD3 LPC_AD3
PU at LAN side 35,7 LPC_AD2
LPC_AD2 7 PWM Output C510 2 1 100P_0402_50V8J ECAGND
46 VR_HOT#
2 @ 1 H_PROCHOT# 39,4,40
LPC_AD1 8 LPC_AD2 63 BATT_TEMP
35,7 LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP 39,40
LPC_AD0 10 LPC & MISC 64
35,7 LPC_AD0 LPC_AD0 GPIO39 65 ADP_I
ADP_I/GPIO3A ADP_I 40,41 D

1
+3VALW_EC RP12 CLK_PCI_LPC 12 66 AD_BID0
7 CLK_PCI_LPC CLK_PCI_EC AD Input GPIO3B
PLT_RST# 13 75 H_PROCHOT#_EC 2 Q50
35,8 PLT_RST# PCIRST#/GPIO05 GPIO42
1 8 EC_SMB_DA1 EC_RST#_R 37 76 EC_PME# G L2N7002LT1G_SOT23-3
EC_RST# IMON/GPIO43 EC_PME# 29
2 7 EC_SMB_CK1 EC_SCI# 20 S
6,9 EC_SCI#

3
3 6 EC_SMB_CK2 WLAN_ON 38 EC_SCII#/GPIO0E
4 5 EC_SMB_DA2
31 WLAN_ON GPIO1D 68
Latest design guide suggest change to
+3VS DAC_BRIG/GPIO3C 70 EN_DFAN1
EN_DFAN1 37
74LVC1G06.
2.2K_0804_8P4R_5% EN_DFAN1/GPIO3D 71
DA Output IREF/GPIO3E
KSI0 55 72
+3VS KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F
KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
R488 1 @ 2 10K_0402_5% EC_SMI# KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 LAN_PWR_EN# EC_MUTE# 36
KSI4/GPIO34 USB_EN#/GPIO4B LAN_PWR_EN# 29
R492 1 @ 2 10K_0402_5% EC_SCI# KSI5 60 85 WLAN_PME#
KSI5/GPIO35 CAP_INT#/GPIO4C WLAN_PME# 31
KSI6 61 PS2 Interface 86 EC_ENTERING_RW
KSI6/GPIO36 EAPD/GPIO4D EC_ENTERING_RW 35
C511 1 2 0.01U_0402_16V7K PLT_RST# KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 35
XEMC@ KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 35
KSO1 40
KSO1/GPIO21
ESD request KSI[0..7]
KSO2 41
KSO2/GPIO22
R509 1 @ 2 0_0402_5% ACIN 39,41,8
KSO3 42 97 VGATE_3V
32,35 KSI[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE_3V 8
2 KSO4 43 98 USB_CHARGE_2A# 2
KSO[0..17] KSO4/GPIO24 WOL_EN/GPXIOA01 USB_CHARGE_2A# 33
KSO5 44 99 HDA_SDO EC_ACIN C512 2 1 100P_0402_50V8J
X1 @
32,35 KSO[0..17]
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 VCIN0_PH_R
HDA_SDO 6
32.768KHZ_12.5PF_FC-135 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00
KSO7/GPIO27 SPI Device Interface
EC_XCLK1 2 1 EC_XCLK0 KSO8 47
KSO9 48 KSO8/GPIO28 119 EC_SI_SPI_SO 1 R158 2 940@ 49.9_0402_1% EC_SI_SPI_SO_R
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SO_SPI_SI 1 R159 2 940@ 49.9_0402_1% EC_SO_SPI_SI_R
1 1
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPICLK_R 1 R160 2 940@ 49.9_0402_1% EC_SPICLK
KB930&9012 Co-Layout Item
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SPICLK 32
C513 C514 KSO12 51 128 EC_SPICS#/FSEL# 1 R146 2 49.9_0402_1% EC_SPICS#/FSEL#_R
@ 15P_0402_50V8J 15P_0402_50V8J @ KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A 940@ +EC_VCC 1 @ 2
2 2 KSO13/GPIO2D +3VALW
KSO14 53 R691 2 1 100K_0402_5% R494 0_0402_5%
KSO15 54 KSO14/GPIO2E 73 ENBKL R495 1 @ 2 0_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 ENBKL 8 +3VLP
KSO16 81 74 930_PECI
KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 FSTCHG
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG 41 Pin 111 is a power source for HW operation of KB9012.
90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 91 EC_WLAN_LED#
BATT_BLUE_LED# 35 So, power plan will be different between KB930 and KB9012.
CAPS_LED#/GPIO53 EC_WLAN_LED# 35
EC_SMB_CK1 77 GPIO 92 PWR_LED PWR_LED 35 930_PECI R496 1 940@ 2 43_0402_1%
40,41 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 H_PECI 4
EC_SMB_DA1 78 93 BATT_AMB_LED#
40,41 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# 35
EC_SMB_CK2 79 SM Bus 95 SYSON 9012_PECI R497 1 9012@ 2 43_0402_1%
18,24,7 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 38,43
EC_SMB_DA2 80 121
18,24,7 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 PM_SLP_S4#
PM_SLP_S4#/GPIO59 PM_SLP_S4# 8
Pin74(KB930),Pin118(KB9012) are with different PECI pin location,
PM_SLP_S3# 6 100 PCH_RSMRST#
8 PM_SLP_S3#
PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT#
PCH_RSMRST# 8 so HW must co-layout for it.
8 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 9 Please make sure which EC pin will be connected to PECI circuit.
EC_SMI# 15 102 VCIN1_PROCHOT
8 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05
R605 1 DEG@ 2 E51TXD_P80DATA 16 103 H_PROCHOT#_EC
32 EC UART_TXD GPIO0A H_PROCHOT#_EC/GPXIOA06 H_PROCHOT#_EC 40
0_0402_5% TS_EN 17 104 GPXIOA07 9012_PCH_PWROK 2 9012@ 1
R606 1 DEG@ 2 E51RXD_P80CLK 25 TS_EN VCCST_PG_EC 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF# R498 0_0402_5%
32 EC UART_RXD 11,8 VCCST_PG_EC GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# 25
0_0402_5% WL_OFF# 19 GPIO 106 PBTN_OUT# GPXIOA07 2 940@ 1
31 WL_OFF# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 8 PCH_PWROK 8
EC_SPOK 25 107 GPU_ACIN R499 0_0402_5%
40 EC_SPOK EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 GPU_ACIN 18 +3VALW_EC
R565 FAN_SPEED1 28 108 MINI1_LED# 2 9012@ 1
MAINPWON 40,42
3
32 REC_MODE_L 0_0402_5% 2 @ 1 37 FAN_SPEED1 REC_MODE_L_R 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 MINI1_LED# 31 R500 0_0402_5% 3

E51TXD_P80DATA 30 EC_PME#/GPIO15
31 E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN Pin104 This co-layouted circuit is for power fail function of
31 E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
9012_PCH_PWROK 32 112 EC_ON
PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 35,42 KB930 and KB9012.At KB930, PCH_PWROK will be connected to pin 104.

2
PWR_SUSP_LED# 34 114 ON/OFF
35 PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF 35 At KB9012,PCH_PWROK will be connected to pin 32,
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 32,33
SUSP#/GPXIOD05
116 SUSP#
SUSP# 38,41,43,44,45
@ @ and VCOUT0_PH will be connected to pin 104.
117 VCCST_PWRGD R696
GPXIOD06 VCCST_PWRGD 11,45
118 9012_PECI R697 10K_0402_5%

1
PECI_KB9012/GPXIOD07
AGND/AGND

EC_XCLK1 122 10K_0402_5% VCIN0_PH_R R501 1 @ 2 0_0402_5%


XCLKI/GPIO5D VCIN0_PH 40
For abnormal shutdown R502 1 940@ 2 123 124
GND/GND
GND/GND
GND/GND
GND/GND

EC_XCLK0 +V18R VCIN1_PROCHOT


8 SUSCLK XCLKO/GPIO5E V18R VCIN1_PROCHOT 40
0_0402_5% 1
GND0

D25 R504 2 940@ 1


RB751V40_SC76-2 100K_0402_5% C515
EC_SPOK 1 2 PCH_RSMRST# 4.7U_0603_6.3V6K PU will disable PH function +3VALW_EC
C516 1 2 20P_0402_50V8 9012@ KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113

69

D26 940@ 20mil


RB751V40_SC76-2 KSO1 R507 2 940@ 1 47K_0402_5%
@ 1 2 PCH_PWROK Follow KB930 checking List ECAGND 1 2 D28 design for Debug board flash SPI ROM
L32 (can be short after MP) KSO2 R508 2 940@ 1 47K_0402_5%
BLM18AG121SN1D_2P
SM010030010 200ma 120ohm@100mhz DCR 0.2
KB932 use 256KB ROM +EC_SPI +3VALW_EC
KB932&9012 Co-Layout Item
KB9012 Embedded 128KB ROM D28 1 2 940@ RB751V40_SC76-2
+3VALW_EC EC_SPICS#/FSEL#_R
32 EC_SPICS#/FSEL#_R
1 DEG@ 2 EC_SI_SPI_SO_R U29 C518 1 2 940@ 0.1U_0402_16V4Z
Board ID 32 EC_SI_SPI_SO_R1
R598 0_0402_5% 1
/CS VCC
8 R511
2

Analog Board ID definition, R510 2 7 SPI_HOLD# 1 940@ 2 4.7K_0402_5% +EC_SPI


R503 1 @ 2 4.7K_0402_5% SPI_WP# 3 DO_IO1 /HOLD 6 EC_SPICLK
Please see page 3. +EC_SPI /WP CLK
Ra 100K_0402_5% 4
GND DIO_IO0
5 EC_SO_SPI_SI_R 1 DEG@ 2
EC_SO_SPI_SI_R1 32
4 1 940@ 2 R600 4
32,6,7 SPI_WP1#_R
R601 W25X20BVSNIG_SO8 0_0402_5%
1

AD_BID0 U28 1K_0402_5% SA00003GM10


940@
1

1 EC_SPICLK 2 XEMC@ 1 XEMC@


R506 C517 R513 0_0402_5% C520 33P_0402_50V8K
Rb 100K_0402_5% 0.1U_0402_16V4Z
@
2 KB932QF-A0_LQFP128 Security Classification Compal Secret Data Compal Electronics, Inc.
2

940@ 2012/07/10 2013/07/10 Title


Issued Date Deciphered Date
SA000055I00 EC ENE-KB9012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 11, 2013 Sheet 34 of 52
A B C D E
A B C D E

KB Conn.
KSI[0..7]
KSI[0..7] 32,34
SW7 BA51FP@ SW8 BA51FP@
JKB1 KSO[0..17] TP_CLK TJE-532QR5_4P TJE-532QR5_4P
KSO[0..17] 32,34
TP_DATA LEFT_BTN# 3 1 RIGHT_BTN# 3 1

100P_0402_50V8J
KSO0 1
1

C553

XEMC@ C551
100P_0402_50V8J
KSO1 2 KSI0_SW R577 1 9012@ 2 0_0402_5% KSI0 1 1 4 2 4 2
KSO2 3 2 KSO5_SW R585 1 9012@ 2 0_0402_5% KSO5
KSO3 4 3

5
6

5
6
KSO4 5 4
5 2 2

XEMC@
KSO5_SW 6 +3VALW_EC
KSO6 7 6 C522 940@
KSO7 8 7 0.1U_0603_25V7K U41
KSO8 9 8 2 1 1 2 KSO5
1 1
KSO9 10 9 VCC 1Y1 5 SW9 BA51NFP@ SW6 BA51NFP@
KSO10 11 10 KSO5_SW 3 1Y0 4 ON/OFF TJE-532QR5_4P TJE-532QR5_4P
KSO11 12 11 KSI0_SW 9 1Z 1S LEFT_BTN# 3 1 RIGHT_BTN# 3 1
KSO12 13 12 2Z 10 KSI0
KSO13 14 13 6 2Y1 7 F3_BTN 4 2 4 2
KSO14 15 14 11 GND 2Y0 8 ON/OFF
KSO15 16 15 PAD 2S

5
6

5
6
KSO16 17 16 NX3L4684TK_MO-229-10_3X3
KSO17 18 17 940@
KSI0_SW
KSI1
19
20
18
19 To TP/B Conn.
KSI2 21 20
KSI3 22 21 +5VS
KSI4 23 22 +3VALW_EC C663 9012@
23 JTP2
KSI5 24 C523 940@ 0.1U_0402_16V4Z
KSI6 25 24 27 0.1U_0603_25V7K U44 940@ 1 1 2
KSI7 26 25 G1 28 2 1 1 5 1 2 SW4 EA50@ SW5 EA50@
26 G2 VDD GND 2 TP_DATA 34
3 TJE-532QR5_4P TJE-532QR5_4P
3 TP_CLK 34
ON/OFF 2 6 4 LEFT_BTN# 3 1 RIGHT_BTN# 3 1
PWR_BTN# EC_ENT_RW EC_ENTERING_RW 34 4
E-T_6905-E26N-01R 5 RIGHT_BTN#
CONN@ F3_BTN 3 7 R586 1 940@ 2 5 6 LEFT_BTN# 4 2 4 2
BTN_A EC_IN_RW EC_IN_RW 9 6
SP01000IJ00 0_0402_5%
4 8 R589 1 940@ 2 7
EC_RST# 32,34

5
6

5
6
BTN_B EC_RST# 0_0402_5% GND 8
GND
F3 + Power BTN --> Reset EC
KB Conn.
JKB2 SLG4N059VTR_TDFN8_2X2
PAD
9
ACES_88514-00601-071
CONN@ 100g for Press 100g for Press
2 KSO0 1 SP010014M00 2
KSO1 2 1
KSO2 3 2
3
KSO3
KSO4
KSO5_SW
4
5
6
4
5
KB BackLight Conn.
KSO6 7 6 +5VS
KSO7 8 7 JBL1
8
S

KSO8 9 3 1 +5VS_BL 4 6
9 +5VALW 4 G2
KSO9
KSO10
KSO11
10
11
12
10
11 R451
BL@
Q44
3
2
1
3
2
G1
5

PWR_LED#
LED LED6 +3VALW
G

PWR_LED# 33
2

KSO12 13 12 100K_0402_5% DMG2301U-7_SOT23-3 1 BATT_BLUE_LED# 1 2 1 2


13 D 34 BATT_BLUE_LED# B

1
KSO13 14 1 BL@ 2 KBL_EN_R ACES_50504-0040N-001 Q17 R699 51_0402_5%
KSO14 15 14 CONN@ 2 L2N7002LT1G_SOT23-3
15 34 PWR_LED
KSO15 16 1 @ 2 SP01000Z300 G 34 BATT_AMB_LED# BATT_AMB_LED# 3 4 1 2
16 A

1
KSO16 17 R592 S R698 680_0402_5%
D

3
17
1

KSO17 18 0_0402_5% 1 R535


KSI0_SW 19 18 2 100K_0402_5% LTST-C295TBKF-CA_AMBER-BLUE
19 34 KBL_EN#
KSI1 20 G C524 LED7
KSI2 21 20 Q26 avoid flash issue when
S 0.1U_0603_25V7K
3

2
KSI3 22 21 L2N7002LT1G_SOT23-3 2 abnormall shutdown PWR_LED# 1 2 1 2
22 @ B
KSI4 23 @ R700 51_0402_5%
KSI5 24 23
KSI6 25 24 27 PWR_SUSP_LED# 3 4 1 2
25 G1 34 PWR_SUSP_LED# A
KSI7 26 28 R701 680_0402_5%
26 G2 +3VS

E-T_6905-E26N-01R HDD LED For BCM57786X


LTST-C295TBKF-CA_AMBER-BLUE

2
3 CONN@ +3VS 3

SP01000IJ00 +3VS +3VS


R632
10K_0402_5% LED8

5
R740 LED4 U39

1
51_0402_5% 2 EC_WLAN_LED# 1 2 1 2

P
B 5IN1_LED# 29 34 EC_WLAN_LED#
1 2 2 1 MEDIA_LED# 4
Y
A R702 499_0402_1%
A A
1
PCH_SATALED# 6

G
LTST-C191KFKT-2CA_ORANGE
LTST-C191TBKT-CA_BLUE MC74VHC1G08DFT2G_SC70-5

3
ON/OFF BTN +3VALW_EC +3VLP
2

R522 R534

D24
100K_0402_5%
940@
100K_0402_5%
9012@ TPM Board JTPM1
1

2 8 CLKRUN# CLKRUN# 1 2 LPC_AD3


ON/OFF 34 1 2 LPC_AD3 34,7
ON/OFFBTN# 1 34,8 PLT_RST# PLT_RST# 3 4 LPC_AD2
3 4 LPC_AD2 34,7
3 51ON# 5 6 CLK_PCI_TPM
51ON# 39 5 6 CLK_PCI_TPM 7
7 8 LPC_FRAME#
7 8 LPC_FRAME# 34,7 +3VS
BAV70W_SOT323-3 +3VALW 9 10 LPC_AD1
9 10 LPC_AD1 34,7 R392
+3VS 11 12 LPC_AD0
11 12 LPC_AD0 34,7
13 14 LPCPD#_R 2 TPM@ 1
D 13 14
1

Test Only 15 16 SERIRQ SERIRQ 34,9


SW3 EC_ON 2 15 16
4 34,42 EC_ON 10K_0402_5% 4
TJE-532QR5_4P G 12/9 modify pin define
2

1 3 S Q39 FOX_QT510166-L010-7H R444


3

TOP R624 L2N7002LT1G_SOT23-3 CONN@ 8 LPCPD# 1 @ 2


2 4 10K_0402_5% 940@ SP020011OA0 0_0402_5%
940@
@
Security Classification Compal Secret Data Compal Electronics, Inc.
6
5

Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM Connector & LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
32,33 ON/OFFBTN# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 35 of 52
A B C D E
A B C D E

Int. Speaker Conn.


+5VS +VDDA JSPK1
J6 SPKR+ R527 1 XEMC@ 2 0_0603_5%
40mil SPK_R+ 1
40mil 1 2 40mil SPKR- R528 1 XEMC@ 2 0_0603_5% SPK_R- 2 1
2
1 SPKL+ R532 1 XEMC@ 2 0_0603_5% SPK_L+ 3 5
3 G1
C554 JUMP_43X118 4.75V SPKL- R533 1 XEMC@ 2 0_0603_5% SPK_L- 4
4 G2
6
@
0.1U_0402_16V4Z ACES_88266-04001

3
EMC@ 2 CONN@ GND
+VDDA
SP02000K200
Reserved for ESD D27 D37
AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3
XEMC@ XEMC@
(output = 300 mA)

1
1 GND 1
R523
HP_PLUG#_1 100K_0402_5%

1
SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04

2
+PVDD_HDA
40mil D

1
L33 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q31 2 HP_PLUG# GND GND
+VDDA
HCB2012KF-221T30_0805 1 1 L2N7002LT1G_SOT23-3 G

1
10U_0603_6.3V6M
C608
C558 C559 S
Headphone Out

3
2 2 GNDA
@ C444 C445
2 2 2 XEMC@ XEMC@ JHP1
GNDA 330P_0402_50V7K 330P_0402_50V7K COM_MIC 4
1 1
GND GND
Place near Pin41 Place near Pin46 3
L36
HP_LEFT R238 1 2 60.4_0603_1% HPOUT_L_1 1 XEMC@ 2 0_0603_5% HPOUT_L_2 1
L55 1 @ 2 0.1U_0402_16V4Z +3VS_VDDA
+3VS
1 HP_RIGHT R237 1 2 60.4_0603_1% HPOUT_R_1 1 XEMC@ 2 0_0603_5% HPOUT_R_2 2
HD Audio Codec
1
10U_0603_6.3V6M
C605

0_0603_5% C604 5
L38
GNDA
2

2 HP_PLUG# 6 7

GNDA SINGA_2SJ3053-100111F
Place near Pin40 CONN@
20mil +MIC2_VREFO COM_MIC DC230009K00
SM010030010 200ma 120ohm@100mhz DCR 0.2
+3VS_DVDD 0.1U_0402_16V4Z L52 1 @ 2 +3VS HP_PLUG# GNDA

1
+AVDD1_HDA

2
0_0603_5% R539
L54 1 @ 2 0.1U_0402_16V4Z 20mil 1
@ C582
1
C636
1
C564 MIC2JD_1 2.2K_0402_5% D1
+VDDA
10U_0603_6.3V6M
C567

1 1 Q28 @ R542 AZ5125-02S.R7G_SOT23-3


D
1

1
2 0_0603_5% 10U_0603_6.3V6M LBSS138LT1G_SOT-23-3 22K_0402_5% EMC@ 2

2
C561 C562 2 2 2 2 MIC2JD 1 2 COM_MIC
@ 0.1U_0402_16V4Z G
2

2 2 S 1

2
0.1U_0402_16V4Z GND Place near Pin1, 9 C571
GNDA R543
26

40

41

46

36

1
1

9
Place near Pin25, 38 U34 10U_0603_6.3V6M 22K_0402_5%
2

CPVDD

DVDD

DVDD_IO
AVDD1

AVDD2

PVDD1

PVDD2
Internal MIC INT_MIC_R 2 1 INT_MIC C770 1 2 LINE2_C_L 24 GNDA

1
R726 1K_0402_5% 4.7U_0603_6.3V6K LINE2_L
C62 1 2 C769 1 2 LINE2_C_R 23
EMC@ 1000P_0402_50V7K 4.7U_0603_6.3V6K LINE2_R 35mA 42 SPKL+
GNDA C568 1 2 MIC2_C_L 17 68mA 600mA SPK_OUT_L+
GNDA GNDA GND
COM_MIC 2 1 COM_MIC_R 4.7U_0603_6.3V6K MIC2_L
Combo MIC
R540 1K_0402_5% C569 1 2 MIC2_C_R 18 43 SPKL-
4.7U_0603_6.3V6K MIC2_R SPK_OUT_L-
22 45 SPKR+
LINE1_L SPK_OUT_R+
21
LINE1_R 44 SPKR-
19 SPK_OUT_R-
MIC1_L 32 HP_LEFT
20 HPOUT_L
MIC1_R 33 HP_RIGHT
35 HPOUT_R
1 CBN 8 HDA_SDIN0_AUDIO 1 R547 2 HDA_SDIN0 6
C570 SDATA_IN 33_0402_5%
2.2U_0402_6.3V6M 37 5
2 CBP SDATA_OUT HDA_SDOUT_AUDIO 6
29 10 HDA_SYNC_AUDIO 6
+MIC2_VREFO MIC2_VREFO SYNC
10mil 11 HDA_RST_AUDIO#
RESETB HDA_RST_AUDIO# 6
30
3 MIC1_VREFO_R 6 3
+INTMIC_VREFO 10mil31 BCLK HDA_BITCLK_AUDIO 6
MIC1_VREFO_L XEMC@ +INTMIC_VREFO
C584 1 2
10mil27 1 XEMC@ 2 1 2 C573
GNDA LDO1_CAP
10U_0603_6.3V6M R548 0_0402_5% 22P_0402_50V8J
Int. MIC

1
GNDA C574 1 2 39 GND R417
10U_0603_6.3V6M LDO2_CAP 2
C583 1 2 7 GPIO0/DMIC_DATA 10K_0402_5%
GND LDO3_CAP
10U_0603_6.3V6M 3 15mil L51 15mil
R546 2 1 20K_0402_1% 15 GPIO1/DMIC_CLK 0_0603_5% JMIC1
GNDA

2
JDREF 47 INT_MIC_R 1 XEMC@ 2 INT_MIC_R_1 1
PD# EC_MUTE# 34 2 1
R529 2
Place near 1
GND 47K_0402_5% C550
codec C575 1 2 2.2U_0402_6.3V6M CPVEE 34 12 MONO_IN 2 1 BEEP#_R 1 @ 2 XEMC@ 3
CPVEE PCBEEP BEEP# 34 G1
10mil13 220P_0402_50V7K 4
HP_PLUG#_1 R545 2 1 39.2K_0402_1% SENSE_A 16 C555 2 G2
MIC2JD_1 R549 2 @ 1 20K_0402_1% 14 SENSE A MONO_OUT 38 1U_0402_6.3V6K R530 ACES_88266-02001
SENSE B AVSS2 47K_0402_5% CONN@
2

28 CODEC_VREF 1 1 2 GND SP020008Y00


MIC2JD 48 VREF XEMC@ PCH_SPKR 9
SPDIFO 10mil 1 1 1
2.2U_0402_6.3V6M
C577

R531
4.7K_0402_5%

C556
@ 100P_0402_50V8J
0.1U_0402_16V4Z
C576

10U_0603_6.3V6M
C578

4 25 GNDA
DVSS AVSS1 2
1

49 2 2 2
GND
ALC3225-CG_MQFN48_6X6

GND
GNDA Place next pin27 GNDA
J7 J14
JUMP_43X39 JUMP_43X39
4 1 2 1 2 4
@ 1 2 @ 1 2
GNDA
J11 J12
JUMP_43X39 JUMP_43X39
1 2 1 2
@ 1 2 @ 1 2

GND GNDA GND GNDA


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC3225
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0

http://sualaptop365.edu.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 36 of 52
A B C D E
FAN1 Conn
+5VS C632
4.7U_0603_10V6K H3 H4 H5 H6 H9 H10 H11 H12 H17 FD1 FD2
1 2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

@ @

1
U31

1
1 8 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2 EN GND 7
+VCC_FAN1 3 VIN GND 6 FD3 FD4
2 @ 1 4 VOUT GND 5 @ @ @ @ @ @ @ @ @
34 EN_DFAN1 VSET GND
R515 1 AP2113AMTR-G1_SO8 H13 H14 H15 H16 H20 H24 @ @

1
0_0402_5% H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0
C626 FIDUCIAL_C40M80 FIDUCIAL_C40M80
0.1U_0402_16V4Z
2 @

1
C627 @ @ @ @ @ @
4.7U_0603_10V6K
+3VS 1 2 H21 H27
H_3P0 H_3P7
@ C631
1

1000P_0402_50V7K
R516 1 2

1
10K_0402_5%
40mil JFAN1
2

+VCC_FAN1 1 @ @
2 1 4
34 FAN_SPEED1 2 GND
3 5
3 GND
1
C630 H22 H23
1000P_0402_50V7K ACES_88231-03041 H_2P5N H_2P5X3P5N
XEMC@ CONN@
2
SP020020710
@ @

1
+3VS
1

R518 +3VS
10K_0402_5%
GSEN@ U2 GSEN@
1 C633 1 2 10U_0603_6.3V6M
2

8 Vdd_IO GSEN@
4 CS 14 C628 1 2 0.1U_0402_16V4Z
15,16,7 D_CK_SCLK SCLSPC Vdd
15,16,7 D_CK_SDATA 6
7 SDA/SDI/SDO
R519 1 @ 2 10K_0402_5% SDO/SA0 11 G_SEN_INT
+3VS INT1 G_SEN_INT 8
R520 1 GSEN@ 2 10K_0402_5% 16 9
15 ADC1 INT2
13 ADC2 10
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 37 of 52

http://sualaptop365.edu.vn
A B C D E

Normall Platform (Not support M-STATE and Deep Sleep)


+5VALW TO +5VS
+5VALW +5VS
U33
DMN3030LSS-13_SOP8L-8
8 1 U11 @ J36
7 2 +3VALW 1 14 +3VS_OUT 1 2 +3VS
VIN1 VOUT1 1 2

2
4.7U_0603_10V6K
C587

1U_0402_10V6K
C588
6 3 1 1 2 13
VIN1 VOUT1

4.7U_0603_10V6K
C585

4.7U_0603_10V6K
C586
1 1 5 35V@ R551 47K_0402_5% C976 JUMP_43X118
35V@ 470_0603_5% SUSP# 2 R927 1 3VS_ON 3 12 2 1 330P_0402_50V7K
35V@ 35V@ C980 ON1 CT1
1 1

4
2 2 1 2 4 11
+5VALW

1
2 2 +5VS_R 0.1U_0402_16V4Z VBIAS GND
2 @ 1 5VS_ON 5 10 2 1
ON2 CT2

3
R926 330P_0402_50V7K
0_0402_5% C979 +5VALW 6 9 C967 @ J37
1 2 EMC@ 7 VIN2 VOUT2 8 +5VS_OUT 1 2
20mil R553 1 35V@ 2
10mil 5VS_GATE 5 SUSP 0.1U_0402_16V4Z VIN2 VOUT2 1 2 +5VS
+VSB
100K_0402_5% Reserved for ESD 15 JUMP_43X118
Q30B GPAD
1

4
6 Reserved
C592 DMN66D0LDW-7_SOT363-6 TPS22966DPUR_SON14_2X3
0.1U_0603_25V7K 35V@
35V@
SUSP 2 2

Q30A
1

DMN66D0LDW-7_SOT363-6
35V@
+5VALW
+0.675VS +1.05VS_VTT +1.8VS_6511

2
+3VALW TO +3VS

2
R552
100K_0402_5% R566 R567 R568
+3VALW +3VS @ 470_0603_5% 470_0603_5% 470_0603_5%
U35 @ @ @

1
DMN3030LSS-13_SOP8L-8 SUSP
43 SUSP

1
8 1
7 2 C19 2 1 +0.675VS_R +1.05VS_VTT_R +1.8VS_6511_R

2
4.7U_0603_6.3V6K
C594

4.7U_0603_6.3V6K
C595

4.7U_0603_6.3V6K
C596
2 2 2 6 3 2 1 XEMC@ 330P_0402_50V7K 2
D D D

1
Reserved for ESD

1U_0402_6.3V6K
C597
35V@ 5 35V@ R558
D

1
470_0603_5% @ 2 SUSP 2 SUSP 2
6511_PWR_EN# 27
35V@ 35V@ 2 G G G
34,41,43,44,45 SUSP#
4

1 1 1 2 G S Q36 S Q37 S Q38

6 1

3
1
+3VS_R S L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3

3
R555 Q29 @ @ @
10mil 10K_0402_5% L2N7002LT1G_SOT23-3
20mil @
+VSB 2 35V@ 1 3VS_GATE 2 SUSP

2
+1.35V +5VALW
R559 1 Q32A
1
3

150K_0402_1% C598 DMN66D0LDW-7_SOT363-6

2
0.1U_0603_25V7K 35V@
35V@ R573 R554
SUSP 5 2 470_0603_5% 100K_0402_5%
@ @
Q32B
4

1
DMN66D0LDW-7_SOT363-6 SYSON#
35V@ For ESD +1.35V_R

3
3VS_GATE 11

6
+5VS +3VALW_PCH +CPU_CORE +1.05VS_VTT

5 SYSON
SYSON 34,43
1 2 2 SYSON# Q40B
EMC@ C93 Q40A DMN66D0LDW-7_SOT363-6

4
10U_0603_6.3V6M
1 1 1 22U_0805_6.3V6M DMN66D0LDW-7_SOT363-6 @

1
EMC@ @
C92

C39 C64
3 EMC@ EMC@ 3
2 2 2
22U_0805_6.3V6M
+3VS to +3VSDGPU for GPU 22U_0805_6.3V6M

+3VS +3VSDGPU
U12 VGA@ 100mil(1.5A)
1 +5VALW +3VSDGPU +1.8VSDGPU +0.95VSDGPU +VGA_CORE +1.5VSDGPU
5 OUT
IN
2
1

2
2
GND

2
4 C621 R556 R574 R575 R570 R571
IN VGA@ 470_0603_5% R557 47_0603_5% 47_0603_5% 47_0603_5%
2 100K_0402_5%
C620 3 1 4.7U_0603_6.3V6K @ @ 47_0603_5% @ @ @
4.7U_0603_6.3V6K EN @
2

1
VGA@ G5243T11U_SOT23-5

1
1 VGA_ON# +3VSDGPU_R +1.8VSDGPU_R +0.95VSDGPU_R +VGA_CORE_R +1.5VSDGPU_R
3

3
+3VS VGA_ON 5 2 VGA_ON# VGA_ON# 2 5 VGA_ON# VGA_ON# 2 5 VGA_ON#
Q55B Q41B Q45B
DMN66D0LDW-7_SOT363-6 Q55A Q41A DMN66D0LDW-7_SOT363-6 Q45A DMN66D0LDW-7_SOT363-6
4

4
4 4
5

@ DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 @ DMN66D0LDW-7_SOT363-6 @


@ @ @
VCC

1
8,9 VGA_ON IN1 4
OUT VGA_ON_R 47
R77 1 VGA@ 2 2
GND

+3VSDGPU IN2
20K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
C63 VGA@
0.1U_0402_16V7K

1
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title
3

U38
MC74VHC1G08DFT2G_SC70-5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
2 VGA@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 38 of 52
A B C D E
A B C D

+5VS
1 VIN 1

CONN@ PJP101 EMI@ PL101


ACES_50305-00441-001_4P HCB2012KF-121T50_0805
DC_IN_S1 1 2
1 +3VALW
2
3
4
GND
1

1
GND ESD@ PC101 EMI@ PC102 EMI@ PC104 @ PR102
0.1U_0603_25V7K 100P_0603_50V8 1000P_0603_50V7K 34,4,40 H_PROCHOT# 47K_0402_1% @ PR103
2

2
10K_0402_1%

2
8
@ PC105
D

6
0.022U_0402_16V7K 3

P
+ BATT_TEMP 34,40
2 2 1 1
@ PQ101A G O 2
-

G
DMN66D0LDW-7_SOT363-6 @ PU102A

1
S LM393DR_SO8

4
@ PD102

1
LL4148_LL34-2 @ PR104

1
1.5M_0402_5%
@ PC106 @ PR101

2
100P_0402_50V8J 100K_0402_1%

2
1
2
@ PR106 2

H_PROCHOT# 47K_0402_1%

VIN @ PU102B

8
@ PC107 LM393DR_SO8
D

3
0.022U_0402_16V7K 5

P
5 2 1 7 +
O

2
@ PQ101B G 6
- ACIN 34,41,8

G
@ PD101 DMN66D0LDW-7_SOT363-6

1
LL4148_LL34-2 S

4
@ PD103
930@ PD104 LL4148_LL34-2 @ PR107

1
LL4148_LL34-2 @ PJ101 1.5M_0402_5%
2 1 1 2

2
1 2 1

1
BATT+ JUMP_43X39 @ PR108 @ PR109
68_1206_5% 68_1206_5%
930@ PQ102
TP0610K-T1-E3_SOT23-3
2

2
N1 3 1
VS
1

930@ PR110 @ PC109


100K_0402_1% 930@ PC108 0.1U_0603_25V7K
0.22U_0603_25V7K
2

930@ PR111
2

22K_0402_1%
1 2
3
35 51ON# 3

@ PR105
0_0402_5%
1 2
+3VLP +CHGRTC

- PBJ101 @ + PR113
560_0603_5%
PR112
560_0603_5%
2 1 1 2 1 2 +RTCBATT

ML1220T13RE
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9531P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 39 of 52

http://sualaptop365.edu.vn
A B C D
A B C D

+3VLP
CONN@ PJP201
SUYIN_200275GR008G13GZR
10 EMI@ PL201
GND 9
BATT+ <45,47>
HCB2012KF-121T50_0805
GND 8 BATT_S1 1 2
8 7

1
7 6 BI @ PC209
6 5

1
TH 2 1 0.1U_0603_25V7K
+3VLP

2
5 4

1
EC_SMCK PR206
1
4 3 EC_SMDA 6.49K_0402_1% EMI@ PC202 @ PR229 @ PR230
1

3 2

1
PR203 1000P_0402_50V7K 10K_0402_1% 10K_0402_1%

2
2 1 PR202 PR208 1K_0402_1%

2
1
1
100_0402_1% 1K_0402_1%

1
1 2 @ PU204
BATT_TEMP 34,39
PR201 @ PR231 1 8

2
100_0402_1% 100K_0402_1% VCC TMSNS1
EC_SMB_CK1 34,41
2 7 2 1
2

GND RHYST1
EC_SMB_DA1 34,41

1
MAINPWON 3 6 @ PR232
OT1 TMSNS2 47K_0402_1%
4 5 @ PH202
OT2 RHYST2 100K_0402_1%_TSM0B104F4251RZ
G718TM1U_SOT23-8

2
2 2

For KB9012
OTP
For KB9012
sense 20mΩ
Active Recovery

92℃ 1.2V, Active 65W 84W,1.2V 56W,1.2V

56℃ 2.255V, Recovery 90W 117W,1.2V 77W,1.2V


@ PQ202
TP0610K-T1-E3_SOT23-3

3 1 +VSBP
PH201 under CPU botten side : 120W
B+
CPU thermal protection at 92 degree C ( shutdown )
0.22U_0603_25V7K

0.1U_0603_25V7K
1

Recovery at 56 degree C
1

+3VLP +EC_VCCA
PC205

PC206

@ PR211
34 EC_SPOK
100K_0402_1%
2

3 3

@ PR212 @ @
2

22K_0402_1% ADP_I 34,41


VL 2 1
65W@ PR218

1
23.2K_0402_1%
1

@ PC207 @ PR214 PR228

1
@ PR213 0.1U_0603_25V7K 21K_0402_1% 12.4K_0402_1% 90W@ PR218

2
1
100K_0402_1% 78.7K_0402_1%
@ PR217 @ PU201

2
@ PR219 @ PR216 100K_0402_1% 1 8
2

D VCC TMSNS1
1

0_0402_5% 100K_0402_1%

2
1 2 2 34,39,4 H_PROCHOT# 2 7 2 1 VCIN0_PH 34
2
42 SPOK G @ PQ203 GND RHYST1 @ PR220
2N7002KW_SOT323-3
D 34,42 MAINPWON MAINPWON 3
~OT1TMSNS2
6 9.53K_0402_1%
1

S
3

@ PC208 2 1 2 4
~OT2 RHYST2
5 1 2 VCIN1_PROCHOT 34
1U_0402_6.3V6K G
2

@ PQ204 @ PR221 G718TM1U_SOT23-8 @ PR222 PR204


S 2N7002KW_SOT323-3 1_0402_1% 16.2K_0402_1% 127K_0402_1%
3

1
1 2 H_PROCHOT#_EC 34
PH201

1
100K_0402_1%_TSM0B104F4251RZ @ PR222
@ PJ201 B value:4250K±1% 10.5K_0402_1% 65W@ PR225
1 2 90W@ PR225 78.7K_0402_1%
+VSBP +VSB

2
1 2 53.6K_0402_1%
JUMP_43X39

2
1

1_0402_1%
PR227
0_0402_5%
PR226
For 65W adapter==>action 84W , Recovery 56W @
4 4

2
2
For 90W adapter==>action 117W , Recovery 77W
34 ECAGND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
Date: Tuesday, March 26, 2013 Sheet 40 of 52
A B C D
A B C D

for reverse input protection


D

1
2 PQ301
G 2N7002KW_SOT323-3
S

3
PQ304
SIS412DN-T1-GE3_POWERPAK8-5
1 2 1 2 1
2
1
PR302 PR301 5 3 1
1M_0402_5% 3M_0402_5%
100ppm

0.01U_0402_50V7K
VIN PQ302 P1 PQ303 P2 B+ CHG_B+

4
AON6414AL_DFN8-5 SIS412DN-T1-GE3_POWERPAK8-5 PR303

1_0402_1%
1 1 0.02_1206_1% EMI@ PL301

PC308

PR305
1
2 2 1.2UH_PNS40201R2YAF_3A_30%
5 3 3 5 1 4 1 2

2200P_0402_50V7K
4x4x2

2
0.1U_0402_25V6
2 3

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K

2
0.1U_0402_25V6
4

4
1

1
1_0402_1%

PC303

PC304

@EMI@ PC305

EMI@ PC307
PR304 BQ24735_BATDRV 1 2
1

1
VIN
PC301

PC302
PC306 PR306

2
0.1U_0402_25V6 4.12K_0603_1%
2

2
@ 1 2
2

2
0.1U_0603_25V7K

0.1U_0402_25V6
PD302
BAS40CW_SOT323-3

1
PC311

PC309
2

1
4.12K_0603_1%

4.12K_0603_1%
PC310
0.047U_0402_25V7K
1

1 2
PR307

PR308

5
10_1206_1%

0_0603_5%
1

PR310
PR309
2

PR311 PQ305
0_0603_5% SIS412DN-T1-GE3_POWERPAK8-5

BQ24735_ACN
BQ24735_ACP
2 2

BQ24735_BST 2

1
DH_CHG 1 2 DH_CHG-1 4

BQ24735_LX
1 2 PD303

DH_CHG
RB751V-40_SOD323-2
PC312 PL302 PR312

3
2
1
1U_0603_25V6K 1 2 10UH_FDSD0630-H-100M-P3_3.8A_20% 0.01_1206_1%
BQ24735_LX 1 2 CHG 1 4 BATT+
PC313

5
2 3

680P_0402_50V7K 4.7_1206_5%
1U_0603_25V6K

20

19

18

17

16

SIS412DN-T1-GE3_POWERPAK8-5

@EMI@ PC316 @EMI@ PR313


PU301

1 CSOP1

1 CSON1
VCC

PHASE

HIDRV

REGN
BTST

10U_0603_25V6M

10U_0603_25V6M
21

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC314

PC317

PC315

PC318
1

1
PQ306
1 15 DL_CHG 4

2
ACN LODRV

2
1
2 14
ACP GND PR314

3
2
1
BQ24735RGRR_QFN20_3P5X3P5 10_0603_5%

0.1U_0603_25V7K

2
BQ24735_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP

PC321
BQ24735_ACDRV 4 12 SRN 1 2 CSON1

2
ACDRV SRN PR315
6.8_0603_5%
+3VLP 1 2 ACOK 5 11 BQ24735_BATDRV
PR316 ACOK ACDET BATDRV
100K_0402_1%
IOUT

SDA

ILIM
SCL
3 34,39,8 ACIN 3
6

10
ACDET PR317
316K_0402_1%
2 1 +3VALW
1

100K_0402_1%
1
PR318 VIN

0.01U_0402_25V7K
PC322
PR320

1
2M_0402_1%

Vin Detector
2

2
2
1
1

PR321
PR322
422K_0402_1%
Min. Typ Max.
2M_0402_1% L-->H 17.520V 18.006V 18.504V
H-->L 16.967V 17.593V 18.237V
2
1 2

ACDET
2200P_0402_50V7K

PQ307
ILIM and external DPM
1

PR323 PDTC115EU_SOT323-3 EC_SMB_CK1 34,40


1
PC326

100K_0402_1% PR324
34 FSTCHG
1 2 2 64.9K_0402_1%
EC_SMB_DA1 34,40 Min. Typ Max.
2

@ PR325 Close EC 3.906A 4.006A 4.108A


2

PQ308 0_0402_5%
D
1

2N7002KW_SOT323-3 2 1 1 2
ADP_I 34,40
3

2
34,38,43,44,45 SUSP#
1

G PC324 @ PC325
4
100P_0402_50V8J 0.1U_0402_25V6 4

S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 41 of 52
A B C D
5 4 3 2 1

D D

@ PR415
0_0402_5%
1 2

B+ EN1 and EN2 dont't floating PR410


PU401 1K_0402_1%
EMI@ PL401 7 1 3V_EN_R 1 2 3V5V_EN @ PR413 PR401
HCB2012KF-121T50_0805 IN EN1 0_0402_5% 499K_0402_1%

4.7U_0603_6.3V6K
1 2 3V_VIN 8 3 FB_3V 1 2 ENLDO_3V5V 1 2
IN EN2 B+

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0603_6.3V6K
PR404 PC401

1
150K_0402_1%
@ PC426
6 1
BST_3V 2BST-1_3V
1 2 PC428 0.01U_0402_25V7K PR414 1K_0402_1%
BS

@ PC425

PR405
0_0603_5% 1 2 FB-1_3V 1 2
1

1
@EMI@ PC403

EMI@ PC410

PC408

PC405
0.1U_0603_25V7K

2
PL402

2
10 LX_3V 1 2
+3VALWP
2

2
@ LX

@EMI@ PR409
9 4 1UH_FDSD0630-H-1R0M-P3_11A_20%
GND OUT

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
680P_0603_50V7K 4.7_1206_5%
2 5
+3VALWP PG LDO +3VLP

PC411

PC416

PC414

PC413
1
SY8208BQNC_QFN10_3X3

2
PC422

13V_SN
4.7U_0603_6.3V6K

2
1

PR416
100K_0402_1%
C C

3.3V LDO 150mA~300mA

@EMI@ PC423
2

2
Vout is 3.234V~3.366V
40 SPOK

TDC=8A
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118

1ENLDO_3V5V
@ PR411
0_0402_5%
B+ EMI@ PL404
HCB2012KF-121T50_0805 PU402

2
1 2 5V_VIN 8 1 3V5V_EN PC427 PR412
IN EN1
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

6800P_0402_25V7K 1K_0402_1%
3 FB_5V 1 2 FB-1_5V 1 2
EN2 PR403 0_0603_5% PC404 0.1U_0603_25V7K
1

1
PC406

PC407

EMI@ PC409

@EMI@ PC402

B 6 BST_5V 1 2BST-1_5V 1 2 B
BS
2

@ PL403
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3.3V 5 4 1UH_FDSD0630-H-1R0M-P3_11A_20%
VCC OUT
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%

1
@EMI@ PC424 @EMI@ PR408

SPOK 2 7
PG LDO VL
1

PC420

PC417

PC418

PC415

PC412
4.7U_0603_6.3V6K

SY8208CQNC_QFN10_3X3

2
15V_SN
2

2
1

PC421
4.7U_0603_6.3V6K
2

@ PJ402
+5VALWP 1 2 +5VALW
2

1 2
JUMP_43X118
Vout is 4.998V~5.202V
5V LDO 150mA~300mA TDC=8A
PR407
2.2K_0402_5%
1 2
34,35 EC_ON
@ PR402
1 2
34,40 MAINPWON 0_0402_5%
A A

3V5V_EN
1M_0402_1%

4.7U_0603_6.3V6K
1

1
PR406

PC419

Security Classification Compal Secret Data Compal Electronics, Inc.


2

@ 2012/07/10 2013/07/10 Title


Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
EN1 and EN2 dont't floating AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

http://sualaptop365.edu.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9532P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 42 of 52
5 4 3 2 1
A

+1.35VP EMI@ PL507


HCB2012KF-121T50_0805
Ipeak = max{ 0.7*Ibudget, 1st +2nd max loading} 1.35V_B+ 2 1 B+
Ipeak = max{ 12.34*0.7 , 4.2+8.14 }

2200P_0402_50V7K
10U_0805_25V6K
Ipeak=12.34A ; 1.2Ipeak=14.808A ;Imax=8.638A

0.1U_0402_25V6
1/2Delta I=0.7353A (F=300K Hz)

1
PC502

EMI@ PC503

ESD@ PC521
PR504=(1.2Ipeak-1/2Delta I) *Rds(on)(max)*1.2/9uA=8.45Kohm

5
choose PR504=8.45Kohm (for safety >1.2Ipeak)

MDV1525URH_PDFN33-8-5

2
Rds(on)=5.0m ohm(max) ; Rds(on)=4.2m ohm(typical) +1.35VP
Ilimit_min=(8.366K*9uA)/(5.0m*1.2)=15.058A

PQ502
Ilimit_max=(8.535K*11uA)/(4.2m*1.2)=22.352A UG_1.35V 4
Iocp=Ilimit+1/2Delta I=15.79A~23.09A

JUMP_43X39
PJ503
Iocp(min)>1.2Ipeak

1
2012/9/6

3
2
1
2
@

2
OVP=110% 115% 120% PR502
2.2_0603_5%
PC504
0.1U_0603_25V7K
PL501
S COIL 1.5UH 20% TMPB0604M-1R5MN-Z01 11A
BST_1.35V 2 1 BST_1.35V-1 2 1 1 2
+0.675VSP 6.6x7.3x3.8 TAI-TECH +1.35VP

S TR MDU1512RH 1N POWERDFN56-8
靠近Output Cap PAD

10U_0805_25V6K

10U_0805_25V6K
LX_1.35V

1
DCR:8.5mΩ

5
20

19

18

17

16
1

1
PC501

PC505
PU501 ESD@ PR503
4.7_1206_5% 1

VTT

VLDOIN

BOOT

UGATE

PHASE
21
2

2
PAD

PQ503
+ PC506
1 15 LG_1.35V 4 330U_2.5V_M
VTTGND LGATE

1
ESD@ PC507
680P_0402_50V7K 2
2 14

2
VTTSNS PGND PR504

3
2
1
8.45K_0402_1%
3 13 2 1
GND RT8207MZQW_WQFN20_3X3 CS

4 12 Rds=4.2mΩ(Typ)
+VTT_REFP VTTREF VDDP
5.0mΩ(Max)
5 11 2 1
+1.35VP VDDQ VDD
+5VALW

PGOOD
PR505
+3VALW
1

1U_0603_10V6K
5.1_0603_5% @ PJ504

TON
@ PR513 PC508 +1.35VP 1 2 +1.35V

FB

S3

S5
0.033U_0402_16V7K 1 2

10K_0402_1%
0_0402_5%
2

1
PC509
15 DDR_VTT_PG_CTRL 1 2 JUMP_43X118

S3_1.35V 7

S5_1.35V 8

10

PR506
PC510
1U_0603_10V6K @ PJ505

2
@ PR501 1 2
680K_0402_1% @ 1 2

2
34,38,41,44,45 SUSP# 1 2 PGOOD_1.35V JUMP_43X118

@ PR507 PR508
0_0402_5% 887K_0402_1%
1 34,38 SYSON 1 2 2 1 1.35V_B+
1
@ PJ506
2
1

PR509 +0.675VSP 1 2 +0.675VS


8.06K_0402_1% JUMP_43X79
1

@ PC512 2 1
@ PQ501 0.1U_0402_25V6
2N7002KW_SOT323-3 D FB=0.75V @ PJ511
1

2
1

1 2
2 To GND = 1.5V +0.95VSDGPUP 1 2
38 SUSP SUSP
G
@ PC511
0.1U_0402_25V6 PR510 To VDD = 1.8V JUMP_43X118 +0.95VSDGPU
2

10K_0402_1%
S
3

VGA@ PR532 VGA@ PC531


44,45,47 VGA_PG
0_0402_5% 0.22U_0603_10V7K
VGA@EMI@ PL505 1 2 2 1
HCB2012KF-121T50_0805
1 2 0.95V_VIN
+3VALW

22U_0805_6.3V6M

22U_0805_6.3V6M

16

15

14

13
1

1
PC533

VGA@ PC534
VGA@ PL506

BOOT
VIN

EN

PWRGD
1UH_PCMB063T-1R0MS_12A_20%
2

2
@ 1 12 LX_0.95V 1 2
VIN PH
+0.95VSDGPUP

1
@EMI@ PR533
4.7_0402_1%
2 11

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
VIN PH

1
VGA@ PC535

VGA@ PC536

VGA@ PC537

VGA@ PC538
VGA@ PU504
TPS54618
3 10

2
GND PH

2 SNUB_0.95V
4 9
GND SS/TR

VSENSE

RT/CLK
COMP

2200P_0402_50V7K
AGND

680P_0402_50V7K
17
PWRPD

VGA@ PC542

@EMI@ PC539
1

VGA@ PC540
22P_0402_50V8J
19.1K_0402_1%
5

1
VGA@ PR535

1
3300P_0402_50V7K 18K_0402_1%

169K_0402_1%
VGA@ PR537

VGA@ PR534

2
1

2
2
STATE S3 S5 1.35VP VTT_REFP 0.675VSP

1 2

2
S0 Hi Hi On On On VGA@ PC541
FB=0.799V

1
Off 2 +0.95VSDGPUP
S3 Lo Hi On On (Hi-Z)
VGA@ PR536
100K_0402_1% Ipeak=4.28A ; 1.2Ipeak=5.136A ;Imax=2.996A
F=131904/(PR534^0.9492)=1000KHz, PR534=169KΩ

2
S4/S5 Lo Lo Off Off Off
(Discharge) (Discharge) (Discharge) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

Note: S3 - sleep ; S5 - power off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35VP/0.675VSP/0.95VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
Date: Tuesday, March 26, 2013 Sheet 43 of 52
A
5 4 3 2 1

VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V VGA@EMI@ PL504
Freq=290KHz(typ) HCB2012KF-121T50_0805
1.5VSG_B+ 2 1
D B+ D
Cesr= 15m ohm

2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
SIS412DN-T1-GE3_POWERPAK8-5
Ipeak= 4.7A Imax= 3.29A Iocp=5.64A

VGA@EMI@ PC516

VGA@ PC517

@ PC518

@EMI@ PC519
Iocp= 5.72A~6.43A

1
VGA@ PQ504

2
4

VGA@ PR517 VGA@ PC514

3
2
1
VGA@ PU502 2.2_0603_1% 0.1U_0603_25V7K
VGA@ PR512 1 10 BST_1.5VSG 1 2 1 2
56.2K_0402_1% PGOOD VBST
2 1 TRIP_1.5VSG 2 9 DH_1.5VSG VGA@ PL502
TRIP DRVH 4.7UH_PCMB063T-4R7MS_5.5A_20% +1.5VSDGPUP
3 8 SW_1.5VSG 1 2
43,45,47 VGA_PG EN SW

5
FB_1.5VSG 4 7

SI7716ADN-T1-GE3_POWERPAK8-5
VFB V5IN +5VALW

1
RF_1.5VSG 5 6 DL_1.5VSG 1
TST DRVL

VGA@ PQ505
1

1
11 VGA@EMI@ PR518 + VGA@ PC523
TP VGA@ PC515 4 4.7_1206_5% 330U_2.5V_M
Resistance(KΩ) Frequency(KHz) VGA@ PR514 TPS51212DSCR_SON10_3X3 1U_0603_10V6K

2
470K_0402_1% 2
470 290
2

1
C Rds=13.5mΩ(Typ) VGA@EMI@ PC522 C

3
2
1
200 340 16.5mΩ(Max)
680P_0402_50V7K

2
100 380
39 430 VGA@ PR515
FB=0.704V 11.5K_0402_1%
2 1
1

VGA@ PR516 +3VS


10K_0402_1%
2

1
@ PC526
1U_0402_6.3V6K

2
Note:Iload(max)=3A
PU503
APL5930KAI-TRG_SO8
6
B 5 VCNTL B

0.022U_0402_16V7K
3
9 VIN VOUT 4 +1.5VSP
VIN VOUT

1
1

PC528 8
EN

1
PC529

22U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6K 7 2 PR519

GND
POK FB 20K_0402_1%
2

1
FB=0.8V

PC525

PC524
1
@ PR523 FB_1.5VSP
0_0402_5%

2
1 2 +1.5VSP_ON @
34,38,41,43,45 SUSP#

1
1

PR521
1

@ PR522 22.6K_0402_1%
@ PJ509 @ PC527 22K_0402_5%

2
+1.5VSDGPUP 1 2 +1.5VSDGPU 0.1U_0402_25V6
2

1 2
2

JUMP_43X118

@ PJ510
1 2
1 2
JUMP_43X118

Ien=10uA, Vth=0.3V, notice


@ PJ508 the res. and pull high
A A
+1.5VSP
1
1 2
2
+1.5VS voltage from HW
JUMP_43X39

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP/+1.5VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 44 of 52

5 http://sualaptop365.edu.vn 4 3 2 1
5 4 3 2 1

+1.05VSP Ipeak=5.36A ; Imax=3.752A ; 1.2Ipeak=6.432


Delta I=0.xxxxA=>1/2Delta I=0.xxxxA,F= 800K Hz(typ)

PR603
D 1K_0402_1% D
2 1 SUSP# 34,38,41,43,44

@ PR607
1M_0402_1%
1 2

B+ PC606
PU601 0.1U_0402_25V6

2200P_0402_50V7K
8 1 EN_+1.05VSP PR602 PC605 1 2
IN EN

10U_0805_25V6K

10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K

0.1U_0402_25V6
6 BST_+1.05VSP 1 2 1 2 PL601
BS

1
@EMI@ PC602

EMI@ PC603

PC604

PC623
0.68UH_PCMC063T-R68MN_15.5A_20%
9
GND LX
10 SW_+1.05VSP 1 2 +1.05VSP

2
4

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
FB_+1.05VSP
FB

1
1

PC624

PC625

PC626

PC627

PC628

PC629
+3VS 1 2 3 7
@ PR613 ILMT BYP
+3VALW

2
1
10K_0402_1% 2 5 @EMI@ PR604
PG LDO

1
PR619 4.7_0805_5% @
@ PC614 1M_0402_1% SY8208DQNC_QFN10_3X3

1 2
0.1U_0402_25V6
2 @EMI@ PC607

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
2
680P_0402_50V7K

2
1

1
PC601

PC608
C PR618 C
10K_0402_1% PR605

2
+3VS 2 1 100K_0402_1%
2 1 @ PJ602
PC609 1 2
+1.05VSP 1 2 +1.05VS_VTT
VFB=0.6V 4700P_0402_25V7K
11,34 VCCST_PWRGD 2 1 JUMP_43X118
@ PJ603
1 2
1 2

1
JUMP_43X118
PR608
127K_0402_1%
+3VS

2
1

@ PC615
1U_0402_6.3V6K
2

+3VS
Note:Iload(max)=3A
PU602

1
APL5930KAI-TRG_SO8
6 @ PC617
5 VCNTL 3 0.022U_0402_16V7K 1U_0402_6.3V6K
+1.8VS_6511

2
9 VIN VOUT 4
VIN VOUT
1
1

B
PC610 8 B
EN
1

Note:Iload(max)=3A
PC611

7 2

22U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6K PR609
GND

POK FB 20K_0402_1%
2

FB=0.8V VGA@ PU603


2

1
PC613

PC612
APL5930KAI-TRG_SO8
1

@ PR610 FB_1.8VS_6511 6
0_0402_5% 5 VCNTL 3

0.022U_0402_16V7K
+1.8VSDGPU
2

2
9 VIN VOUT 4
27 6511_PWR_EN 1 2 +1.8VS_6511_ON @
VIN VOUT
1

1
1

VGA@ PC620
VGA@ PC618 8
EN
1

1
7 2

22U_0805_6.3V6M

22U_0805_6.3V6M
PR611 4.7U_0603_6.3V6K VGA@ PR614

GND
POK FB
1

@ PR612 15.8K_0402_1% 20K_0402_1%

2
FB=0.8V

VGA@ PC621
@ PC616 22K_0402_5%
2

PC622
0.1U_0402_25V6
2

1
FB_1.8VSDGPU
2

2
43,44,47 VGA_PG @

1
1
VGA@ PR616
@ PR617 15.8K_0402_1%
22K_0402_5%

2
Ien=10uA, Vth=0.3V, notice

2
the res. and pull high
voltage from HW

A A
Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VSP/+1.8VSDGPU/+1.8VS_6511
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 45 of 52

http://sualaptop365.edu.vn
5 4 3 2 1
5 4 3 2 1

51622_VREF

1
150K_0402_1% 100K_0402_1%

39K_0402_1% 274K_0402_1%

392K_0402_1% 8.87K_0402_1%
1

1
PH705

PR702

PR703

PR704
100K_0402_1%_TSM0B104F4251RZ
CPU_B+
B value:4250K Close MOS.
EMI@ PL701

2
PC748 @ HCB2012KF-121T50_0805

2
PR708 4700P_0402_25V7K 2 1 B+

2200P_0402_50V7K
10K_0402_1% 1 2

1
2 1 THERM

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

68U_25V_M_R0.36
1

PR705

PR706

PR707

1
PC747 +

PC702

PC703

PC709

EMI@ PC704

@EMI@ PC705

PC706
0.1U_0402_25V6 PR709 PR710
D 2 1 392K_0402_1% 56K_0402_1% D

2
1 2 1 2 2
@ PR711 @
10K_0402_1%
1 2 SLEWA OCP-I

1
PR712 B-RAMP
39K_0402_1% EMI@ PC749
2 1 F-IMAX 1000P_0402_50V7K

2
O-USR PU702
PR713 CSD97374CQ4M_SON8_3P5X4P5 +CPU_CORE
10K_0402_1% PR701 2.2_0603_5% 5 1 SKIP#
CPU_B+ 1 2 VBAT 2 1CPU_BOOT1 6 VIN SKIP# 2
+5VS PL702
PC701 0.1U_0603_25V7K BOOT_R VDD 3 0.22UH_PCMB104T-R22MS_35A_20%
1 2CPU_BOOT1-1 7 PGND1 4 CPU_PHASE1 1 4
PWM1 8 BOOT VSW
9 PWM

1
CSP1-1 2 3

680P_0402_50V7K 4.7_1206_5%
PGND2

EMI@ PR714
PC740

1
1U_0603_10V6K DCR:0.82mΩ±5%

2.21K_0402_1%
2

PR715
PR716

1 2
24.9K_0402_1%

2
1 2
16

15

14

13

12

11

10

EMI@ PC714
PH702 PR717
10K_0402_1%_TSM0A103F34D1RZ
VBAT

IMON
THERM

OCP-I

O-USR
SLEWA

B-RAMP

F-IMAX

2
3.01K_0402_1%
1 2 1 2
CSP1 17
CSP1 VR_ON
8
VR_ON 11 Close choke.
PC711 B value:3435K
CSN1 18 7 SKIP# 0.1U_0402_25V6
CSN1 SKIP#

1
@ PR718 0_0402_5% 1 2
2 1 19 6 PWM1 PR734
@ PR719 0_0402_5% CSN2 PWM1 10K_0402_1% PC712
1 2 20 PU701 5 0.082U_0402_16V7K
C CSP2 PWM2 C
1 2 CSN1

2
+3VS 21 TPS51622RSM_QFN32_4X4~D 4
PU3 N/C CSP1
22 3
N/C PGOOD VGATE 11,8
@ PR721 0_0402_5%
11 VSS_SENSE 1 2 GFB 23
GFB VDD
2 VDD 2 1 +3VS Use X7R is better or far away inductor.

2
@ PR722 0_0402_5%
Maximum current: 32A
VR_HOT#

ALERT#

1 2 24 1
DROOP

11 VCC_SENSE VFB @ PR724 @ PR725


VFB VDIO
COMP

1
VREF

VCLK

0_0402_5% 2K_0402_1%
GND

PAD
V5A

PC746
1U_0402_6.3V6K

1
25

26

27

28

29

30

31

32

33

+1.05VS_VTT

75_0402_1%

130_0402_1%
54.9_0402_1%

0.1U_0402_25V6
1

1
PR729

PR730

PR731

PC741
Close to PWR IC
DROOP

2
COMP

PC742 @
51622_VREF

2
100P_0402_50V8J
2 1

PR726 PR727 VR_SVID_DATA 11


10K_0402_1% 3.48K_0402_1%
2 1 2 1 VR_ALERT# 11

VR_SVID_CLK 11
1

PC743 PR728 PC744


1500P_0402_50V7K 10K_0402_1% 0.33U_0402_10V6K
VR_HOT# 34
2 1 1 2
2

V5A 2 1 +5VS
PR732
22_0603_5%
1

B PC745 B
2.2U_0402_6.3V6M Consider use 0603 for inrush power.
2

VIN 12V-20V
MAX current 32A
Thermal current 10A
Dynamic current 27A
Over current level 45A
Switching frequency 600KHz
Boot voltage 1.7V
DC Load- line 2m Ohm

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic

http://sualaptop365.edu.vn
Date: Tuesday, March 26, 2013 Sheet 46 of 52
5 4 3 2 1
5 4 3 2 1

VGA Chipset Default VID6 VID5 VID4 VID3 VID2 VID1 VID0 +VGA_B+ VGA@EMI@ PL801
HCB2012KF-121T50_0805
Voltage 2 1 B+
AMD 0.9V 0 1 1 0 0 0 0

2200P_0402_50V7K
VGA@EMI@ PL803

0.1U_0603_25V7K
MARS XT

10U_0805_25V6K

10U_0805_25V6K
HCB2012KF-121T50_0805

@EMI@ PC801

VGA@EMI@ PC802

VGA@ PC803

VGA@ PC804
2 1

1
18
18
18
18
18
GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1

2
MDU1516URH_POWERDFN56-8-5
5
@ PR801
0_0402_5% +3VSDGPU
D D

VGA@ PQ803
1 2
38 VGA_ON_R

1
@ PC805 4
0.1U_0402_25V6

2
VGA@ PR802 VGA@ PC806
@ PR803 2.2_0603_5% 0.22U_0603_10V7K

3
2
1
1

1
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
VGA@ PR845

VGA@ PR843

@ PR841

@ PR839

@ PR837
1_0402_1% BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 VGA@ PR848
1 2 2.2_0603_5%
18 GPU_DPRSLPVR UGATE2_VGA 1 2 UGATE2-1_VGA VGA@ PL804

1
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
@ PR804 PHASE2_VGA 1 2
+VGA_CORE

2
0_0402_5%
GPU_VID_1 V2N_VGA

MDU1511RH_POWERDFN56-8-5
5

10K_0402_1%
VGA@ PR806

VGA@ PR807
GPU_VID_2

3.65K_0402_1%
2

1
DCR: 0.97mΩ±5%

VGA@ PR808
GPU_VID_3
7x7x4

1_0402_1%
GPU_VID_4

VGA@ PQ804
GPU_VID_5
VGA@ PR809
LGATE2_VGA 4 VGA@EMI@ PR805 10K_0402_1%

2
1

1
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
@ PR846

@ PR844

VGA@ PR842

VGA@ PR840

VGA@ PR838
4.7_1206_5% 1 2V1N_VGA

VSUM+_VGA VSUM-_VGA

3
2
1

1
2

2
VGA@EMI@ PC807 ISEN2_VGA
680P_0402_50V7K

2
+3VSDGPU
1

10K_0402_1%
VGA@ PR814

VGA@ PC808
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

C C
1 2
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
2

VGA@ PR810 30
100K_0402_1% BOOT2 29
VGA@ PR811 1 UGATE2 28
43,44,45 VGA_PG PGOOD PHASE2
47K_0402_1% +3VS 1 2 2 27 @ PR812
2 1 3 PSI# VSSP2 26 @ PR813 0_0402_5%
4 RBIAS LGATE2 25 0_0402_5% 2 1
VR_TT# VCCP +5VS
5 24 2 1
6 NTC PWM3 23
VW LGATE1
7
COMP VSSP1
22 VGA_CORE
8 21
5.9K_0402_1%

FB PHASE1 Freq.=400KHz
VGA@ PR815

1000P_0402_50V7K

1 2 9
ISEN3 Imax=27.00A
1

UGATE1
VGA@ PC811

10
BOOT1
ISUM+

ISEN2
1

1
ISEN1

ISUM-
VSEN

Ipeak=40.50A
IMON

@ PC809 VGA@ PC810


VDD
RTN

VIN

33P_0402_50V8J 41 1U_0603_10V6K
AGND Iocp=49.00A
2

VGA@ PU801 LL= disable


2

11
12
13
14
15
16
17
18
19
20

VGA@ PR816
499_0402_1%
ISL62883CHRTZ-T_TQFN40_5X5 Cesr= xx mOHM
1 2 1 2
@ PR817
VGA@ PC812 0_0402_5%
VGA@ PC813 470P_0402_50V7K 2 1 +5VS
47P_0402_50V8J
1 2 1 2 @ PR819
VGA@ PR818 0_0402_5%
3.57K_0402_1% 2 1 +VGA_B+
ISEN2_VGA
1 2 1 2 VGA@ PR821
ISEN1_VGA 1_0402_1%
VGA@ PC814 VGA@ PR820 2 1 +VGA_B+
+5VS
150P_0402_50V8J 324K_0402_1%
0.22U_0402_10V4Z

0.22U_0402_10V4Z
1

1
VGA@ PC815

VGA@ PC816

VGA@ PC817

VGA@ PC818
1U_0603_10V6K

0.22U_0603_25V7K
2

MDU1516URH_POWERDFN56-8-5
B B

10U_0603_25V6M

10U_0603_25V6M
BOOT1_VGA

VGA@ PC819

VGA@ PC820
1

1
VGA@ PQ801
VSUM-_VGA VGA@ PR847
2.2_0603_5%

2
VGA@ PR823 UGATE1_VGA 1 2 UGATE1-1_VGA 4
10_0402_5%
1 2
+VGA_CORE VSUM+_VGA
VGA@ PR824 VGA@ PC821
2.2_0603_5% 0.22U_0603_10V7K

3
2
1
2 1 BOOT1_1_VGA 1 2
1
82.5_0402_5%

2.61K_0402_1%

VGA@ PL802
VGA@ PR826

20 VCC_GPU_SENSE S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A


1

@ PR827

PHASE1_VGA 1 2
+VGA_CORE
0.22U_0603_16V7K

0.1U_0603_25V7K
1

VGA@ PC823

@ PC824

V1N_VGA
2

MDU1511RH_POWERDFN56-8-5
1

5
11K_0402_1%

10K_0402_1%
VGA@ PR828

VGA@ PR831
VGA@ PC822
1

1
330P_0402_50V7K DCR: 0.97mΩ±5%
2

1
7x7x4

VGA@ PR830

VGA@ PR832
330P_0402_50V7K

3.65K_0402_1%
VGA@ PQ802

1_0402_1%
@ PC825

0.01U_0402_25V7K

2
1

VGA@ PR833
2
@ PC827

LGATE1_VGA 4 VGA@EMI@ PR829 10K_0402_1%

2
1

4.7_1206_5% 1 2V2N_VGA
2

2
2

VGA@ PC826 VGA@ PH801


1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
2
1

3
2
1
20 VSS_GPU_SENSE VSUM-_VGA
2

1
VSUM+_VGA
Layout Note:
VGA@EMI@ PC828
VGA@ PR835 VGA@ PR836 Place near Phase1 Choke 680P_0402_50V7K

2
10_0402_5% 953_0402_1% ISEN1_VGA
1 2 1 2 VSUM-_VGA

A A
1

VGA@ PC829
0.1U_0402_25V6
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+GPU_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

http://sualaptop365.edu.vn
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, March 26, 2013 Sheet 47 of 52
5 4 3 2 1
5 4 3 2 1

PWR Rule
CPU DCLL=1.5m ohm dedign 330uF/9m *0, 22uF *30 +CPU_CORE

1
22U_0805_6.3V6M
PC902

22U_0805_6.3V6M
PC903

22U_0805_6.3V6M
PC904

22U_0805_6.3V6M
PC905

22U_0805_6.3V6M

22U_0805_6.3V6M
PC907

22U_0805_6.3V6M

22U_0805_6.3V6M
PC909
@ @

PC906

PC908
2

2
D D

For BOT side

1
22U_0805_6.3V6M
PC920

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC924

22U_0805_6.3V6M
PC925

22U_0805_6.3V6M
PC926

22U_0805_6.3V6M
@ @ @

PC921

PC922

PC923

PC927
2

2
+CPU_CORE

1 1 1 1 1 1 1 1

22U_0805_6.3V6M
PC934

22U_0805_6.3V6M

22U_0805_6.3V6M
PC936

22U_0805_6.3V6M
PC937

22U_0805_6.3V6M
PC938

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@

PC935

PC939

PC940

PC941
2 2 2 2 2 2 2 2

For TOP side


C 22u *25, @*7 C
1 1 1 1 1 1 1 1

22U_0805_6.3V6M

22U_0805_6.3V6M
PC950

22U_0805_6.3V6M
PC951

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC955

22U_0805_6.3V6M
@

PC949

PC952

PC953

PC954

PC956
2 2 2 2 2 2 2 2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
5
http://sualaptop365.edu.vn
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2 Date: Tuesday, March 26, 2013 1 Sheet 48 of 52
A
B
C
D
2 1 2 1

VGA@ PC1039 VGA@ PC1028

5
5

+VGA_CORE
22U_0805_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1
+VGA_CORE

VGA@ PC1040 VGA@ PC1029 VGA@ PC1019 VGA@ PC1009 VGA@ PC1001
22U_0805_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1041 VGA@ PC1030 VGA@ PC1020 VGA@ PC1010 VGA@ PC1002
22U_0805_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1042 VGA@ PC1031 VGA@ PC1021 VGA@ PC1011 VGA@ PC1003
22U_0805_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1043 VGA@ PC1032 VGA@ PC1022 VGA@ PC1012 VGA@ PC1004
22U_0805_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1

VGA@ PC1033 VGA@ PC1023 VGA@ PC1013 VGA@ PC1005


10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1

VGA@ PC1034 VGA@ PC1024 VGA@ PC1014 VGA@ PC1006


10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1
2
1
+

4
4

VGA@ PC1035 VGA@ PC1025 VGA@ PC1015 VGA@ PC1007


2.2U_0402_6.3V6M 560U_2.5V_M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
2
1
+

VGA@ PC1036 VGA@ PC1026 VGA@ PC1016 VGA@ PC1008


10U_0402_6.3V6M 560U_2.5V_M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1
1
+

2@

VGA@ PC1037 PC1027 VGA@ PC1017

Issued Date
10U_0402_6.3V6M 330U_D2_2.5VY_R9M 2.2U_0402_6.3V6M
2 1 2 1

Security Classification
VGA@ PC1038 VGA@ PC1018
10U_0402_6.3V6M 10U_0402_6.3V6M

2012/07/10
meet ripple
AMD MARS
AMD MARS
GPU_CORE

3
3

22uF*5+10uF*11
10uF*8+2.2uF*16
560uF*2+330uF*1

http://sualaptop365.edu.vn
Compal Secret Data
Deciphered Date
2013/07/10

2
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title

Date:
Custom
Size Document Number

Tuesday, March 26, 2013


VGA_CORE CAP

1
1

Sheet
49
Compal Electronics, Inc.

of
V5WE2 M/B LA-9531P Schematic
52
Rev
0.1
A
B
C
D
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2


for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
PR801 change to 20K
Add PC805, PR814
D
1 Tune VGA sequence Tune VGA sequence VGA Delete PR615, PC619, PR511, PC513, PR530, 11/06 DVT
D
PR531, PC530
2 Module Design Module Design change 3/5V solution 3/5V 11/13 DVT
3 Change RTC type to non-charge 39 Un-pop PR112, PR113 11/13 DVT
Recovery at PVT phase
4 Check no need keep with HW 39 Delete PR112, PR113, PBJ101 11/20 DVT
Add PR518, PC522, PR714, PC714, PR829, PC828,
5 EMI request EMI PR806, PC807, PC749 11/20 DVT
Change PR701 to 2.2

6 EMI request EMI confirm remove EMI Delete PL102, PC103, PC101, PL202, PC201 and PL703 11/26 DVT
7 Costdown 42 Change PL402, PL403 from 5x5x3 to 7x7x3 12/13 DVT2
8 SY8208B/C update 42 Add PR411, PR413 12/22 DVT2
+1.05V ripple close Add PC609 into 4700P
9 Adjust output voltage and add Cff 45 12/22 DVT2
upper and mean too low Change PR608 from 133K to 127K
Change PR801 from 20K to 0
10 VGA_CORE can't disable Modify VR_ON to VGA_ON_R net 47 01/04 DVT2
Reserve PC805
11 Improve CPU transient character 46 Change PR709 from 150K to 390K, PR732 from 10 to 22,
PC745 from 1U to 2.2U, PC711 from 0.082U to 0.1U
01/09 DVT2
12 Improve CPU transient character 48 Unpop PC902 01/09 DVT2
C C

13 Tune sequence 42 Change PC428 from 4700p to 10n, 02/04 PVT


PC427 from 0.047u to 6.8n
14 0 ohm reduce Change PR801,PR507,PR513,PR523 to R-pad 02/22 PVT
15 To meet MARS/AMD ripple SPEC 49 Add PC1028~PC1043 02/22 PVT
16 Provide 3/5V PG signal to EC 42 Add PR416 02/22 PVT
17 EMI request Modify H-Gate resistor 47 Change PR847, PR848 from 0 to 2.2 02/25 PVT
18 ESD request 39 Add PC101 into 0.1uF 02/26 PVT
19 ESD request 43 Add PC521, PR503, PC507 02/26 PVT
20 Use HW to control VCIN1 function 40 Add PR204 03/05 PVT
Change PC303,PC304,PC315,PC318,PC517,
21 ME issue Shrink component to reduce Z height 03/26 PVT2
PC819,PC820 from 0805 to 0603

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 50 of 52
5 4 3 2 1
A B C D E
1123A------------------- 1107A-------------------
A --> B1 Change List 1.Delete +3VALW to +3VALW_PCH MOS Circuit:
Page12, Delete C589,C414,R77,Q10,C590,C591
1. Page04, Move R25 to JXDP1.60
Update U1 option component for CPU
1203A------------------- Page34, Delete U28.16 PCH_PWR_EN# off page 2. Page6,8, Change EC_SMI from GPIO77 to GPIO34
1.Page11, R169 change to @ 2.Page12, Unpop R210 ,Pop L3 and C22 for +1.05VS_VTT high ripple Delete R445
2.Page36, Mound R417 (Cancel AMIC@) 3.Unpop and Componment reduce----------------------------- 3. Page07, Change Y2 to X3G024000DC1H(SJ10000CS00)
3.Page18, R898, R899, R409, D22 change BOM Structure to VGA@ Page16, Delete C824,C828,C831,C836,C839 for unpop reduce. 4. Page08, U17, U43, R310 change to @
4.Page34, R485, R483 change to 9012@ Page20, Delete C870,C871,C923,C922,C921,C920 for unpop reduce. Mount R65
R479, R478 change to 940@ Page27, Change R399,L30,L47 TO R_Short R310.1 change to +3VS
5.Page35, C663, SW4, SW5 change to 9012@ Delete C456,C637,C474,C497,C580,C581 5. Change all 932@ to 940@
6.Page19, Delete R1035, X7601/X7603/X7604 Pop R80 and unpop R396,Q25,C411,R584,Q52 R161, D29, R564, U6, R569, C522, C523, C552, D36, Q39, R522,R586, R589, R607,
7.Page17, R1006 change to VGA@ Page28, Delete C606,C646,C607 R610, R624, R693, U41, U44, C516, C518, D28, R146, R158, R159, R160, R496, R499,
8.Page09, R306 add BOM structure UMA@ Change R239 to R_short R504, R507, R508, R511, R601, U28, U29
1 1
9.Page06, C153, C154 change to 15P_0402 Page29, Delete C775,C776,C778,C781,C782 6. Page11, R169 change to XDP@
10. Page18, C848, C849 change to 12P_0402 Page31, Delete C461,C462 7. Page12, add C414 and change PCH_PWR_EN to PCH_PWR_EN#
11.Page07, C2, C3 change to 10P_0402 Change R423 to R_short delete Q33, R561, R563
1129A------------------- Page32, Delete C161 8. Page16, delete R58, R298, R300, C163, R299, R302
1.Page32, JODD1.11 Reserve a TestPoint for DFT Change R308 to R_short 9. Page17, Add option component (U51) for SUN_XT
2.Page29, Pop C779, C783 Page34, Change R495 to R_short 10. Page19, Add R900, R901 with BOM structure @
3.Page17, Update U51 BOM Structure for BOM Select Page36, Chagne L55,L54,L52 to R_short 11. Page24, delete R405, U20, R362, R401, C164
4.Page04, Add QDJC@ BOM Structure for U1 4.Page24, SWAP RP41.1,RP41.2 Change U8 to G5243AT11U(SA000028Y10)
1128A------------------- 5.Page27, Change R123,R127 Pull high to +HDMI_5V_OUT 12. Page25, delete R367, D7, F1, D8, D19
1.Page18, Add D22 to prevent GPU_ACIN leakage 1122A------------------- 13. Page26, change L47, L48 to BLM18AG121SN1D(SM010030010)
2.Broadcom recommend modify(Add componment Function Field is 45.1) 1. Page22, Add X7603@ for VRAM 2Gb*4 HYN 128M16 14. Page27, Delete D31, F2, C450
Page29, Add C803 0.1uF to U48.20(VDDO_CR), Add X7604@ for VRAM 2Gb*8 HYN 128M16 15. Page28, Delete R781, D23, R782, R785, U49, C803
Page29, Add L74(BLM31PG601SN1) between Q6.1 and +3V_LAN 1121A------------------- 16. Page29, Delete R792
Add C820 (1uF) to Q6.1 1. Page06, Add R937 for EC_SCI# Path to GPIO34 change T1 to GST5009-E (SP050006B10)
Page30, Add L75(BLM31PG601SN1) between Q9.1 and 2. Page09, RP28.5 connect to GPIO34 17. Page30, delete R414, C166
+XDPWR_SDPWR_MSPWR 1120A------------------- R438, Q20 change to @
Add C820 (1uF) to Q9.1 1. Page06, Delete chargeable RTC circuit Change U9 to G5243AT11U(SA000028Y10) with BOM@
3.Page18, Change L69 to R_Short Change ODD to SATA port1 18. Page31, delete R595, R587, Q34, R597, R596, R562
4.Page20, Change L72 to BLM18AG121SN1D (the same to L71) Page32, Modify ODD SATA netname to SATA port 1 . 19. Page32, Change U25 to SY6288D10CAC_MSOP8(SA00004KB10)
5.SW confirmed function Change JUSB1 to OCTEK_USB-09EAAB(DC233008O20)
Page08, unpop R245,d21 (ACPRESENT tp PCH no need) 2. Page29, +1.2V_LAN_OUT add 680P for EMI Delete R472, R469, R460, R462, C635, U46, R459, R463, R464
Page36, unpop R529 (EC_BEEP no need) 3. Page37, Modify H21 from 2P5 to 3P0 20. Page33, Mount R503
6.Default EC_SCI# to GPIO34 4. Page38, Add 2 jump for power cousumption measure Change R506 to 8.2K
Page06, Pop R937 J36(+3VS),J37(+5VS) Change R509 to R_Short with BOM @
Page09, Unpop R66 5. Delete XDP port and related circuit Delete R491, R493, D20
2
7.Reserve DGPU_HOLD_RST# direct to PLTRST_VGA# path Page04, Delete C63,C64,C96,C97,C98,R20,R21,R22,R23,R27~R31 21. Page34, add R535 (100K_0402) 2

Page08, Add R405 0ohm connect DGPU_HOLD_RST# and PLTRST_VGA# Delete R3,R86,R87,R88,R89,R90,R91,R4,C92,C93 Mount R632
8.Page35, Chagne R702 to 680ohm (ME confirm) Delete R5,R14,R15,R16,R7,R19,R25,C35,JXDP1 21. Page35, L51 change to BLM18AG121SN1D(SM010030010)
9.Page35, Delete SW1 (debug) for Layout convenience Page07, Delete R66,R67 Change JMIC1 to ACES_88266-02001(SP020008Y00)
10.Page24,Change L6 to (4.7uH_SH00000GS00) same as Q5WV8 6. ESD DVT Modify: Delete R143, R668, R162, R181, C719, R671
11.Page29,Change RP22 to R768,R769,R770.R771 for SD 3.0 EMI Page08, Delete C39 23. Page37, delete R424, C169
1127A------------------- Page24, Delete D6 Change U12 to G5243AT11U(SA000028Y10)
1.Page24, Change U50.11 connect from L6.2 to L6.1 Page28, Delete D7,D18 24. Page43, SW1 change BOM Structure to @
2.Page34, Change R502 from R_short to 940@ 0ohm Page30, Delete D38 1015A-------------------
3.Page36, Change R237,R238 to 60 Ohm(Codec vendor recommend) Page33, Delete D16 1. Modify BOM Structure/Function Field for EMC@(45.1)
4.Page09, Add R67 for EC_SCI# -> GPIO 10 option Page35, Delete D25,D30,D34 Page06, RP14
1126A------------------- Page36, Delete D26,R544,C572 Page07, RP19, R390
1.Page36, Delete D26 (ESD Confirm) Page37, Delete ESD TP JUMPs: Page24, L11
2.EMI part Schematics modify(EMI confirm1123) J10,J20,J17,J21,J16,J19,J18 Page25, R368, R369, R370, R371, R372, R373, R374, R375
Page26, Change R368,R369,R370,R371,R372,R373,R374,R375 to 0403 J22,J24,J28,J25,J29,J23,J27 Page27, L42, L45, L46,R175, R180
R_short J26,J30,J31,J33,J32,J34,J35 Page28, R774
Page28, Change R175,R180 to 0603 R_short Page29, C786 change to EMC@ Page29, R897, C814, D39
Page36, Change L36,L38,L51,R527,R528,R532,R533 to 0603 R_short Page04, Add C96 to DIMM_DRAMRST# Page32, L24, L25, R458, R461
Page32, Delete C408,C398 Page33, C487 change to EMC@ and 0.1uf Page35, R527, R528, R532, R533, L36, L38, D1, C62
Page33, Delete R453,R455,R456,R457 Delete D4 2. Modify BOM Structure/Function Field for XEMC@(45.1)
3.Page38, Change 3/5 VS circut BOM Structer to 35V@ Page26, C378 change to EMC@ Page04, C63, C64, C96, C97, C98, C94, C95, C60, C92, C93, C35
4.Page32, Modfiy JHDD1 to LTCX004LGA0 (S H-CONN CCM C387 change to EMC@ Page07, R104, C152, R402, C453
C127043HR022M27FZR 22P H3.05 HDD) 1119A------------------- Page08, C39
Modfiy JODD1 to LTCX004HZ00 (S H-CONN SANTA 20190X-X 13P 1. Page06, Add a nochargeable RTC battery. Page24, C528, C549, C364, C365, D6
H3.6 ODD) 2. Page15, Add R191 for DDR_VTT_PG_CTRL pull high +5VS option. Page25, D2, L13, L14, L15, L16
3 3. Add page24, Reserve eDP to LVDS translator (RTD2132R) Page28, C792, C786 3
Add bom structure TL@(translate) and EDP@(eDP mode) Page29, R26, C26, C806, C807, C808, C809, JP1, JP2, D38
4. Page25, Add R947 for ENVDD option. Page31, C408, C398
Add connect TL_INVT_PW to INVTPWM Page32, D15, D16, D4, C487, R453,R455, R456, R457, L26
Add connect RTD2132R TL_HPD to EDP_HPD Page33, R477, C501, R513, C520, C506, C507, C511
Modify JLVDS1 pin net name fo Co-Lay eDP & LVDS Page34, C551, C553, D25, D30, D34
Page35, R548, C573, R671, C719, C556, C550, C444, C445, D27, D37, D26, R544, C572
Page36, C630
3. Modify Function Field to 45.1 only (BOM Structure is same as before)
Page04, R27, R28, R29, R30, R31
Page07, RP20
Page33, R160
Page35, R143, L51
4. Display BOM structure and Value of U1 (CPU)
5. Display BOM structure of R0402_0OHM-NEW and R0603_0OHM-NEW (R Short Pad show BOM Structure @)
6. Page08, Update note of GPIO66

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 26, 2013 Sheet 51 of 52
A B C D E
A B C D E

C --> Pre-MP Change List


B1 --> B2 Change List B2 --> C Change List
0411---------------------
0114---------------------------- 0306--------------------- 1. Change U51 PN to R3 (SA00006G610, SA000061J20)
1.Page03, Add U1 with QDJA@ 1.Page27, Mount R410, R411 2. Page06, unmount R446, C168, D32
2.Page30, R897 change to SM01000LU00 Change R240, R241 with @ Mount D23, C151
3.Page24, L63,L73 change to SM01000EJ00 Change R418 to 4.7K 0329---------------------
4.Page25, L11 change to SM01000EJ00 0304--------------------- 1.Page04, Add SR16Q@ and SR170@ for U1
5.Page36, L33 change to SM01000EJ00 1.Page20, Mount C872, C873, C874, C889, C917, C918, C919 2.Page06, Change C151, D23 with @
6.Page31, U9, C165 with IOAC@ 2.Page25, change C371,C372, C369, C370 with EDP@ Mount R446, D32, C168
1
0110---------------------------- 3.Page33, Change L24, L25 to SM070001E00 0326--------------------- 1
1.Page32, Delete R312,R313,R314,R315 0301--------------------- 1.Page1, Change PCB PN to DA60000XL10
Add C392,C393,C391,C394 with EA50@ 1.Page08, change R62,R65 to 0 ohm 2.Page29, Mount C815
2.Page27, Add C35 2.Page12, Add C408 Update Power Schematics
3.Page38, Delete Q45,R570,R571 3.Page34, Add D25 0321---------------------
0108---------------------------- Reserved D26 1.Page8, G_SEN_INT change from GPIO80 to GPIO52.
1. Page33, R458, R461 change to R0402_0OHM-NEW 0227--------------------- 2.Page34, change R506 to 100K_0402_5%
Add JFP1 1.Page29, Del R766
2. Page26, Delete L13, L14, L15, L16 2.Page32, change JDB1 to E-T_1001K-F50C-05R_50P-S
3. Page29, Delete C792, C99 0226B--------------------
4. Page31, Delete J4 Modify for ESD
5. Page10,25 change Touch screen port from USB port 5 to port6. 1.Page11, Mount C13,C14 (10U_0603)
6. Page25,34 change net name of TS_INT to TS_EN 1.Page12, Change C40 to 10U_0603
7. Page10 add USB port 5 for Finger Print Mount C31 (1U_0402)
8. Page38, Add C19 3.Page15, Mount C117 (10U_0603)
9. Page26, Add C396, C398 Add C161 10U_0603
10.Page36, Mount C554 4.Page33, Mount C483 with 0.1U
11.Page38, Mount C979 Reserved D3 with XEMC@
12.Page35, Reserved SW6,SW7,SW8,SW9 5.Page38, Add C39, C64,C92,C93 22U_0805
13.Page32, Add C534, C535, C536, C537 for JHDD2 with BA51@ Update power schematics
change C391,C392,C393,C394 to R312,R313,R314,R315 0226--------------------
Update Power schematics 1.Page12, Del T99
0107---------------------------- 2.Page27, Mount R204,R241, R407,R408
1. Page06, R937 change to R0402_0OHM-NEW Change R412,R413 with @
R75 change to R0603_0OHM-NEW 3.Page28, Add R312 with @
2. Page07, R108 change to 15_0402_5% with 1ROM@ 4.Page34, Del R590 (Add offpage for H_PROCHOT#_EC)
2 RP19 change to 15_0804_8P4R_5% with 1ROM@ Del R505 2
Add R105, R106 with 1ROM@ for PCH_SPI_IO2_1, PCH_SPI_IO3_1 Update Power Schematics
Change R102, R103, R109, U7, C67, PR20 to 2ROM@ 0221--------------------
3. Page08, R62, R65 change to 0402_0OHM-NEW 1.Page18, R898, R899 change to R0402_0OHM-NEW
4. Page10, Change Touch Screen USB port frum Port3 to Port5. 2.Page25, Add TS@ for R81, R414, R426
R155 change to R0603_0OHM-NEW
5. Page24, Change Q53 to @ 0219--------------------
6. Page25, R947,R363,R949 change to R0402_0OHM-NEW 1.Page08,34,37 G_SEN_INT connecto to PCH_GPIO80
Add C376,C377,C388,C389 with TL@ Change U2.4, U2.6 to D_CK_SCLK/D_CK_SDATA
Add R414, R426 2.Page29, Reserved C815
Add R424, R425 with @ 3.Page22, Add C1024, C1025, C1026, C1023, C1027, C1028, C1029, C1030 with 128@
7. Page27, R80 change to R0603_0OHM-NEW 4.Page23, Add C1031, C1032, C1033, C1034, C1038, C1036, C1037, C1035 with VGA@
L48 change to R0603_0OHM-NEW 5.Page38, Reserved R556, R574, Q55, R557, R575, Q41, R570, R571, Q45
8. Page29, C99 change to XEMC@ 0218--------------------
R774 change to 56_0402_5% 1.Page06, Update Y1 CIS Symbol
9. Page32, R49, R593 change to R0805_0OHM-NEW Add D23, C151
9. Page34, R236 change to R0805_0OHM-NEW Change R446, D32, C168 to @
10. Page38, R926 change to R0402_0OHM-NEW 2.Page18, Change C823, C827, U52, R798 with @
0103---------------------------- 2.Page29, Add R781, C792
1.Page35, R698,R701 change to 680 ohm 3.Page30, Add R782 and Mount C822
R702 change to 499 ohm 2.Page34, Change R506 to 33K
2.Page18, Un-mount C847
3.Page38, Add U38, R77, C63
Update Power Schematics
1228----------------------------
3 1. Page25, Add USB20_P3/N3 on JLVDS1.35/36 3
Add R81
2. Page35, Delete JTP1, R609, R610, C552, R693, R607, R608, D36
3. Page34, change Q50 to L2N7002LT1G_SOT23-3
change R506 to 18K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS V5WE2 M/B LA-9531P Schematic
http://sualaptop365.edu.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 26, 2013 Sheet 52 of 52
A B C D E

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