BSC3153

Nokia GSM/EDGE BSS, Rel. BSS13, BSC and

TCSM, Rel. S13, Product Documentation, v.1

CLS

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The information in this document is subject to change without notice and describes only the
product defined in the introduction of this documentation. This documentation is intended for the
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contained in the document are adequate and free of material errors and omissions. Nokia
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Copyright © Nokia Siemens Networks 2008. All rights reserved.

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 Contents

Contents

Contents 3

List of tables 4

List of figures 5

Summary of changes 7

1 CLS overview 9

2 Logical structure of CLS 13

3 Mechanical structure of CLS 15

4 Plug-in units of CLS 17

5 Operation of CLS 19

6 CLOC and CLAB cartridge intermediate cabling 21

7 Power consumption of CLS 27

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List of tables

Table 1. Power Consumption of CLS 27

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 List of figures

List of figures

Figure 1. Operating environment of the CLS 10

Figure 2. Block diagram of the CLS 13
Figure 3. Two CLxTG plug-in units in the CLOC cartridge 15
Figure 4. Two CLAB plug-in units in the CLAC cartridge 16
Figure 5. Connector points associated with the Clock Equipment in the CLOC
cartridge. 22
Figure 6. Intermediate cabling connectors associated with the Clock Equipment in
the CLAC cartridge 24

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 Summary of changes

Summary of changes

Changes between document issues are cumulative. Therefore, the latest

document issue contains all changes made to previous issues.

Changes made between issues 3-0 and 4-0

Editorial changes made.

Changes made between issues 2-2 and 3-0

Modular structure modified.

Figures describing the front panels of the plug-in units added.

Changes made between issues 2-1 and 2-2

Online structure improved.

Changes made between issues 2-0 and 2-1

Figure DN01195492 has been replaced with figure DN9834199 in section

Mechanical structure.

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 CLS overview

1 CLS overview
Main functions of CLS

The synchronisation unit of the Clock and Synchronisation Unit (CLS) is

synchronised with a synchronisation signal coming from an upper level in
the synchronisation hierarchy of the network. Normally, the
synchronisation signal is extracted from the PCM circuit signal coming to
the network elements. The synchronisation unit generates the basic timing
signals for the units in its own rack needing clock signals. The Clock and
Tone Generator (CLxTG) acts as the synchronisation unit in the exchange.

In applications containing an expansion rack, the timing signals are taken

from the synchronisation unit to the rack-specific Clock and Alarm Buffer
(CLAB). The CLAB uses the timing signals to generate the cartridge-
specific basic timing signals for the units in its own rack.

The CLxTG and CLAB units are duplicated for 2n redundancy.

Operating environment of CLS

The operating environment of the CLS is shown in the figure below.

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SYNCHRONIZATION DATACOMMUNICATIONS
SIGNALS INTERFACE CONTROL BUSES

GSW0 GSW1 CLABs AND HWAT

CL x TG0 CL x TG1 CLAB0 CLAB1

BACKUP BACKUP
UNIT UNIT
INTERFACE INTERFACE
OTHER
*)
CLABs
IN THE SAME
*)
RACK ROW

*)

*)

*) TIMING SIGNAL BUSES

BASIC TIMING SIGNALS FOR BASIC TIMING SIGNALS FOR

THE CARTRIDGES OF BASIC RACK THE CARTRIDGES OF EXPANSION RACK
DN9986652

Figure 1. Operating environment of the CLS

The CLS has the following interfaces with the other equipment:

. synchronisation signal interface

. basic timing signal interface with Clock Generator
. basic timing signal interface with Clock and Alarm Buffer
. datacommunications interface with Clock Generator
. supervision bus interface with Clock and Alarm Buffer
. backup unit interface with Clock Generator
.
backup unit interface with Clock and Alarm Buffer
. timing signal bus interface
.
power supply interface

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 CLS overview

The CLxTG receives the 8 kHz synchronisation signal (TCL) extracted by

the Exchange Terminal (ET) from the incoming PCM circuit signal. The ET
generates the TCL signal by means of the frame alignment time slot in the
incoming PCM circuit signal. The CL1TG contains three and the CL3TG
contains four TCL synchronisation signal inputs.

The CL3TG unit also contains two synchronisation inputs (FS1 and FS2)
for an external synchronisation source. The frequency of the external
synchronisation source can be (N x 4 kHz, N = 2 to 4096). The CL3TG is
automatically adapted to the frequency of the incoming signal.

The CLxTG and CLAB units distribute the basic timing signals in a rack-
specific manner. The cartridge-specific basic timing signal pairs 8M and 8k
are distributed from the units to the rack. One unit contains 15 basic timing
signal pairs. The cartridge-specific cabling used to distribute the basic
timing signals is not duplicated. The active unit sends the basic timing
signal to the common line. The CLxTG handles the clock distribution of the
main rack and the CLAB units handle the clock distribution in the
expansion rack.

The CLxTG is connected to the Operation and Maintenance Unit (OMU)

via the Group Switch (GSW) by means of an HDLC-based control channel
(64 kbit/s). The other end of the control channel is connected to the
Adapter for CCITT no. 7 (AS7), located in the control computer of the GSW
in the exchange. The control messages between the control computer of
the GSW and the OMU are conveyed via the message bus.

The CLAB is connected to the Hardware Alarm Terminal (HWAT) in the

OMU via an HDLC-based asynchronous supervision bus, which is
duplicated for 2n redundancy.

The CLxTG and CLAB normally control the changeover independently.

The changeover occurs based on the hardware alarm data passing
between the halves and the supervision data conveyed on the program-
based message channel. The handshaking signals between the halves
are used in the changeover.

The timing signals (16.384 MHz and 8 kHz) are taken from the CLxTG to
the CLAB along a timing signal bus provided with redundancy. The CLAB
receives the timing signal pair sent by the active CLxTG based on the
changeover signal passing in the bus cable. The CLAB units provide a
wired alarm for the supervised active incoming signal pair to the CLxTG.
The CL3TG has six bus outputs and the CL1TG has four. One bus usually
handles the distribution to the CLAB units in one rack row.

The units in the Clock Equipment generate their own operating voltages
from the battery voltage UB.

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For more information, see

Logical structure of CLS

Mechanical structure of CLS

Plug-in units of CLS

Operation of CLS

CLOC and CLAB cartridge intermediate cabling

Power consumption of CLS

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2 Logical structure of CLS

The Clock and Synchronisation Unit (CLS) consists of the following
functional blocks:

. synchronisation unit
.
clock buffer

The figure below shows a block diagram of the CLS.

SYNCHRONIZATION SYNCHRONI- CLOCK CLOCK

SIGNALS ZATION UNIT BUFFER BUFFER

DN9986664 BASIC TIMING SIGNALS

Figure 2. Block diagram of the CLS

Synchronisation unit

The synchronisation unit is implemented by a CL1TG or CL3TG plug-in

unit. The 16.384 MHz basic timing signal needed by the exchange is
generated in either unit by a temperature-compensated crystal oscillator
(TCXO).

The stabilities of the oscillators in the synchronisation units are presented

in the plug-in unit description of the unit concerned.

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The synchronisation unit also distributes the basic timing signals to its own
rack. The unit is equipped with 15 basic timing signal outputs (8M and 8k)
for this purpose.

Clock buffer

The basic timing signals are distributed to the expansion rack by rack-
specific Clock and Alarm Buffers (CLAB). The CLAB unit receives the
timing signals sent by the synchronisation unit via the bus and uses these
signals to generate the basic timing signal pairs 8M and 8k to be
distributed to the cartridges in the rack.

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3 Mechanical structure of CLS

Mechanically, the CLS is composed of the equipped CLOC and CLAC
cartridges. The duplicated synchronisation unit is installed in the CLOC
cartridge and the duplicated CLAB unit is installed in the CLAC cartridge.
The equipping of the CLOC and CLAC cartridge is shown in the figures
below.

Note

In some first-generation BSCs, the CLS units in the main rack may be
housed in a CLAC cartridge instead of the CLOC cartridge.
CLxTG 0

CLxTG 1

00 03

DN01195492

Figure 3. Two CLxTG plug-in units in the CLOC cartridge

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CLAB

CLAB

00 01 02 03 04 05

DN9834206

Figure 4. Two CLAB plug-in units in the CLAC cartridge

The CLOC and CLAC cartridges are 1/6-shelf wide and their dimensions
(without the cable trough and connector frames) are 120 mm (width) x 262
mm (height) x 260 mm (depth).

The CLxTG and CLAB plug-in units are constructed on printed circuit
boards with the dimensions 233.4 mm x 220 mm. They are connected to
the back panel of the cartridge by two 3 x 32 -pin female connectors and
one 3 x 14 -pin male connector. The Clock and Tone Generator CL3TG is
45 mm wide.

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4 Plug-in units of CLS

For more information on the individual plug-in units of the CLS:

Clock and Tone Generator CLxTG

CL3TG

CL1TG

Clock and Alarm Buffer CLAB

CLAB

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5 Operation of CLS
For more information on the operation of the individual plug-in units of the
CLS, see the following Plug-in Unit Descriptions:

Jumper settings of the plug-in units

Jumper Settings of CL1TG

Jumper Settings of CL3TG

Front panel LED indicators for CLxTG

Operation of CL1TG

Operation of CL3TG, CL3TG-S, CL2TG-S

Front panel LED indicators for CLAB

Operation of CLAB

See also:

CLOC and CALB cartridge internediate cabling

CLOC and CALB cartridge internediate cabling

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6 CLOC and CLAB cartridge intermediate

cabling
CLOC cartridge

The cabling associated with the CLxTG is connected to the connector

points at the rear of the CLOC cartridge. The figure below shows the
connector points for the intermediate cabling connected to the Clock
Equipment in the CLOC cartridge. The figure also indicates the strapping
groups used in the cartridge settings.

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04 03 02 01 00

B04R1 B01R1 B00R1

1 B00R2

B04R3 B02R3 B00R3

3 2 B01R4

B04R5 B02R5

5 4 B01R6

B04R7 B02R7 B01R7

7 6 B01R8

PL2 PL1

13 1 11 1
W2 W1

B04S1 B03S1 B02S1 B01S1 B00S1

9 B03S2 8 B01S2 B00S2

B04S3 B03S3 B02S3 B01S3 B00S3

11 B03S4 10 B01S4 B00S4

W3
B04S5 B02S5 B01S5

13 12 B01S6

B04S7 B02S7 B00S7

W4
15 14 B00S8

04 03 02 01 00

DN9986707

Figure 5. Connector points associated with the Clock Equipment in the CLOC
cartridge.

The power supply cable (UB) to the CLxTG0 unit is connected to

connector point PL1 and to the CLxTG1 unit to connector point PL2.

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 CLOC and CLAB cartridge intermediate cabling

Three synchronization signals from the ET units are connected to

connector points B00R1, B00R2 and B00R3. The fourth synchronization
input when using the CL3TG is connected to connector point B01R1.

The synchronization signals from the external frequency standard when

using the CL3TG are connected to connector points B01S5 and B01S6.

The PCM interfaces with the switch are connected to connector points
B00S7 (switch 0) and B00S8 (switch 1). The changeover signal of the
switch from the switch control computer is connected to connector point
B01R4 (switch 0) and B01R8 (switch 1).

A maximum of four timing signals buses are connected from the CLOC
cartridge to the CLAC cartridges when using the CL1TG and a maximum
of six timing signal buses when using the CL3TG. The bus is terminated in
the CLOC and in the last CLAC cartridge. The cabling is connected to
connector points B00S1...B00S4, B01S1...B01S2 (0-side buses) and
B03S1...B03S4, B01S3...B01S4 (1-side buses).

The basic timing signals going to the cartridges in the rack are cabled from
connector points B02R3, B02R5, B02R7, B02S1, B02S3, B02S5, B02S7,
B04R1, B04R3, B04R5, B04R7, B04S1, B04S3, B04S5 and B04S7.

The supervision buses are connected for termination to connector points

B01R6 (bus 0) and B01R7 (bus 1).

CLAC cartridge

The figure below shows the connector points for the intermediate cabling
connected to the Clock Equipment in the CLAC cartridge. The figure also
indicates the strapping groups used in the settings of the CLAB unit.

Note

The information on connections for the CL1TG units in this section refer
to the special case when a CLAC cartridge is used in the main cabinet
for housing the Clock and Synchronization units. This kind of a
configuration can only be found in some first-generation BSCs.

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04 03 02 01 00

B04R1 B03R1 B01R1 B00R1

B01R2 B00R2

B04R3 B03R3 B01R3 B00R3

B01R4

B04R5 B03R5 B01R5

B01R6

B04R7 B03R7 B01R7

B01R8

W3 W2 W1
X02 X00

PL2 PL1

B04S1 B03S1 B02S1 B01S1 B00S1

B02S2 B01S2 B00S2

B04S3 B03S3 B02S3 B01S3 B00S3

B02S4 B00S4

B04S5 B03S5 B01S5

B01S6

B04S7 B03S7 B01S7 B00S7

B00S8

04 03 02 01 00

DN9986719

Figure 6. Intermediate cabling connectors associated with the Clock

Equipment in the CLAC cartridge

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The power supply cables (UB) to the CLAB0 unit (or CL1TG0, if CLAC is
used in the main rack) are connected to connector point PL1. The supply
cables to the CLAB1 (or CL1TG1) unit are connected to connector point
PL2.

With CL1TG equipping, the synchronization signals from the ET or SSIF

unit are connected to connector points B00R1, B00R2 and B00R3.

With CL1TG equipping, the PCM interfaces with the switch are connected
to connector points B00S7 (switch 0) and B00S8 (switch 1).

The changeover signal cables coming from the switch control computer
are connected to connector points B01R4 (switch 0) and B01R8 (switch 1).

The timing signal bus is connected to the cartridge with CLAB equipping to
connector point B01S3 (0-side bus) and connector point B01S7 (1-side
bus). The bus is chained to the other CLAC cartridge from connector point
B01S2 (0-side bus) and connector point B01S6 (1-side bus).

With CL1TG equipping, the outgoing timing signal buses are cabled from
connector points B00S1, B00S2, B00S3, B00S4 (0-side buses) and
connector points B02S1, B02S2, B02S3, B02S4 (1-side buses). Timing
signal bus 1 is chained to its own cartridge as the incoming bus at
connector points B01S3 (0-side bus) and B01S7 (1-side bus) and further
to the other CLAC cartridge from connector points B01S2 (0-side bus) and
B01S6 (1-side bus).

Supervision bus 0 is connected to connector point B01R2 (outgoing from

cartridge) and B01R3 (incoming to cartridge). Supervision bus 1 is
connected to connector point B01R6 (outgoing from cartridge) and B01R7
(incoming to cartridge).

The basic timing signals to the cartridges in the rack are connected from
connector points B03R3, B03R5, B03R7, B03S1, B03S3, B03S5, B03S7,
B04R1, B04R3, B04R5, B04R7, B04S1, B04S3, B04S5, B04S7.

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7 Power consumption of CLS

The CLxTG and CLAB units generate the needed operating voltages from
the battery voltage UB in their built-in power supply sections. The power
consumption of the units is indicated in the table below.

Table 1. Power Consumption of CLS

Unit Power consumption (-48 V) W

CL1TG 11.5
CL3TG 11.5
CLAB 13.7

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