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Assessment :

Tittle
(1 mark)
Objective
(2 marks)
Methodology (2
UNIVERSITI TEKNOLOGI MARA marks)
KAMPUS TAPAH Presentation of
data
(2 marks)

PHY 340 Discussion (2


marks)
Conclusion (1
marks)
ELECTRONICS Answer to
questions
(2 marks)
References (2
LABORATORY REPORT marks)

TOTAL (14)

NAME
STUDENT ID
MUHAMMAD AZRIN BIN MD YUSOF
2016140235
MUHAMMAD FARIS BIN HAMDAN
2016144763
IMAN NUR ASHRAF BIN NORHASIM
2016351127
MOHD MU’IZZ BIN MOHD SHUKRI
2016326491
Name of lecturer
RAFAEL BIN JULIUS
EXPERIMENT 1 : Basic Logic Gates
Objectives:

 To verify the operation of OR, AND and NOT gates.


 To construct a simple combinational logic circuits.

Equipment /Components

 Hex Inverter IC (7404) -1


 Quad 2 Inputs AND gate IC (7408) -1
 Quad 2 Inputs OR gate IC (7432) -1
 Digital logic trainer -1

Part A: AND Gate

Procedure:

1. The AND gate circuit connected as shown in Fig 1-1.


Note: Pin 7 and pin 14 of IC 7408 connected to GND and +5V respectively.
2. The power supply has been ON.
3. The LED output had been observed when both input switches set to the ‘0’ level.
4. The output for the various inputs combinations recorded as shown in Table 1.
Note: When LED lit, X = 1 and when LED is out, X = 0
5. The power supply had been turned OFF.

Part B : OR Gate

Procedure;

1. OR gate circuit connected as shown in Fig. 1-2.


2. The power supply had been ON
3. The output for the various inputs combinations recorded as shown in Table 2.
4. The power supply had been turned OFF.
Part C: NOT Gate or Inverter

Procedure

1. OR gate circuit connected as shown in Fig. 1-3.


2. The power supply had been ON
3. The output for the various inputs combinations recorded as shown in Table 3.
4. The power supply had been turned OFF.

Part D: Gate Conversions

Procedure:

1. OR gate circuit connected as shown in Fig. 1-4.


2. The power supply had been ON
3. The output for the various inputs combinations recorded as shown in Table 4.
4. The power supply had been turned OFF.
5. OR gate circuit connected as shown in Fig. 1-5.
6. The power supply had been ON
7. The output for the various inputs combinations recorded as shown in Table 5.
8. The power supply had been turned OFF.
Result:

Table 1

INPUTS OUTPUTS
A B X= A . B
0 0 0
0 1 0
1 0 0
1 1 1
Table 2

INPUTS OUTPUTS
A B X= A + B
0 0 0
0 1 1
1 0 1
1 1 1
Table 3

INPUTS OUTPUTS
A ̅
X= 𝑨
0 1
1 0
Table 4

INPUTS OUTPUTS
A B X
0 0 0
0 1 1
1 0 1
1 1 1
Table 5

INPUTS OUTPUTS
A B X
0 0 0
0 1 0
1 0 0
1 1 1
Questions:

1. The output of an AND gate will be high if all of its inputs are high.
2. The output of an OR gate will be low if none of its inputs are high.
3. The logic equation for a 3-inputs AND gate shown is Y = A . B . C

4. The logic equation for a 4-inputs OR gate shown is Y = A + B + C + D

5. ̅
The output of the logic circuit shown below is Y = 𝑨

6. The OR gate is formed by inverting the inputs and output of an AND gate.
7. The AND gate is formed by inverting the inputs and output of an OR gate
8. The power supply voltage for TTL ICs is typically 5 volts.
9. Show the output waveform of the OR gate shown below.

10. Show the output waveform of the AND gate shown below.
Discussion:

According to Table 1, The AND operation is defined as the output as high (1) if all the inputs are high (1).
IC 7408 is the two inputs AND gate. A & B are the input terminals and X is the output terminal. Its logical
equation:

X=A.B

According to Table 2. The OR gate operation is defined as the output is high if one or more than 0 inputs
are high). IC 7432 is the two inputs OR gate. A & B are the input terminals and X is the output terminal. Its
logical equation:

X=A+B

According to Table 3. The NOT gate is also known as Inverter. IC 7404 is the one input NOT and one
output. Its logical equation:

X=𝐴

According to Table 4. The OR gate is formed by inverting the inputs and output of an AND gate.

X=A+B

According to Table 5. The AND gate is formed by inverting the inputs and output of an OR gate
X=A.B

Conclusion:

The objective achieved. Based on the experiment the logical equation was proven by set up circuit as given
by the procedure.
EXPERIMENT 2 : NAND & NOR GATES
OBJECTIVES:
1. To determine output of NAND gate
2. To determine output of NOR gate
3. To determine the gate conversion output
MATERIALS:
Hex inverter IC7404, Quad 2 inputs NAND gate IC7400 , Quad 2 Inputs NOR gate IC7402 , Digital logic
trainer

PROCEDURE:

Part A (NAND gate)

1. The 2 inputs NAND gate circuit was connected as shown in Figure 2.1
2. The power supply was turned ON.
3. Input switches to each of the 4 possible states were set and the outputs were recorded in table 1.
4. The power supply was turned OFF.
Part B (NOR gate)

1. The 2 inputs NOR gate circuit were connected as shown in Figure 2.2
2. The power supply was turned ON.
3. Table 2 was completed.
4. The power supply was turned OFF
Part C (Gate Conversion)
1. The circuit was connected as shown in Figure 2.3
2. The power supply was turned ON.
3. Table 3 was completed.
4. The power supply was turned OFF.
5. The circuit was connected as shown in Figure 2.4
6. The power supply was turned ON.
7. Table 4 was completed.
8. The power supply was turned OFF.`
TABLE 1
INPUTS OUTPUTS
A B ̅̅̅̅
X=𝐴𝐵
0 0 1
0 1 1
1 0 1
1 1 0
TABLE 2
INPUTS OUTPUTS
A B ̅̅̅̅̅̅̅̅
X=𝐴 +𝐵
0 0 1
0 1 0
1 0 0
1 1 0
TABLE 3
INPUTS OUTPUTS
A B X
0 0 0
0 1 0
1 0 0
1 1 1
TABLE 4
INPUTS OUTPUTS
A B X
0 0 0
0 1 1
1 0 1
1 1 1
DISCUSSION:

NAND and NOR gates are two important gates because they are considered universal gates. We can
construct all of the other basic gates using only NAND or only NOR gates. A NAND gate is an inverted
AND gate while a NOR gate is an inverted OR gate.

The output of a two input NOR gate is low, when either one or both inputs are “High”. In Comparison,
the output of a two input NAND gate is high, when either one or both inputs are “LOW”. To configure a
NAND or NOR gate to function like an inverter, connect the inputs together.

Based on the experiment that has been carried out, the ouput result we obtained is exactly same as the
output theory, so this experiment is considered successful.
QUESTIONS:

1. Which logic gate can be used to replace the circuit as shown in Figure 2.3 and Figure 2.4?
AND gate can replaced the circuit in Figure 2.3 while OR gate can replaced the circuit in Figure
2.4.

2. The OR gate can be obtained by inverting the inputs of a NOR gate.


3. Inverting the output of a NOR gate will produce an OR gate.
4. With logic diagram and equation, show how 1-2 inputs NAND gate can be used as an inverter.

𝑋 = ̅̅̅̅
𝐴𝐴
= 𝐴̅

5. The output of the logic gate as shown below is 0100100.

6. Construct a 2-inputs Nor gate by using only 2-inputs NAND gate.

7. Draw the electrical equivalent circuits of the 2-inputs NAND and 2-inputs NOR gates using only
switches and lamp.

Switch Representation of the NAND Function


Switch Representation of the NOR Function

CONCLUSION:

In conclusion, a NAND gate is an inverted AND gate, and a NOR gate is an inverted OR gate. The
output of a two input NOR gate is low, when either one or both inputs are “High”. In Comparison, The
output of a two input NAND gate is high, when either one or both inputs are “LOW”. To configure a
NAND or NOR gate to function like an inverter, connect the inputs together.

REFERENCES
1. http:///chpt-3/gate-unihttps://www.allaboutcircuits.com/textbook/digitalversality/
2. https://www.electronics-tutorials.ws/boolean/bool_4.html
3. http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/
Experiment 3: Boolean Algebra.
Objective:
 To apply De Morgan theorem and Boolean expressions in studying the logical functions of
combined logic gates.

Materials:
 Breadboard
 Digital Logic Trainer
 IC 7404
 IC 7408
 IC 7432
 IC 7400
 IC 7402

Procedure:

Part A: Boolean Algebra

Figure 3.1

Expression for gate A, B, C, D, E and F in figure 3.1 are included in result for part A.

Part B: De Morgan’s Theorem

Figure 3.2
Figure 3.3
1. The intergrated circuits (IC) was connected as shown in figure 3-2 on the breadboard
2. The circuit then was connected to the Digital Logic Trainer.
3. The power supply of the Digital Logic Trainer was turned on.
4. The Table 1 was completed and the result was captured on the camera.
5. The power supply was turned off.
6. The IC was changed and was connected as shown in figure 6-4 on the breadboard.
7. The circuit then was connected to the Digital Logic Trainer.
8. The power supply of the Digital Logic Trainer was turned on.
9. The Table 2 was completed and the result was captured on the camera.
10. The power supply was turned off.

Part C:

Figure 3.4

Figure 3.5
Circuit was connected as in figure 3.4 and then figure 3.5. The Power supply was turned on and the result
was confirmed and filled in table 3.3 and 3.4. Power supply was turned off.

Result:

Part A:

Gate A: A+B
Gate B: B+C
Gate C: 𝐶̅ + 𝐷
Gate D: (A + B) . (B + C)
Gate E: (𝐶̅ + 𝐷) . 𝐴̅
Gate F: [(𝐴 + 𝐵) . (𝐵 + 𝐶)] + [(𝐶̅ + 𝐷) . 𝐴̅]

Part B:

Figure 3.2A Figure 3.2B


Inputs Outputs Inputs Outputs
A B Y = ̅̅̅̅̅̅̅
𝐴•𝐵 A B Y = 𝐴̅ + 𝐵̅
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
Table 3.1

Figure 3.6 00, 01, 10, 11 input results for figure 3.2A
Figure 3.6 00, 01, 10, 11 input results for figure 3.2B

Figure 3.3A Figure 3.3B


Inputs Outputs Inputs Outputs
A B Y = ̅̅̅̅̅̅̅̅
𝐴+𝐵 A B Y = 𝐴̅ • 𝐵̅
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
Table 3.2

Figure 3.7(1) 00, 01,


10, 11 input results for figure
3.3A
Figure 3.7(2) 00, 01, 10, 11 input results for figure 3.3B

Part C:
Figure 6.5
inputs outputs
A B C D
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Table 3.3
Figure 3.8(1) Result for gate combination according to figure 6.5 with ‘ABCD’ input label.
Figure 3.8(2) Result for gate combination according to figure 6.5 with ‘ABCD’ input label.
Figure 3.8(3) Result for gate combination according to figure 6.5 with ‘ABCD’ input label.

Figure 6.6
inputs outputs
A B C D
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Table 3.4
Figure 3.9(1) Result for gate combination according to figure 6.6 with ‘ABCD’ input label
Figure 3.9(2) Result for gate combination according to figure 6.5 with ‘ABCD’ input label.
Discussion:
Boolean algebra finds its most practical use in the simplification of logic circuits. If we translate a
logic circuit’s function into symbolic (Boolean) form, and apply certain algebraic rules to the resulting
equation to reduce the number of terms and or arithmetic operations, the simplified equation may be
translated back into circuit form for a logic circuit performing the same function with fewer components. If
equivalent function may be achieved with fewer components, the result will be increased reliability and
decreased cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this section for use in reducing
expressions to their simplest forms. The identities and properties already reviewed in this chapter are very
useful in Boolean simplification, and for the most part bear similarity to many identities and properties of
“normal” algebra. However, the rules shown in this section are all unique to Boolean mathematics.

Question:

1. Do the results in Table 3.1 and Table 3.2 prove the two De Morgan’s Theorem?
Yes.

2. What can you conclude from the results in Table 3?


The identical outputs for every combination of identical inputs confers that the IC in
combinations are using same principle over different type of logic gates and wiring. The
principle could be explained by using Boolean Algebra to which it led to the exact same
solution.
𝐴̅𝐶̅ + (𝐴𝐶̅ + 𝐴̅𝐶)(𝐷
̅ + 𝐵̅ )

3. Simplify the equation.


a) Z = ( ̅𝐴 + 𝐵)(𝐵̅ + 𝐴)
= (𝐴̅𝐴 + ̅𝐴𝐵̅ + 𝐵𝐴 + 𝐵𝐵̅ )
= 0 + 𝐴̅𝐵̅ + 𝐴𝐵 + 0
= 𝐴̅𝐵̅ + 𝐴𝐵

b) Z = ( ̅𝐴 + 𝐶)(𝐷
̅ + 𝐵)
= (𝐴̅B + ̅𝐴𝐷
̅ + 𝐵𝐶 + 𝐶𝐷
̅)
Simplify the expressions and draw the logic circuit for the simplified expressions.
a) 𝑍 = 𝐴𝐵𝐶 + 𝐴𝐵̅ (𝐴̅ . 𝐶̅ )
= 𝐴𝐵𝐶 + 𝐴𝐴̅𝐵̅ . 𝐴𝐵̅ 𝐶̅
= 𝐴𝐵𝐶 + 0𝐵̅ . 𝐴𝐵̅ 𝐶̅
= 𝐴𝐵𝐶 + 0
= 𝐴𝐵𝐶

b) 𝑍 = 𝐴̅𝐶(𝐴̅𝐵𝐷) + 𝐴̅𝐵𝐶̅ . 𝐷
̅ +A𝐵̅C
= 𝐴̅𝐶𝐵𝐷 + 𝐴̅𝐵𝐶̅ . 𝐷
̅ +A𝐵̅C
= 𝐴̅𝐵(𝐶𝐷 + 𝐶̅ . 𝐷
̅ )+A𝐵̅C
= 𝐴̅𝐵(𝐶𝐷 + 𝐶̅ 𝐷
̅ ) + 𝐴𝐵̅ 𝐶

Conclusion:
The table used to represent the boolean expression of a logic gate function is commonly called a
Truth Table. A logic gate truth table shows each possible input combination to the gate or circuit
with the resultant output depending upon the combination of these input(s).

References:
 http://users.senet.com.au/~dwsmith/boolean2.htm
 http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic1.html
 http://www.electronics-tutorials.ws/boolean/bool_7.html
EXPERIMENT 4 : DECODING COUNTERS AND DIGITAL DISPLAY

OBJECTIVES :
 To test a seven-segment LED display
 To connect and operate a decoder with a seven-segment LED display
MATERIALS REQUIRED :
 Digital Logic Trainer
 Solid-state devices : IC 7447 and common-anode seven-segment LED
PROCEDURE :

1. The circuit was connected as shown in Figure 4.1 B & C


2. The power supply was turned ON
3. The Table 1 was completed
4. The power supply was turned OFF

RESULT :
INPUT OUTPUT
SW1 SW2 SW3 SW4 a b c d e f g Binary
0 0 0 0 1 1 1 1 1 1 0 0000
0 0 0 1 0 1 1 0 0 0 0 0001
0 0 1 0 1 1 0 1 1 0 1 0010
0 0 1 1 1 1 1 1 0 0 1 0011
0 1 0 0 0 1 1 0 0 1 1 0100
0 1 0 1 1 0 1 1 0 1 1 0101
0 1 1 0 0 0 1 1 1 1 1 0110
0 1 1 1 1 1 1 0 0 0 0 0111
1 0 0 0 1 1 1 1 1 1 1 1000
1 0 0 1 1 1 1 0 0 1 1 1001
1 0 1 0 0 0 0 1 1 0 1 1010
1 0 1 1 0 0 1 1 0 0 1 1011
1 1 0 0 0 1 0 0 0 1 1 1100
1 1 0 1 1 0 0 1 0 1 1 1101
1 1 1 0 0 0 0 1 1 1 1 1110
1 1 1 1 0 0 0 0 0 0 0 1111
DISCUSSION :
A Digital Decoder IC is a device which converts one digital format into another and one of
the most commonly used devices for doing this is called the Binary Coded Decimal (BCD) to 7-
Segment Display Decoder. 7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal Display)
type displays, provide a very convenient way of displaying information or digital data in the form
of numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual coloured LED’s (called the
segments), within one single display package. In order to produce the required numbers or HEX
characters from 0 to 9 and A to F respectively, on the display the correct combination of LED
segments need to be illuminated and BCD to 7-segment Display Decoders such as the 74LS47
do just that.
In this experiment, for 0000, number zero will light up.0001, number one will light up. 0010,
number two light up. 0011 number three light up. 0100, number 4 light up. 0101, number five light
up. 0110, number six light up. 0111, number seven light up. 1000, number eight light up. Lastly,
1001 will light up number nine.
CONCLUSION :
A standard 7-segment LED display generally has eight (8) input connections, one for each
LED segment and one that acts as a common terminal or connection for all the internal display
segments. Some single displays have also have an additional input pin to display a decimal point
in their lower right or left hand corner.
REFERENCE :
https://www.electronics-tutorials.ws/combination/comb_6.html
https://en.wikipedia.org/wiki/Binary-coded_decimal
CLOCKED –R- FLIP –FLOP AND D TYPE FLIP-FLOP
OBJECTIVE :
 To study the overview of S-R flip-flop and D type flip-flop.

PROCEDURE :

1. SN7400 was plugged into the trainer unit and wire the circuit like in Fig.10-1
2. LOGIC SWITCHES was used to SET and RESET data combinations. A single clock pulse was
entered by depressing and releasing PULSER one time for each data entry.
3. Depressed and then released caused the output to go from “0” to “1” and back to “0”. The output
logic level Q and 𝑄 was recorded from each R and S input combination followed the CLOCK
pulse.
PROCEDURE :

1. SN7400 was plugged into the trainer unit and wire the circuit like in Fig.11-1.
2. The input conditions, D was entered. Each entry was followed with a CLOCK pulse and the
resultant output conditions at Q and 𝑄 was observed. The observation was recorded in the table.
3. The CLOCK input was disconnected and connected it to the CLOCK OUTPUT of trainer unit.
The clock rate was set at 1Hz. A LED MONITOR was connected to the CLOCK INPUT. The
input and output transitions was observed simultaneously with LED MONITORS :
LED7-----CLOCK INPUT
LED6----Q OUTPUT
LED5---𝑄 OUTPUT
Table 1
Inputs at 𝑡𝑛 Outputs at 𝑡𝑛 + 1
Reset Set Q 𝑄̅
0 0 0 1
0 1 1 0
1 0 0 1
1 1 1 0
DISCUSSION
In digital circuits the output of any circuit should not only depends on inputs of the circuit, in-
addition to the inputs some sort of triggering mechanism should be provided for synchronized operation
digital circuit which enables to provide a real time data at the output of the circuit. Consider a digital circuit
with two gates connected in series with each gate delay of 1ms. In this condition the output of the first gate
will be available after 1 ms of input data triggering time. The second gate provides the output within the
same time with out waiting for the first gate output and this may results in wrong output of digital circuit. If
an external clock cycle is provided to trigger the two gates at the same time will provide a real time output
at the end of the digital circuit. In RS flip flop as soon the inputs R & S available the change in output state
will results, so to control this state change according to the input a triggering clock is provided in addition
to the input. This circuit is clocked RS flip flop.
This circuit is formed by adding two NAND gates to NAND based SR flip – flop. The inputs are active
high as the extra NAND gate inverts the inputs. A clock pulse is given as input to both the extra NAND
gates.
Hence the transition of the clock pulse is a key factor in functioning if this device. Assuming it is a positive
edge triggered device, the truth table for this flip – flop is shown below
Table 2
Inputs at 𝑡𝑛 Outputs at 𝑡𝑛 + 1
D Q 𝑄̅
0 0 1
1 1 0
DISCUSSION
The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent the
S and R inputs from being at the same logic level. The D Flip Flop is by far the most important of the
clocked flip-flops as it ensures that ensures that inputs S and R are never equal to one at the same time. The
D-type flip flop are constructed from a gated SR flip-flop with an inverter added between the S and
the Rinputs to allow for a single D (Data) input.
Then this single data input, labelled “D” and is used in place of the “Set” signal, and the inverter is used to
generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop from a level-
sensitive SR-latch as now S = D and R = not D as shown.
The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the
clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both
held at logic level “1” so it will not change state and store whatever data was present on its output before
the clock transition occurred. In other words the output is “latched” at either logic “0” or logic “1”.

CONCLUSION
Based on the experiment of clocked – R – flip-flop, the state of Q is prohibited if S is “1” and R is
“Q”. Based on the D flip-flop experiment the state of Q will equal ‘D’ when D input is high and a clock
pulse is applied.

REFERENCE
1. https://www.electronicshub.org/sr-flip-flop-design-with-nor-and-nand-logic-gates/
2. https://www.electronics-tutorials.ws/sequential/seq_4.html
3. https://en.wikipedia.org/wiki/Flip-flop_(electronics)

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