LIST OF EXPERIMENTS

Exp. Page No
Title
No
Basic op-amp circuits
1
Inverting , Non-inverting voltage amplifiers & voltage follower

2 Differentiator & Integrator

3 Rectifiers

4 Comparator(Basic comparator & Schmitt trigger)

5 Wave Shaping Circuits

6 Waveform generator using Opamp and IC555

7 Design of LPF, HPF Band pass and Band reject filters

8 IC voltage regulator

9 R-2R DAC

10 Flash type ADC

11 Simulation experiment using EDA tools

i
 1. BASIC OP-AMP CIRCUITS

1.1 OBJECTIVE
1. To design the following basic op-amp circuits and explain the operation of each:
a. Inverting amplifier
b. Non-inverting amplifier
c. Voltage follower

1.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 1.5K Ω 2

4 Dual Regulated power supply (0 -30V), 1A 1

5 Function Generator (0-2) MHz 1

6 ASLK PRO Kit Refer data sheet in 1

appendix

1.3THEORY
An op-amp is a high gain, direct coupled differential linear amplifier choose response
characteristics are externally controlled by negative feedback from the output to input, op-
amp has very high input impedance, typically a few mega ohms and low output impedance,
less than 100.
Op-amps can perform mathematical operations like summation integration,
differentiation, logarithm, anti-logarithm, etc., and hence the name operational amplifier op-
amps are also used as video and audio amplifiers, oscillators and so on, in communication
electronics, in instrumentation and control, in medical electronics, etc.

1
1.3.1 Circuit symbol and op-amp terminals

The circuit schematic of an op-amp is a triangle as shown below in Fig. 1-1 op-amp
has two input terminal. The minus input, marked (-) is the inverting input. A signal applied to
the minus terminal will be shifted in phase 180o at the output. The plus input, marked (+) is
the non-inverting input. A signal applied to the plus terminal will appear in the same phase at
the output as at the input. +VCC denotes the positive and negative power supplies. Most op-
amps operate with a wide range of supply voltages. A dual power supply of +15V is quite
common in practical op-amp circuits. The use of the positive and negative supply voltages
allows the output of the op-amp to swing in both positive and negative directions.

+Vcc

inverting input offset null

-
uA741 output

+
non-inverting offset null
input
-Vcc

Fig-1-1 op-amp circuit symbol

2
1.3.2 Op amp internal circuit
Commercial integrated circuit OP-amps usually consists of your cascaded blocks as shown in
figure 1-2shown below.

V2
Differential Differential Buffer and Output
Amplifier Amplifier Level driver Vo
V1 Translator

Fig 1-2Internal block schematic op-amp

The first two stages are cascaded difference amplifier used to provide high gain. The third
stage is a buffer and the last stage is the output driver. The buffer is usually an emitter
fallowing whose input impedance is very high so that it prevents loading of the high gain
stage. The output stage is designed to provide low output impedance. The buffer stage along
with the output stage also acts as a level shifter so that output voltage is zero for zero inputs.

In this laboratory experiment, you will learn several basic ways in which an op-amp
can be connected using negative feedback to stabilize the gain and increase the frequency
response. The extremely high open-loop gain of an op-amp creates an unstable situation
because a small noise voltage on the input can be amplified to a point where the amplifier in
driven out of its linear region. Also unwanted oscillations can occur. In addition, the open-
loop gain parameter of an op-amp can vary greatly from one device to the next. Negative
feedback takes a portion of output and applies it back out of phase with the input, creating an
effective reduction in gain. This closed-loop gain is usually much less than the open-loop
gain and independent of it.

1.3.3 Closed – loop voltage gain, ACL

The closed-loop voltage gain is the voltage gain of an op-amp with external feedback.
The amplifier configuration consists of the op-amp and an external negative feedback circuit
that connects the output to the inverting input. The closed loop voltage gain is determined by
the external component values and can be precisely controlled by them.

1.3.4 Non-inverting amplifier

3
 An op-amp connected in a closed-loop configuration as a non-inverting amplifier with
a controlled amount of voltage gain is shown in Fig 1-3.
R f

R 1 +V cc

-
uA 741 V o

-V c c
V in

Fig. 1-3 Non-inverting amplifier configuration of op-amp

The input signal is applied to the non-inverting (+) input. The output is applied back to the
inverting(-) input through the feedback circuit (closed loop) formed by the input resistor R 1
and the feedback resistor Rf. This creates negative feedback as follows. Resistors R1 and Rf
form a voltage-divider circuit, which reduces VO and connects the reduced voltage Vf to the
inverting input. The feedback is expressed as
R1
Vf  ( )Vo
R1  R f

The difference of the input voltage, Vin and the feedback voltage, Vfis the differential input of
the op-amp. This differential voltage is amplified by the gain of the op-amp and produces an
output voltage expressed as
 Rf 
Vo  1  Vin
 R1 

The closed-loop gain of the non-inverting amplifier is, thus

Rf
ACL ( NI )  1 
R1

Notice that the closed loop gain is

 independent of open-loop gain of op-amp
 set by selecting values of R1 and Rf

4
An expression for the input impedance of a non-inverting amplifier can be written as
Z in ( NI )  (1  AOL  ) Z in

Where AOL = open-loop voltage gain of op-amp

Zin = internal input impedance of op-amp (without feedback)
 = attenuation of the feedback circuit
Vf R1
 
Vo R1  R f

Above equation shows that the input impedance of the non-inverting amplifier configuration
with negative feedback is much greater than the internal output impedance of the op-amp
itself.
The output impedance of a Non-Inverting amplifier can be written as
Zo
Z o ( NI ) 
1  AOL

This equation shows that the output impedance of non-inverting amplifier is much less than
the internal output impedance, Zo of the op-amp.

1.3.5 Voltage follower

The voltage follower configuration is a special case of the non-inverting amplifier
where all the output voltage is feedback to the inverting input by straight connection, as
shown in fig. 1.4

+Vcc

-
uA741 Vo

-V c c
V in

Fig. 1.4 Voltage follower configuration of op-amp

As you can see, the straight feedback connection has a voltage gain of (which means there is
no gain).
ACL (VF) = 1

5
The most important features of the voltage follower configuration are its very high input
impedance and its very low output impedance. These features make it a nearly ideal buffer
amplifier for interfacing high-impedance sources and low-impedance loads.
Z IN (VF )  (1  AOL ) Z in

ZO
Z O (VF ) 
1  AOL
As you can see, the voltage follower input impedance is greater for a given A OL and Zin than
for the non-inverting amplifier. Also, its output impedance is much smaller.

1.3.6. Inverting amplifier

An op-amp connected as an inverting amplifier with a controlled amount of voltage
gain is shown in fig. 1.5 R f

R 1 +Vcc

-
uA 741 Vo
V in
+

-V c c

Fig.1.5 inverting amplifier

The input signal is applied through a series input resistor R 1 to the inverting input. Also, the
output is fed back through Rf to the same input. The non-inverting input is grounded. An
expression for the output voltage of the inverting amplifier is written as
Rf
VO   Vin
R1

The –ve sign indicates inversion. The closed-loop gain of the inverting amplifier is, thus
Rf
ACL ( I )  
R1

The input & output impedances of an inverting amplifier are

Zin(I) = R1
Zo
Z O( I ) 
1  AOL 

The output impedance of both the non-inverting and inverting amplifier configurations is
very low; in fact, it is almost zero in practical cases. Because of this near zero output

6
impedance, any load impedance connected to the op-amp output can vary greatly and not
change the output voltage at all.

1.3.7. Design Constraints

 The output signal is limited by the IC's power sources: the output signal cannot be greater
than +15V.

7
1.4 PRE LAB QUESTIONS

1. Identify each of the op-amp configurations

R f
R f

R 1 +Vcc
+Vcc R 1 +Vcc Vin
-
- - uA741 Vo
uA741 Vo
uA741 Vo
+
Vin +
Vin + -Vcc
-Vcc
-Vcc

Fig.(a)
2. A non-inverting amplifier has R1 of 2K & Rf of 200K. Determine Vf and 
(Feedback voltage and feedback fraction), if VO = 5V

3. For the amplifier in Fig.(b) determine the following: (a) ACL(NI) (b) VO (c) Vf

R f = 560k

R 1 = 1 .5 k +Vcc

-
uA741 Vo

Vin +
10 mVrms
-Vcc

Fig.(b)

1.5 EXPERIMENT
(1) Non-Inverting amplifier
1.1 Design a non-inverting amplifier for the gain of 10. Let R1=1.5k Assemble the circuit.
1.2 Feed sinusoidal input of amplitude 1V and frequency 1KHz
1.3 Observe the input voltage and output voltage on a CRO. Tabulate the reading in Table

(2) Voltage follower

2.1 Assemble a voltage follower circuit.
2.2 Feed sinusoidal input of amplitude 10V and frequency 1KHz.
2.3 Observe the input and output voltages on a CRO. Tabulate the readings in Table.

8
(3) Inverting amplifier
3.1 Design an inverting amplifier for the gain of 10. Let R 1=1.5k. Assemble the
circuit.
3.2 Feed sinusoidal input of amplitude 1V and frequency 1KHz.
3.3 Observe the input and output voltages on a CRO. Tabulate the readings in Table

op-amp Input signal Output signal Voltage gain

configuration /
Designed Observed
circuit Amplitude Frequency Amplitude Frequency
value value
Non-inverting
amplifier
Voltage
follower
Inverting
amplifier
1.6. POST LAB QUESTIONS
1. What is the relationship, if any, between the polarity of the output and input voltages in
your experimental op-amp? Refer to your data.
2. Comment on the statement: “The closed-loop gain-bandwidth product is a constant for a
given op-amp”.
3. Find the value of Rf that will produce closed-loop gain of 300 in each amplifier in
fig.(c) R f

R 1 = 12k +Vcc

-
uA741 Vo

Vin +

-Vcc

9
 Fig.(c)
4. Determine the approximate values for each of the following quantities in
Fig.(d).
If R f = 22k
R f
-----

R 1 = 2 .2 k +Vcc R 1 = 2 .2 k
V in +Vcc
Vin - 1V -
uA741 Vo -----
Iin uA741 Vo
+
+
-Vcc
Fig.(d) -Vcc

5. If a signal voltage of 10mV is applied to each amplifier in Fig.(e), what are the
output voltages?

R f=100k
R f=1M

R 1 = 100k +Vcc
+Vcc
R 1=47k +Vcc
Vin -
- uA741 Vo -
uA741 Vo uA 741 Vo
+
Vin + V in +
-Vcc
-V c c
-Vcc

R f=10k

R f=100k
R 1=10k +V cc
R 1=1k -
+Vcc V in uA741 Vo
V in R 2=10k
- +
uA741 Vo
R 2=1k -V c c
+ R 1=10k

-V c c

Fig. (e)

10
 2. INTEGRATOR AND DIFFERENTIATOR

2.1 OBJECTIVE
1. Design an integrator for a frequency of 1KHz, given R=1KΩ , C=0.1 µF and Rf
= 1MΩ. Conduct the experiment and plot integrated output waveforms for various
input waveforms and analyze
2. Design an differentiator for a frequency of 1KHz, given R=10KΩ , and C=0.1µf
and Rf = 470Ω. Conduct the experiment and plot integrated output waveforms for
various input waveforms and analyze

2.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 1K Ω 1

1M Ω 1

10 K Ω 1

470 Ω 1

4 Capacitors 0.1µf 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

7 ASLK PRO Kit 1

2.3 THEORY
In this laboratory experiment, you will learn several basic ways in which an op-amp
can be connected using negative feedback to stabilize the gain and increase the frequency
response. The extremely high open-loop gain of an op-amp creates an unstable situation
because a small noise voltage on the input can be amplified to a point where the amplifier in
driven out of its linear region. Also unwanted oscillations can occur. In addition, the open-
loop gain parameter of an op-amp can vary greatly from one device to the next. Negative
feedback takes a portion of output and applies it back out of phase with the input, creating an

11
effective reduction in gain. This closed-loop gain is usually much less than the open-loop
gain and independent of it.

2.3.1 Integrator
An op-amp integrator simulates mathematical integration which is basically a
summing process that determines the total area under the curve of a function ie., the
integrator does integration of the input voltage waveform. Here the input element is resistor
and the feedback element is capacitor as shown in fig.2-1.
C

R +Vcc
V in
-
uA741 Vo

-V c c

Fig.2-1 Basic op-amp integrator

The output voltage is given by
t
1
RC o
VO   VS dt  VC (t  0)

Where VC (t=0) is the initial voltage on the capacitor. For proper integration, R C has to be
much greater than the time period of the input signal.

It can be seen that the gain of the integrator decreases with the increasing frequency
so, the integrator circuit does not have any high frequency problem unlike a differentiator
circuit. However, at low frequencies such as at dc, the gain becomes infinite. Hence the op-
amp saturates (ie., the capacitor is fully charged and it behaves like an open circuit). A
practical integrator circuit is shown in Fig. 2-2.
R f

R +V cc
V in
-
uA741 Vo

-V c c

Fig. 2-2 Practical op-amp integrator

2.3.2 Differentiator

12
 An op-amp differentiator simulates mathematical differentiation, which is a process of
determining the instantaneous rate of change of a function. Differentiator performs the
reverse of integration function. The output waveform is derivative of the input waveform.
Here, the input element is a capacitor and the feedback element is a resistor. An ideal
differentiation is shown in fig. 2-3.

R f

C +Vcc
V in
-
uA741 Vo

-V c c

Fig.2-3 Basic op-amp differentiator

The output voltage is given by
dVS
VO   RC ( )
dt
For proper differentiation, RC has to be much smaller than the time period of the input signal.
It can be seen that at high frequencies a differentiator may become unstable and break into
oscillation. Also, the input impedance of the differentiator decreases with increase in
frequency, thereby making the circuit sensitive to high frequency noise. So, in order to limit
the gain of the differentiator at high frequencies, the input capacitor is connected in series
with a resistance R1 and hence avoiding high frequency noise and stability problems. A
practical differentiator circuit is shown in fig. 2-4.

Fig. 2-4 Practical op-amp differentiator

13
2.3.3. Design Constraints
Integrator circuit
 The output of the integrator cannot rise indefinitely as the output will be limited.
 The output of the op amp integrator will be limited by supply voltage.
 When designing one of these circuits, it may be necessary to limit the gain or increase
the supply voltage to accommodate the likely output voltage swings.
 While small input voltages and for short times may be acceptable, care must be taken
when designing circuits where the input voltages are maintained over longer periods of
time.

Differentiator circuit
 Output rises with frequency: One of the key facts of having a series capacitor is that
it has an increased frequency response at higher frequencies. The differentiator output
rises linearly with frequency, although at some stage the limitations of the op amp will
mean this does not hold good. Accordingly precautions may need to be made to account
for this. The circuit, for example will be very susceptible to high frequency noise, stray
pick-up, etc.
 Component value limits: It is always best to keep the values of the capacitor and
particularly the resistor within sensible limits. Often values of less than 100kΩ for the
resistor are best. In this way the input impedance of the op amp should have no effect
on the operation of the circuit.\

2.4 PRE LAB QUESTIONS

1. Determine the input and output impedances for each amplifier configuration, (Z in=10M,
ZO=75, AOL = 175,000) in fig.(a)

R f=560k R f=150k

+Vcc
R 1 = 2 .7 k +Vcc R 1=10k +Vcc
-
- uA741 Vo V in -
uA741 Vo uA741 Vo
Vin +
V in + +
-Vcc -V c c
-V c c

Fig. (a)

14
2. Determine the BW of each of the amplifiers in fig(b). The op-amps have an open-loop
gain of 90dB and a unity gain bound width of 2MHz.

R f=47k
R f=220k

R 1=1k +Vcc
R 1 = 3 .3 k +Vcc
V in -
- uA741 Vo
uA741 Vo
+
V in +
-V c c
-V c c

Fig.(b)

3. Determine the output voltage of each amplifier in Fig (c).

R f=10k R f=10k R f=100k

3V 1 k 1 k
0 .2 V +V cc R 1=10k +Vcc
+V cc
1V 1 k 2V -
- -
0 .5 V uA741 Vo uA741 Vo
8V 1 k uA741 Vo 1 k R 1=10k
3V +
+
+
-V c c
-V c c R f=100k
-V c c

R f=10k
R f=25k
R f=10k

1V 100 k R 1=10k +Vcc

3V 47 k +Vcc
2V -
+V cc 2V 100 k
2V 100 k uA741 Vo
-
- R 1=10k
3V 100 k uA741 Vo 3V +
8V 10 k uA741 Vo
4V 100 k + -V c c
+ R f=10k
-V c c
-V c c

Fig.(c)

15
2.5 EXPERIMENT
(1) Integrator
1.1 Assemble an integrator circuit with R=1K and C=0.1µf. Connect Rf of value 1M
across the capacitor.
1.2 Feed +1V, 500Hz square wave input.
1.3 Observe the input and output voltages on a CRO.
1.4 Determine the gain of the circuit and tabulate the readings in table. Model waveform is
shown.
1.5 Plot the input and output voltages on the same scale on a linear graph sheet.

(2) Differentiator
2.1 Assemble a differentiator circuit with R=10K and C=0.1µf. Connect a resistor R1 of
value 470 between the source and the capacitor.
2.2 Feed +1V, 500Hz square wave input.
2.3 Observe the input and output voltages on a CRO.

op-amp Input signal Output signal

configuration /
Amplitude Frequency Amplitude Frequency
circuit
Integrator
Differentiator
2.4 Determine the gain of the circuit and tabulate the readings in table. Model waveform is
shown.
2.5 Plot the input and output voltages on the same scale on a linear graph sheet.

16
a)

(b)

Fig.2.5 Waveform for (a) op-amp integrator, (b) op-amp differentiator

2.6 POST LAB QUESTIONS

1. Determine the gain-bandwidth product of each amplifier.
2. Determine the input and output impedances of each amplifier.
3. (a) What is the normal output voltage in fig. 2-14?
(b) What is the output voltage of R2 opens?
(c) What happens if R5 opens?
10k
R f=10k
10k
1V
R 1=1k +Vcc +V cc
V in
- 0 .5 V 10k
uA741 Vo -
0 .2 V 10 k uA741 Vo
+

-V c c 0 .1 V +
10 k
R 3
0 .9 1 k
-V c c
Fig. 2-14

17
18
 3. RECTIFIERS

3.1 OBJECTIVE
a. To study the operation of active diode circuits (precisions circuits) using op-amps, such as
half wave rectifier and full wave rectifier

3.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 10 K Ω 6

4 Semiconductor(Diode) 1N4002 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

7 ASLK PRO Kit Refer data sheet in 1

appendix

3.3 THEORY
The major limitation of ordinary diodes is that it cannot rectify voltage below 0.6v,
thecut in voltage of the diode. The precision rectifier, which is also known as a super
diode, is a configuration obtained with an operational amplifier in order to have a circuit
behaving like an ideal diode and rectifier. It can be useful for high-precision signal
processing.

3.3.1 Active Half Wave Rectifier

Op-amps can enhance the performance of diode circuits. For one thing, the op-amp
can eliminate the effect of diode offset voltage, allowing us to rectify, peak-detect, clip, and
clamp low-level signals (those with amplitudes smaller than the offset voltage). And because
of their buffering action op-amps can eliminate the effects of source and load on diode

19
circuits. Circuits that combine op-amps and diodes are called active diode circuits. Fig. (a)
shows an active HWR, with gain.

Fig(a) Active HWR, (b) input and output waveforms

When the input signal goes positive, the op-amp goes positive and turns on the diode. The
circuit then acts as a conventional non-inverting amplifier, and the positive half-cycle
appears across the load resistor. On the other hand, when the input goes negative, the op-amp
output goes negative and turns off the diode. Since the diode is open, no voltage appears
across the load resistor. This is why the final output is almost a perfect half-wave signal.

The high gain of the op-amp virtually eliminates the effect of offset voltage. For
instance, if the offset voltage equals 0.7V and open-loop gain is 100,000, the input that just
turns on the diode is

0.7V 
Vin 7 V .
100,000

When the input is greater than 7µV, the diode turns on and the circuit acts like a voltage
follower. The effect is equivalent to reducing the offset voltage by a factor of A.

The active HWR is useful with low-level signals. For instance, if we want to
measure sinusoidal voltages in the millivolt region, we can add a milli ammeter in series

with RL with the proper value of RL, we can calibrate the meter to indicate rms millivolts.
1.3.2 Design Constraints

20
 The output signal is limited by the IC's power sources: the output signal cannot be
greater than +15V

3.3.3 Experiment
1. Connect the circuit as shown in the figure. Consider all resistors value 10kΩ . Use
1N4002 diodes. Assemble the circuit.
2. Feed sinusoidal input of amplitude 200mVPP and frequency 100Hz. Using a CRO
observe the input and output voltages simultaneously. Determine the amplitude and
frequency of the output voltage.
3. Increase the frequency of the input signal till distortion appears in the output. Record
this frequency in the below table
4. Plot the input and output voltages on the same scale.

Particulars Amplitude Time period Frequency

Input Voltage

Output Voltage

3.3.4 Full Wave Rectifier

A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc
voltage using both half cycles of the applied ac voltage. It uses two diodes of which one
conducts during one half cycle while the other conducts during the other half cycle of the
applied ac voltage.

During the positive half cycle of the input voltage, diode D1 becomes forward
biased and D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The

load current flows through D1 and the voltage drop across R L will be equal to the input
voltage. During the negative half cycle of the input voltage, diode D1 becomes reverse
biased and D2 becomes forward biased. Hence D1 remains OFF and D2 conducts. The

load current flows through D2 and the voltage drop across R L will be equal to the input
voltage.

21
Input waveform

Output waveform:

Fig (a) Full wave rectifier, (b) input and output waveforms
Experiment
1. Connect the circuit as shown in the figure. Consider all resistors value 10kΩ . Use
1N4002 diodes. Assemble the circuit.
2. Feed sinusoidal input of amplitude 200mVPP and frequency 100Hz.
3. Using a CRO observe the input and output voltages simultaneously. Determine the
amplitude and frequency of the output voltage. Increase the frequency of the input signal
till distortion appears in the output. Record this frequency in the below table.
4. Plot the input and output voltages on the same scale.
Particulars Amplitude Time period Frequency
Input Voltage
Output Voltage

3.4 PRE-LAB QUESTIONS

1. What is a precision diode
2. Give the uses of precision diode

22
 3. Give some applications of precision diode
4. What are the major limitations of an ordinary diode?

5. For a precision HWR, draw the output waveform if V in is a 300mV peak sine wave at
1 KHz.

3.5 POST LAB QUESTIONS

1. If the diode is reversed in half wave rectifier, what would the output voltage be?
2. Draw the equivalent circuit of a full wave rectifier for input voltage less than zero
volts(Vi<0)
3. Draw the circuit of a Clipper which will clip the input signal below a reference voltage.
4. What is Clamper circuit?

23
 4. COMPARATOR
4.1 OBJECTIVE:
1. Design the comparator for a frequency of 1 KHz sine wave with 5 Vpp at the non-
inverting input terminal and apply 1V dc voltage as reference voltage at the inverting
terminal of IC741
2. Design a Schmitt Trigger and conduct an experiment to obtain VUTP and VLTP for various
values of R1 and R2 for the specified design constraint with upper and lower threshold
should be ±1V, for the frequency range of 100 Hz to 10KHz.

4.2 COMPARATOR
4.2.1 Apparatus required:

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet 1

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Multimeter 1

4 Resistors 10 kΩ 2

6 Dual Regulated power supply (0 -30V), 1A 1

4.2.2 Theory:
A Comparator is a non-linear signal processor. It is an open loop mode application of
Op-amp operated in saturation mode. Comparator compares a signal voltage at one input with
a reference voltage at the other input. Here the Op-amp is operated in open loop mode and
hence the output is ±Vsat. It is basically classified as inverting and non-inverting comparator.
In a non-inverting comparator Vin is given to +ve terminal and Vref to –ve terminal. When
Vin < Vref, the output is –Vsat and when Vin > Vref, the output is +Vsat (see expected
waveforms). In an inverting comparator input is given to the inverting terminal and reference
voltage is given to the non inverting terminal. The output of the inverting comparator is the
inverse of the output of non-inverting comparator. The comparator can be used as a zero
crossing detector, window detector, time marker generator and phase meter

24
 .

4.2.3 Experiment
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 1 KHz sine wave with 5 Vpp at the non-inverting input terminal of IC741 using a
function generator.
4. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
5. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
6. Observe the input sinusoidal signal at channel-1 and the corresponding output square
wave at channel-2 of CRO. Note down their amplitude and time period.
7. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
8. Plot the output square wave corresponding to the sine input with Vref = 1V.

25
4.2.4 Expected Waveforms: Comparator Input & Output Waveforms

Observations
Theoretical Reference voltage (From the circuit)

Practical Reference voltage (From output waveform)

4.2.5 Pre Lab Question:

1. How many basic input parameters are required for a comparator?
2. How is Vo related to Vin and Vref?
3. Why this circuit is called a non-inverting comparator?
4. What do these maximum and minimum values correspond to?

4.2.6 Post Lab Question:

1. Draw the circuit diagram of a non-inverting comparator and inverting comparator.
2. What do you think is the role of resistors R1 and R2?
3. What is the output of a non-inverting comparator and inverting comparator if the
input is triangular signal?
4. What happens when Vref becomes greater than the maximum value of Vin?
5. What happens when Vref becomes less than the minimum value of Vin?

Result:

4.3 SCHMITT TRIGGER CIRCUITS

26
4.3.1 Apparatus required:

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet 1

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Multimeter 1

4 Resistors 10K Ω 2

56 K Ω 1

5 Dual Regulated power supply (0 -30V), 1A 1

6` Function Generator (0-2) MHz 1

4.3.2 Theory:
Circuit shows an inverting comparator with positive feedback. This circuit converts an
irregular shaped waveform to square wave or pulse. This circuit is known as Schmitt trigger
or Regenerative comparator or Squaring circuit. The input voltage Vin triggers (changes the
state of ) the output Vo every time it exceeds certain voltage levels called Upper threshold
voltage, VUT and Lower threshold voltage, VLT. The hysteresis width is the difference between
these two threshold voltages i.e. VUT – VLT. These threshold voltages are calculated as
follows.
VUT = (R2/R1+R2) Vsat when Vo= Vsat
VLT = (R2/R1+R2) (-Vsat) when Vo= -Vsat

The output of Schmitt trigger is a square wave when the input is sine wave or triangular
wave, where as if the input is a saw tooth wave then the output is a pulse wave.

27
 Schmitt trigger circuit using IC 741
Design Equations:
R2
VUTP =
R1 +R 2
( 
VSat )

R2
VLTP =
R1 +R 2
( 
VSat )
R2
VHyst =VUTP -VLTP =
R1 +R 2
( 
VSat 
 VSat )

4.3.3 Design Constraints

 Minimum Input voltage is 1v and maximum output voltage is 10v.
 Biasing voltage is ±12v
 Frequency range is 100 Hz up to 10kHz

4.3.4 Experiment:
1. Connect the components / equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 5 Vpp and 1KHz input sine wave using function generator.
4. Connect the channel - 1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down voltages at positions on sine
wave where output changes its state. These voltages denote the Upper threshold voltage
and the Lower threshold voltage (see EXPECTED WAVEFORMS below).
7. Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas given in the THEORY section above.
8. Sketch the waveforms by noting down the amplitude and the time period of the input
Vin and the output Vo.

4.3.4 Model output Schmitt trigger input and output Waveforms:

28
29
Observation Table

Theoretical Values Practical Value

Sl
R2 R2
no. R1 R2 VUTP =
R1 +R 2
( VSat ) VLTP =
R1 +R 2
( VSat ) VUTP VLTP

4.3.5 Pre Lab Question:

1. Which is type of comparator called Schmitt trigger using IC741?
2. What is the output wave of Schmitt trigger if the input is sine wave?
3. What type of waveform is obtained when triangular or ramp waveforms are applied to
Schmitt trigger circuit?

4.3.6 Post Lab Question:

1. How do you calculate the theoretical values of VUT and VLT in the case of IC741?
2. What is the Hysteresis width?
3. What is the minimum amplitude of the input sine wave in the case of Schmitt trigger
using IC741

Results:
5. WAVE SHAPING CIRCUITS

5.1 OBJECTIVE
a. To study the operation of wave shaping circuits (clipper and clamper) using op-amps, such as

30
half wave rectifier and full wave rectifier

5.2HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 2.2 K Ω, 4.7K, 3

10KPOT

4 Semiconductor(Diode) 1N4002 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

7 ASLK PRO Kit Refer data sheet in 1

appendix

5.2.1 THEORY
ACTIVE CLIPPER

Clipper is a circuit that is used to clip off (remove) a certain portion of the input
signal to obtain a desired output wave shape. In op-amp clipper circuits, a rectified diode ma
be used to clip off certain parts of the input signal. Fig. 2-2-4 (a) shows an active positive
clipper, a circuit that removes positive parts of the input signal. The clipping level is
determined by the reference voltage

31
 Fig 3(a) Active clipper

(b) (c)

Fig 4 (b) input & output waveforms with +Vref, (c) input & output waveforms with -Vref

With the wiper all the way to the left, V ref is o and the non-inverting input is grounded.

When Vin goes positive, the error voltage drives the op-amp output negative and turns on the

diode. This means the final output VO is 0 (same as Vref) for any positive value of Vin.

32
 When Vin goes negative, the op-amp output is positive, which turns off the diode

and opens the loop. When this happens, the final output VO is free to follow the negative
half cycle of the input voltage. This is why the negative half cycle appears at the output. To

change the clipping level, all we do is adjust Vref as needed.

Active clamper
In clamper circuits, a predetermined dc level is added to the input voltage. In other
words, the output is clamped to a desired dc level. If the clamped dc level is positive, the
clamper is called a positive clamper. On the other hand, if the clamped dc level is negative, it
is called a negative clamper. The other equivalent terms for clamper are dc inserter or dc
restorer.
A clamper circuit with a variable dc level is shown in fig (a). Here the input wave

form is clamped at +Vref and hence the circuit is called a positive clamper.

1uF
C1
-+ Vo

Vp RL
Vin 1k
R
4.7k +VCC D1

uA741
+
Rp -VCC
10k

Fig 5 (a) Peak clamper circuit

The output voltage of the clamper is a net result of ac and dc input voltages applied to the
inverting and non-inverting input terminals respectively. Therefore, to understand the circuit

operation, each input must be considered separately. First, consider V ref at the non-inverting

input. Since this voltage is positive, is +V o is positive, which forward biases diode D1. This
closes the feedback loop and the op-amp operates as a voltage follower. This is possible

33
because C1 is an open circuit for dc voltage. Therefore Vo = Vref. As for as voltage Vin at the

inverting input is concerned during its negative half-cycle D1 conducts, charging C1 to the

negative peak value of the VP. However, during the positive half-cycle of Vin diode D1 is

reverse biased and hence the voltage VP across the capacitor acquired during the negative

half-cycle is retained. Since this voltage VP is in series with the positive peak voltage VP, the

output peak voltage Vo=2VP. Thus the net output is Vref +VP, so the negative peak of 2VP is

at Vref. For precision clamping C1Rd<<T/2, where Rd is the forward resistance of the diode

D1 (100Ω typically) and T is the time period of Vin. The input and output wave forms are
shown in figure.

(i) (ii)

34
 (iii)
Fig 6(b) Input and output waveforms (i) with Vref=0V, (ii) with +Vref, (iii) with -Vref

Resistor R is used to protect the op-amp against excessive discharge currents from capacitor

C1 especially when the dc supply voltages are switched off. Negative clamping at a negative
voltage is accomplished by reversing diode D1 and using the negative reference voltage –

Vref.
5.2.2 Experiment
1. Connect the components/equipment R=2.2KΩ use IN4002 diode. Sinusoidal input
amplitude 3v and frequency 1Khz.as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
4. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
5. Observe the input sinusoidal signal at channel-1 and the corresponding output square
wave at channel-2 of CRO. Note down their amplitude and time period.
6. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
7. Plot the output wave form.

Active clamper
1. Connect the components/equipment clamping level at zero as shown in fig.5 (a). Note

that Vref = 0V. Consider C1 = 0.1µF, R = 4.7 KΩ and RL = 10 KΩ . Use 1N4002

diode. Feed 5VPP, 10 KHz sinusoidal inputs.

35
 2. Switch ON the power supply.
3. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
4. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
5. Observe the input sinusoidal signal at channel-1 and the corresponding output square
wave at channel-2 of CRO. Note down their amplitude and time period.
6. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
7. Plot the output wave form.

Observation Clipper

Observation Clamper

36
Prelab

1. Find the output waveform for when Vin < Vref

2. Determine the output waveform for a clamper with input =4Vpsinewave and Vref=1V.
Postlab
1. If the diode is reversed in fig. 3 (a), what would the output be like?
2. If the diode is reversed in fig. 5(a), what would be the output?

Result

37
 6. WAVEFORM GENERATOR: USING OPAMP AND
IC555

6.1 OBJECTIVE
1. Design a Monostable multivibrator for an ON- time of 11secs, with capacitor value of 1
µF. Conduct the experiment and plot appropriate graphs
2. Design an Astable multivibrator for a frequency of 1KHz with 60% duty cylcle using
555 timer
3. Design a square wave generator using opamop

6.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

Refer data sheet in

1 IC 555 Timer 1
appendix

Refer data sheet in

2 IC 741 1
appendix

3 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

330 Ω 1
15K Ω 1
4 Resistors 10 M Ω 1
6.8 K Ω 1
1K Ω 1

0.1µf 2
5 Capacitors
1µf 2
6 Regulated power supply (0 -5V), 1A 1

7 Function Generator (0-2) MHz 1

6.3 THEORY

38
 The 555 Timer is a monolithic timing circuit that can produce accurate and highly
stable time delays or oscillations. The timer basically operates in one of the two modes—
monostable(one-shot) multivibrator or as an as table(free-running) multivibrator. In the
monostable mode, it can produce accurate time delays from microseconds to hours. In the
astable mode, it can produce rectangular waves with a variable duty cycle. Frequently, the
555 is used in astable mode to generate a continuous series of pulses, but you can also use the
555 to make a one-shot or monostable circuit.

Applications of 555 timer in monostable mode include timers, missing pulse detection,
bounce free switches, touch switches, frequency divider, capacitance measurement, pulse
width modulation (PWM) etc.

In astable or free running mode, the 555 can operate as an oscillator. The uses include
LED and lamp flashers, logic clocks, security alarms, pulse generation, tone generation, pulse
position modulation, etc. In the bistable mode, the 555 can operate as a flip-flop and is used
to make bounce-free latched switches, etc.

39
 Pin diagram of IC55
Functional block diagram of IC 555
6.3.1 MONOSTABLE MULTIVIBRATOR
The circuit has an external resistor and capacitor. The voltage across the capacitor is
used for the threshold to pin 6. When the trigger arrives at pin 2, the circuit produces output
pulse at pin 3. Initially, if the output of the timer is low, that is, the circuit is in a stable state,
transistor Q1 is on and the external capacitor C is shorted to ground. Upon application of a
negative trigger pulse to pin 2, transistor Q1 is turned off, which releases the short circuit
across the capacitor and as a result, the output becomes high. The capacitor now starts
charging up towards vcc through RA. When the voltage across the capacitor equals 2/3vcc
the output of comparator 1 switches from low to high, which in turn makes the output low via
the output of the flip-flop. Also, the output of the flip-flop turns transistor Q1 on and hence
the capacitor rapidly discharges through the transistor. The output of the monostable
multivibrator remains low until a trigger pulse is again applied. The cycle then repeats. Below
figure shows the trigger input, output voltage, and capacitor voltage waveforms. As shown,
the pulse width of the trigger input must be smaller than the expected pulse width of the
output waveform. Moreover, the trigger pulse must be a negative-going input signal with an
amplitude larger than 1/3 vcc. The time for which the output remains high is given by time
period = 1.1RAC

Where RA is in ohms, C in farads and time period in seconds. Once the circuit is triggered, the
output will remain high for the time interval time period. It will not change even if an input
trigger is applied during this time interval. In other words, the circuit is said to be non-
retriggerable. However, the timing can be interrupted by the application of a negative signal

40
at the reset input on pin 4. A voltage level going from +vcc to ground at the reset input will
cause the timer to immediately switch back to its stable state with the output low.

The trigger input may be driven by the output of astable multivibrator with high duty
cycle. If the desired pulse width is of the order of seconds, the output can be seen using a
LED and the resistance value used will be of the order of MΩ. In this case the trigger can be
supplied manually by grounding the trigger input for a fraction of a second.

Input and output waveform

41
Design
Time period of
pulse=T=1.1RC=11s
Let C=100f
T=1.1RC

11s=1.1*R*1uf

R=10M
6.3.2 ASTABLE MULTIVIBRATOR
An astable multivibrator is a wave-generating circuit in which neither of the output
levels is stable. The output keeps on switching between the two unstable states and is a
periodic, rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’.
Also, no external trigger is required to change the state of the output, hence it is also called
‘free-running multivibrator’. The time for which the output remains in one particular state is
determined by the two resistors and a capacitor externally connected to the 555 timer.

If the output is high initially, capacitor C starts charging towards vcc through R A and
RB. As soon as the voltage across the capacitor becomes equal to 2/3 vcc, the upper
comparator triggers the flip-flop, and the output becomes low. The capacitor now starts
discharging through RB and transistor Q1. When the voltage across the capacitor becomes
1/3vcc, the output of the lower comparator triggers the flip-flop, and the output becomes
high. The cycle then repeats.

The output voltage and capacitor voltage waveforms are shown in Figure below.

42
Output voltage waveform
the time during which the capacitor charges from 1/3vcc to 2/3 vcc is equal to the time the
output is high and is given by
ton =0.69(RA + RB)C
the time during which the capacitor discharges from 2/3vcc to 1/3vcc is equal to the time the
output is low and is given by
toff =0.69RBC
the total period of the output wave form is

T=ton+toff=0.69(RA+2RB)C
Thus the frequency of oscillation is
fo=1/T=(1.45/(RA+2RB)C)
Design Constraints
 The 555 Timer is a very versatile low cost timing IC that can produce a very accurate
timing periods with good stability of around 1%
 Duty cycle should be greater than 50% to 80%

43
 Single RC network connected to a single positive supply of between 4.5 and 16 volts.
 Load resistance minimum value is 1KΩ
6.3.3 Square wave generator
The square wave generator circuit is forced to operate in the saturated region.
That is, the o/p of the Op-Amp is forced to swing between positive saturation (+V sat)
and negative saturation (-Vsat), resulting in the square wave output. This square wave
generator is also called free running or astable multivibrator.


R2/[R1+R2]Vout = βVout

A fraction of the output (βV◦) is feedback to the input non-inverting terminal.

Thus the Vref is βV◦ and may take values as + βVsat or – βVsat. The output is also
feedback to the negative i/p terminal after integrating by means of a low pass RC
combination. Whenever the i/p at the negative terminal exceeds V ref switching takes
place resulting in a square wave output. Time period of square wave is given as

for R1 = 1.16 R2, it can be seen that T = 2RC.

T = 1.6 ms
V◦ = 24 V
Vsat = 12V; βVsat = 4v

44
6.3.4 RC phase shift oscillator
The feedback network consists of three identical RC sections. Each section produces a phase
shift of 60o Therefore, the net phase shift of the feedback is 180 o
The amplifier stage
introduces a phase shift of 180 o Therefore, the total phase shift between the input and output
is 360 o or 0 o. When the circuit is energized, by switching on the supply, the circuit starts
oscillating. The oscillations will be maintained if the loop gain is at least equal to unity.
Feedback fraction of the RC phase shift network
=1/29
The frequency of oscillation
f0=1/2 πRC6.
Circuit diagram

C=0.1µF, R=1.5K, R1=15K, RF=1M pot

Design:
f0=1/2 πRC6

Rf ≥ 29R1

R1 ≥ 10R
Choose C =0.1µF
f0 = 500 Hz

R= 1 = 1
62πf0C 62πx500x0.1x10−6

R = 1.3 KΩ
Choose R = 1.5KΩ

45
R1≥15KΩ (to prevent loading)

Therefore, R1 = 10R = 15KΩ

Rf = 29R1=29x15KΩ=435KΩ (Use 1MΩpot)

6.3.5 Wein Bridge Oscillator
It is commonly used in audio frequency oscillator. The feedback signal is connected in the
input terminal so that the output amplifier is working as a non-inverting amplifier. The Wien
bridge circuit is connected between amplifier input terminal and output terminal. The bridge
has a series R network, in one arm and a parallel RC network in the adjoining arm. In the
remaining two arms of the bridge, resistor R1 and Rf are connected. the phase angle criterion
for oscillation is that the total phase shift around the circuit must be zero. This condition
occurs when bridge is balanced. At resonance frequency of oscillation is exactly the
resonance frequency of balanced Wien bridge and is given by f0 = 1/ (2πfC).assuming that
the resistors are input impedance value and capacitance are equal to the value in the reactive
stage of Wien bridge. At this frequency, the gain required for sustained.

Design
Given, fo = 1KHz;
Assume C = 0.0015µF
fo = 1/(2π RC),
R = 100KΩ
Rf = 2R = 200KΩ

46
Design Constraints
 The loading effect of the amplifier on the feedback network has an effect on the
frequency of oscillations and can cause the oscillator frequency to be up to 25% higher
than calculated. Then the feedback network should be driven from a high impedance
output source and fed into a low impedance load such as a common emitter transistor
amplifier but better still is to use an Operational Amplifier as it satisfies these
conditions perfectly.
 The voltage gain of the Wein bridge oscillator circuit must be equal to or greater than
three “Gain = 3″ for oscillations to start.
 Due to the open-loop gain limitations of operational amplifiers, frequencies above
1MHz are unachievable without the use of special high frequency op-amps.

6.4 PRE-LAB
1. Choose the correct answer
I. A quasi-stable state is such that the output
1 a) does not change at all
b) Changes unpredictably
c) Changes after a predetermined period of time
d) Changes just after a very short duration of time.

II. A monostable multivibrator is also called a ‘one-shot multivibrator’ because

a) Each time a trigger pulse is applied, the circuit produces a single pulse.
b) The circuit has to be triggered only once
c) The output pulse duration is very small
d) None of the above.

III. true/false
Pin 5 is bypassed to ground through a 0.01 μF capacitor to prevent problems due to random
electrical noise. (True / False)

2. Give the condition which determines the frequency of oscillation

3. Give the formula to calculate frequency of oscillation for RC and Wein bridge oscillator.
4. Where do you use IC oscillators?

47
6.5 EXPRIMENT
6.5.1 MONOSTABLE MULTIVIBRATOR
1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply.
3. Give the trigger pulse to pin 2 just by touching the pin for second.
4. Trigger can be obtained from either CRO external 2v or FG.
5. Check the response by LED glowing upto the designed RC time delay.

6.5.2 ASTABLE MULTIVIBRATOR

1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.

Theoretical O/P Practical O/P

TOTAL TIME TOTAL TIME
TON TON
TOFF TOFF
AMPLITUDE of AMPLITUDE of
Close to VCC
Square . Square .
Charge & Discharging 2/3 VCC – 1/3 VCC Charge & Discharging

Of Capcitor by 3.3 – 1.6 = 1.7 v Of Capcitor by

measuring Amplitude measuring Amplitude

6.5.3 SQUARE WAVE GENERATOR

1. Connect the circuit as shown in the figure with the designed values. Choose
Rf=25KΩ, R1=100KΩ, R2=86KΩ and c=0.01uf.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.

48
Theoretical O/P Practical O/P
TOTAL TIME TOTAL TIME
TON TON
TOFF TOFF
AMPLITUDE of AMPLITUDE of
Close to VCC
Square . Square .
Charg& Discharging βVsat Charg& Discharging

Of Capcitor by Of Capcitor by
measuring Amplitude measuring Amplitude

6.5.4 WEIN BRIDGE OSCILLATOR

1. Design the circuit for f 0=500Hz.calculate R1,R2,and Rf
2. Connect the circuit as shown in the figure with the designed values.
3. Switch on the power supply and observe the waveform.
4. Note down the amplitude and time period.
5. Plot the waveforms on a graph sheet.
6.5.5 RC PHASE SHIFT OSCILLATOR
1. Design the circuit for f 0=1KHz.calculate R and Rf
2. Connect the circuit as shown in the figure with the designed values.
3. Switch on the power supply and observe the waveform.
4. Note down the amplitude and time period.
5. Plot the waveforms on a graph sheet.

Oscillator Amplitude Time Period

RC Phase shift
Wein Bridge Oscillator 6.5

6.6 POST LAB QUESTION

1. If the diode is connected across RB in the astable multivibrator circuit, what is condition
on RA and RB to achieve duty cycle of 50%?
2. What is the output state of a 555 timer connected in a monostable mode with a high
trigger input?

49
3. For the proper functioning of a monostable multivibrator, what must be the relative
magnitude of the pulse-width of the trigger input in comparison to the expected pulse-
width of the output waveform?
4. What are the merits and Demerits of RC phase shift oscillator?
5. Why do we need three RC networks for a phase shift oscillator?
6. Explain the main difference between an amplifier and an oscillator.

Result:

7. DESIGN OF LPF, HPF, BAND PASS FILTER AND

BAND REJECT FILTER.

7.1 OBJECTIVE
To design a low pass, high pass, Band pass and Band stop filter and plot the frequency
response.

S.No Equipment/Component name Specifications/Value Quantity

50
 Refer data sheet in
1 IC 741 1
appendix

2 Resistor 100KΩ,7.95KΩ 2

3 Capacitor 0.01uf 2

4 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

6 Regulated power supply (0 -5V), 1A 1

7 Function Generator (0-2) MHz 1

7.2 THEORY
A filter is a circuit that lets certain frequencies pass and blocks other frequencies. This
selective nature can be done two ways, either with passive filters or with active filters.
Passive filters completely comprised of passive elements; namely resistors, capacitors and/or
inductors. Active filters use active devices, i.e. an op-amp, to filter out unwanted signals.

Active filters have the following advantages over passive filters.

 Gain and frequency adjustment and tuning.
 No inductors (reduces cost and size).
 No loading effects.

Some disadvantages of active filters.

 Bandwidth limitations
 Fabrication tolerances
 Can only respond to a specific range of signal magnitudes.

Figure 1 shows the performance of an ideal low-pass, band-pass, and high pass circuit. Active
filters can be classified as; low-pass, high-pass, band-pass, notch, or all pass circuit. These
circuits are all used for different purposes, but this lab will focus on the design of second
order low pass and high pass Filters using PSPICE.

51
 Fig 1.Graph of practical (a) low pass and (b) high pass filter (c) Band Pass filter
(d) Band Stop filter

SECOND ORDER LOW PASS FILTER

Fig.2.Second-Order low-pass filter

Design:
Given fc=2khz,
Choose C1=C2=0.01uf fc=1/2πRC R1=100kΩ α=3-A
Α=1.414 A=1.586
A=1+Rf/R1

SECOND ORDER HIGH PASS FILTER

52
 Fig.3.Second-Order high-pass filter
BAND PASS FILTER
The bandpass filter passes one set of frequencies while rejecting all others. The band-stop
filter does just the opposite. It rejects a band of frequencies, while passing all others. This is
also called a band-reject or band-elimination filter. Like bandpass filters, band-stop filters
may also be classified as (i) wide-band and (ii) narrow band reject filters.

The narrow band reject filter is also called a notch filter. Because of its higher Q, which
exceeds 10, the bandwidth of the narrow band reject filter is much smaller than that of a wide
band reject filter.
Design:
Fc=1/2πRC choose c1=c2=0.01uf A=1+Rf/R1

Band Pass Filter

Fig 4 Band Pass Filter

Design:

53
f1=1Khz
F’=10Khz
R1=10K c1=c2=0.04uf

This cascading together of the individual low and high pass passive filters produces a low
“Q-factor” type filter circuit which has a wide pass band. The first stage of the filter will be
the high pass stage that uses the capacitor to block any DC biasing from the source. This
design has the advantage of producing a relatively flat asymmetrical pass band frequency
response with one half representing the low pass response and the other half representing
high pass response as shown.

The higher corner point ( ƒH ) as well as the lower corner frequency cut-off point ( ƒL ) are
calculated the same as before in the standard first-order low and high pass filter circuits.
Obviously, a reasonable separation is required between the two cut-off points to prevent any
interaction between the low pass and high pass stages. The amplifier also provides isolation
between the two stages and defines the overall voltage gain of the circuit.

The bandwidth of the filter is therefore the difference between these upper and lower -3dB
points. For example, if the -3dB cut-off points are at 200Hz and 600Hz then the bandwidth of
the filter would be given as: Bandwidth (BW) = 600 – 200 = 400Hz. The normalized
frequency response and phase shift for an active band pass filter will be as follows.

While the above passive tuned filter circuit will work as a band pass filter, the pass band
(bandwidth) can be quite wide and this may be a problem if we want to isolate a small band
of frequencies. Active band pass filter can also be made using inverting operational amplifier.
So by rearranging the positions of the resistors and capacitors within the filter we can
produce a much better filter circuit as shown below. For an active band pass filter, the lower
cut-off -3dB point is given by ƒC2 while the upper cut-off -3dB point is given by ƒC1.

54
BAND-STOP (OR REJECT) FILTER.

Fig 5 Band Stop Filter

55
A wide band-stop filter using a low-pass filter, a high-pass filter and a summing amplifier
is shown in figure. For a proper band reject response, the low cut-off frequency f L of high-
pass filter must be larger than the high cut-off frequency f H of the low-pass filter. In addition,
the pass band gain of both the high-pass and low-pass sections must be equal.

This is also called a notch filter. It is commonly used for attenuation of a single frequency
such as 60 Hz power line frequency hum. The most widely used notch filter is the twin-T
network illustrated in fig. (a). This is a passive filter composed of two T-shaped networks.
One T-network is made up of two resistors and a capacitor, while the other is made of two
capacitors and a resistor. One drawback of above notch filter (passive twin-T network) is that
it has relatively low figure of merit Q. However, Q of the network can be increased
significantly if it is used with the voltage follower. Here the output of the voltage follower is
supplied back to the junction of R/2 and 2 C.

7.3 PRE-LAB
1. Compute the transfer function of the amplifier in Figure assuming an ideal op-amp.
Use the PSPICE model of an op-amp and verify your results in PSPICE using the following
values: Vcc=+12V, Vee=-12V, R1=1kΩ, and VS being a sin wave with a frequency of 10 kHz
and amplitude of 1mV.

7.4 EXPERIMENT

7.4.1 Low pass filter

56
Design a Second order low pass filter as shown in figure 2 for the values R1 = R2=3.3KΩ,
C2=C4=0.047uF, Rx=5.8KΩ, Ry-10KΩ and sinusoidal input of amplitude 1V and frequency
10KHz.

7.4.2 High pass filter

Design a Second order High pass filter as shown in figure 3 for the values R1 = R2=3.3KΩ,
C2=C4=0.047uF, Rx=5.8KΩ, Ry=10KΩ and sinusoidal input of amplitude 1V and frequency
10KHz.

7.4.3 Band Pass Filter

Design a Band Pass Filter as shown in figure 4 keep the same values of low pass and high
pass filter values and sinusoidal input of amplitude 1V and frequency 10KHz.

7.4.4 Band Stop Filter

Design a Band Stop filter as shown in figure 5 for the corresponding values as in figure and
sinusoidal input of amplitude 1V and frequency 10KHz.

7.5 TEST PROCEDURE

1. Open the Pspice AD Lite software by double clicking its icon.
2. After few moments Command window will appear.
7. Go to the File Menu and select a New text file. (File Newtext file)
8. A blank text file will appear with a title ‘untitled’
9. Now start typing your program. After completing, save the text file as .cir with
appropriate name. To execute the program go to Debug Menu and select Run.
10. After execution output will appear in the Command window. If there is an error then with
an alarm, type of error will appear.
11. If the results contain errors, start up the text editing program again and modify the net list.
12. Rectify the error if any and go to Debug Menu and select Run.
13. If there is no errors go to Trace menu and click add trace. Enter the output node voltage
and click ok then the output will display.

57
7.6 POST LAB QUESTION

1. Derive the transfer function of the circuit in Figure. By observing the transfer function,
what is the purpose of this topology? Verify your results in PSPICE with an “AC”
simulation using R1=500 Ω, R2=2.5kΩ, a source with a 0.5V magnitude, and C=0.01F.
Do the PSPICE results agree with what you derived?

58
 8. IC VOLTAGE REGULATOR
8.1 OBJECTIVES

Design a voltage regulator of 9v using op amp IC741.

RZ=5k, RL =100, RF1=5K
RF2=10K
NPN TRANSISTOR BF=100
DIODE D1N746

8.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Resistors 5K Ω 2

100 Ω 1

10K Ω 1

3 Transistor BF100 1

4 Diode DIN746 1

5 Dual Regulated power supply (0 -30V), 1A 1

6 Multimeter 1

8.3 THEORY
A voltage regulator is a voltage stabilizer that is designed to automatically stabilize a
constant voltage level. A voltage regulator circuit is also used to change or stabilize the
voltage level according to the necessity of the circuit. Thus, a voltage regulator is used for
two reasons:
1. To regulate or vary the output voltage of the circuit.
2. To keep the output voltage constant at the desired value in-spite of variations in the
supply voltage or in the load current.
All electronic voltage regulators will have a stable voltage reference source which is
provided by the reverse breakdown voltage operating diode called zener diode. The main
reason to use a voltage regulator is to maintain a constant dc output voltage. It also blocks
the ac ripple voltage that cannot be blocked by the filter. A good voltage regulator may also
include additional circuits for protection like short circuits, current limiting circuit, thermal
shutdown, and over voltage protection. Electronic voltage regulators are designed by any of
the three or a combination of any of the three regulators given below.

59
 A zener controlled voltage regulator is used when the efficiency of a regulated power
supply becomes very low due to high current. There are two kinds of zener controlled
transistor voltage regulators. Zener Controlled Transistor Series Voltage Regulator is a
circuit is also named an emitter follower voltage regulator. It is called so because the
transistor used is connected in an emitter follower configuration. The circuit consists of an
N-P-N transistor and a zener diode. As shown in the figure below, the collector and emitter
terminals of the transistor are in series with the load. Thus this regulator has the name series
in The output of the rectifier that is filtered is then given to the input terminals and regulated
output voltage Vload is obtained across the load resistor Rload. The reference voltage is
provided by the zener diode and the transistor acts as a variable resistor, whose resistance
varies with the operating conditions of base current, Ibase. The main principle behind the
working of such a regulator is that a large proportion of the change in supply or input
voltage appears across the transistor and thus the utput voltage tends to remain constant.
The output voltage can thus be written as
Vout = Vzener – Vbe
The transistor base voltage Vbase and the zener diode voltage Vzener are equal and thus the
value of Vbase remains almost constant.
Operation
When the input supply voltage Vin increases the output voltage Vload also increases. This
increase in Vload will cause a reduced voltage of the transistor base emitter voltage Vbe as
the zener voltage Vzener is constant. This reduction in Vbe causes a decrease in the level of
conduction which will further increase the collector-emitter resistance of the transistor and
thus causing an increase in the transistor collector-emitter voltage and all of this causes the
output voltage Vout to reduce. Thus, the output voltage remains constant. The operation is
similar when the input supply voltage decreases. The next condition would be the effect of
the output load change in regard to the output voltage. Let us consider a case where the
current is increased by the decrease in load resistance Rload. This causes a decrease in the
value of output voltage and thus causes the transistor base emitter voltage to increase. This
causes the collector emitter resistance value to decrease due to an increase in the conduction
level of the transistor. This causes the input current to increase slightly and thus compensates
for the decrease in the load resistance Rload. The biggest advantage of this circuit is that the
changes in the zener current are reduced by a factor β and thus the zener effect is greatly
reduced and a much more stabilized output is obtained. The output voltage of the series
regulator is Vout = Vzener – Vbe. The load current Iload of the circuit will be the maximum
emitter current that the transistor can pass. For a normal transistor like the 2N3055, the load
current can go upto 15A. If the load current is zero or has no value, then the current drawn
from the supply can be written as Izener + Ic(min). Such an emitter follower voltage regulator
is more efficient than a normal zener regulator. A normal zener regulator that has only a
resistor and a zener diode has to supply the base current of the transistor.
Limitations
The limitations listed below has proved the use of this series voltage regulator only suitable
for low output voltages.
1. With the increase in room temperature, the values of Vbe and Vzener tend to
decrease. Thus the output voltage cannot be maintained a constant. This will further
increase the transistor base emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to the small amplification process provided by only one transistor, the circuit
cannot provide good regulation at high currents.
4. When compared to other regulators, this regulator has poor regulation and ripple
suppression with respect to input variations.

60
 5. The power dissipation of a pass transistor is large because it is equal to Vcc Ic and
almost all variation appears at Vce and the load current is approximately equal to collec-
tor current. Thus for heavy load currents pass transistor has to dissipate a lot of power
and, therefore, becoming hot.

Fig 1
RZ=5k RL =100 RF1=5K RF2=10K
NPN TRANSISTOR BF=100
DIODE D1N746

Calculations:
Zener voltage Vz= 3V RF2=10k, RF1=5K,
Output voltage = 3 x (1+10/5) = 9V.

EXPERIMENT
1. Setup the circuit as shown in Figure-1.
2. Reference voltage VR is set as 5V and input voltage Vi=10v
3. Find the output voltage Vo for different values 0f RF2.
Experimental data and observations
Load Regulation VIN=

S.NO. RL(Ω) VOUT(V)

Line Regulation RL=

S.NO. RL(Ω) VOUT(V)

61
PRE LAB QUESTIONS
1. A voltage regulator with a no-load output dc voltage of 12v is connected to a load with a
resistance of 10. If the load resistance decrease to 10.9v. Calculate load current and the
percent load regulation.
2. The ________ regulator is less efficient than the ________ type, but offers inherent short-
circuit protection.

POST LAB QUESTIONS

1. Calculate the voltage regulation of a power supply having VNL = 50 V and VFL = 48 V.
2. What is the purpose of an additional RC filter section in a power supply circuit?

Result:

9. R-2R LADDER DAC

62
9.1 OBJECTIVES
1. Design a D to A Convertor with a resolution of 0.3125V using R-2R network.
Assume the logic 1 to be 5V and logic 0 to be 0V.
2. Design a D to A Convertor with a resolution of 0.3125V using binary weighted
resistors. Assume the logic 1 to be 5V and logic 0 to be 0V.

9.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

3 Resistors 4K Ω 1

2K Ω 7

1K Ω 4

5 Dual Regulated power supply (0 -30V), 1A 1

5 Regulated power supply (0 -5V), 1A 1

6 Multimeter 1

9.3 THEORY
In electronics, a digital-to- analog converter (DAC or D-to-A) is a device for converting a
digital (usually binary) code to an analog signal (current, voltage or electric charge). Digital-
to-analog converters are the interface between the abstract digital world and the analog real
life. An analog-to-digital converter (abbreviated ADC, A/D or A to D) is an electronic circuit
that converts continuous signals to discrete digital numbers. Most of the real world physical
quantities such as voltage, current, temperature, pressure and time are available in analog
form. Even though an analog signal represent a real physical parameter with accuracy, it is
difficult to process, store or transmit the analog signal without introducing considerable error
because of the superimposition of noise as in the case of amplitude modulation. Therefore,
for processing, transmission and storage purposes, it is often convenient to express these
variable in digital form. It gives better accuracy and reduces noise.
D/A conversion is an important interface process for converting digital signals to
analog (linear) signals. An example is a voice signal that is digitized for storage processing,

63
or transmission and must be changed back into an approximation of the original audio signal
in order to drive a speaker.

Figure-1: A basic DAC

D/A Conversion fundamentals
The DAC fundamentally converts finite-precision numbers (usually fixed-point binary
numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage
is a linear function of the input number.

Figure-2: Block Schematic of a basic DAC

Figure-2 shows the basic configuration for digital-to-analog (D/A) conversion. The
input is an n-bit binary word D and is combined with a reference voltage VR to give an
analog output signal. The output of a DAC can be either a voltage or current. For a voltage
output DAC, the D/A converter is mathematically described as
-1 -2 -n
Vo = K VFS (d12 + d22 +….+dn2 )

Where, Vo = output voltage

VFS = full scale output voltage

K = scaling factor usually adjusted to unity

d1 d2... dn = n-bit binary fractional word with the decimal point located at

64
 the left d1 = most significant bit (MSB) with a weight of V FS / 2

n
dn = least significant bit (ISB) with a weight of V Fs / 2

Since the input to the D/A converter has a finite number of digital combinations, the resulting
analog output also has a limited number of possible values (unlike pure analog signals, which
may have an infinite number of values). The greater the number of possible values, the closer
the analog output will be to the ideal value. The number of possible levels is determined by
the number of lines or bits in the digital number. More specifically, the number of states is
computed as 2N where N is the number of bits in the digital number. For example, an 8-bit
D/A converter could be expected to produce 2 8, or 256, discrete output steps. If the full-scale
range of the converter is 0 to 10 volts, then each step will be 10/256, or about 39 millivolts. If
finer resolution is required, we need more bits in the digital number. Thus, a converter with
10-bit resolution would provide 210, or 1024, steps with each step being equivalent to
10/1024, or about 9.8 millivolts. Accuracy of a D/A converter describes the amount of error
between the actual output of the converter and the theoretical output for a given input
number. This rating inherently includes several other sources of error.

A certain amount of time is required for the output of a D/A converter to be correct
once a particular digital number has been applied at the input. Two major factors cause this
delay. First, it takes time for the changes to pass through the converter circuitry; this is called
propagation time. Second, the output of the D/A converter has a maximum rate of change
called slew rate, which is identical to the slew rate problems discussed with reference to op
amps. The delays caused by slew rate limiting and propagation time are collectively referred
to as settling time--the total time required for the analog output to stabilize after a new digital
number has been applied to the input.

65
 The overall operating range of a D/A converter can be shifted up or down from the
optimum point. This DC offset is called offset error. In a somewhat similar manner, one end
of the range can be correct but the other extreme too high or too low. This is called a gain
error or scaling error.

As with A/D converters, we normally want a monotonic output. In other words, the
output should increase whenever the input number increases. However, it is possible for a
D/A converter to have a reduction in analog output at a particular point in its range, even
though the digital input is increasing uniformly.

Figure-3: Oscilloscope display showing several imperfections in a low-quality D/A converter.

Figure-3 shows the performance of a low-quality D/A converter. Several of the potential
problems described are present in the converted waveform. The input to the converter is a 4-bit
down counter (e.g., 15, 14, 13... 2, 1, 0, 15), and the analog output should be 16 equally spaced,
decreasing steps for each cycle, producing a reverse saw tooth waveform. If you examine the
waveform carefully, you can see the 16 distinct output levels; however, the steps are not equal in
amplitude (linearity problems)--the midpoint level actually increases instead of decreasing (non
monotonic), and there are several glitches caused by switching transients.

66
R2R LADDER D/A CONVERTER
One of the most popular methods for D/A conversion is shown in Figure-5. It is called
an R2R ladder D/A converter, since the input network resembles the rungs on a ladder and the
resistors in the input network are either equal (R) or have a 2:1 ratio (2R). One advantage of
the R2R converter over the weighted converter previously discussed is immediately apparent;
the resistors have a 2:1 ratio regardless of the number of bits being converted. This makes
matching resistors much easier and even makes the use of integrated resistors practical.
An easy way to analyze the operation of the circuit is to Thevenize the input circuit
for one or more digital input numbers. Once the input circuit has been simplified with The
venin’s Theorem, you will be left with a simple inverting amplifier circuit whose input
voltage is the The venin equivalent voltage and whose gain is determined by the ratio of
feedback resistance to The venin equivalent input resistance. By performing several analyses
with different input numbers, you will discover that the least significant input (b0) produces
the least effect on output voltage, and the next input (bl) has twice as much effect on output
voltage. Similarly, bit b2 has twice the effect of b1, but only half the effect onoutput voltage
of b3. These variable effects are identical to the relative weights of the digits in a binary
number.

Figure-5: A 3-bit R2R ladder D/A converter utilizing a 741 op amp

Calculations: Output Voltage is given by

Vo = - VR * (Rf / 2R) * ( b2/2 + b1/4 + b0/8 )

67
 where, VR = 5V , Rf = 2R , b2(MSB bit ) and b0 (LSB bit )
Design Constraints
 Resistance should be use ±1 to ±5 tolerance
 Input voltage should be 5V for high and 0V for low.

EXPERIMENT

(a) R-2R LADDER DAC

1. Setup the circuit as shown in Figure-5. Select the approximate value of R and
2R
2. Set the approximate value of R and 2R.
3. Reference voltage VR is set as 5V
4. Find the output voltage Vo for different combinations of digital binary inputs
from 000 to 111.
5. Compare the calculated values with observed values and plot DAC
characteristics

(b) Experimental data and observations

R-2R LADDER DAC

b2 b1 b0 Vo ( observed) Vo ( Calculated)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 0 1
1 1 0
1 1 1

68
PRE LAB QUESTIONS

1. Classify DACs on the basis of their output.

2. How many resistors are required in a 12-bit weighted-resistor DAC?
3. How many levels are possible in a 2-bit DAC? What is its resolution if the output voltage
range is 0 to 3 V?
4. A 5-bit D/A converter is available. Assume that ‘00000’ corresponds to an output of +10 V
and that the D/A converter is connected for -0.1V per increment. What output voltage will be
produced for ‘11111’?

POST LAB QUESTIONS

1. Determine the output voltage of the DAC in Figure-7(a). The sequence of four-digit binary codes
represented by the waveforms in Figure-7(b) are applied to the inputs. A high level is a binary l,
and low level is a binary 0. The least significant binary digit is Do.

Figure-7

2. The R-2R ladder DAC shown in Figure-8 below consists of 10K & 20KΩ resistors, V REF =
2V and R1 = 10KΩ. Determine the values required for R F such that VFS = 10V.

Figure-8

69
 10. FLASH TYPE ADC

10.1 OBJECTIVES
To construct a FLASH type A to D Convertor using PSPICE simulation.

10.2HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 LM324 Refer data sheet in 1

appendix

3 Resistors 1K Ω 8

5 Dual Regulated power supply (0 -30V), 1A 1

5 Regulated power supply (0 -5V), 1A 1

6 Multimeter 1

10.3THEORY
A flash ADC (also known as a direct-conversion ADC) is a type of analog-to-digital
converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to
compare the input voltage to successive reference voltages. Often these reference ladders are
constructed of many resistors; however, modern implementations show that capacitive
voltage division is also possible. The output of these comparators is generally fed into a
digital encoder, which converts the inputs into a binary value (the collected outputs from the
comparators can be thought of as a unary value).Flash converters are extremely fast
compared to many other types of ADCs, which usually narrow in on the "correct" answer
over a series of stages. Compared to these, a flash converter is also quite simple and, apart
from the analog comparators, only requires logic for the final conversion to binary. For best
accuracy, often a track-and-hold circuit is inserted in front of the ADC input. This is needed
for many ADC types (like successive approximation ADC), but for flash ADCs there is no
real need for this, because the comparators are the sampling devices.

A flash converter requires a huge number of comparators compared to other ADCs,

especially as the precision increases. A flash converter requires comparators for an n-bit
conversion. The size, power consumption and cost of all those comparators makes flash
converters generally impractical for precisions much greater than 8 bits (255 comparators). In
place of these comparators, most other ADCs substitute more complex logic and/or analog
circuitry that can be scaled more easily for increased precision. Flash ADCs have been
implemented in many technologies, varying from silicon-based bipolar (BJT) and
complementary metal–oxide FETs (CMOS) technologies to rarely used III-V technologies.
Often this type of ADC is used as a first medium-sized analog circuit verification.

70
 The earliest implementations consisted of a reference ladder of well matched resistors
connected to a reference voltage. Each tap at the resistor ladder is used for one comparator,
possibly preceded by an amplification stage, and thus generates a logical 0 or 1 depending on
whether the measured voltage is above or below the reference voltage of the resistor tap. The
reason to add an amplifier is twofold: it amplifies the voltage difference and therefore
suppresses the comparator offset, and the kick-back noise of the comparator towards the
reference ladder is also strongly suppressed. Typically designs from 4-bit up to 6-bit and
sometimes 7-bit are produced.
Designs with power-saving capacitive reference ladders have been demonstrated. In
addition to clocking the comparator(s), these systems also sample the reference value on the
input stage. As the sampling is done at a very high rate, the leakage of the capacitors is
negligible.Recently, offset calibration has been introduced into flash ADC designs. Instead of
high-precision analog circuits (which increase component size to suppress variation)
comparators with relatively large offset errors are measured and adjusted. A test signal is
applied, and the offset of each comparator is calibrated to below the LSB value of the ADC.
Another improvement to many flash ADCs is the inclusion of digital error correction. When
the ADC is used in harsh environments or constructed from very small integrated circuit
processes, there is a heightened risk that a single comparator will randomly change state
resulting in a wrong code. Bubble error correction is a digital correction mechanism that
prevents a comparator that has, for example, tripped high from reporting logic high if it is
surrounded by comparators that are reporting logic low.

71
 Fig 1 Flash type ADC

Fig 2 IC pin configuration LM324

Fig 3 IC pin configuration 74LS148

EXPERIMENT
Flash type ADC
Setup the circuit as shown in Figure-1. Select the approximate value of R=1K ohm.
Reference voltage Vref is set as 5V
Find the output voltage Vo by adjusting Vin and obtain digital output.

72
 Compare the analog input values with observed Digital output.
Experimental data and observations
Analog Comparator o/p Digital o/p Analog i/p
Observed
i/p _ _ _ _ _ _ _ _ _ _ _
(0-5v) I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 (v)

0-0.5 1 1 1 1 1 1 1 0 0 0 0
0.5-1.0 1 1 1 1 1 1 0 1 0 0 1
1.0-1.5 1 1 1 1 1 0 1 1 0 1 0
1.5-2.0 1 1 1 1 0 1 1 1 0 1 1
2.0-2.5 1 1 1 0 1 1 1 1 1 0 0
2.5-3.0 1 1 0 1 1 1 1 1 1 0 1
3.-3.5 1 0 1 1 1 1 1 1 1 1 0
3.5-4.0 0 1 1 1 1 1 1 1 1 1 1

Design Constraints
 Resistance should be use ±1 to ±5 tolerance
 Input voltage should be 5V for high and 0V for low.

PRE LAB QUESTIONS

1. Classify ADCs on the basis of their output.
2. Mention the control lines present in ADC.
3. Which type of ADC follows conversion technique of changing the analog input voltage as a
function of frequency?

POST LAB QUESTIONS

1. Calculate the conversion time of a 12-bit counter type ADC with 1MHz clock
frequent to convert a full scale input?
2. How many comparators are required for 4-bit ADC?

73
 11 SIMULATION EXPERIMENT USING EDA TOOLS
AC AMPLIFIERS
11.1 OBJECTIVE
To sketch the following basic op-amp circuits and explains the operation of each:
Inverting amplifier
Non-inverting amplifier

11.2 SOFTWARE REQUIRED

ORCAD 9.2

11.3 THEORY

11.3.1 AC AMPLIFIER

The inverting and non-inverting op-amp amplifier configurations respond to both ac and dc
signals. To get the ac frequency response of an op amp or if the ac input signal is
superimposed with dc level, it becomes essential to block the dc component. This is achieved
by using an AC amplifier with a coupling capacitor. AC amplifiers are of inverting and non-
inverting type.

11.3.2 INVERTING AC AMPLIFIER

The circuit is shown in below figure. The capacitor blocks the dc component of the input and
together with the resistor R1 sets the lower 3 dB frequency of the amplifier.

74
11.3.3 NON-INVERTING AMPLIFIER
In most cases it is possible to DC couple the circuit. However in this case it is necessary to
ensure that the non-inverting has a DC path to earth for the very small input current that is
needed. This can be achieved by inserting a high value resistor, R3 in the diagram, to ground
as shown below. The value of this may typically be 100 k ohms or more. If this resistor is not
inserted the output of the operational amplifier will be driven into one of the voltage rails.
When inserting a resistor in this manner it should be remembered that the capacitor-resistor
combination forms a high pass filter with a cut-off frequency. The cut-off point occurs at a
frequency where the capacitive reactance is equal to the resistance.

Inverting Amplifier
Design an inverting amplifier for the gain of 15. Let R1=1.5k, C=0.1µF.

Non-Inverting amplifier
Design a non-inverting amplifier for the gain of 15. Let R1=1.5k , C=0.1µF.

75
TEST PROCEDURE
1. Open the Pspice AD Lite software by double clicking its icon.
2. After few moments Command window will appear.
3. Go to the File Menu and select a new text file. (File  New text file)
4. A blank text file will appear with a title ‘untitled’
5. Now start typing your program. After completing, save the text file as .cir with
appropriate name. To execute the program go to Debug Menu and select Run.
6. After execution output will appear in the Command window .If there is an error then
with an alarm, type of error will appear .
7. If the results contain errors, start up the text editing program again and modify the
net list.
8. Rectify the error if any and go to Debug Menu and select Run.
9. If there is no errors go to Trace menu and click add trace. Enter the output node
Voltage and click ok then the output will display.

Prelab
1. What is the input impedance of a non inverting op-amp amplifier?
2. If the open loop gain of an op-amp is very large, does the closed loop gain depend upon
the external components or the op-amp?
3. Define common mode rejection ratio
4. Explain the meaning of open loop and closed loop operation of an op- amp?
5. What is a practical op-amp? Draw its equivalent circuit.

Postlab
1. Determine the bandwidth of a non-inverting amplifier, voltage follower and inverting
amplifier
2. Determine the gain-bandwidth product of each amplifier.
3. Determine the input and output impedances of each amplifier.

76