1997 IEEE International Symposium on Circuits and Systems, June 9-12,1997, Hong Kong

High-Level Power Estimation of VLSH Systems

W.Fornaciari (l), P.Gubian (2), D S c i u t o (l), C.Silvano (2)
( I ) Politecnico di Milano, Dip. di Elettronica e Informazione, P.zza L.Da Vinci, 32 - 201133 Milano, Italy
(2) Univ. degli Studi di Brescia, Dip. di Elettronica per l'Automazione, Via Branze, 38 - 25123 Brescia, Italy

Abstract
The goal of this paper is to present an innovative conceptual
framework suitable for achieving accurate and eficient
estimation of power dissipation for data-path intensive
architectures described at RT and Behavioral levels. The aim is to
provide the designer with the capability of analyzing different
solutions in the architectural design space, before the synthesis
tasks.
The proposed methodology addresses all the elements
composing a typical data-path architecture, such as storage units,
functional units and multiplexers. The paper includes
experimental results demonstrating the validity of the proposed
approach.
1. Introduction
Power dissipation has become one of the main constraints during
the design of integrated circuits (ICs) in the recent years, due to
the steady increasing of integration level and operating frequency.
Such aspects, combined with the growing demand of portable
systems supplied with limited batteries (e.g., portable PCs, lap-
tops, PDAs, cellular phones) contributed to increase the
importance of power dissipation issues during the design of
electronic systems.
VLSI designers need for advanced techniques and related tools
for the early estimation of power dissipation during the design
phases, in order to satisfy the power constraints without reducing
significantly the global performances. The goal is to meet the
design tum-around time deadlines, while exploring the space of
possible design altematives. Accuracy and efficiency of a high
level analysis approach should be the "booster" to meet the power
requirements, avoiding a costly redesign process. It has to be
pointed out that relative accuracy in power estimation is more
important than absolute accuracy since, usually, the main goal is
to compare altemative design solutions [l].
General surveys of VLSI power estimation techniques can be
found in [ I ] , [2], [3], [4] An important aspect is that most of the
average power dissipation in CMOS technology i s strongly
related to the switching activity of the circuit nodes. Such a fact is
indicated in [3] as stating that the power estimation is a pattem-
dependent process.
Analytical and stochastic power estimation techniques at
behavioral level have been proposed in [5], targeting real time
DSP applications on ASIC architectures. The power dissipated by
some ASIC components, such as data-path components, have
been analytically estimated from the Control Data Flow Graph
(CDFG) representing the design. For other ASIC components,
such as interconnects and controllers for which the power
information available at the behavioral level are not sufficient,
statistical models were built to estimate power based on a
stochastic study on 23 different ASICs, showing an average error
of approximately 20%. However, the proposed models do not
account for the power consumed by multiplexers and memories.
Power estimation techniques based on high level descriptions
have been also proposed in [ 6 ] ,tailored to data-path architectures.
These techniques derive stochastic models of busses and intemal
modules from the statistic behavior of inputs. In [ 7 ] , a power
estimation model for data-path architectures operating at the RTL
level is described. The model accounts for the switching activity
by using the Dual Bit Type (DBT) method, considering two input
bit types rather than one: the random activity of the least
significant bits (LSB's) and the correlated activity of the most
significant bits (MSB's).
The aim of this paper is to provide a conceptual analysis
framework for accurate and efficient estimation of power
dissipation in embedded and VLSI systems at the architectural
level. Such a choice is motivated by the fact that architectural
level and its corresponding RTL description, are the dl-sign entry
point for the majority of embedded systems and IC designs.
In the proposed approach, the target embedded system
architecture for power estimation (to be implemented in a single
ASIC) is similar to those proposied in [ 5 ] ,[8] (see figure 1).
MElrlIlRY
Figure 1. Target architecture at RT level
The ASIC architecture is defined at a pre-synthesis RT-Level and
consists of the following components:
data-path, composed of storage units, functional units and
multiplexers. The typical operaition along the data-path implies a
register-to-register transfer, consisting of operand read from
storage units, an operation performed on the operands and the
results stored in another register [8];
memories, such as single and multi-port memories, cache
memories, TLBs, FIFOs and LIFOs, etc.; we assuime that all
readwrite accesses to the mernory will be performed through a
register;
control unit, implemented as a set of finite state machines and
generating the control lines for the data-path components and the
memories;
embedded core processor, such as a standard processor, a
microcontroller, a DSP, etc ..., with its memory (even if part of the
memory can be extemal) implementing the SW bound part;
clock distribution logic;
crossbar network, to interface the architectural units by using a
communication protocol at system level. The interconnection
power of the crossbar network is included in the power dissipated

0-7803-3583-X/97 $10.00 01997 IEEE 1804

by the outputs of data-path, memories and control logic;
primary UOpads.
Due to space limits, this paper deals only with the estimation of
the data-path power budget. The proposed analysis framework is
based on the ASIC model at the behavioralmT level specified by
using the VHDL language. The entire analysis is based on the
probabilistic estimation of the switching activity. The inputs for
the analysis are:
the ASIC specification, consisting of a hierarchical VHDL
description implementing the target system architecture depicted
in figure 1;
an aZlocation library, composed of available components
implementing basic blocks such as registers, adders, multipliers.
multiplexers, logic gates, 1/0 buffers, etc. Each component is
specified in terms of models describing logic behavior, input
capacitances, area and power characteristics dependent on the
chosen technology;
technological parameters, such as frequency, power supply,
derating factors (considering the effects of variations in process,
voltage and temperature), etc.;
the switching behavior, of the ASIC primary 110 pads in terms of
toggle rate of the input, output and bi-directional nets.
The paper is organized as follows. The discussion starts by
introducing the switching activity factors, derived from system
specifications, constituting the basis of the analysis. The proposed
estimation model is presented in Section 3, along with its formal
definitions. Results obtained from a data-path application
benchmark are reported in Section 4, which also outlines the
future developments of our investigation.
2. Background of the analysis
Power dissipation in CMOS circuits can be considered as
composed of both static and dynamic components. Static power is
mainly due to leakage currents due to reverse-biased diodes and
suh-threshold transistor conduction. However, the dominant part
of the power budget in CMOS circuits is due to dynamic power
and it is composed of two terms [2].The first term, indicated as
switching activity power (Psw), is due to the charge and discharge
of the circuit node capacitances on the output of each logic gate
and usually accounts for over 90% of the total power [2].The
second term, indicated as short-circuit power (PSH),represents the
short-circuit current from the supply to ground during output
transition, which can be usually ignored, since it represents the
5t10 % of the dynamic power [I], [2]. In general, the values of
Psw and PSH are not directly accessible separately, being the
available data of standard libraries normally expressed in terms of
average power, gathering both dynamic contributions [9].
Regarding the switching activity of each signal(a primary I/O or
an internal signal), it is fully characterized by the following two
components[4]: a static component, takmg into account the static
probability of a signal; a dynamic component, taking into account
the timing behavior of the circuit.
The static component can be expressed in terms of the static
signal ],robability pnlof each node n (note that p,,’5 1 and p,,” = 1
- P,,’).
The dynamic component is based on the definition of the
transition probability pno’ of each node n, that is the probability of
a zero to one transition. In the spatial and temporal independence
assumption ( [ 3 ] ) ,the transition probability p i i 1 is given by the
probability that the current state is zero times the probability that
the next state is one: pii1 = p / p n z = (1 - pnl)pnl. Under the same
assumption, the switching activity actor of a node 12, indicated as
it
q, i s given by: W, = pI:’ + p n = 2 p n l ( l - pn1J Given the
switching activity factor cl, of a node n, the corresponding toggle
rate can be defined as TR,= ol, fc-K, where f c L K is the system
1805
clock frequency.
The values of the toggle rates for the input, output and bi-
directional nets of the ASIC should be provided with the
specifications at the system-level. The values of these parameters
for the internal nets will be derived from the specifications in the
proposed model.
3. Power estimation model of the target architecture
In the proposed single ASIC architecture, the average power PAVE
can be subdivided into PAvE=PIo+P~oRE, where PIo and Pco, are
the average power of the I/O nets and intemal nets of the ASIC,
respectively.
The proposed model is based on the following assumptions:
the supply and ground voltage levels in the ASIC are fixed,
although it is worth noting the impact of supply voltage
reduction on power;
the design style is based on synchronous sequential circuits;
the data transfer occurs at the register-to-register level;
a Zero Delay Model has been used, thus ignoring the
contribution of glitches and hazards to power.
PIo estimation. Although a pre-synthesis analysis is performed, it
is assumed to know the ASIC interface in terms of primary I/O
buffer characteristics and related switching activity from the
system specifications.
The set S of input, output and bidirectional nets of the ASIC can
be subdivided into sets s k of nk nets each, corresponding to the
same type tk of I/O buffers S= {sI,sz, ..., sk, ..., sN}. If the generic
set sk is composed of output buffers of type tk, the average power
of the set sk can be estimated as Pk = nk PtkT R k 6, where nk is the
number of output nets in the set ski Plk is the average power
consumption per MHz of a single output buffer of type tk. The
value of Ptk is computed as a function of the output load Ck at a
given reference frequency fo. “RI, is the toggle rate of the output
nets of the set sk, derived from system specifications; 6 is the
derating factor takmg into account the derating of the power
values contained in the target library; this parameter models the
variations in process, voltage and temperature (note that the
previous equation for P, is valid in a range of fO). Similarly, the
average power of input buffers can be computed, depending on
estimated intemal standard loads and input ramptime.
PcoRE estimation. The PCoE estimation model is based on the
different components of the target architecture at RTL level. P,,,,
can be detailed as:
PCoRE=PDP + PMEM+ PcNTR+ P P R ~ Cwhere , the single terms
represent the average power dissipated by the data-path, the
memories, the control logic and the embedded core processor. The
present paper takes into account only the terms related to the data-
path power.
Pnp estimation. Let P D represents
~ the average power of the data-
path, expressed as P D ~ PEG
= + PMUX + Pw, where PREG is the
power of the registers or reaster files; PMUXis the power of the
multiplexers; PFu is the power of the functional units.
PREGestimation. The preliminary step is the estimation of the
required registers and, consequently, the values of the maximum
toggle rate TR, for each of them. According to the considered
level of abstraction, such data are directly available for RTL
description or live variable analysis [8] can be applied to VHDL
behavioral level specifications.
The algorithm to estimate the number of registers is similar to the
one proposed in [8], for the computation of the lifetime of a
variable in terms of its definition and use over a selected set of
code statements. New steps have been added to the algorithm
proposed in [8] to obtain information conceming the registers
switching activity. The proposed algorithm can be summarized as
follows (more details can be found in [I I]):
I . compute the lifetimes of all the variables in the given VHDL code,
composed of S statements. A variable y is said to live over a set of
sequential code statements (i, i+l, i+2, ..., i+n}, when the variable is
written in statement i and it is last accessed in statement i+n. When a
variable is written in a statement i+k in the set, but last used in the
same statement i+k of the next iteration, it is assumed to live over the
entire set;
2. represent the lifetime of each variable as a vertical line from statement
i through statement i+n in the column j reserved for the
correspondingvariable v,;
3. determine the maximum number N of overlapping lifetimes
computing the maximum number of vertical lines intersecting with
any horizontal cut-line [8];
4. estimate the minimal number N of set of registers necessary to
implement the code by using register sharing. Registers sharing has to
be applied whenever a group of variables, with the same bit-width bi,
can be mapped to the same register. The total number of registers is
N
given by Cb, ;
i=l
5. select a possible mapping of variables into registers by using registers
sharing;
6 . compute the number wi of write to the variables mapped to the same
set of registers;
I. estimate a, of each set of register dividing wI by the number of
statementsS: a,=wI / S; hence TR,MAX= aIfCLK.
Considering PREG, it is worth noting that the power of latches and
flip/flops is consumed not only during output transitions, but also
during all clock edges by the intemal clock buffers, even though
the data stored in it does not change. The non-switching power
dissipated by intemal clock buffers accounts for approximately
30% of the average power for the LCBSOOK technology supplied
by LSI Logic [9]. The technology features geometries with
0.5-micron drawn gate length, 0.38-micron effective channel
length optimized for 3.3 V operation.
Note that the internal clock buffers are independent of the output
load, thus the non-switching power of latches and flip/flops are
load-independent, but dependent on the clock input ramptime.
Globally, the average power of the registers can be estimated as:
N The value of Pk for each multiplexer k is given by:
pF3ZG = c ( p k + PNSk)
k= 1
where N is the number of set of registers sk constituted by the
same type of latches or D flip/flops and PI, is the average power of
each set sk and PNskis the average non-switching power dissipated
by the intemal clock buffers of the registers in the set sk,that is the
average power dissipated by the internal clock buffers when there
is no output transition.
It has to be pointed out, that the measured average power Pk,
tabulated in the target library, includes also the power dissipated
by the internal clock buffers during clock edges corresponding to
output transitions. Hence the estimated value of Pk should account
for an activity factor given by the TR,, while the estimated values
of the PN,k should consider an activity factor of (fCLK - T R k ) .
The estimated value of Pk and PNSkfor each set sk is given
respectively by:
F& = nk P&T R K 6
PNSk nk (fCLK -mk16
where:
nk = estimated number of registers in the set sk;
Prk= average power consumption per MHz of a single register of
type tk at a given reference frequency fo, for different output
standard loads Ck (representing both load cells and
interconnections) and clock input ramptime;
P()k = non-switching power consumption per MHz of a single
register of type tk at a given reference frequency fo, as a function of
the clock input ramptime;
TRk estimated toggle rate of the: registers in the set sk, being the
values computed with the live variable analysis;
6 = derating factor.
PMuxestimation. To estimate the size and number of miultiplexers
from the VHDL code, it is necessary to determine the inumber of
paths in the data-path. The analysis of design paths and the related
notations are similar to those performed in [8], however in the
proposed approach we consider also the paths from primary
inputs to intemal registers and from intemal registers lo primary
outputs.
Once the size and number of multiplexers has been computed, we
derive the switching activity of he multiplexers, given the model
of the ?-input non-inverting multiplexer depicted in figure 2.
-1
Figure 2. The 2-input non-inverting multiplexer model for power
estimation
A simplified model for the maximum switching activity of the
output Z of a 2-input non-inverting multiplexer is:
az = a, (1 - P S I ) + aB ps'
where CLA is the switching activity of the input A; aB is the
switching activity of the input B and ps' is the static signal
probability of the selection net S .
Globally, the average power diss#ipatedby the multiplexers can be
estimated as:
N
k= 1
where N is the estimated number of multiplexers and Pk is the
average power of each multiplexer.
P k = Ptk TR, 6
where Ptkis the average power consumption per MHz of a 2-input
non-inverting multiplexer; T R k the estimated toggle rate of the
multiplexer and 6 the derating factor.
PFu estimah'on. The power model for functional units is a
complexity-based model [8], estimating the complexity of
functional units in terms of equivalent gates. The number of
equivalent gates necessary to implement the l o g c from the VHDL
code is derived from a library of macro-functions such as adders,
multipliers, etc.. The library should include the estimated number
of logic gates for each macro-function, depending on the number
of operands and the parallelism. Once the number of equivalent
gates for each macro-function has been evaluated, the estimated
power dissipated by the functional units can be expressed as:
N
P w = CPk
lc= 1
where N is the number of macro-functions, and PKis the power of
each macro-function given by:
Pk n k PTECH mk 6
where PTECH is a technological parameter expressed in [pW/(gate
MHz)]; nk is the estimated number of logic gates in the macro-
function k; TRk is the toggle rate of the gates of the macro-
function k.
4. Experimental results and conclusions
To verify the advantages of the proposed analysis over
conventional approaches, several experiments has been carried
out. To give the flavor of the potential mismatches existing even
in simple designs, this section reports the experimental data
obtained by developing a benchmark ASIC reported in figure 3.
The architecture contains some of the typical elements composing
a generic data-path: two sets of registers, an adder, the U 0 pads, a
battery of 64 multiplexers and a clock distribution tree. The
synthesis data have been obtained by using the Synopsys
Design Compiler environment and we used the state-of-the-art
HCMOS6 technology, featuring 0.35ym and 3.3 V, supplied by
SGS-Thomson Microelectronics at the target operating frequency
of 100 MHz.
A I1 12 CMD
cfl cfl
Figure 3. The ASIC architecture of the power estimation benchmark
Experimental results are reported in table 1, considering several
input switching activities (0.75, 0.5, 0.25 and 0.1). The results
obtained by the proposed methodology have been compared to the
results obtained by the Synopsys Design Power tool on the gate-
level netlist. Note that both the estimation methods are based on a
Zero Delay Model. Regarding the global power, the proposed
method provides an over-estimation: the percentage error is in the
range from the 1.59% to the 4.16% with respect to the Synopsys
estimates. However, being the switched capacitance of I/O nodes
usually larger than the switched capacitance of the intemal nodes
up to three orders of magnitude, the major contribution to the
global power is constituted by the I/O power. In the benchmark,
the U0 power represents the 94.83%, on average, of the total
power, due to the reduced size of the core logic. Thus, a more
realistic measure derives from the comparison of the core power:
the model provides an over-estimation from the 8.52% to the
3 1.64%. In particular, the results show an average percentage
error of 24.87% for the registers, 30.49% for the multiplexers and
-0.54% for the adder. Globally, the relative accuracy of our
approach compared with the Design Power gate-level tool is
considered satisfactory at this level of abstraction. Furthermore,
traditional gate-level methods suffer from a main drawback with
respect to our approach: the need to perform time-consuming
tasks such as the synthesis. On the contrary, our approach, by
avoiding to move down to the gate-level description, represents an
innovative methodology encompassing the requirements to
achieve accurate power estimation in a reasonable design time.
Work is in progress aiming at integrating the proposed conceptual
framework and the related power metrics within the partitioning
task of a more general hardware-software co-design environment
for embedded systems [lo]. Moreover the analysis will be
extended to consider also the control-units and the embedded core
processor and memories of the target system architecture.
Design Power 1 3s 14.3’) 0.24 z.ox 164.11
Perc. Error 0 0%~ 36 27%, 13 339, -0 5 8 % I 4%
Ave.Perc. Err. -09% 2 4 . ~ 7 %31).4~a,-II.s~%, I 4%
Table I . Power estimation comparison results for the data-path
benchmark ASIC
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