0.

15pm CMOS with High Reliability and Performance

K.Takeuchi, T.Yamamoto, A.Tanabe, T.Matsuki, T.Kunio, M.Fukuma,
*K.Nakajima, 'H.Aizaki, *H.Miyamoto and 'E.Ikawa
Microelectronics Research Labs. and *ULSI Device Development Labs., NEC Corporation
1120. Shimokuzawa, Sagamihara-shi, Kanagawa 229, JAPAN

Abstract current is obtained.

0 . 1 5 ~CMOSFETs with high reliability and Hot Carrier Lifetime for nMOS
performance have been realized. The acceptable power
supply voltage V, was estimated to be 1.9V. A To determine the allowable V , the hot carrier
reasonably short ring oscillator delay of 33ps was obtained reliability for both nMOS and PMOS was examined. Fig3
for the 1.9V V, maintaining an 0.4V threshold voltage. shows shift in the drain current AI& (linear region), and
Anomalous surface state generation and Vm shift for the shift in the charge pumping current &, as a function of
PMOS were observed, though the degradation was less stress gate voltage V,, for the nMOS (gate length
severe than the nMOS. LQ=0.18pm, effective channel length I-=O.l6pn). The
surface state generation (AIcp) shows a well-known 'bell'
Introduction shape, and the peak coincides with the maximum in
substrate current ,I vs V, curve, as usual. However, the
Recently, MOSFET miniaturization down to 0 . 1 p corresponding peak in the AIJ, vs V, curve is not
gate length and below is explored. One of the key issues distinct. This suggests that enhanced electron trapping
for achieving high performance with such small devices occurs at high V,, causing an ID degradation comparable
is the choice of power supply voltage V, and hence, hot to that in the maximum 1- condition. The enhanced
camer reliability. It is particularly important for room trapping may have occurred due to some process-related
temperature operation, since Vm is difficult to be scaled problem. Since the worst case stress condition is not clear,
down due to the stand-by current requirements, while the lifetime extrapolation for both maximum I, and V,=VD
delay is roughly proportional to VJ(V,-V,3. conditions were performed (ng. 4). The extrapolated
In this paper, hot carrier reliability and performance lifetime (defined by Ag,,,/g,=lOQ, where g, is the
of 0 . 1 5 ~CMOSFETs are presented. transconductance in the linear region) is shorter for the
maximum I, condition. The acceptable V, to guarantee
Device Fabrication 10 year dc lifetime was estimated to be 1.9V.
Fig.1 shows a schematic cross section of the 0 . 1 5 ~ Hot Carrier Lifetime for PMOS
CMOS. The gate oxide thickness is 5nm. Gate electrodes
were drawn by electron beam lithography. The n+ and p+ Fig.5 shows shift in the threshold voltage AVm, and
gates were doped simultaneously with the source/drain shift in the charge pumping current &,as a function of
formation. The source/drain consists of a shallow stress gate voltage V,, for the PMOS (LQ=0.18pm,
extension [l] and a deeper contact region. The junction L8pp--O.l3pm). Usually, electron trapping dominates in
depth and gate-todrain overlap of the source/drain PMOS degradation, causing a sharp positive peak in a
extensions were suppressed by depositing a thin SiO, AVm vs V, plot at low IV,I. However, in the present
blanket before their implantation. The activation was done case, significant surface state generation (&), and large
by RTA. TiSi, salicidation was used to reduce both the negative AVm, presumably caused by the surface state,
gate poly and the source/drain resistances. All the pattem are observed. Similar AIm vs V, results, but without
layers except for the gate were formed by i-line significant AVm, is found in the literature [2].
lithography, using 0 . 6 ~design rules. Therefore, to The peculiar AIm vs V, curve seems to reflect the rate
reduce the junction capacitance, the channel impurity for of hole injection into the gate oxide; The peak around
punchthrough stop was implanted only around the gate vQ=-2v should correspond to the m a x i " of hot hole
electrode (within 0 . 3 ~of the nominal gate edge), generation, and the monotonic increase for V,<-4V be
covering most of the source/drain regions with a caused by the increase in hole-attractive field near the
photoresist. Fig.2 shows typical I-V curves for a poly gate drain. One reason for the enhanced surface state
length L,=0.15~. Good tum-off and reasonably large generation may be the more hole-attractive vertical field

36.2.1
0-7803-1450-6 $3.00 0 1993 IEEE IEDM 93-883
in surface channel pMOSFETs, compared with buried
channel ones. Electron trapping also occurs, as indicated
by the slight positive AVm at lower lVol stress. However,
it seems to be less significant in determining the device
lifetime.
The results of PMOS lifetime extrapolation m
shown in Fig.6. Bias conditions similar to the nMOS case
(Vo=VJ2 and V,=V,J were chosen. The lifetime was
defined by AVm=20mV, since AVm was severer than Agm.
The estimated allowable V, (2.5V) is much larger than
that for the nMOS.
Switching speed
Applying the 1.9V supply voltage, a reasonably short
ring oscillator delay zpdof 33ps (Fig.7) was obtained for
FO=1, &=0.15pm, while suppressing the standby-current
to about lOpA/pm (IVmI=0.4V).
According to SPICE simulations, junction capacitance
C,, overlap capacitance Cov, and source/drain resistance
RSD are the key parasitic factors that determine the
inverter delay. By means of the area-restricted channel
implant technique. C, is adjusted to be equivalent to
0 . 1 5 design,
~ while using 0 . 6 design
~ rules. Further
reduction of C, is possible by cutting down the alignment
tolerance ( 0 . 3 ~ ) Though
. Cov is controlled by the SiO,
blanket, there still remains room for suppressing the
PMOS overlap ( L 0 - u 0 . 0 6 p ) . By reducing both C, and
CO,, 2, about 2Ops should be possible. Parasitic
resistance becomes a serious problem. In spite of the TiSi,
salicidation, high source/drain doping, and large contact
holes, RsD caused, through the reduction of the drive
current, more than 10%increase in zpp The effect of gate
sheet resistance was not serious in this work, since the
channel width used was small (W4p.m. W p 8 p ) .
Closer look at nMOS hot carrier effects
In Fig.8, the allowable V, is compared with that for
0 . 4 generation
~ devices. The 1.9V V, for the 0 . 1 5 ~
devices is much higher than expected from the constant
field scaling ( V e L , ) , and even higher than the square-
root scaling level (V,=LovL) [3]. This can be a result of
non-stationary carrier transport, which is expected to occur
when the channel length approaches 0 . 1 ~ Therefore,
. T.Horiuchi for their useful suggestions.
channel length dependence of nMOS hot carrier effects
have been examined.
Fig.9 shows 'charge to lifetime' (TI,,) vs impact
ionization rate ( I d , , ) plots [4] for various effective
channel lengths LBpp. The lifetime z is defined by either
(A) relative shift in transconductance (Ag,,,/gm=lO%),or
(B) absolute shift in source-to-drain linear resistance
(AR=300sZm). For a given I d , , the absolute degradation
in R is independent from & down to 0 . 1 ~ The . &
dependence of z in the case of (A) is merely due to the
difference in the initial R. A shorter device has smaller R,
and hence suffers from a larger relative degradation
36.2.2
884-IEDM 93
-
-m
(AR/R=AgJgJ for the same absolute degradation AR.
Fig.10 shows ISJD as a function of VD-VmAT for long
and short devices, where VmATis the potential of the
pinch-off point. V, can be determined from the
I d D data itself, as was first pointed out in [5]. TO
obtain more well-defined results, particularly for short
channel devices, VmAT was extracted from Isv$ID VS VD
curves, instead of I, vs V, ones. The horizontal shift of
a curve from the one for Vo=Vm was taken as equal to
VNAT, assuming V , a for V,=V,. Here, V, for
vD=O.lv was used. Following this VmAT determination
procedure, I d D VS VD-VNAT curves almost
independent from LBpp.
Thus, if the voltage applied to the pinch-off region
(=VD-VNAT) is fixed, the electron energy distributions near
the drain is considered to be independent from the
channel length even down to 0 . 1 ~ No . singular I-
dependence is detected. However, the results do not mean
the absence of non-stationary carrier transport. Rather, it
is believed to have occurred, but equally in all the
samples, resulting in the failure of its detection. To
experimentally catch it, samples with different pinch-off
region length must be compared.
Conclusion
Hot carrier reliability of 0 . 1 5 nMOS
~ and PMOS
was evaluated. The allowable V, was as high as 1.9V.
The degradation of PMOS, though much different from
conventional devices, was less severe than nMOS.
Applying the 1.9V, a ring oscillator delay T,, of 33ps
was obtained, maintaining sufficiently high V,. The
results demonstrate that 0 . 1 5 CMOS
~ with both high
speed and reliability is feasible.
No singular channel length dependence was found,
either in hot carrier degradation or impact ionization,
down to 0 . 1 ~ To . experimentally detect non-stationary
carrier transport, the length of pinch-off region, rather
than channel length, should be varied as a parameter.
Acknowledgement
The authors would like to thank N.Ehdo for his
continuous encouragement, and I.Sakai, H.Abiko,
References
[l] G.A.Sai-Halasz et al., in 1987 IEDM Tech. Dig., p.397.
[2] F.Matsuoka et al., IEEE Trans. Electron Devices, ED-
37, 1487 (1990).
131 M.Kakumu et al., EEE Trans. Electron Devices, ED-
37, 1334 (1990).
[4] C.Hu et al., IEEE Trans. Electron Devices, ED-32, 375
(1985).
[5] T.Y.Chan et al., IEEE Electron Devices Letters, EDL-
5, 505 (1984).
 !3D extension lisp
/ A lpMos1
Schematic MOSFET cross section.

fp)qEm
I \ I
/ P- i
punchthrough t of5nm
stopper

E- -04

8 4
-1

-1Z -2
VDM Vo M Vo M Vc M
(a) nMOS (b) PMOS

Fig2 EV curves of n and pMOSFETs. L.&.lSp.

L A . 1 3 p m for nMOS and 0 . 1 0 for
~ PMOS. respecuvely.

Fig3 Shift in linear drain current I,, and charge pumping Fg.4 Lifetime extrapolation for nMOSFET. The lifetime is
current Icp vs stress gate voltage V,. for nMOSFET defined by Ag./&=lO%, where & is the maximum
(LgpP--.16~). transconductance in the linear region.

-1 60 0.5
stress @VD-5V, 310s

VG (v) 1 /VD or')

Fig.5 Shift in threshold voltage V, and charge pumping Fig.6 Lifetime extrapolation for pMOSFET. The lietime is
current I, vs stress gate voltage Vo. for pMOSFET d e f d by AV+2OmV. AVm is much more severe than
W . 1 3 ~ ) . ND.

36.2.3 IEDM 93-885

 /-
. ’ 0:r
lk. 1
I
Fig.7 Output waveform of a 101 stage ring oscillator with GATE LENGTH ( p m)
F-1, L , # . 1 5 ~ . W , 4 w W,=8~lm, IVm14.4V and
V e 1 . 9 V . The delay ~ ~ - 3 3 ~ s .
Figs Canparison of allowable , V between 0.15 and
0.4- generations. Junction depth, gate oxide thickness,
substrate concentration are different between the generations.
SD is for single drain.

Fig.10 Is& VS V,-V, for various V,’S and two

different G s . Though slight horizontal shift (SOmV)
between W . 1 0 and 1 . 0 is~ observed, the shape of the
curves are almost identical.

105 10-2 lo-’ 1 00

ISUB/ID

Fig.9 ‘51, VS IsvJrDfor IMOSFETSwith various where

‘c is for (A) AgJg-=lO% and (B) AR=30OS&m. R is the
source-to-drainresistance at V,=2V in the linear region.

36.2.4
886-IEDM 93

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