SRI KRISHNA COLLEGE OF TECHNOLOGY

(AN AUTONOMOUS INSTITUTION)

KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

2 MARKS
1. List the Attributes of an Ideal Operational amplifier. R C402.1
2. If the input to the circuit of figure is a sine wave the output will be

U C402.1

3.

AP C402.1

4. An Op – Amp has offset voltage of 1mV and is ideal in all other respects. If this Op
–Amp is used in the circuit shown in figure. The output voltage will be (Select the
nearest value)
AP C402.1
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

5.

AP C402.1

6. In the circuit of the figure, V0 is

AP C402.1

7. If the differential voltage gain and the common mode voltage gain of a
differential amplifier are 48 dB and 2 dB respectively, then its common mode U C402.1
rejection ratio is
8. Why open loop configuration of an op-amp has limited applications? U C402.1
9. Define CMRR. What are the conditions to make CMRR infinite? U C402.1
10. Draw the internal Block diagram of an Operational amplifier. R C402.1
11. What are the requirements of a good current source? U C402.1
12. Why RE is replaced by a constant current bias circuit in a differential amplifier? U C402.1
13. Design a Unity gain amplifier using operational amplifier. U C402.2
14. Name the type of feedback used if an external component is connected
U C402.2
Between the output terminal and the inverting input. Justify your answer
15. The non-inverting amplifier has a gain of 11, Assume that Vin = 1.0 V. AP C402.2
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

Find the value of Vf ?

16. How Diodes are useful in op-amp circuits? Draw the structure of
R C402.2
Positive peak Detector?.
17. How the problem of instability and High frequency noise is eliminated
U C402.2
in op-amp based Differentiator circuit?
18. Define Slew rate of an op-amp R C402.2
19. Consider the Schmitt trigger circuit shown below.

U C402.2

A triangular wave which goes from -12V to +12V is applied to the inverting input of
op-amp. Assume that the output of op-amp swings from +15V to -15V
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

Find out the voltage at the Non-inverting terminal that switches between -----
20. What is the difference between normal rectifier and Precision rectifier? U C402.2
21. Determine the output voltage for the following circuit shown in figure

U C402.2

22. State how second order Butterworth LPF give Flat response ? U C402.2
23. The inverting op-amp shown in the figure has an open-loop gain of 100. The
closed-loop gain V0 / VS is

AP
C402.2

24. How many op-amps are required to implement this equation AP C402.2
25.

26. For the Op-Amp circuit shown in the figure. Find V0

 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

AP C402.2

27. Assume that the op-amp of the figure is ideal. If Vi is a triangular wave, then V0
will be

C402.2
U

28.
U C402.2
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

29. Mention the applications of Analog Multiplier.

U C402.3

16 MARKS
1. A basic current mirror is to provide a collector current of 1 mA with VCC=10V.
Assume β=125 and VBE=0.7V. Determine
AP C402.1
a) the value of R1
b) value of R1 for IC =10µA.

In continuation with previous question, What is the change that can be

incorporated into the basic current mirror circuit by maintaining the same AN C402.1
collector current of 10µA with lower R1 value? Explain

2. Derive the gain of Inverting and Non-inverting amplifier for closed loop
U C402.2
configuration

For a Non inverting amplifier let R1=5kΩ, Rf=50kΩ and Vi=1V. A load resistor of
5kΩ is connected at the output. Calculate
a) V0 AP C402.2
b) ACL
c) Load current iL
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

3. Draw neatly, Derive the expression and explain a 3 op-amp instrumentation U C402.2
amplifier and state the use of buffers in the circuit.
Calculate the output voltage Vo for the instrumentation amplifier, given R=
1K(Gain Adjustable resistor), R’= 2K(Feedback resistor of buffers), R1=1.5K(input
resistance of Differential amplifier), R2=3K (Feedback resistance of Differential AP C402.2
amplifier), V1= 0.5V(Input voltage applied to lower op-amp), V2=4V(Input voltage
applied to upper op-amp)

4. Describe the operation of op-amp based Transconductance amplifier with its U C402.2
types.
What is the need of frequency compensation technique in op-amp?
with a suitable illustration, explain any one frequency compensation technique. U C402.2

5. Given V1= 4 V and op-amp is supplied with ± 12V.

What will be the allowable range for V2?
AN C402.2

Explain in detail the circuit that produces multiplication of two input signals using
gilbert cell. U C402.3

6. Explain the meaning of the following terms in not more than 5 lines each along
R,
with suitable sketches. Setup time, Hold time, Clock skew, Settling time (D/A C402.4
converter) U

7. Explain with suitable diagram (s) how you would set up the comparator reference
levels for a 4 bit parallel AID converter to obtain a ± Y2 LSB accuracy.(Do not draw U C402.4
or explain the entire circuit of the parallel converter)
 SRI KRISHNA COLLEGE OF TECHNOLOGY
(AN AUTONOMOUS INSTITUTION)
KOVAIPUDUR, COIMBATORE - 641042.
Affiliated to Anna University and Approved by AICTE
Accredited by NBA - AICTE and NAAC – UGC

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

17EC309 – Analog Integrated Circuits
QUESTION BANK

8. Explain the schematic diagram of an n-bit successive approximation ADC

converter R C402.4

9. Explain (a) 8-bit flash ADC (b) Dual slope type ADC R C402.4

10. Explain the operation of Phase Locked loop with neat diagram.also derive the U C402.3
equation for its Lock-in range and capture range.

11. How a PLL circuit used in Analog and Digital FM circuits, also explain how U C402.3
frequency translation and multiplication is done through PLL.

12. Explain the functional diagram of 555 Timer , how a timer is connected as U C402.5
monostable multivibrator also derive the equation.

13. With neat diagram explain how free running oscillations are produced by 555 U C402.5
timer. List the applications of 555 in Astable and monostable mode.

14. Compare Linear and switching regulators, explain the operation of IC 723 U C402.5
regulator in low voltage and high voltage operations.

15. Explain the operation of Audio power amplifier and Isolation amplifier U C402.5

16. Explain i) Fiber optic ICs, U C402.5

ii) Opto couplers
iii) Video amplifier