INTERNATIONAL SCHOOL OF ASIA AND THE PACIFIC

Alimannao Hills, Peñablanca, Cagayan 3502

COLLEGE I
OF NFORMATION TECHNOLOGY AND ENGINEERING
Subject Code : COMP ORG
Subject Title : COMPUTER ORGANIZATION
Term : FINAL
Semester : FIRST School Year: 2018-2019

Name: _______________________________________ Year and Section: _____________

Proctor: ______________________________________ Score: ______________________

I. Write your answer on the space provided beside the number in CAPITAL LETTERS. Avoid
erasures.
1. These are several reasons why an I/O device or peripheral device is not directly connected to the system bus,
except for one.
a. There are a wide variety of peripherals with various methods of operation.
b. The data transfer rate of peripherals is often much slower than that of the memory or processor. Thus it is
impractical to use the high speed system bus to communicate directly with a peripheral.
c. Peripherals often use different data format and word length than the computer to which they are attached.
d. It would be practical to include the necessary logic within the processor include the several devices.

2. I/O function includes a ____ and _____ requirements to coordinate the flow of traffic between internal
resources and external devices.
a. control and timing c. management and timing
b. control and management d. None of the above

3. It uses special memory locations in the normal address space of the CPU to communicate with real world
devices.
a. DMA c. Memory-mapped I/O
b. I/O mapped input/output d. Programmed I/O

4. A special form of memory mapped I/O where the peripheral device reads and writes memory without going
through the CPU.
a. DMA c. Memory-mapped I/O
b. I/O mapped input/output d. Programmed I/O

5. A computer can address more memory than the amount physically installed on the system. This extra memory
is actually called ________ and it is a section of a hard disk that's set up to emulate the computer's RAM.
a. NVRAM c. SDRAM
b. Virtual Memory d. CDROM

6. Following are the situations, when entire program is not required to be loaded fully in main memory, except
for one.
a. User written error handling routines are used only when an error occurred in the data or computation.
b. Many tables are assigned a fixed amount of address space even though only a small amount of the table is
actually used.
c. More number of I/O would be needed to load or swap each user program into memory.
d. Each user program could take less physical memory, more programs could be run the same time, with a
corresponding increase in CPU utilization and throughput.

7. Used to activate peripheral devices and instruct it what to do. For example, a magnetic tape unit may be
instructed to rewind or to move forward one record. These commands are specific to a particular type of
peripheral device
a. Control c. Read
b. Test d. Write

8. This is quite similar to a paging system with swapping where processes reside in secondary memory and
pages are loaded only on demand, not in advance.
a. Page Replacement Algorithm c. Reference String
b. Demand Paging d. FIFO Algorithm

9. If the data is in the cache it is called a ________.

a. Read or Write hit c. Read hit
b. Read or Write miss d. Write miss

10. What is the total size of cache?

a. 64k c. 2048
b. 4k d. 1080

11. It is a sub-routine – may belong to a different user than the one being executed and then halted.
a. I/O c. FIFO
b. OPT d. ISR

12. Processor hardware ignores the interrupt request line until the execution of the first instruct ion of the ISR
completed.
a. Disabling Interrupts c. Special Interrupt Request Line
b. Ignoring Interrupts d. Both A and C

13. It tells where the Interrupt Service Routines (ISR) are located.
a. ITD c. DTI
b. DIT d. IDT

14. It is also called as read write memory or the main memory or the primary memory.
a. RAM c. SRAM
b. ROM d. DRAM

15. Stores crucial information essential to operate the system, like the program essential to boot the
computer.
a. RAM c. SRAM
b. ROM d. DRAM

16. It can be programmed by user. Once programmed, the data and instructions in it cannot be changed.
a. EPROM c. PROM
b. EEPROM d. ROM

17. Gets the amount of memory on the computer, in bytes that can be used by the cache.
a. Physical memory Limit c. Polling Interval
b. Default Cache Capabilities d. Cache Memory Limit

18. Gets the maximum time after which the cache updates its memory statistics.
a. Physical memory Limit c. Polling Interval
b. Default Cache Capabilities d. Cache Memory Limit

19. To send data to an input device, the ______ simply moves that data to a special memory location in the I/O
address space if I/O mapped input/output is used or to an address in the memory address space if memory
mapped I/O is used.
a. Memory c. CPU
b. Registers d. Cache

20. In case of ____________, same address space is used for both memory and I/O devices. Some of the
memory address spaces are kept reserved for I/O devices.
a. DMA c. Memory-mapped I/O
b. I/O mapped input/output d. Programmed I/O

II. Enumerate the following; 2 pts each

1-5. Major functions of an I/O module

6-9. Steps in Processor Communication
10-13. 4 Basic form of input and output systems
14-17. 4 types of I/O commands that an I/O module will receive when it is addressed by a processor
18-20. 3 Advantages of Demand Paging
21-22. 2 Types of memory
23-25. 3 Mapping Functions

III. Give the abbreviation of the ff. acronym: 2 pts each

1. I/O
2. LRU
3. OPT
4. FIFO
5. MMU
6. CPU
7. RAM
8. DMA
9. LFU
10. MFU

IV. Modify True or False. If the answer is True write LOVE and if the answer is False write HURT
then change the word that makes the sentence false.

1. LFU is based on the argument that the page with the smallest count was probably just brought in and
has yet to be used.
2. Bus consists of 3 set of lines: Address, Data, and Control.
3. The register communicates the device address via a set of wires normally included as part of the I/O
bus.
4. In Memory -mapped I/O portions of address space are assigned to I/O devices and reads and writes to
those addresses are interpreted as commands to the I/O device.
5. When a device wants to notify the processor that it has completed some operation or needs attention,
it causes the processor to be interrupted.
6. In disabling interrupts processor automatically disables interrupts before starting the execution of the
ISR.
7. To transfer large blocks of data at high Speed, between EXTERNAL devices & Main Memory, DMA
approach is often used
8. DMA controller allows data transfer directly between I/O device and Memory, with minimal intervention
of processor.
9. The computer systems registers architecture is to interface to the outside world.
10. An essential task of an I/O module is error detection

“Don’t stop until you’re PROUD”

Prepared by:
Reviewed by:
JENYLL T. MABBORANG
Instructor DAN PAOLO E. RAMOS, MSHM
Quality Assurance Moderator for Academics and
Checked by: Administration

NORWAY T. SALUDARES, LPT, MIT Approved by:

Program Coordinator
PRESENITA C. AGUON PH. D.
Noted by:
Vice President for Academic Affairs
CB RONIE E. SUGAROL, MPBM
School Overseer