Two-stage Operational Amplifier Design using Gm/Id method

Abhinav Kumar, BT15ECE046

NIT, Uttarakhand
abhinavkool19@gmail.com

Abstract— A two-phase Operational Amplifier is reenacted utilizing gm/ID based approach. With the given particulars, for example,
Gain, Phase Margin, Input regular mode range and Unity gain frequency, operational amplifier has been composed such that every
one of the transistors are in saturation. Rhythm recreations are completed utilizing gpdk 180 nm technology. The reenacted comes
about show concurrence with the determination for 1.8 V supply.

Keywords— CMOS Integrated Circuit, Low power, Gain margin, Phase margin, Pole, Zero, gain-bandwidth product, gain .

INTRODUCTION
The operational enhancers (Op-amp) are most imperative building square of numerous simple and blended flag circuits like
intensifiers, channels, comparators and so on. With the scaling of transistors and supply, now daily's multistage speakers are
regularly utilized. In low voltage outlining cascading can't be utilized on account of headroom constraints. Consequently
planner has been moved towards falling, on the grounds that it maintains a strategic distance from vertical stacking of
transistors henceforth evacuates the headroom issue. With a specific end goal to accomplish a high voltage pick up, it is
profitable to utilized in excess of two phases. In any case, to plan such a multistage operational enhancer is a testing
assignment since high impedance hubs lead precariousness issues. To settle the operation amp a few remuneration systems has
been proposed [1]. The Nested mill operator remuneration (NMC) system experiences data transfer capacity diminishment,
issue while NMC with nulling resistor experiences right half plane zero issues [2,3]. The multipath NMC (MNMC) builds the
data transmission by dropping the non-overwhelming post with zero. Significant disadvantage of this method is that slight
variety in temperature or some other parameter may change the area of zero, which leads despicable cancelation [4]. The
turned around NMC (RNMC) presents the correct half plane zero, thus diminishes the transmission capacity and stage edge
[5]. The Gm-C pay strategy is substantially simpler to break down as contrast with MNMC. The power utilization by
encourage forward stages can be controlled by legitimate executions [6,7]. In this paper Gm-C pay method has been embraced
for two-phase operation amp outlining.

DESIGN APPROACH
The Gm/ID based technique has been adopted to bias all the transistors in saturation in order to achieve best trade-off among gain,
bandwidth and power. In this methodology transistors are characterized under same environment to plot the intrinsic gain and
ID/(W/L) as a function of Gm/ID. Gm/ID is a ratio which measures the efficiency to translate current into transconductance, i.e. large
transconductance can be achieved by making the ration large [8,9]. Since the above plots are independent to size hence it becomes
quite easy to size each transistor for a given current. The required current can be obtained from specifications. The transfer function of
two-stage op-amp can be written as,

( )( )

In this expression Ao is open loop gain and is unity gain frequency. In order to make op-amp as single pole system it is
necessary that one pole must be far from UGB. Hence in this way op-amp can be stabilize but it consumes large power [7].

[1] SPECIFICATIONS
In order to design two-stage op-amp following specification has been used,

1. Supply, VDD = 1.8V and VSS = 0V. 3. GBW =60 MHz

2. Gain > 65 dB 4. ICMR =0.9v to1.7

0
5. Phase Margin = 60
[2] DESIGN EQUATIONS

Following relations has been adopted,

UGB= 2

Power =Vdd* Id6

Vcmmax= -|Vpmax| -VSDsAt1 +Vdd

Vcmmin= -|Vpmax| +VSDsAt1 +Vdd

The size of the all the transistor is calculated as follows

M1 and M2 are of equal size

M3 and M4 are of equal size

M5 and M8 are same

M6
Gm6>=10Gm1

M7
 Figure 1 Two stage op-amp

[3] DESIGN PARAMETERS AND TRANSISTORS SIZE

With the help of above specifications, design equations and G m/ID plots aspect ratios of all the transistors has been calculated and
simulated results for size of transistors belong to core block has been summarized in Table 1.

Table1: Summary of size of transistors after simulation

Transistors W/L ratio (Simulated value)

M3,M4 4.5/0.5
M5,M8 11/0.5
M1,M2 1.5/0.5
M6 51/0.5
M7 64/0.5
SIMULATION RESULTS

The Cadence simulation has been carried out using gpdk 180nm technology. The supply has been chosen as 1.8V and the simulated
results have been summarized in Table 2.

1. FREQUENCY RESPONSE
o
The simulated result shows that op-amp has an open loop gain of 67 dB, UGB is 58 MHz and phase margin is 60 for 1 pF capacitive
load.
 Figure 2 Frequency response of a two-stage op-amp

2. CMRR vs frequency

The common mode rejection ratio (CMRR) of a differential amplifier (or other gadget) is a metric used to evaluate the capacity of the
gadget to dismiss common mode signals, i.e., those that show up all the while and in-stage on the two information sources. A perfect
differential enhancer would have interminable CMRR, however this isn't achievable by and by. A high CMRR is required when a
differential flag must be opened up within the sight of a potentially vast normal mode input, for example, solid electromagnetic
impedance (EMI). An illustration is sound transmission over adjusted line in sound support or recording.

Figure 3 CMRR vs frequency

3. Step response and slew rate

In gadgets, slew rate is characterized as the difference in voltage or current, or some other electrical amount, per unit of time.
Communicated in SI units, the unit of estimation is volts/second or amperes/second or the unit being examined, (however is generally
communicated in V/μs). Electronic circuits may indicate least or most extreme points of confinement on the huge number rates for
their data sources or yields, with these cutoff points just substantial under some arrangement of given conditions (e.g. yield stacking).
At the point when given for the yield of a circuit, for example, a speaker, the large number rate determination ensures that the speed of
the yield flag progress will be at any rate the given least, or at most the given greatest. At the point when connected to the contribution
of a circuit, it rather demonstrates that the outside driving hardware needs to meet those breaking points with a specific end goal to
ensure the right activity of the accepting gadget. In the event that these cutoff points are disregarded, some mistake may happen

Figure 4 Slew Rate

The simulated results have been summarized in Table 2.

Table 2: Comparison of parameters for 1pF load

Parameter
CL = 1 pF
Gain 67 dB
UGB 58 MHz
o
Phase Margin 62
Slew Rate 100 V/µs
ICMR 0.9 V- 1.7V
Power Consumed (IVDDx VDD) 2.86 mW
CONCLUSION

In this paper a two-phase Gm-C remunerated operational speaker has been outlined utilizing Gm/ID approach and gpdk180 nm
innovation. Every one of the transistors are saturation region keeping in mind the end goal to accomplish best trade-off among pick
up, zone, and transfer speed. The reproduced comes about demonstrate that operation amp is competent to give an open circle pick up
of 67 dB at a stage edge of 62 and UGB of 62 MHz for 1 pF capacitive burdens. Consequently reproduced outcome indicates superb
understanding with specifications.

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