Title: “Verification coverage upboost for Mixed Signal SoC using

scientific model evolution”

Statement of Problem: Hand shaking between Analog and Digital IPs, leads to
many states for mixed signal system of chip(SoC)[1], which increase the engineering
effort to come up with good simulation based environment, with correct set of tests.
To respect time-to-market, designer won’t be able to verify all the states of system,
which ends up to possibilities of missing important states of system which eventually
prone to ‘bugs’ in a system [2].
- As the complexity of mixed signal SoC increases, it is very difficult and time
consuming to signoff the functionality of product by achieving full
coverage[6][7].
- Another daunting task of complex products is to come up with list of all
required functionality/test scenario of product.

Research Goal: Analysis of data and come up with predefine pattern is convention
way of developing tool till now. Scientific model needed to come up with algorithm
where machine can learn from data. Minimizing the gap between coverage and test
scenario, could be big gain for verification world. This can be achieved by
automatically modifying the next test scenario to achieve the missed functionality.
- Genetic algorithmic or Reinforcement Learning(ML) of Artificial
Intelligence, can be adopted, in such a way that my system automatically
upgrades the test scenario based on previous result and coverage of design
simulation [8][9].
- To draft the functionality list of complex soc from datasheet, an algorithmic
evolution with help of supervised learning is needed.
 A Brief Outline of the proposed Research Program.

Mixed signal System on Chip(SoC) has been evolved during recent years, and with
it comes the complexity of signals traversing through boundaries of digital and
analog domain [1]. Continuous state space of analog circuits and various discrete
states of digital circuits, altogether leading to
complexity in mixed signal verification [2].
Problem has been stated with help of figure 2(which is a small porting of complete
SoC Figure 1)
Buck Converter
has been
considered for
stating a
problem

Figure 1. A sample of Mixed signal SoC.

Let’s assume the functionality of buck converter we want to verify with top level
SoC [3]as:
1) Check over voltage behavior at Vout, occurs during load release.
2) Check under voltage behavior, occurs during load stepping.
3) Check for over current behavior, occurs during load release and load stepping.
4) Check OV fault. 5) Check UV fault
6) Check for over current fault. 7)Check Load Vs Line regulation. 8) Duty Cycle

Figure 2 DC-DC Buck Converter

Digital Verification engineer most of the does not familiar with exact functionality
of each sub block in SoC (say Buck converter here), they write the test scenario
based on there understanding and provide stimuli to simulation environment [4][5],
in the test scenario engineers write the constrains in such a way all the above-
mentioned functionality met. They will randomize the stimuli and run regression and
there is high chance that upon simulation few of the functionality hasn’t cover,
because of insufficient constraints. Verification engineer need spend time to debug
which functionality has been missed and they must either update their constraints or
write a direct test case to check the corresponding functionality.
A SoC has more than 1000 functionality to verify, and almost impossible for a
verification engineer to come up with good test cases, which caters 100% coverage
of SoC. So hence verification takes significant amount of product cycle[6].
This is the main bottleneck to in reducing the verification cycle time.

SoC Functionality Test Scenario

Challenging to achieve 100% Domain limitation – Verification engineers founds
coverage difficult in coming with good SoC testing conditions.

Phase 1: Verification engineer not able to cover all functionality in several run, this
limitation is giving a chance to propose a new methodology to implement
‘Reinforcement Learning’, this process “learns by creating output, analyzing the
results based on various metrics, recommending changes intended to improve the
results, and then going around the loop again”. On very first run of randomization
of whole DUT plus verification environment, observe what are the functionality
cover (based on coverage report (OV, UV)) and then upgrade the test scenario in
such a way what ever functionality has been missed out in previously would cover
in subsequent run, by this way we will able to achieve ~100% coverage with minimal
human interaction [7].
This can be achieved by monitoring the randomization log and scientifically
feedback to test cases for upgrading their constraints. A Genetic algorithm can be
use full to implement this, although Reinforcement Learning of Machine learning
could be also an optimum solution [8][9].
Phase 2: Another important
can be explore is to come up
with functionality list of SoC
and write a Test cases on
behalf of verification engineer,
this will take a lot of
information from open source
and has to analyze 1000 of data
before reach to conclusion.
The input set required here is Datasheet of SoC and open web space to explore.
Functional verification of AMS designs is a relatively young and is in yet to mature
phase. Challenging problems associated with hybrid system leads a problem which
can be address by combine efforts of AMS engineer [10], control engineers, and
computer scientists[5]. This results in a coherent framework and criteria that allows
a theoretical analysis and comparison method.
Machine learning could be an enabling technique for electronics modeling [11] [12]
and design optimization, which bridges the gap between design verification and post
silicon verification. That’s why we need to think of scientific model evolution to
streamline the flow of verification.
Declaration: I confirm that all the information furnished, and entries made in this
application are correct to the best of my knowledge and belief. If admitted, I shall
abide by all the rules and regulations of the Institute.

Tushar Pandey
_____________________
Date: May 14th, 2018 Signature of the Applicant
 REFERENCES

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[11] Vivienne Sze, Yu-Hsin Chen, Joel Emer, Amr Suleiman, Zhengdong Zhang, Hardware for
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[12] Brian Bailey, “Machine Learning meets IC Design”, June 29th, 2017
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