IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)
Design Methodologies and Circuit
Optimization Techniques for Low Power
CMOS VLSI Design
Dr.B.T.Geetha1 ,B.Padmavathi2
Associate Professor1,Assitant Professor2
Department of ECE
Jeppiaar Maamallan Engineering College
Chennai,India
dr.geetha.bt@gmail.com
Abstract— Low power is the real test for late hardware
businesses. Control scattering is an essential thought as far as
execution and area for VLSI Chip outline. Control administration
procedures are for the most part used to configuration low power
circuits and frameworks. Insights demonstrate that 40% or
considerably higher rate of the aggregate power utilization is
because of the leakage of transistors. This rate will increment with
innovation scaling unless streamlining methods are acquainted
with bring leakage inside points of confinement. This paper
concentrates on circuit improvement and plan mechanization
strategies to fulfill this target. It additionally portrays many issues
with respect to circuit outline at building, legitimate and gadget
levels and exhibits different procedures to beat the previously
mentioned issues. The initial segment of the paper gives a diagram
of primary wellsprings of leakage current in CMOS transistor.
The second part of the paper depicts various circuit streamlining
procedures for controlling the standby leakage current. Some
leakage current lessening procedures like rest approach; stack
approach, and lector strategy are talked about for planning
CMOS entryways which fundamentally chops down the leakage
streams. The benefits of lector method are it doesn't require any
extra control and observing hardware, in this way constraining
the range increment and furthermore the power dissipation in
dynamic state when contrasted with different systems and it
doesn't influence the dynamic power which is the significant
confinement with the other leakage diminishment strategies, is
likewise examined in this paper.
Keywords- VLSI, Power consumption, Dynamic power,
Clock gating, lector method etc
I. INTRODUCTION
In the previous decades, the real test for the VLSI architect was
region, execution, cost and power utilization. As of late, in any
case, this has started to change and, progressively control
utilization is being given practically identical weight to region
and speed contemplations. The thoughts for lessening power
utilization vary from application to application and circuits to
978-1-5386-0814-2/17/$31.00 ©2017 IEEE
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V.Perumal
Associate Professor3. Department of CSE
Saveetha Engineering College
Chennai,India.
circuits. In the zone of small scale controlled battery worked
compact applications, for example, mobile phones, the
objective is to keep the battery lifetime and weight sensible and
bundling cost low. Scaling of CMOS gadgets has empowered
the semiconductor business to take care of its demand for
higher execution and higher coordination densities. However as
the component measure gets to be distinctly littler, in light of
short direct lengths it brings about expanded sub-threshold
leakage current through a transistor when it is off condition.
Another purpose behind expanded sub-threshold leakage
current is that, transistors can't be turned off totally. Henceforth
leakage control dissipiation has turned into a vital bit of the
aggregate power utilization for silicon innovations. The
significant three plan parameters are power, speed and area. In
CMOS VLSI circuits, control dissipation is basically because
of the three essential elements: dynamic, static and short out. A
few enhancement strategies have been proposed for leakage
current lessening. One essential thing in CMOS VLSI circuit
configuration is to lessen the power dissipation while keeping
up the superior of the circuit. The edge voltage must be scaled
to keep up the execution of the circuit. In VLSI circuit outline
the power utilization has turned into an essential issue. In this
manner the real test in versatile framework configuration is to
diminish the power utilization of coordinated circuits through
outline improvements. Various strategies have been proposed
by scientists to take care of the power utilization issue. In any
case, there are no influences to meet trade-off between power,
postponement and region .Appropriate systems must be picked
that fulfils the application and item needs. At last, for better
execution, no battery worked frameworks, for example,
workstations, set-beat PCs and interactive media computerized
flag processors, the general objective of force minimization is
to lessen framework cost (cooling, bundling and vitality
utilization) while guaranteeing long haul gadget unwavering
quality. These diverse necessities impacts how control
improvement is managed and how much the planner will
bargain in cost or execution to get bring down power
dissipation.
 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)
II. SOURCES OF POWER DISSIPATION
When we perceived power utilization as a plan limitation,
Power per MHz is normally utilized as a recurrentation of a
segment. Electric current is not steady amid operation and
pinnacle power is a critical concern. The gadget will
breakdown because of electro migration and voltage drops
regardless of the possibility that the normal power utilization is
low. The condition for the normal power utilization is given as
Pavg = Pdynamic + Pshort + Pleakage + Pstatic
So the aggregate normal power utilization relies on upon
Dynamic power utilization, Short-circuit control utilization,
Leakage control utilization and static power utilization. The
leakage current is controlled by the manufacture innovation,
which comprises of turn around inclination current in the
parasitic diodes shaped amongst source and deplete
dissipiations and the mass district in a MOS transistor and in
addition the sub threshold current that emerges from the
reversal charge that exists at the door voltages beneath the edge
voltage. The short out current which is because of the DC way
between the supply rails amid yield moves and the charging
and releasing of capacitive burdens amid rationale changes.
The short out and leakage streams in CMOS circuits can be
made little with appropriate circuit and gadget outline
procedures. The fundamental wellspring of force scattering is
the charging and releasing of the junction capacitances.
Exchanging movement is a measure for the quantity of
entryways and their yields that change their bit an incentive
amid a clock cycle. To flip between rationale zero and rationale
one can released and charged the junction capacitor. The
electric current that streams amid this procedure causes
dynamic power dissipation Pdynamic. The dynamic power is
rely on the capacitive yield stack Cout and the supply voltage
Vdd and recurrence of clock flag.
Pdynamic = K Cout Vdd2 f
K is the average number of positive transitions during one
clock cycle and f the clock frequency. By reducing the power
supply will have a larger effect on saving power, taking into
consideration that typically Pdynamic is responsible for 80% of
Pavg.
III. SOURCES OF STATIC LEAKAGE POWER
DISSIPATION
1. Reverse-biased junction leakage current (Irev)
2. Gate induced drain leakage (Igidl)
3. Sub-threshold (weak inversion) leakage (Isub)
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A. Junction leakage
At the point when a transistor is off, the junction leakage
happens from the source or deplete to the substrate through the
turned around one-sided diodes. This leakage current has two
principle parts: one is minority bearer dissipation close to the
edge of the exhaustion locale; the other is because of electron-
opening pair era in the consumption district of the turnaround
one-sided junction. In the event of an inverter with low
information voltage, the NMOS is OFF, the PMOS is ON, and
the yield voltage is high. Thus the deplete to-substrate voltage
of the OFF NMOS transistor is equivalent to supply voltage.
This causes leakage current from the deplete to the substrate
through the turned around one-sided diode.
B. Gate-induced drain leakage
The door instigated deplete leakage current, is the deplete to-
substrate leakage created by high field impact in the deplete
junction of MOS transistors. At the point when the deplete of a
NMOS is one-sided at the supply voltage (VDD) and the door
is one-sided at either zero or negative voltage, an exhaustion
locale is framed under the entryway and deplete cover district.
This causes noteworthy band bowing in the deplete permitting
electron gap combine era because of torrential slide
augmentation. A profound exhaustion condition is made as the
openings are quickly cleared out to the substrate. In the mean
time electrons are gathered by the deplete, bringing about
Gate Induced Drain Leakage current.
C. Sub-threshold leakage
Sub-threshold leakage is the current that streams between the
source and deplete of a MOSFET. At the point when a
transistor is working in the powerless reversal district, that is,
for entryway to-source voltages beneath the limit voltage. This
is brought about because of the diffusion current of the
minority carriers in the channel for a MOS gadget. The sub-
threshold leakage current is much bigger than the other leakage
current segments. This is mostly as a result of the moderately
low VT in cutting edge CMOS gadgets.
IV. LEAKAGE CONTROL IN ACTIVE MODE
A. Multiple threshold cells
To manage the leakage issue, multi limit CMOS circuit, which
has both high and low edge transistors in a solitary chip can be
utilized. Sub limit leakage current is stifled by the high edge
transistors while low edge transistors are utilized to accomplish
the superior. However utilization is constrained to utilizing low
VT transistors, with addition rates on the request of 20% or less
since the standby power is much bigger for low VT transistors
contrasted with the high VT transistors. The dynamic power
 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

part or the outline size is not unfavourably influenced since the
TOX and entryway lengths are same for high and low VT
transistors. The disadvantage of this strategy is that variety
because of doping is uncorrelated between the high and low
limit transistors and additional cover steps acquire a procedure
cost.
B. Long channel devices
power supply and ground. Amid standby mode, rest transistors
are killed, along these lines making the virtual way between the
power supply and the ground. It is important to have rest
transistor with high limit esteem else it will have high leakage
current. This innovation is actualized with a few sorts of
transistors with various VT values. Transistors with a low VT
are utilized to actualize the rationale, while high VT gadgets
are utilized as rest transistors.

There is VT move off because of short channel impact. B. Sub-threshold power reduction techniques
Consequently dynamic leakage of CMOS entryways can be
diminished by expanding their transistor channel lengths. Sub-limit leakage current is turning into the essential
However the entryway capacitance increments for longer wellspring of force dissipiation in CMOS beneath 90nm.
transistor lengths used to accomplish high edge transistors. Subsequently power is supplanting different components like
This negatively affects the execution and element control execution and silicon zone in planning CMOS circuits.
dissipation. Long channel inclusion has comparative or lower
prepare cost contrasted and various limit voltages taken as the 1. Conventional CMOS technique.
size increment instead of the veil cost. The disadvantage of this
system is that the dynamic power dissipation of the up-sized
In this method reciprocal CMOS circuit is utilized that has a
entryway builds relative to the compelling channel length
NMOS pull down system to interface with "0" (GND) and
increment. Consequently movement variable of the influenced
PMOS pull up system to associate with the yield to "1" (VDD).
entryways must be low to spare the circuit control scattering.
It is a fundamental approach that is utilized for the most part in
V. STANDBY MODE LEAKAGE REDUCTION all methods. Fig 2 demonstrates the piece outline.
TECHNIQUE
Most electronic frameworks invest significant energy in a
standby state. Thus battery life stays sit out of gear for long
stretch aside from when being used and depletes off a large
portion of the power, which thus decreases the battery life.
Hence battery life can be spared by closing it down from the
supply when not being used.

A. Multi-threshold CMOS technique

In this procedure, high edge voltage transistor is associated in
arrangement with the power supply and existing PMOS and
NMOS arrangement circuit to make a virtual ground and a
virtual power supply as appeared in the fig. 1
Fig 2. Conventional CMOS circuit structure
2. . Stack technique:
Another strategy for leakage control diminishment is stack
approach, that depends on the way that characteristic stacking
of MOSFET help to lessen the leakage current. At the point
when two transistors associated in arrangement are killed
together, instigated turn around predisposition between the two
transistors causes in the decrease of sub-limit leakage current.
However isolated transistors increment defers essentially
restricting the execution. Fig.3 demonstrates the circuit
schematic for the same.

Fig.1 Power gating circuit

In dynamic express, the rest transistor is ON, encouraging

typical operation as there is an immediate way between the

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 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)
Fig.3 Stack technique circuit structure
3. Modified lector technique.
The essential thought behind LECTOR procedure for leakage
current lessening depends on the successful stacking of
transistors in the way from supply voltage to ground. This
depends on the idea that "a state with more than one transistor
OFF in a way from supply voltage to ground is less cracked
contrasted with a state with just a single transistor OFF in any
supply to ground way. Fig.4 demonstrates the circuit schematic
for the LECTOR method. Between hubs N1 and N2 two LCTs
(leakage control transistor) are currented. The entryway
terminal of each LCT is controlled by the wellspring of the
other. Henceforth called self controlled stacked transistors. As
LCTs are self controlled, no outside circuit is required. In this
manner the restriction with the rest transistor system has been
overcome. The leakage current is diminished in light of the fact
that the currentation of LCTs builds the resistance of the way
from VDD to ground. In this strategy, two LCTs were included
each CMOS entryway, a PMOS added to the draw up system
and a NMOS added to the draw down system and the door
terminal of one LCT is controlled by the wellspring of the
other. Accordingly one of the LCTs is constantly close to its
cut-off area of operation for any offered contribution to the
CMOS entryway. This gives extra resistance in the way from
supply voltage to ground consequently diminishing the sub-
threshold leakage current, thusly the static
power.
Fig.4 Lector CMOS gate
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VI. SYSTEM DESIGN
Framework level low power plan systems ought to be most
encouraging for decreasing vitality utilization. Two systems are
meant in this segment.
A. HW/SW Partitioning
The MicroPP Plus will be an installed framework with two
processor centres, a controller and a DSP. Administrations can
be actualized either in programming running on these centers,
or in committed equipment. In our plan stream this will be
chosen amid the progression of hardware software dividing.
This procedure has awesome impact on framework control.
This is shown in the accompanying case: Specific equipment is
for the most part more productive. 330mW are expended to
play out an expansion utilizing a SPARClite processor centre
in a commendable innovation (0.32mm/1.8V/16.8 MHz). A
custom viper in a similar innovation expends just 2mW or
more extra correspondence overhead.
B. Integration of Chip Components
Actualizing frameworks utilizing current day innovation brings
about third or a greater amount of aggregate power being
expended at the chip's information/yield (I/O) ports. The bigger
capacitances of chip's limits contrasted with inner doors and
higher voltages are the explanation behind this perception.
Common qualities for inner capacitances dwell around 10's of
femtofarads, where I/O pins achieve measurements of 10's of
microfarads. These days supply voltages for chip cores have a
tendency to be lower then 2.0V. In mechanical frameworks not
all segments of an outline may be best in class and require
higher voltages or specialized limitations require them. Still,
these distinctive parts need to impart over their I/O. This makes
double voltage frameworks (bring down voltage for the centers
– higher voltage for I/O) very normal.
VII. CONCLUSION
The leakage current turns out to be more basic in compact
frameworks with profound sub-micron and nanometre
advancements, where battery life is of essential concern.
Dealing with leakage power is an incredible test in nanometre
scale innovations since sub-limit leakage control gets to be
distinctly good to element control utilization. The upside of
Lector system is that as it doesn't require any extra control and
checking circuits it doesn't influence the dynamic power. A low
voltage/low limit innovation and circuit configuration
approach, focusing on supply voltages around 1 Volt and
working with decreased edges.
 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017)

• Low power interconnect, utilizing propelled

innovation, lessened swing or diminished action
approaches.
• Dynamic power administration systems, changing
supply voltage and execution speed as per movement
estimations. This can be accomplished by parcelling
the plan into sub-circuits whose vitality levels can be
freely controlled and by shutting down sub-circuits
which are not being used

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