Digital SoC Synthesis, STA, FV and ECO:

Top level SoC implementation bridging RTL and physical design including logic
synthesis with Synopsys/Cadence tools, formal verification, timing constraint creation +
validation and functional ECO creation.

Bachelor's degree in Science, Engineering, or related field. 5+ years ASIC design, or

related work experience.

5+ years experience in logic synthesis, formal verification, timing constraint

creation/validation and/or functional ECO creation.

Synthesis Engineer:
Running physical aware , low power synthesis for high performance DSP cores in
different technology nodes and delivering good quality netlist (meeting Frequency, Area
and Power targets) to PD team ,
Working with PD team for floorplan convergence, Debugging Timing issues and
working with RTL and PD team for timing fixes , Doing Power Aware Equivalence
Checking at different stages of implementation flow (RTL vs Gate, Gate vs Gate)

Hands on experience in physical aware synthesis and Equivalence checking , knowledge

on STA and PD implementation flow , Good analytical and debugging skill , Quick learner
and ability to work independently

Physical Design Engineer:

Physical Design Engineer withExperience in RTL2GDS of complex digital designs with
focus on below skillset Skills: Floorplan, Physical Design closure, Static timing Analysis,
Physical verification, TCL, perl, Python, ICC2, Innovus, 14nm/10nm/7nm nodes
exposure in PD Hands on experience on the entire PD Flow from Netlist to
GDSII(Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO,
STA) Working knowledge about OCV, MM/MC optimization and multi power
designs(Level shifters, Isolation cells etc)

Exposure STA in designsthat have Crosstalk delay OR noise /EM Strong in areas on CTS
and skew fixing Working knowledge on Physicalverifications tasks at lower nodes (data
base merging /DRC/LVS/ ERC/PERC/ Antenna/ESD/LUP analysis/fixing ) at block
level/chip level Job would require complete ownership from netlist to GDS for blocks at
Block level OR full chip level Exposure to scripting skills (TCL, perl, python) and timing
analysis will be an added advantage.
Low Power Implementation Engineer:
Developing UPF for DSP cores having multiple power domains, Validating UPF through
CLP at RTL and Netlist level , Ensuring proper insertion of isolation , level shifter during
synthesis

Good understanding of UPF (standard 1.0, 2.0 , 2.1 etc) , Hands on experience in writing
UPF for blocks having multiple power domains , Hands on experience in low power
verification using CLP tool at RTL and Netlist level

knowledge in dynamic and leakage power analysis using PTPX and debug , knowledge
in debugging MV cell insertion issues during synthesis , TCL programming experience

STA Engineer:
STA Engineer B.Tech/M.Tech with 3 to 5 years of industry experience in the following
technical areas and hands-on working experience in 14nm/10nm/7nm technology
nodes static timing -Hands-on experience on Static timing analysis (STA) and timing
closure -Static timing analysis (STA) tools and timing closure methodologies -Power
grid, clock tree, and low-power reduction implementation methods.

Working knowledge about signal integrity and timing closure issues such as
OCV/AOCV/Statistical Timing, FP, Placement, CTS -Strong in areas on CTS and clock
skew fixing -STA in designs that have Crosstalk delay/Noise - Job would require
complete ownership of STA and timing closure for given Sub-systems - Knowledge in
RTL2GDS of complex digital designs and Physical design implementation (FP, CTS, STA)
for high performance cores - Good knowledge in scripting languages like PERL, Shell,
Python, TCL -Strong verbal and written communication skills