RW W FE ATURE

John Wood

F
or those working in the
field of gallium nitride
(GaN) power transistors
and amplifiers, this arti-
cle’s subtitle (“A Perspec-
tive on Transistor Modeling for
GaN High-Power Amplifier De-
sign”) is probably self-explanatory.
Others may have questions: What
is transistor modeling? What is
GaN? Why is it important for pow-
er amplifier (PA) design? So, first, I
will try to answer these questions,
and others, to provide some per-
spective on transistor modeling for
GaN PA design.
I will focus on field-effect tran-
sistors (FETs), the workhorse tran-
sistor in RF and microwave circuit

Compact,
Portable,
and Easy to Use
John Wood (john.wood.mc5@gmail.com) is with Wolfspeed, a Cree Company, Durham, North Carolina, United States. He was working as a
consultant with Obsidian Microwave when the paper upon which this article is based was presented at PAWR 2018.
Digital Object Identifier 10.1109/MMM.2018.2862540
Date of publication: 12 October 2018

80 1527-3342/18©2018IEEE November/December 2018

 measurements of the tran-
sistor itself.
Often, such transistor
mo­­dels are known as com-
pact models, although this
term seems to be used quite
loosely (not least, by me)
and is frequently modified
by a number of additional
adjectives: physics-based,
equivalent-circuit, measure-
ment-based, table-based, behav-
ioral, linear, nonlinear—a sort
of glossary would be use-
ful. I associate the adjective
compact with something that
is small and neatly packed
together—like a Volkswa-
gen G o l f , perhaps. So, a
compact model should be
one whose circuit simula-
tor has a small number of
parameters or equations or
components or nodes. But
what do compact models
consist of, and what do they
look like? (Or, for the pedan-
tically erudite, how are com-
pact models compacted?)
A detailed physics-based
model will solve funda-
mental equations such as
Poisson’s equation, Schrö­
dinger’s equation, and the
c h a rge t ra n s p or t equa-
tions, given the physical
footage firm, inc.
structure, materials, dop-
i ng, a nd other m at e r i a l
properties of the transis-
applications over the past 20 or 30 years, particular­ tor—and, of course, the terminal stimuli and loads of
­ly for high-frequency and high-power applications. interest. This approach is known as TCAD—short for
While bipolar transistors, in the form of gallium arse- “technology CAD.” Such a model comprises (usually)
nide-based heterojunction bipolar transistors (HBTs), millions of cells covering the device structure, and
have found a sweet-spot application with the lower- the numerical solution of the equations is carried out
power PAs in cellphones, I will not be considering HBT self-consistently over this mesh of cells to produce the
modeling here [1], [2]. charge density, velocity (related to current), energy
(related to temperature), and potential (related to volt-
What Do We Mean by Modeling? age) in each cell, from which the transistor’s terminal
Essentially, a model is a mathematical representation behavior can be determined.
of the transistor’s electrical behavior. The model can Companies such as Synopsis and Silvaco produce
be as simple or complicated as you like, but circuit software to carry out this task: an example screenshot
designers generally want something that accurately of the Synopsis Sentaurus model is given in Figure 1.
represents the transistor’s electrical behavior, simu- Solving these equations of the fundamental physics
lates quickly, and can be used in their favorite circuit over the transistor structure takes a long time, and this
design (computer-aided design, CAD) tool. The folks modeling approach, while extremely useful for device
who produce the transistor models would also like designers to understand the impact of microscopic
the model parameters to be easily determined from physical changes on the transistor performance, is not

November/December 2018 81

Doping
Concentration (cm–3)
4.7 E+20
2.1 E+17
9.8 E+17
–5.6 E+12
–1.2 E+16
–2.7 E+19
Figure 1. An example of the mesh used in a fully 2-D physical model simulator. (Image
courtesy of Synopsis, Inc.)
usable for circuit design. But it is possible to use the
results of dc current voltage, bias-dependent S param-
eters, and even simulated load-pull to generate a com-
pact model that can be used for circuit design [3], [4].
The term compact model often refers to a physics-
based model, where the physics of the device is cap-
tured in an analytical or semianalytical formulation
that is simplified so it can be used in circuit design but
still contains enough detail to predict device develop-
ments in line with current technological trends. While
this sounds like a lofty goal, the physics-based com-
pact model is commonly used for bipolar/HBT mod-
els, wherein the device operation is well described
by the basic equations of the charge carrier transport
across the p-n junction; these fundamental equations
can be found in many semiconductor textbooks.
On the other hand, the physics of the charge den-
sity and transport in the channel of FETs, high-elec-
tron mobility transistors (HEMTs), and the like is
more difficult to describe succinctly in a few equations
and regions of the device, although several notable
Cgd Rgd
G D
Cgs
gm, t Cds Rds
Rgs
S S
Figure 2. A commonly found FET small-signal model
equivalent circuit. (Used with permission from [13].)
82 November/December 2018
attempts have been made with
some success. Snowden and
colleagues [5]–[8] developed
a quasi-two-dimensional (2-D)
solution for the physics-based
model by noticing that the FET
channel is effectively a thin
sheet; this is particularly the
case for HEMT devices in which
the conducting channel is con-
fined by the heterojunction
structure. If you can imagine
that the complete transistor
die is represented by a four-
story apartment block, then
the interesting physics of the
electron transport in the FET
would occur in the lighting
wires in the ceiling of a broom
c upb o a r d on the top floor.
So the focus of the quasi-2-D
model is in this region, and
you do not need to solve the
full 2-D mesh equations in the
remaining 99% of the structure. This saves a lot of time
and computer memory.
More recently, new physics-based compact models
for GaN FETs have been published [9]–[11] based on
the surface potential equations. These seem to offer
good performance—although, as yet, without wide-
spread adoption in design or simulation tools.
The qualifier measurement-based is frequently seen to
des­­cribe a transistor model. One might ask, if the model
is not based on some form of measurements, then
what is it based upon? Even the physics-based model
uses characteristics that have been obtained by mea-
surement to inform the solution. What we mean here
is that the transistor is measured in several regions of
operation where it might typically be used, including dc,
small-signal RF for frequency response, and large-signal
behavior at a given bias or set of biases and loads, for
example. As David Root has said [12], “the device knows
best” how it is going to respond to a given set of stimuli
and loads; as modelers, it is our job to create a mathemat-
ical model that mimics the transistor’s terminal behavior
under those conditions and also be predictive for other
similar stimuli and loads. The broad scope of what is
similar often determines how useful the model is.
On top of this, there are several forms that the mea-
surement-based model can take. A popular approach
is an equivalent-circuit model. This is easier to see
with a linear model: broadband S-parameter measure-
ments can be converted into Y parameters, and the real
and imaginary parts mapped onto conductance and
susceptance (usually capacitance in the case of FET
models); this leads to the common representation of
the small-signal FET model shown in Figure 2.
 The gate-source and gate-drain branches are often
described as series R-C networks, as shown in Fig-
ure 2, because the series resistance is thought to model
the resistance of the gate diode in a more physically
realistic manner. In practice, these series resistances
are difficult to measure accurately. This equivalent-
circuit model reduces the number of model parameters
to eight rather than the number of frequencies mea-
sured times eight (for the real and imaginary parts of
the S or Y parameters). That seems pretty compact.
The equivalent-circuit approach has also been adopt­
­ed for nonlinear FET models. This is usually accom-
plished by adding a voltage dependence to several of
the components of Figure 2, particularly the capacitors,
and a pair of diodes at the gate node to represent the
gate Schottky diode contact. Additional R-C networks
are often included to model the frequency dispersion
associated with trapping effects, for example, in the
GaN device. Gate-drain breakdown at high voltages is
a problem in gallium arsenide (GaAs) and laterally dif-
fused metal–oxide–semiconductor (LDMOS) devices
and somewhat less so (although not entirely absent) in
GaN: such effects are often modeled by adding shunt
diodes on the output side of the model. A generic exam-
ple of such a large-signal model is shown in Figure 3;
a comparison with Figure 2 indicates where the large-
signal effects have been added.
While this seems an eminently plausible approach,
adding gate-source and drain-source voltage dependen­
ces to the two-terminal capacitances has been shown not
to conserve charge [14]–[16], which can lead to errors and
poor convergence in simulation. This is outlined in more
detail in “Taking Charge.”
The measurement-based model can also be built
as a table-based model. A good example of this is
the ADSFET model, found in the Keysight Advanced
Design System (ADS) circuit simulator. This is a large-
signal model derived correctly from bias-dependent
S-parameter measurements to be charge conserva-
tive. The values of the model’s charge and current at
gate and drain are stored in tables, indexed by the gate
and drain voltages. At every instant in the simulation,
these node voltages are used to read the instantaneous
charge and current; hence,
they determine the FET model
Gate
gate and drain currents. While
Current
the tables can be quite large, G D
the model is fast to simulate Cgd
and as accurate as the mea-
Cgs
surements and the method
of interpolation between data Rgs
points permits.
S S
Finally, we come to FET
behavioral modeling. This is
also known, sometimes dis- Figure 3. A simple FET large-signal model equivalent circuit obtained by adding voltage
paragingly, as curve-fitting. dependence to some of the components of the small-signal model. (Used with permission
But, given that the physics from [13].)
November/December 2018 83
of FET devices is quite complicated to describe in
a few equations, transistor structures (particularly for
power FETs) are fairly complicated, and the material
properties of GaN devices are not as fully understood
as those of silicon or GaAs devices, the use of curve-
fitting to create models to mimic the measured ter-
minal behavior of these devices is an expedient way
forward. Indeed, the use of such behavioral models
has been standard practice in RF and microwave FET
circuit design for the past 20 or 30 years, and it has
been extraordinarily successful. Of course, you need
to be careful about the equations and functions used
to fit the data: that is part of the challenge in devising
a good GaN power FET model.
Here, we will review an approach for the develop-
ment of a compact (i.e., having a small number of param-
eters), measurement-based, nonlinear behavioral model
for use in the design of discrete and monolithic micro-
wave integrated circuit (MMIC) GaN PAs for RF and
microwave and millimeter-wave applications.
GaN Power Transistors and PA Design
GaN is a good candidate for high-power applications
at frequencies from RF through millimeter-wave. It is
a wide-bandgap material, which means that its break-
down electric field is high, enabling GaN transistors
to support high voltages and, therefore, high output
powers. GaN also has high electron mobility and satu-
rated velocity, so the transit time in the channel under
the gate is short, enabling FET operation up to high
frequencies. The GaN semiconductor material is usu-
ally grown on a silicon carbide (SiC) substrate. SiC is
a semi-insulating material with a high dielectric con-
stant, which is good for constructing MMICs, as well
as high thermal conductivity, so it is a good heat-sink-
ing material, enabling a high power density from the
GaN transistors. The combination of high-power and
high-frequency operation is commercially very attrac-
tive, pushing solid-state PAs into the realm tradition-
ally dominated by tube amplifiers.
The usual picture of a heterojunction FET shows a
simple structure onto which the small-signal param-
eters can be mapped fairly straightforwardly. This is
Rgd
lds, t Cds Rds
Dispersion
Breakdown
 Taking Charge
The small-signal capacitances we derive from the
measured Y parameters, as seen in Figure 2, can 100 pF
Increasing Vgs
be specified in terms of the static bias conditions, Vgs = 4.5 V
VGS, VDS, the control voltages at the gate and drain 90 pF

Capacitance (Cgs)
terminals. The instantaneous charge on a two-
80 pF
terminal capacitor is related to the voltage across its
terminals; therefore, the charge on the C gs capacitor
70 pF
is given only by Vgs and is not dependent on some
remote voltage.
60 pF Vgs = 2 V
Consider, for example, the gate-source and
gate-drain capacitances shown in Figure S1. While
50 pF
the capacitances have unique values at any given 0 1 2 3 4 5 6 7 8 9 10
Vds
pair of bias voltages ^VGS, VDS h, these capacitances
(a)
cannot be realized by a simple two-terminal nonlinear
25 pF
capacitor where the capacitance value depends on
the voltage across the terminals. In some models,
20 pF
the nonlinear gate-drain capacitance function is

Capacitance (Cgd)
described as a function of the gate-drain voltage, 15 pF
Vgd . Notwithstanding the fact that Vgd is not a control Increasing Vgs
voltage but a derived value from Vgs, Vds, it is clear 10 pF
from Figure S1(b) that a C gd cannot be described by
a single-valued function of Vgd . The behavior of a 5 pF
two-terminal capacitor whose value depends on two
voltages, such as Vgs and Vds, requires a much more 0 pF
careful definition under large-signal operation. 0 1 2 3 4 5 6 7 8 9 10
Vds
Snider [15] has shown clearly and elegantly that
(b)
using a remote voltage to change the capacitance and,
hence, alter the charge on a two-terminal capacitor
Figure S1. The (a) gate-source and (b) gate-drain
breaks the laws of conservation of charge and energy.
small-signal capacitances of a laterally diffused
The conservation of charge is something we tend to
metal–oxide–semiconductor (LDMOS) power FET as
take for granted: charge can be neither created nor
functions of the applied bias voltages V gs, Vds . (Figure
destroyed. But, by using capacitors that are functions
courtesy of Cambridge University Press.)
of two independent, instantaneous voltages, it is all
too easy to create non-charge-conserving elements in
a large-signal compact model.
And, while you might think that running afoul of
a couple of the laws of nature is bad enough, Root
Contour 1
and Hughes [14] noted that such a component can
B
accumulate a net charge under steady-state periodic Capacitance (pF)
signal conditions, even though the voltage across A
the capacitor’s two terminals returns to the same Contour 2
value at the end of the period. Further, Staudinger Vds Direction: Integrate Cgd
et al. [23] showed that by changing the model Vgs Direction: Integrate Cg
description of the gate capacitors only, using first
the classical Schottky junction model and then the
Figure S2. The 2-D capacitance field at the gate in
Statz [21] symmetrical capacitance model, and finally
coordinates ^V gs, Vdsh . The points A and B represent
using a fully charge-conservative model, only the the locations of two instantaneous signal voltages
charge-conserving capacitance model could predict in this field, and contours 1 and 2 are two different
accurately the measured third-order intermodulation paths connecting A to B. (Reprinted with permission
distortion and adjacent channel leakage ratio data for from [25].)
an RF power amplifier.
Clearly, any large-signal FET model that we build circuit simulator. This means that the state variables of
needs to be current and charge conservative if we our model need to be current and charge, rather than
want it to be accurate and run successfully in the current and capacitance.

84 November/December 2018
 Taking the large-signal gate charge Q g as an
example, the concept of charge conservation is
described in the form of a conservative vector field of
× 10–11
capacitance. The two-dimensional (2-D) capacitance 4
field for the gate charge Q g is shown in Figure S2. 3
The gate-capacitance components of this field are 2

Charge
the C 11 and C 12 terms (from the small-signal Y 1
parameters), and the vector directions are Vgs and Vds, 0
respectively [25], [30]: –1
–2
C = C 11 (Vgs, Vds) uVgs + C 12 (Vgs, Vds) uVds . 10
5 80
60
0 40
We can integrate along any contour between Gate Voltage 20
–5 0 Drain Voltage
two points in this field to obtain the difference in
(a)
charge between the two points. Integration around
any closed contour in the field brings us back to
the starting point, and no charge has been lost or × 10–11
8
accumulated: the charge is conserved.
The gate charge is related to the component 6
capacitances through the partial derivatives: 4
Charge

2
2Q g
= 1 Im ^Y11 h = C 11 (Vgs, Vds) 0
2Vgs ~
–2

and –4
–6 –5
80 60 0
2Q g
= 1 Im ^Y12 h = - C 12 (Vgs, Vds) . 40
20 0 10
5
2V d s ~ Drain Voltage Gate Voltage
(b)

We obtain the gate charge at any instantaneous value

Figure S3. The (a) gate and (b) drain charge surfaces
of ^Vgs, Vdsh by integrating the differential equations
(in coulombs) for an LDMOS power FET model as
from an arbitrary starting point, say ^Vgs0, Vds0 h, where
functions of the applied bias voltages V gs, Vds . (Used
the gate charge is Q g0:
with permission.)

Vgs
Q g (Vgs, Vds) = #V gs0
C 11 (v gs, Vds0) dv gs
where C m is the transcapacitance defined earlier.
+ #V
Vds
C 12 (Vgs, v ds) dv ds + Q g0 . We have, therefore, included the time delay, x,
ds 0
from the small-signal model automatically in the
charge-conservative description of our large-signal
The constant of integration Q g0 (in other words, model. This overcomes the historical problem in
the integration starting point) is arbitrary and can be small- to large-signal inconsistency in the S-parameter
set to zero: we are interested only in the displacement prediction caused by not including the time delay
current dQ/dt in the simulation of the model. parameter explicitly in the description of the large-
Similarly, we can derive the drain charge from signal current in equivalent-circuit models, such as
the integration of the C 21 and C 22 small-signal those described by Figure 3.
capacitance components: We now have the gate and drain charge surfaces
Vgs
in the large-signal voltage space ^Vgs, Vdsh . These are
Q d (Vgs, Vds) = #V gs0
C 21 (v gs, Vds0) dv gs shown in Figure S3 for an LDMOS power transistor.
Vds These surfaces were obtained from the ADSFET (also
+ #V ds 0
C 22 (Vgs, v ds) dv ds + Q d0 . called Root) model, where the integration is performed
using Keysight IC-CAP modeling software. Of course, if
We note that the C 21 component is given by you are building your own model, you will have to write
your own integration routines in MATLAB, Python, or
C 21 = C m - C gd, another favorite mathematical language.

November/December 2018 85
 in Figure 4 a slight asym-
Gate metry in the gate-source and
Source Drain gate-drain separations. The
gate-source separation is usu-
Ls Lg Ld ally kept as small as possible
Rs Rg Rd because it introduces feedback
resistance into the source-to-
Cgs Cds Cgd
ground connection, reducing
Barrier Layer the gain, which is a precious
Rs Rd
Rs Ids Rd commodity at microwave fre-
2-D EG. Layer
quencies. The drain-to-source
Si Substrate Rds separation is the larger of the
two, increasing the drain-gate
breakdown voltage and allow-
Figure 4. A schematic cross section of an HEMT device, showing the assumed locations ing a higher drain-source vol­­­­
of the intrinsic and extrinsic equivalent-circuit elements. (Used with permission from tage to be applied, which i s
[13].) EG: electron gas. useful for getting some pow­­
er out of the transistor.
In practice, power FETs are more complex than the
FP2 simple device outlined previously. A cross section of a
typical GaN power transistor is presented in Figure 5,
Gate + FP1 showing a number of features typical of power FETs.
First, the drain-to-gate separation is much increased,
S D
allowing the device to support high drain-source volt-
ages and, hence, be able to supply high power. The
HEMT Epilayers
transistor also has two field plates. The first of these is
100-mm High-Purity Semi-Insulating 4-H SiC integrated with the gate metallization, and it produces
electric field shaping at the drain side of the gate to
Figure 5. A schematic cross section of a GaN HEMT reduce the peak electric field and, hence, increase the
power transistor, showing the gate structure, field plates drain voltage capability. It also reduces the gate (para-
(FP), and large drift region [17]. sitic) resistance by increasing the cross-sectional area
of the gate metal. After a layer of passivation over the
exposed regions of the device, the second field plate
1 is added and connected electrically to the source,
providing further electric field shaping at high drain
Normalized Drain Current

0.8 voltages. It also reduces the gate-to-drain feedback

Load Line
0.6
0.4
0.2
QOP
0 mum power. Saturated class-A or class- AB PAs are
0 5 10 15 20 25 30 35 40 45 50
Drain Voltage (Vds)
Figure 6. The idealized output characteristics of an FET
device, showing the class-AB quiescent bias point and the
load line for maximum output power. QOP: quiescent
operating point. (Used with permission from [13].)
illustrated in Figure 4; the intrinsic circuit elements
can be identified from Figure 2, and the remaining
resistors and inductors comprise the extrinsic or para-
sitic components associated with the gate, drain, and
source metallizations needed to build the FET and
connect it to the outside world. One can (barely) see
capacitance, enabling higher-frequency operation of
the power transistor.
Solid-state PA design at microwave and millimeter-
wave frequencies has traditionally focused on maximiz-
ing the output power; efficiency has been a secondary
concern, although efficiency is at its highest at maxi-
commonly used, with harmonic tuning for improved
efficiency (when harmonic energy is available). This
approach is very successful for constant-envelope mod-
ulation signals; when analog linearization is applied,
power outputs within a few decibels of the saturated
power can be attained with digitally modulated signals
of modest peak-to-average power ratio (PAPR) [18].
Class-AB PAs are designed at a fixed gate–drain
bias. The load line is generally chosen to provide the
maximum drain voltage and current swing, as shown
by the FET output characteristics depicted in Figure 6.
The current and voltage will generally follow the load
line, which, in practice with GaN FETs, will become
slightly elliptical due to the small output capacitance

86 November/December 2018
of these transistors. The device model needs to be
accurate around the quiescent operating point (or bias
point) and over a relatively small range of output char-
acteristics; often, a constant output capacitance can be
used successfully in this PA design.
Modern communications signals (for example, cel-
lular or satellite) employ complex digital modulation
formats to achieve high data throughput while using
the available bandwidth efficiently. Typically, these
modulation techniques involve multilevel quadra-
ture amplitude modulation, perhaps with additional
coding, and the spectral efficiency of such modula-
tion schemes can be very high. A consequence of
using such signals is that the PAPR can be very high,
over 10 dB.
The PA must be able to handle the peak signals,
which requires traditional class-B/AB PAs to be oper-
ated in deep backoff from the peak, resulting in very
low efficiency at the average power. This has led to
the development of several PA architectures that have
high efficiency at both peak power and (in backoff)
average power. These include Doherty, outphasing,
and polar modulation, as outlined in “High-Efficiency
PAs.” A feature of these high-efficiency PA designs is
that the output signal traverses a considerable portion
of the FET output characteristics, so now the transistor
model must be accurate over the whole output current-
voltage (I-V) space, and the nonlinearity and voltage
dependence of the current and charge (capacitance) of
the device must be considered in building the model.
For a model-based MMIC design, the transistor
size-scaling rules are a necessary feature: the compact
model must be able predict the desired performance
parameters with similar accuracy over a wide range
of device dimensions. Scaling can include a number
of gate fingers, unit gate widths, source-to-source and
drain-to-drain spacings, and through vias, for example.
Scaling rules are dominated by the extrinsic param-
eters, and the complete compact model must include
these as well as the nonlinear intrinsic part. The PA
performance parameters for the MMIC will cover
much the same set as for the discrete PA—power and
efficiency, optimum loads and contours, gain, and
return losses—but now over a range of bias condi-
tions. Additionally, there may be size constraints on
the MMIC, which can affect the thermal behavior: an
accurate dynamic thermal model is required so that
the device size and layout can be adjusted for opti-
mal performance.
Modeling Considerations
for GaN Power FETs
Microwave PAs are designed almost exclusively with
FETs. It is fair to say that almost all compact models for
FETs available in commercial electronic design auto-
mation (EDA) , i.e., CAD, tools are derived from mod-
els originally developed in the 1990s for transistors
November/December 2018 87
operated nominally in a class-A bias (see, for example,
[19]–[22] and numerous others). Such models typically
comprise a dc component, where the static dc I-V rela-
tionship is based on a threshold voltage and modeled
using a hyperbolic tangent (or similar) function, with
voltage-dependent capacitance elements derived from
S parameters. These are known as quasistatic models,
derived in the expectation that the device behavior
changes only slowly over frequency. For FETs biased
in class A using only modest signal amplitudes, this
is a generally satisfactory assumption. However, the
approach is not adequate to describe the large-signal
operation of transistors in PA applications, where
thermal effects are important, nor in cases where
memory effects such as trapping play a significant
role in the terminal behavior, e.g., in GaAs- and GaN-
based FETs.
Further, in virtually all of these FET models, the
intrinsic voltage-dependent capacitances have been
determined in a manner that neglects the law of
charge conservation. Such models will not conserve
charge during the simulation, creating potential off-
sets or charge buildup that needs to be redistributed
elsewhere in the circuit; these models will therefore
produce the wrong answer, which constitutes a seri-
ous drawback. In [23], Staudinger et al. showed that,
by changing the model description of only the gate
capacitors and comparing the classical Schottky junc-
tion model, the Statz [21] symmetrical capacitance
model, and a fully charge-conservative model, only
the charge-conserving capacitance model could accu-
rately predict the measured third-order intermodu-
lation distortion and adjacent channel leakage ratio
performance for an RF PA.
The recipe for constructing a charge-conservative
FET model from S-parameter measurements made
over the Vgs - Vds bias space was first outlined by
Ward and Dutton [24] and expanded on by Root and
Hughes [14] and Wood et al. [25] for GaAs FETs and
LDMOS power FETs, respectively; a review of charge-
and energy-conservative transistor modeling can be
found in [16]. A summary of the charge-conservative
modeling approach is presented in “Taking Charge.”
[As an aside, a conservative charge model is not to be
confused with Gummel symmetry [26], which is asso-
ciated with continuity in the drain current expression
across Vds = 0, although both effects are important
in the correct simulation of distortion. A brief note is
included in “Model (A)Symmetry.”]
Based on the previous discussion, we can con-
clude that the model should use current and charge,
not capacitance, as the state functions. Following
the lead of Parker [27], we can take the small-signal
model Y-parameter description and map directly
onto the (large-signal) current- and charge-state func-
tions. The Y-parameters small-signal model is shown
in Figure 7.
 High-Efficiency PAs

Doherty PA amplifier—active load-pull or load modulation—so that

The Doherty power amplifier (PA) [S1], [S2] is the
predominant PA architecture used in cellular wireless
infrastructure base stations today and is also found in
some handsets (user equipment). The basic Doherty
amplifier structure is shown in Figure S4.
The main amplifier is usually class AB and is
switched on at all power levels. Initially presented
with a higher-than-optimum load, the main amplifier
delivers peak efficiency when it reaches a maximum
output power at a 6-dB backoff from the PA
maximum power. At this point, the peaking amplifier
switches on, changing the load presented to the main
Main
Amplifier Output
Match
3-dB Hybrid
RF In λ /4
Σ from the 6 dB described by
Summing
Peaking Node
Amplifier
Figure S4. A schematic circuit of the Doherty PA. (Used with permission
from [13].)
the main amplifier continues to operate at maximum
voltage and current swing and, hence, maximum
efficiency. At peak output power from the Doherty
PA, the main and peaking amplifiers contribute half
the power, and high efficiency is maintained over
the whole range from (6-dB) backoff to peak power.
Clearly, the transistor model should be accurate over
this wide range of output characteristics, as shown in
Figure S5, including the knee region, and also model
voltage-dependent output capacitance.
In practical Doherty PAs, the peaking amplifier is
realized by a power transistor operating in a class-C
bias. The peaking amplifier
is then switched on by the
magnitude of the drive signal
itself. Sizing the main and
peaking amplifiers appropriately
and adjusting the value of the
class-C bias allow the switch-on
point to be adjusted to provide
a peak efficiency range different
λ /4 simple theory.
ZL
Doherty PA design requires
that the compact model
be able to predict device
performance not only in the
usual Vgs - Vds class-AB bias space
but also for class-C switched-off

1
1
Normalized Drain Current

0.8
Normalized Drain Current

Ropt
0.8
0.6
0.6
2*Ropt
0.4
0.4 Load Line
0.2 Tracks Signal Envelope
QOP 0.2
0 Class-AB Bias Point
0 5 10 15 20 25 30 35 40 45 50
0
Drain Voltage (Vds) 0 5 10 15 20 25 30 35 40 45 50
Drain Voltage (Vds)
Figure S5. The output characteristics of the main
PA FET during Doherty operation. The load line 2 ×
Ropt represents the load line presented to the main
amplifier in the backoff region before the peaking Figure S6. The principle of envelope tracking: as the drain
amplifier switches on. At higher powers, the peaking voltage supply is reduced, the available signal swing is
amplifier pulls the load seen by the main amplifier reduced to ensure that the output signal swing is always
toward Ropt, the optimum load for maximum power. maximized to yield peak efficiency. (Used with permission
(Used with permission from [13].) from [13].)

88 November/December 2018
 bias conditions. Few, if
any, transistor models
are developed with this
in mind, and validation Digital
of performance in these Baseband
conditions is rare. The I/Q
transistor model should
be able to predict high-
RF Carrier
order nonlinearities. The
addition of the class-C
device to a class-AB
PA to create a Doherty
PA can be shown to
increase the nonlinear
order of the model from,
Figure S7. A schematic of the outphasing architecture [S4]. Dig.: digital.
typically, the fifth degree
for class AB to the 11th
degree or higher for the Doherty PA.
Polar Modulation
Often called envelope tracking (ET), polar
modulation adjusts the power supply to the
transistor dynamically to follow the magnitude of
the modulating signal in such a way as to keep the
amplifier in saturation and, hence, at high efficiency
at all times [S3]. This is illustrated in Figure S6.
The approach has not shown much commercial
success, mainly due to the cost of the high-current
power modulator for the PA power supply, but it
is seeing application in cellular wireless handsets.
While its use of saturated PAs for high peak-to-
average power ratio signals appears attractive
for microwave and millimeter-wave applications,
again, the power modulator design would appear
to be the main drawback with this architecture.
Essentially, it needs a linear, high-power amplifier
with several times the modulation bandwidth to
drive the power supply to the main PA: this, in
itself, is a major cost and design challenge for a
microwave/millimeter-wave PA.
Again, it can be seen that ET operation covers a
considerable area of the FET output characteristics.
A suitable transistor model for ET PA design should
be able to cover the entire Vgs - Vds bias space
and produce accurate terminal responses at dc,
baseband, and RF over this space. Further, because
in ET operation the power transistor receives
signal inputs at two of its terminals—RF at the gate
and envelope or video-band information at the
drain—in addition to nominal dc biases, the model
must be able to respond accurately to signals at all
frequencies from dc through the video bandwidth to
November/December 2018 89
VD
i1
Baseband PA
Signal +
Component
– v1 Y1
Separator
+jX
I/Q I/Q
RL
Dig. to
RF VD –jX
i2
Dig. to
PA
RF +
– v2 Y2
the RF carrier and handle broadband modulation as
well as sinusoidal excitation.
Outphasing
Outphasing is another load modulation technique, in
which the phase of the signal between two amplifiers
is adjusted so that the reconstructed signal preserves
the original signal modulation [S4]. A schematic
outphasing arrangement is shown in Figure S7.
Outphasing is more a transmitter system than a
PA, requiring some signal processing to convert the
input signal into the two-phase modulated, constant-
amplitude RF signals that drive the amplifiers. Saturated
PAs can be used for the outphasing amplifiers, resulting
in high-efficiency operation even for a large backoff,
indicating promise for millimeter-wave operation. While
good results have been obtained in the laboratory at
low frequencies, so far the power and efficiency at
microwave and millimeter-wave frequencies are low.
While this PA is operated in constant envelope
mode in the classic outphasing design, more modern
incarnations include multilevel bias operation, and
the capability of the transistor model to cover a wide
range of the output characteristics is again required.
References
[S1] W. H. Doherty, “A new high efficiency power amplifier for modu-
lated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182, Sept. 1936.
[S2] S. C. Cripps, RF Power Amplifiers for Wireless Communications.
Norwood, MA: Artech House, 2006.
[S3] E . McCune, Dynamic Power Supply Transmitters. Cambridge, UK:
Cambridge Univ. Press, 2015.
[S4] T. W. Barton and D. J. Perreault, “Theory and implementation
of RF-input outphasing power amplification,” IEEE Trans. Microw.
Theory Techn., vol. 63, no. 12, pp. 4273–4283, Dec. 2015.
 The controlled current source is still represented
here in magnitude plus phase form. Recasting this as
real plus imaginary, we can write
g m . exp ^- j~x h = g m + j~C m, (1)
Model (A)Symmetry
The idea behind model symmetry originated in metal–
oxide–semiconductor field-effect transistor (MOSFET)
modeling. Most MOSFETs are structurally symmetric:
looking at the layout of the transistor, it often is not
easy to tell which is the drain and which is the source
contact. So you might expect that the MOSFET model
should be symmetric about Vds = 0. Unfortunately,
many early MOSFET models were not symmetric. You
might also expect that the model drain current would
be zero at Vds = 0. While this may be the case, the
n
derivatives d n /I ds /dV ds can have different limits on
either side of zero: the derivatives are discontinuous,
and the model is singular at Vds = 0.
While this may not be too important for many
applications (and we could perhaps consider PA design
to be one of them), this singularity leads to completely
incorrect results for distortion simulation in circuits
where Vds crosses zero, such as passive mixers. A
standard test for MOSFET model symmetry was derived
by H.K. Gummel in the 1990s (known as the Gummel
symmetry test) [26]. A common interpretation of the
Gummel symmetry test is that swapping the intrinsic
source and drain terminals should result in identical I-V
characteristics. A nice exposition has been presented
by McAndrew [S5], and simple circuits for simulating
the Gummel symmetry test under dc and ac conditions
are shown. These are applied to MOSFETs, where the
structural symmetry is fairly clear.
What is interesting about these tests is that they
can also be applied to power transistor models. How
should we do this? It is difficult to identify the intrinsic
source and drain connections in the power transistor
structure. Looking at Figure 5, for example, should we
use the source and drain edges of the gate metal and
treat the rest of the structure as extrinsic, even though
the field plates and drift region are fundamental to
the operation of the power transistor? For laterally
diffused MOS power transistors, the picture is even
worse: the intrinsic device is asymmetrical.
Generally, I would build a nonlinear model of the
complete device, including the field plates and drift
region: this is what I use as the intrinsic FET. As I am
much more concerned with the correct predictions
of distortions at RF or microwave frequencies, I have
used a form of the RF Gummel symmetry test from
[S6] and find that a (well-constructed) measurement-
90 November/December 2018
where C m is the transcapacitance through which we
have a means of obtaining the drain charge source: see
“Taking Charge” for further details.
The original development of the conservative charge
model by Ward and Dutton [24] used a partitioning
based model can pass the test with ease. All you
need are continuous higher-order derivatives of
n
d n I ds /dV ds across Vds = 0.
But back to the intermodulation distortion
(IMD) measurements and model test reported by
Staudinger et al. [23]: here, the nonlinear I-V model
was the same for all three models; only the gate-
capacitance (charge) model was different. Because
the basic third-order intermodulation prediction of all
the models was basically good, one might presume
that the nonlinear I-V model did indeed have
n
continuous d n I ds /dV ds derivatives of an order of at
least n = 2. The discrepancy between the different
models must, therefore, be due to something else:
the capacitance model. Each of the capacitance
models used in [23] was symmetric in the Gummel
sense of swapping drain and source contacts, but
only the charge-conservative model predicted the
IMD accurately in the simulation.
A noncharge conserving model will create a
buildup of charge over the RF period [12], [14], [16].
This excess charge looks like a discontinuity in the
integration path in the capacitance-voltage field (see
“Taking Charge”) around what should be a closed
loop for the RF cycle: this model has discontinuities.
On the other hand, a charge-conservative model
will not create any excess charge at the end of the
RF cycle. The charge-conservative model might
well be described as symmetric with regard to the
integration path: that is, it does not matter which
way around the loop you go (or, indeed, what the
details of the loop are); you always end up in the
same place—the starting point—at the end of the RF
period. And, because the path is, by construction,
smooth and continuous (and conservative), all time
derivatives of Q are continuous. Charge conservation
might be thought of as a supplement to the Gummel
symmetry test for displacement currents.
References
[S5] C . C. McAndrew, “Validation of MOSFET model source-drain sym-
metry,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2202–
2206, Sept. 2006.
[S6] P. Bendix et al., “RF distortion analysis with compact MOSFET mod-
els,” in Proc. IEEE 2004 Custom Integrated Circuits Conf., Orlando,
FL, Oct. 2004.
scheme to split the channel charge between the drain
and source nodes. This is commonly done when the Ggd + jωCgd
G D
charge sources are associated with the nodes of
the FET. These charge sources are then referenced to
ground, as shown in Figure 8(a), for GaN (and GaAs) Ggs + jωCgs Gds + jωCds
FETs where the source is connected to ground. This
effectively describes the charge sources as branch S Gm .exp(–jωt) S
components. We can then simplify the model as
shown in Figure 8(b): we connect the gate- and drain- Figure 7. The Y-parameters circuit description of the
charge sources to the internal source node and then FET small-signal model. The series R-C gate-source and
redefine the source charge to be Q g + Q d + Q s, so the gate-drain branches of Figure 2 are replaced by the parallel
net current out of the FET source node is still dQ s /dt. G + j~C representations. (Image courtesy of Obsidian
The currents into or out of each node in the FET model Microwave, LLC.)
are unchanged by this transformation. As we assume
that charge will be conserved, the total charge in the
FET, Q g + Q d + Q s, must sum to zero, so we can dis-
pense with the charge source at the FET source node,
as shown in Figure 8(c).

Nonlinear Core
Qg Qs Qd
We are now able to present the schematic for the
nonlinear core of the large-signal GaN FET model,
derived from Y-parameter description and conser-
vative-charge sources, as shown in Figure 9. It looks
simple enough, does it not? (a)
The current and charge functions depend on the
voltages Vgs and Vds, and they are represented by
surfaces over the accessible Vgs and Vds space. The I,
Q surfaces are then represented as functions such as Qg Qd
Q g (Vgs, Vds). For ease of parameter identification, it is
desirable to be able to write these 2-D functions as sep- Qg + Qd + Qs
arable one-dimensional functions; for example, for the
gate charge 2-D function, we have

Q g (Vgs, Vds) = Q gg (Vgs) .Q gd (Vds) . (2)

(b)
We try to find such separable functions wherever
possible, although experience has taught us that this
is not always possible and that some mixed functions
will be required. We aim for the minimum possible Qg Qd
number of parameters consistent with the accurate
representation of the measured data and interpolation
between the measured points as well as for sensibly (c)
constrained extrapolation qualities. Simulation speed
is a concern, so we try to avoid including too many Figure 8. (a)–(c) The conversion of the nodal charge
complex functions. It should be noted, however, that sources to branch charge sources, along with elimination of
in most modern mathematical and EDA tools, func- the need for the charge source, after [28].
tions such as tanh(x) are implemented using interpo-
lated tables and are both very accurate and quick to
Gate Drain
calculate, so they do not incur a significant computa-
tional penalty.
The drain-current function I d (Vgs, Vds) is prob-
ably the most widely studied of these 2-D function Qg Ig Id Qd
approximations, and examples such as the MET [29],
Source
[30] and Fager-Pedro [31] models (for LDMOS) and the
Pedro [32] model (for GaN) already provide a good Figure 9. A large-signal FET intrinsic model. (Used with
starting point: permission from [13].)

November/December 2018 91

0.1
Transconductance and Higher Derivatives
0.08
0.06
0.04
0.02
0 0
–0.02
–0.04
–0.06
–0.08
–0.1
–4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5 0
Gate Voltage
Figure 10. The drain current and transconductance as functions of the gate-source
voltage when comparing measured data and the Pedro model relationship [32]. The
(scaled) third and fifth derivatives of g m are also shown, indicating excellent continuity
and differentiability. (Image courtesy of Wolfspeed.)
V VQ
gst
Id = b . tanh ^aVdsh . ^1 + mVdsh . (3)
^ 1 + kV VPgst h
Here, the relationship for the drain current is shown
to be separable in Vgs and Vds; in practice, however,
the parameter a often includes a Vgs dependence
to account for the features of the knee region in
GaN FETs.
The I d (Vgs, Vds) relationship from the Pedro model
for GaN [32] is used in the preceding expression and,
generally, gives a good approximation of the measured
drain-current and transconductance data (Figure 10).
The equations for gate and drain charge are developed
in “Taking Charge.”
Dynamic Effects
Unlike the quasistatic modeling approach outlined pre-
viously, dynamical models include time or frequency
dependence explicitly in the model formulation. In other
words, they can accommodate memory effects or tran-
sistor behaviors that occur on different timescales. The
most common dynamical effects in FET devices are self-
heating and trapping.
Thermal Effects
PAs are, unfortunately, not 100% efficient: the energy
not converted into RF power is converted into heat,
and the transistor heats up in response to the signal
power. Several compact models include a coupled elec-
trothermal model, which uses an electrical analog for
the thermal resistance and capacitance to determine
the channel temperature of the FET and, hence, mod-
ify the model drain current. This self-heating causes
the drain current (principally) to fall with increasing
92 November/December 2018
temperature, modeling the fall in
0.25 electron velocity as temperature
0.2 rises. The time constant of the
thermal network determines the
0.15
response time of the temperature
0.1 to the signal power and, hence,
Drain Current
0.05 introduces a time delay or mem-
ory effect.
Careful thermal modeling of
gm Model –0.05 the transistor is im­­portant because
gm Measured
–0.1 the self-heating affects the inter-
gm3
gm5 modulation properties of the de­­
–0.15
Id Model vice at high frequencies. A useful
Id Measured –0.2 thermal modeling approach has
–0.25 been proposed by Parker and
0.5
Rathmell [33]. Usually, the thermal
network is a single time constant,
but, in practice, there may be sev-
eral time constants corresponding
to the different elements of the
complete device structure: the
GaN and its SiC substrate, the die
attach, the package, the printed
circuit board, and the heatsink. For MMICs, thermal
coupling between transistors is also important. This
can result in a fairly complicated thermal network
that is not necessarily linear, as the thermal resistivity
of GaN and the SiC substrate are nonlinear.
Additionally, one should include a dependence on
temperature for the threshold voltage. This thermal
function reduces the threshold voltage as temperature
increases, acting in the opposite sense to the self-heat-
ing explained previously. This results in a sweet-spot
bias condition when the two thermal functions cancel
one another out [30].
Charge Trapping
Trapping of the charge is an important, but undesirable,
feature of compound semiconductor FETs and HEMTs;
it can be neglected for LDMOS devices. Trapping is
usually characterized as follows.
•• gate lag, where changes in the gate signal voltage
(Vgs) result in changes in the occupancy of traps
in the channel of the FET, affecting the drain cur-
rent. This is usually seen as a reduction in the
maximum attainable drain current.
•• drain lag, where changes in the drain output volt-
age (Vds) result in changes in the occupancy of
traps at the hetero-interface. This is observed as
the knee walk-out effect, where defining the tran-
sition from the triode to saturation regions moves
to higher values of drain voltage. The effect is most
pronounced at high drain currents and results in a
reduction in the available RF voltage and current
amplitude and, hence, a reduction in power.
The emission of charge from the traps is a much
slower process by several orders of magnitude than the
capture, resulting in a delay in
the drain-current response to the Vds(t )
voltage change: a memory effect. Rcap
A detailed analysis of trapping
based on the Shockley–Read–Hall Vds(t ) – + –
A Kv Vth(t )
mechanism has been performed +
by Rathmell and Parker [34], who C Vc (t )
Remis
have developed a trapping model Vth
for gate and drain lag that is incor-
porated into their compact model Figure 11. A circuit description of trapping effects in GaN transistors, from [38].
for GaAs- and GaN-based FET When Vds (t) > Vc (t), the trap capacitance C charges up rapidly through the small
devices [35]. resistance R cap . When Vds (t) < Vc (t), the capacitor discharges through R emis ; this
A simple circuit-based model time constant is much longer, so the trap voltage decays slowly. Vc (t) is scaled
for gate and drain lag has been and subtracted from Vds (t) and adjusts the threshold voltage Vth (t), producing a
proposed by Jardel et al. [36], with dynamically changing drain current.
a description of how to estimate
the model parameters from pulse profile measurements. trapping conditions from the static load line, changing
Their trapping model produces a time-dependent the PA design target.
adjustment of the FET model’s intrinsic gate voltage
and, hence, mimics the gate- or drain-lag behavior. Extrinsic Parameters
An update to this model for drain lag [37], [38] adjusts The extrinsic shell describes the physical structure of
the threshold voltage, using the same circuit-based the transistor and how the intrinsic core is connected
approach. The circuit model adapted from [38] is shown to the outside world. This is illustrated in Figure 4 for
in Figure 11. an idealized heterojunction FET. In practical devices
One way of demonstrating the effects of gate and for power transistors, there will be additional extrinsic
drain lag in simulations is through transient simulation contributions from the structure, such as field plates
to mimic the pulsed I-V characterization. By a suitable and so on.
choice of the quiescent gate and drain biases, gate- and The extrinsic shell accounts for much of the de­­tailed
drain-lag effects can be induced, and the model will scaling factors in a general model for MMIC design.
mimic the observed pulsed I-V behavior. Figure 12 (a) and The extrinsic parameters can be found from broadband
(b) shows the transient simulation results for the output S-parameter measurements made under cold FET con-
characteristics of a GaN FET model with, respectively, no ditions, where Vds is set to zero, essentially eliminating
trapping included and the models for gate- and drain-lag the controlled drain-current source from the small-sig-
effects turned on. The impact on the I-V is noticeable. It is nal model description [39], [40]. Under conditions where
important to show that the trapping, which is a dynamic Vgs < Vth , the extrinsic and intrinsic models reduce to
effect, can be modeled only by using a dynamic simula- capacitances only; when Vgs >> 0, the capacitances are
tion, such as a transient. I find it hard to understand how effectively shorted, and the measurements are dominated
trapping dynamics can be demonstrated using a static by resistance and inductance. Hence, the extrinsic com-
dc simulation. ponent parameters can be found. Performing this exer-
The impact of trapping on the transistor model cise over a range of device sizes enables the derivation
behavior can be seen in, for example, the harmonic of scaling rules for the given transistor technology.
balance simulation of the GaN FET transistor model The manifold structures are included specifically
under a high-power drive where the PA is in compres- to model the large bond-pad structures found in
sion. Figure 13 shows the dynamic load line—drain power transistors. These are usually modeled using an
current against drain voltage as functions of time—of electromagnetic simulator as multiport S-parameter
the transistor superimposed on the output character- blocks; they describe the bond-wire connections and
istics obtained from transient simulation. Note that, the feeds to the individual transistor gates and drains
in the transient I-V simulation, the nominal operating in the device.
point has been set to be the approximate peak value
of the output voltage. We do this because the traps The Complete Model Structure
are filled in response to the peak of the applied volt- Putting together all we have learned so far, we can see
age in the channel [37]. The dynamic load line follows that a suitable measurement-based behavioral model
the maximum drain-lag current trajectory from the of a GaN microwave power transistor for PA design
transient simulation quite closely. It is clear from this should include the following features:
graphic that trapping has a significant impact on the •• state functions that are current and charge
dynamic I-V characteristics and that the load line for •• coverage of all I-V and Q-V space that is address-
a given application may well be very different under able by the signals in practical PAs

November/December 2018 93
 0.55
Vgs = 1
ADS
0.5
Vgs = 0.5
0.45
Vgs = 0
0.4
Vgs = –0.5
0.35

0.3 Vgs = –1

Pld_trap1 0.25
Vgs = –1.5
0.2

0.15 Vgs = –2

0.1
Vgs = –2.5
0.05
Vgs = –3
0 Vgs = –3.5

–0.05
0 10 20 30 40 50 60 70 80 90
Vds
(a)

0.55
Vgs = 1
ADS
0.5
Vgs = 0.5
0.45
Vgs = 0
0.4
Vgs = –0.5
0.35

0.3 Vgs = –1
Pld_trap1

0.25
Vgs = –1.5
0.2

0.15 Vgs = –2

0.1
Vgs = –2.5
0.05
Vgs = –3
0 Vgs = –3.5

–0.05
0 10 20 30 40 50 60 70 80 90
Vds
(b)

Figure 12. The transient simulation of the output characteristics of a GaN FET model with (a) no trapping effects and (b)
with gate- and drain-lag trapping effects turned on. (Image courtesy of Wolfspeed.)

•• a charge-conservative state function construction
•• continuous and infinitely differentiable functions
•• a dynamic electrothermal model, with adjustable
time constants
•• charge-trapping models for gate lag and drain lag,
with adjustable time constants
••the ability to address video and microwave fre-
quencies independently
•• the ability to operate consistently in all simula-
tion modes, e.g., dc, ac (S parameter), harmonic
balance, transient, and envelope
•• device size scaling for MMIC design.
The model structure is shown schematically in Fig-
ure 14. It comprises a nonlinear intrinsic core embedded in
a passive network of the extrinsic model components. The
nonlinear core is described by current- and charge-state

94 November/December 2018
functions for the gate and drain;
these basic state functions are 0.28
ADS
augmented by dynamical mod- 0.26
els for thermal and trapping 0.24
memory effects. 0.22
0.20
Doing the Measurements

ts (I_Drainlntr.i)
0.18
and Determining the 0.16

ld_PIV
Model Parameters 0.14
The nonlinear core is the heart 0.12
of the model, and measure- 0.10
ments need to be made to allow 0.08
the extraction of the current 0.06
and charge model parameters. 0.04
For the form of the model des­­ 0.02
cribed previously, we would 0.00
perform 1) measurements of –0.02
the I-V characteristics to enable 0 10 20 30 40 50 60 70 80 90
ts (Vds_lntr)
the identification of the current
Vds_PIV
state function parameters and
2) bias-dependent S-parameter
measurements from which the Figure 13. A simulation of the GaN FET model under high-power drive showing
charge state function param- the time-domain dynamic load line I-V trajectory superimposed on the output I-V
eters are estimated after con- characteristics obtained from transient simulation, indicating drain-lag effects.
servative integration of the (Image courtesy of Wolfspeed.)
capacitances.
Typically, we use pulsed
techniques for both I-V and
Manifold Extrinsic Shell Intrinsic Model Manifold
S-parameter measurements.
This is chiefly to prevent the Gate Drain
transistor from heating up dur-
ing the measurement. Very Qg Ig Id Qd
short pulses on the order of 1 µs Source
are used, and the measured
currents are constant across the
measurement window dura- Trapping Model
tion, indicating no appreciable Gain Thermal Model
thermal effects. An example Rfill
of a state-of-the-art pulsed I-V Gain Σ
Vds Vgs_intr
and S-parameter measure- Pdiss Rth Cth
Rempty Vgs
ment system is shown in Fig-
ure 15, courtesy of AMCAD and
Maury Microwave. Normally, Figure 14. A schematic of a power transistor nonlinear model architecture, showing
we would mea­­sure on wafer, input/output manifolds, extrinsic component shell, nonlinear core with I and Q state
using a temperature-control­ functions, and thermal and trapping models. (Image courtesy of Wolfspeed.)
led chuck. By measuring the
pulsed I-V characteristics over a range of chuck tem- a nonlinear vector network analyzer (NVNA), capturing
peratures, we can also estimate the thermal resistance the large-signal behavior over much of the I-V and Q-V
of the transistor. operating space, making this a truly large-signal model.
The recently announced DynaFET model [41] in­­clu­des At the moment, the model is available only in Keysight
many of the desirable features for a GaN power FET ADS, and the characterization and model parameter
model mentioned in this article: it uses current and extraction (ANN training) is available in Keysight IC-
charge as the state functions, is charge conservative, and CAP. This model is very promising for product model
uses continuously differentiable functions (artificial neu- applications. However, device scaling is not so straight-
ral networks, ANNs) for the nonlinear state functions. forward, because the ANNs do not have physically mean-
It also includes electrothermal and trapping dynamics. ingful parameters and one will still need to develop the
The characterization of the transistor is carried out using extrinsic parameter model for the MMIC process.

November/December 2018 95

Figure 15. The AMCAD 3200 pulsed I-V system and
Keysight PNAX for carrying out pulsed I-V/S-parameter
characterization. It is shown here with a connectorized
device; for model estimation, the system would be used on a
wafer-probe station. (Image courtesy of Maury Microwave.)
The trapping model dynamics can be determined
from pulse-profile measurements. The device is pulsed
into conditions to fill the traps; then, when the pulse
bias is changed or removed, the transient response of
the drain current is used to identify the time constants
of the traps.
For gate lag, the bias conditions are
•• quiescent gate voltage Vgs Q < Vth
•• quiescent drain voltage VdsQ = V bias
•• pulsed gate voltage Vgs = 0 V
•• pulsed drain voltage Vds Q = Vds Q,
where V bias is the nominal drain bias for the transistor
in a PA. For drain lag, the bias conditions are
•• quiescent gate voltage Vgs Q > Vth
•• quiescent drain voltage Vds Q >> V bias
•• pulsed gate voltage Vgs = VgsQ
•• pulsed drain voltage Vds << V bias .
The pulse-filling and -emptying biases are sometimes
arranged using a double-pulse method, but the transient
time-domain measurements can be made using a suit-
ably arranged single pulse and measurement window.
As mentioned previously, the extrinsic shell accounts
for much of the detailed scaling factors in MMIC design.
The extrinsic parameters are usually found from broad-
band S-parameter measurements made under cold FET
conditions, where Vds is set to zero [39], [40]. This per-
mits the extrinsic capacitance, inductance, and resistance
parameters to be found and the scaling rules for the
given transistor technology to be determined. Manifold
structures are included specifically to model the large
bond-pad structures found in power transistors. These
are usually modeled using an electromagnetic simula-
tor as multiport S-parameter blocks; these describe the
bond-wire connections and the feeds to the individual
transistor gates and drains in the device. This model
96 November/December 2018
parameter extraction process can be described by the
flowchart shown in Figure 16.
The measurements for model validation include
I-V characterization, broadband S parameters under
active bias conditions, and large-signal measurements
such as single-tone and two-tone power drive-up and
load and source pull, often with harmonic tuning.
These large-signal measurements are usually perfor­
med using a VNA- or NVNA-based load-pull station,
and they are frequently done using pulsed measure-
ments to minimize both the average RF power that
needs to be generated and dissipated and the self-
heating of the device, which may be on wafer and,
therefore, not in an optimal heatsink configuration.
More comprehensive validation of the compact model
will include the design and measurement of a discrete
or MMIC PA such as a Doherty amplifier for micro-
wave or millimeter-wave frequency application and
the testing thereof.
The predominant modeling environment currently
is Verilog-A. This is a well-documented language
that is portable between the common EDA design
tools, making model development and deployment
easier. Historically, compact models were written in
C code and tightly coupled to the numerical proce-
dures built into the simulator. One of the drawbacks
was that the partial derivatives of all parameters to
the node voltages had to be coded by hand, a tedious
and error-prone task. Decoupling the model from the
simulator allowed the use of symbolic derivatives, mak-
ing the model compilation easier. This was enabled by
the development of hardware description languages
such as VHDL and Verilog. The analog subset of Ver-
ilog is now the de facto standard environment for
transportable compact model development. A signifi-
cant amount of best-practice documentation is avail-
able for Verilog-A in terms of model development;
see, for example, [28] and the references therein.
Some Concluding Remarks
Behavioral models for FETs, in general, and for GaN
FET/HEMT power transistors are still the mainstream
modeling approach: they are compact, portable, and
easy to use. The physics-based models such as ASM
appear to be quite interesting, potentially benefitting
both circuit design and the device engineer and pos-
sibly providing a bridge between these two domains.
The characterization of the transistor is now very
sophisticated, with NVNA and very-short-duration
pulsed measurements becoming more commonplace.
The environment for model development is also more
sophisticated, with MathWorks’ MATLAB for parame-
ter identification and Verilog-A for model development
and deployment, using advanced mathematical algo-
rithms and symbolic approaches, becoming standard
practice. Simulation speed, accuracy, and convergence,
however, are still the primary goals.
 Pulsed IV/
dc IV
S-Parameters

Thermal Model Gate,

Drain Lag,
Trapping
Models

Manifold Model
EM Simulation
Deembedding

Broadband Extrinsic
Network
S-Parameters, Deembedding
Cold FET

Bias-Dependent
Small-Signal Model
G Cgd Rgd D

Cgs Rds
Rgs gm, τ Cds
S S

dVgsdvds

Intrinsic Large-Signal Model

Qg Ig Id Qd

Figure 16. The model parameter extraction flowchart with the thermal and trapping model definitions, extrinsic parameter
extraction using cold FET, manifold modeling by electromagnetic (EM) simulation, and integration of the Y parameters defining
the bias-dependent small-signal model to obtain the current- and charge-state variables. (Used with permission from [13].)

References modulation applications,” in Proc. 3rd European Microwave Integrated

[1] P. J. Zampardi and F. Kharabi, “Industrial view of III-V devices
compact modeling for circuit design,” IEEE Trans. Electron Devices,
to be published. in Jan. 2019.
[2] M. Rudolph, Introduction to Modeling HBTs. Norwood, MA: Artech
House, 2006.
[3] G. H. Loechelt and P. A. Blakey, “A computational load-pull system
for evaluating RF and microwave power amplifier technologies,”
in Proc. IEEE MTT-S Int. Microwave Symp. Dig., Boston, MA, June
2000, pp. 465–468.
[4] O. Bengtsson, L. Vestling, and J. Olsson, “A computational load-pull
method for TCAD optimization of RF-power transistors in bias-
Circuits Conf., Amsterdam, The Netherlands, Oct. 2008, pp. 222–225.
[5] C. M. Snowden and R. R. Pantoja, “Quasi-two-dimensional MES-
FET simulations for CAD,” IEEE Trans. Electron Devices, vol. 36, no.
9, pp. 1564–1574, Sept. 1989.
[6] R. R. Pantoja, M. J. Howes, J. R. Richardson, and C. M. Snowden, “A
large-signal physical MESFET model for computer-aided ­design
and its applications,” IEEE Trans. Microw. Theory Techn., vol. 37, no.
12, pp. 2039–2045, Dec. 1989.
[7] R. Drury and C. M. Snowden, “A quasi-two-dimensional HEMT
model for microwave CAD applications,” IEEE Trans. Electron De-
vices, vol. 42, no. 6, pp. 1026–1032, June 1995.

November/December 2018 97
 [8] C. G. Morton, J. S. Atherton, C. M. Snowden, R. D. Pollard, and
M. J. Howes, “A large-signal physical HEMT model,” in Proc. IEEE
MTT-S Int. Microwave Symp. Dig., San Francisco, CA, June 1996, pp.
1759–1762.
[9] U. Radhakrishna, L. W. D.-S. Lee, T. Palacios, and D. Antoniadis,
“Physics-based GaN HEMT transport and charge model: experi-
mental verification and performance projection,” in Proc. Inter-
national Electron Devices Meeting (IEDM), San Francisco, CA, Dec.
2012, pp. 13.6.1–13.6.4.
[10] S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, and T. A.
Fjeldly, “Surface-potential-based RF large signal model for gal-
lium nitride HEMTs,” in Proc. Compound Semiconductor IC Confer-
ence, New Orleans, LA, Oct. 2015.
[11] S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, “Analytical mod-
eling of surface-potential and intrinsic charges in AlGaN/GaN
HEMT devices,” IEEE Trans. Electron Devices, vol. 59, no. 10, pp.
2856–2860, Oct. 2012.
[12] D. E. Root, “Charge modeling and conservation laws,” in Proc. Asia-
Pacific Microwave Conf. Workshop WS2, Sydney, Australia, June 1999.
[13] J. Wood, “RF PA digital pre-distortion and behavioral modeling,”
Obsidian Microwave, LLC, Durham, NC, Short Course Notes, 2017.
[14] D. E. Root and B. Hughes, “Principles of nonlinear active device mod-
eling,” in Proc. 32nd ARFTG Conf. Dig., Tempe, AZ, Dec. 1988, pp. 1–24.
[15] A. D. Snider, “Charge conservation and the transcapacitance ele-
ment: An exposition,” IEEE Trans. Edu., vol. 38, no. 4, pp. 376–379,
Nov. 1995.
[16] J. Wood, “Conservatively speaking,” IEEE Microw. Mag., vol. 15,
no. 7, pp. 110–115, Dec. 2014.
[17] R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W.
L. Pribble, “A review of GaN on SiC high electron mobility power
transistors and MMICs,” IEEE Trans. Microw. Theory Techn., vol. 60,
no. 6, pp. 1764–1783, June 2012.
[18] A. Katz, private communication, 2017.
[19] W. R. Curtice, “A MESFET model for use in the design of GaAs
integrated circuits,” IEEE Trans. Microw. Theory Techn., vol. 28, no.
5, pp. 448–456, May 1980.
[20] W. R. Curtice and M. Ettenberg, “A nonlinear GaAs FET model
for use in the design of output circuits for power amplifiers,” IEEE
Trans. Microw. Theory Techn., vol. 33, no. 12, pp. 1383–1394, Dec. 1985.
[21] H. Statz, P. Newman, I. W. Smith, R. A. Pucel, and H. A. Haus,
“GaAs FET device and circuit simulation in SPICE,” IEEE Trans.
Electron Devices, vol. 34, no. 2, pp. 160–168, Feb. 1987.
[22] I. Angelov, H. Zirath, and N. Rosman, “A new empirical nonlin-
ear model for HEMT and MESFET devices,” IEEE Trans. Microw.
Theory Techn., vol. 40, no. 12, pp. 2258–2266, Dec. 1992.
[23] J. Staudinger, M. C. de Baca, and R. Vaitkus, “An examination
of several large-signal capacitance models to predict GaAs HEMT
linear power amplifier performance,” in Proc. IEEE Radio and
Wireless Conf. (RAWCON), Colorado Springs, CO, Aug. 1998, pp.
343–346.
[24] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS
transistor capacitances,” IEEE J. Solid-State Circuits, vol. 13, no. 5,
pp. 703–707, Oct. 1978.
[25] P. Aaen, J. Plá, and J. Wood, Modeling and Characterization of RF and
Microwave Power FETs. Cambridge, UK: Cambridge Univ. Press, 2007.
[26] C. C. McAndrew, H. K. Gummel, and K. Singhal, “A compari-
son and evaluation of state-of-the-art compact MOSFET models,”
98 November/December 2018
AT&T Bell Laboratories, Murray Hill, NJ, Technical Memorandum,
52864-910119-01TM, Jan. 1991.
[27] A. E. Parker, “Getting to the heart of the matter: Considerations
for large-signal modeling of microwave field-effect transistors,”
IEEE Microw. Mag., vol. 16, no. 3, pp. 76–86, May 2015.
[28] C. C. McAndrew, et al. “Best practices for compact modeling in
Verilog-A,” IEEE J. Electron Devices Soc., vol. 3, no. 5, pp. 383–396,
Sept. 2015.
[29] W. R. Curtice, J. A. Plá, D. Bridges, T. Liang, and E. E. Shumate, “A
new dynamic electro-thermal nonlinear model for silicon RF LD-
MOS FETs,” in Proc. IEEE MTT-S Int. Microwave Symp. Dig., Ana-
heim, CA, June 1999, pp. 419–422.
[30] J. Wood, et al. “A nonlinear electro-thermal scalable model for
high-power RF LDMOS transistors,” IEEE Trans. Microw. Theory
Techn., vol. 57, no. 2, pp. 282–292, June 2009.
[31] C. Fager, J. C. Pedro, N. B. de Carvalho, and H. Zirath, “Predic-
tion of IMD in LDMOS transistor amplifiers using a new large-
signal model,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 12, pp.
2834–2842, Dec. 2002.
[32] P. M. Cabral, J. C. Pedro, and N. B. Carvalho, “Nonlinear device
model of microwave power GaN HEMTs for high power ampli-
fier design,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 11, pp.
2585–2592, Nov. 2004.
[33] A. E. Parker and J. G. Rathmell, “Broadband characterization of
FET self-heating,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 7,
pp. 2424–2429, July 2005.
[34] J. G. Rathmell and A. E. Parker, “Circuit implementation of a theo-
retical model of trap centres in GaAs and GaN devices,” Proc. Int.
Society for Optical Engineering, vol. 6798, pp. 980R1, 2007.
[35] J. Tarazi, J. G. Rathmell, A. E. Parker, and S. J. Mahon, “Extraction
of trapping model over an extended bias range for GaN and GaAs
HEMTs,” in Proc. IEEE MTT-S Int. Microwave Symp. Dig., Honolulu,
HI, June 2017, pp. 1–4.
[36] O. Jardel, et al. “An electrothermal model for AlGaN/GaN power
HEMTs including trapping effects to improve large-signal simula-
tion results on high VSWR,” IEEE Trans. Microw. Theory Techn., vol.
55, no. 12, pp. 2660–2669, Dec. 2007.
[37] L. C. Nunes, J. M. Gomes, P. M. Cabral, and J. C. Pedro, “A new
nonlinear model extraction methodology for GaN HEMTs subject
to trapping effects,” in Proc. IEEE MTT-S Int. Microwave Symp. Dig.,
Phoenix, AZ, 2015, pp. 1–3.
[38] A. Benvegnu, O. Jardel et al., “Non-linear electro-thermal AlGaN/
GaN model including large-signal dynamic thermal-­trapping ef-
fects,” in Proc. IEEE MTT-S Int. Microwave Symp. Dig., San Fran-
cisco, CA, 2016, pp. 1–4.
[39] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new meth-
od for determining the FET small-signal equivalent circuit,” IEEE
Trans. Microw. Theory Techn., vol. 36, no. 7, pp. 1151–1159, July 1988.
[40] J. Wood and D. E. Root, “Bias-dependent linear scalable millime-
ter-wave FET model,” IEEE Trans. Microw. Theory Techn., vol. 48, no.
12, pp. 2352–2360, Dec. 2000.
[41] J. J. Xu, R. Jones, S. A. Harris, T. Nielsen, and D. E. Root, “Dynam-
ic FET model DynaFET for GaN transistors from NVNA active
source injection measurements,” in Proc. IEEE MTT-S Int. Micro-
wave Symp. Dig., Tampa, FL, June 2014, pp. 1–3.