PD - 97074A

IRFI4019H-117P
DIGITAL AUDIO MOSFET

Features Key Parameters h

Ÿ Integrated Half-Bridge Package VDS 150 V
Ÿ Reduces the Part Count by Half RDS(ON) typ. @ 10V 80 m:
Ÿ Facilitates Better PCB Layout Qg typ. 13 nC
Ÿ Key Parameters Optimized for Class-D Qsw typ. 4.1 nC
Audio Amplifier Applications
RG(int) typ. 2.5 Ω
Ÿ Low RDS(ON) for Improved Efficiency
TJ max 150 °C
Ÿ Low Qg and Qsw for Better THD and
Improved Efficiency
Ÿ Low Qrr for Better THD and Lower EMI
Ÿ Can Delivery up to 200W per Channel into
8Ω Load in Half-Bridge Configuration
Amplifier G1
D1

S1/D2

Ÿ Lead-Free Package S2
G2

TO-220 Full-Pak 5 PIN

G1, G2 D1, D2 S1, S2
Description Gate Drain Source
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It
consists of two power MosFET switches connected in half-bridge configuration. The latest process is used
to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery, and
internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such
as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable
device for Class D audio amplifier applications.
Absolute Maximum Ratings h
Parameter Max. Units
VDS Drain-to-Source Voltage 150 V
VGS Gate-to-Source Voltage ±20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 8.7 A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 6.2
IDM Pulsed Drain Current c 34
EAS Single Pulse Avalanche Energyd 77 mJ
PD @TC = 25°C Power Dissipation f 18 W
PD @TC = 100°C Power Dissipation f 7.2
Linear Derating Factor 0.15 W/°C
TJ Operating Junction and -55 to + 150 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)

Thermal Resistance h
Parameter Typ. Max. Units
RθJC Junction-to-Case f ––– 6.9
RθJA Junction-to-Ambient f ––– 65
Notes  through † are on page 2
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IRFI4019H-117P
Electrical Characteristics @ TJ = 25°C (unless otherwise specified) h
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 80 95 mΩ VGS = 10V, ID = 5.2A e
VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V VDS = VGS, ID = 50µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 150V, VGS = 0V
––– ––– 250 VDS = 150V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 11 ––– ––– S VDS = 50V, ID = 5.2A
Qg Total Gate Charge ––– 13 20
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.3 ––– VDS = 75V
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– nC VGS = 10V
Qgd Gate-to-Drain Charge ––– 3.9 ––– ID = 5.2A
Qgodr Gate Charge Overdrive ––– 5.0 ––– See Fig. 6 and 19
Qsw Switch Charge (Qgs2 + Qgd) ––– 4.1 –––
RG(int) Internal Gate Resistance ––– 2.5 ––– Ω
td(on) Turn-On Delay Time ––– 7.0 ––– VDD = 75V, VGS = 10Ve
tr Rise Time ––– 6.6 ––– ID = 5.2A
td(off) Turn-Off Delay Time ––– 13 ––– ns RG = 2.4Ω
tf Fall Time ––– 3.1 –––
Ciss Input Capacitance ––– 810 ––– VGS = 0V
Coss Output Capacitance ––– 100 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 15 ––– ƒ = 1.0MHz, See Fig.5
Coss Effective Output Capacitance ––– 97 ––– VGS = 0V, VDS = 0V to 120V
LD Internal Drain Inductance ––– 4.5 ––– Between lead, D

nH 6mm (0.25in.)
G
LS Internal Source Inductance ––– 7.5 ––– from package
S
and center of die contact

Diode Characteristics h
Parameter Min. Typ. Max. Units Conditions
IS @ TC = 25°C Continuous Source Current ––– ––– 8.7 MOSFET symbol
(Body Diode) A showing the
ISM Pulsed Source Current ––– ––– 34 integral reverse
(Body Diode)c p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 5.2A, VGS = 0V e
trr Reverse Recovery Time ––– 57 86 ns TJ = 25°C, IF = 5.2A
Qrr Reverse Recovery Charge ––– 140 210 nC di/dt = 100A/µs e

Notes: „ Rθ is measured at TJ of approximately 90°C.

 Repetitive rating; pulse width limited by max. junction temperature. … Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
‚ Starting TJ = 25°C, L = 5.8mH, RG = 25Ω, IAS = 5.2A. avalanche information
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. † Specifications refer to single MosFET.
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 IRFI4019H-117P
100 100
VGS VGS
TOP 15V TOP 15V
12V 12V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

10V 10V
9.0V 9.0V
10 8.0V 8.0V
7.0V 7.0V
6.0V 10 6.0V
BOTTOM 5.5V BOTTOM 5.5V

1
5.5V

5.5V 1
0.1

≤ 60µs PULSE WIDTH ≤ 60µs PULSE WIDTH

Tj = 25°C Tj = 150°C
0.01 0.1
0.1 1 10 100 0.1 1 10 100

VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 2.5
ID = 5.2A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current(Α)

2.0

10 TJ = 175°C (Normalized)
1.5

1.0
1 TJ = 25°C

0.5
VDS = 50V
≤ 60µs PULSE WIDTH
0.1
0.0
4 5 6 7 8
-60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
TJ, Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 20
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED ID= 5.2A
VDS = 120V
VGS, Gate-to-Source Voltage (V)

Crss = Cgd
10000 16 VDS= 75V
Coss = Cds + Cgd
VDS= 30V
C, Capacitance (pF)

1000 Ciss 12

100
Coss 8

Crss
10 4

0
1
1 10 100 1000
0 5 10 15 20
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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 IRFI4019H-117P
100 100
OPERATION IN THIS AREA
LIMITED BY R DS (on)

ID, Drain-to-Source Current (A)

ISD , Reverse Drain Current (A)

1msec 100µsec
10 10
TJ = 150°C

DC
10msec
1 1
TJ = 25°C

Tc = 25°C
Tj = 150°C
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 1 10 100 1000
VSD , Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

10 5.0

VGS(th) Gate threshold Voltage (V)

8
ID , Drain Current (A)

4.0
ID = 50µA
6

4
3.0

0 2.0
25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150

TJ , Junction Temperature (°C) TJ , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature

10

D = 0.50

0.20
Thermal Response ( Z thJC )

1
0.10
0.05

0.02 R1
R1
R2
R2
R3
R3 Ri (°C/W) τι (sec)
0.1
0.01 τJ τC
τJ
τ1
τ 1.508254 0.000814
τ2 τ3
τ1 τ2 τ3
2.154008 0.111589
Ci= τi/Ri
Ci= τi/Ri 3.237738 2.2891
0.01

SINGLE PULSE Notes:

( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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 IRFI4019H-117P
0.5 350
RDS (on), Drain-to -Source On Resistance (Ω)

EAS, Single Pulse Avalanche Energy (mJ)

ID = 5.2A ID
300 TOP 0.91A
0.4 1.1A
BOTTOM 5.2A
250

0.3
200

0.2 150

TJ = 125°C 100
0.1
TJ = 25°C 50

0.0
0
4 5 6 7 8 9 10
25 50 75 100 125 150
VGS, Gate-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)

Fig 12. On-Resistance Vs. Gate Voltage Fig 13. Maximum Avalanche Energy Vs. Drain Current

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+
***
VGS=10V
ƒ Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD
*
RG • dv/dt controlled by RG VDD Re-Applied
+
• Driver same type as D.U.T. ** Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* Use P-Channel Driver for P-Channel Measurements *** VGS = 5V for Logic Level Devices
** Reverse Polarity for P-Channel

Fig 14. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

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IRFI4019H-117P

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 15a. Unclamped Inductive Test Circuit Fig 15b. Unclamped Inductive Waveforms

RD
VDS VDS
90%
VGS
D.U.T.
RG
+
-VDD
10%
10V VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 % td(on) tr td(off) tf

Fig 16a. Switching Time Test Circuit Fig 16b. Switching Time Waveforms

Id
Vds

Vgs

L
VCC
DUT
0
Vgs(th)
1K
S
20K

Qgs1 Qgs2 Qgd Qgodr

Fig 17a. Gate Charge Test Circuit Fig 17b Gate Charge Waveform

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 IRFI4019H-117P
TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))

TO-220 Full-Pak 5-Pin Part Marking Information

25

TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/06
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