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Chapter 3
KEY GENERATION USING ESPRESSO ALGORITHM
3.1. Introduction
networks. Even if they are, the requirements for energy efficiency will also be
increasing as they might need to be implemented in mobile devices with limited,
internal power sources. The new stream cipher Espresso has been proposed to solve
many of these issues, however not much work has been done to see if Espresso can
deliver. More in depth testing needs to be carried out in order to determine its
viability as a new standard. For Espresso to be considered as a new standard, it is
relevant to make fair comparisons against the Industry standard AES. This has been
done to some extent, but need to be evaluated further [1].
All remaining feedback functions of G are of type gi(x) = x i+1. The output function
z(x) is specified as follows:
z(x) = x80 ⊕ x99 ⊕ x137 ⊕ x227 ⊕ x222 ⊕ x187 ⊕ x243x217 ⊕ x247x231 ⊕ x213x235 ⊕
x255x251 ⊕ x181x239 ⊕ x174x44 ⊕ x164x29 ⊕ x255x247x243x213x181x174
In order to reduce the propagation delay of the circuit implementing the output
function z(x), we can pipeline it as follows:
256 255 . . . . . . . . . . . . 4 3 2 1
The cipher Espresso is initialized as follows. Let ki denote the bits of the key
k, 0 ≤ i ≤ 127, and IVi denote the bits of the initialization value IV, 0 ≤ i ≤ 95. The key
and IV bits are loaded into the shift register as follows:
xi = ki , 0 ≤ i ≤ 127
xi = IVi−128 , 128 ≤ i ≤ 223
xi = 1 , 224 ≤ i ≤ 254
xi = 0 , i = 255
The initialization phase consists of clocking the cipher 256 times; XORing the
produced output bit with the stages x255 and x217. Thus, in this phase the feedback
functions g255(x) and g217(x) of the NLFSR G are given by
Department of ECE, Dr. AIT, Bengaluru-560056 Page 17
Espresso: A Stream Cipher for 5G Wireless Communication Systems and its Application 2017-18
in Image Encryption and Decryption
After initialization, the cipher is clocked for three more cycles and then the
key stream is produced.
Table 3.2 shows the Design Statics of the generated sequence using espresso
algorithm. It gives the count of cell usage for the corresponding components.
Components Quantity
# Input Outputs 3
Cell Usage :
# BELS 8
# Clock Buffers 1
# Input Buffer 1
# Output Buffer 1
NOTE: These timing numbers are only a synthesis estimate. For accurate timing
information refer to the trace report generated after place- and- route
clk BUFGP
rst IBUF
Timing Summary:
Speed Grade -3
Timing Detail:
Source Out_213
Destination Out_0
Table 3.5: Timing Report of Gate Delay and Net Delay of Data Path Out_213 to
Out_0
Data Path Out_213 to out_0
FDC D -0.024
Table 3.7: Timing Report of Gate Delay and Net Delay of Data Path Out_1 ren to
Out_1
OBUF 1.939