Department of Computer Science Engineering

LAB MANUAL
SUBJECT: DIGITAL ELECTRONICS LAB [ECP-156]

B.E I Year – I Semester

(Branch: CSE)

Chandigarh University
Gharuan, Mohali
 Table of Contents

SR. Topic Page No. Date

NO.
1. Truth table verification of OR, AND, NOT, 3-4
XOR, NAND and NOR gates.

2. Realization of OR, AND, NOT and XOR 5-7

functions using universal gates.

3. (a) To design and verify the truth table of 8-9

Half Adder using gates.
(b) To design and verify the truth table of
Full Adder using gates.

4. (a) To design and verify the truth table of 10-11

Half Subtractor using gates.
(b) To design and verify the truth table of
Full Subtractor using gates.
5. To design and implement the 4:1 12-14
Multiplexer using gates.

6. To design and implement the 1:4 15-17

Demultiplexer using gates.
7. To design and implement the Binary Code 18-21
to BCD converter.
8. To design and implement the 2-bit 22-26
Magnitude Comparator.
9 (a) To verify the truth tables of Flip Flops 27-28
7476 (J-K) and 7474 (D)
(b) To design and implement the S-R flip
flop using NAND / NOR gates.
10. To design and implement the Shift Register 29-32
using D Flip Flops, for various modes:
SISO, SIPO, PISO, PIPO.
11. To design and implement the 4-bit
Asynchronous Counters using J-K Flip
Flops.
 EXPERIMENT NO 1

AIM: Truth table verification of OR, AND, NOT, XOR, NAND and NOR gates

APPARATUS: Logic Trainer Kit, Connecting wires

THEORY: Digital circuits have two state operations. In two state operations all signals are either
low(0) or high(1). Logic gate is a digital circuit with one or more input voltages, but only one
output voltage. It works according to some logical relationships between input & output voltages.
The relation between possible values of input and output voltage is expressed in the form of table,
is called truth table.
NOT Gate: NOT gate has only one input and one output. Output is complement (reverse) of
input. IC for NOT gate is 7404.

OR Gate: OR gate perform a logical addition. If any or all inputs are high, output is high. The IC
used for OR gate ( 7432).

NOR Gate: Combination of NOT gate and OR gate is NOR. All inputs must be low to get a high
output. If any of input is high, output is low. IC used is 7402.

AND Gate: AND gate performs logical multiplication. Output is high only when all the inputs are
high.

NAND Gate: It is combination of AND and NOT gate. All the inputs must be high to get a low
output.

X-OR Gate: The exclusive- OR gate has a high output only when odd number of inputs are high
or all inputs are different, when both inputs are low and high, output is high.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip
package).
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.
3 Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according to truth table.
5. Note down the output readings for half/full adder and sum and the carry bit for different
combinations
of inputs in following Tables where S & V indicating logic value of the output. And fill your result
in
S (V) and C (V) in voltage. Where 5V indicating logic 1 and 0V indicating logic 0.

RESULT :
Truth table of gates and implementation has been verified.

PRECAUTIONS :
1. Connections should be proper & tight.
2. Check the connections checked before switching on kit.
 EXPERIMENT NO 2

AIM: Realization of OR, AND, NOT and XOR functions using universal gates.

APPARATUS: Logic Trainer Kit, Connecting wires

THEORY: Digital circuits have two state operations. In two state operations all signals are either
low(0) or high(1). Logic gate is a digital circuit with one or more input voltages, but only one
output voltage. It works according to some logical relationships between input & output voltages.
The relation between possible values of input and output voltage is expressed in the form of table,
is called truth table.

Designing using UNIVERSAL GATES:

NAND GATE AS A UNIVERSAL GATE :

To prove that any Boolean function can be implemented using only NAND gates, we will show
that the AND, OR, and NOT operations can be performed using only these gates.

oIMPLEMENTING INVERTER USING NAND GATE :

The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).
1. All NAND input pins connect to the input signal A gives an output A’.
2. One NAND input pin is connected to the input signal A while all other input pins are
connected to logic 1. The output will be A’.

IMPLEMENTING AND USING NAND GATE :

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced
by a NAND gate with its output complemented by a NAND gate inverter).
IMPLEMENTING OR USING NAND GATE :
An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced
by a NAND gate with all its inputs complemented by NAND gate inverters).

NOR GATE AS A UNIVERSAL GATE:

To prove that any Boolean function can be implemented using only NOR gates, we will show that
the AND,OR, and NOT operations can be performed using only these gates.

o IMPLEMENTING INVERTER USING NOR GATE :

The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).
All NOR input pins connect to the input signal A gives an output A’.
One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A’.

o IMPLEMENTING OR USING NOR GATE :

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by

a NOR gate with its output complemented by a NOR gate inverter)

IMPLEMENTING AND USING NOR GATE :
An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is

replaced by a NOR gate with all its inputs complemented by NOR gate inverters)

CIRCUIT DIAGRAM:
PROCEDURE:
1. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip
package).
2. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.
3 Make the connections as per the circuit diagram.
4. Switch on VCC and apply various combinations of input according to truth table.
5. Note down the output readings for half/full adder and sum and the carry bit for different
combinations
of inputs in following Tables where S & V indicating logic value of the output. And fill your result
in
S (V) and C (V) in voltage. Where 5V indicating logic 1 and 0V indicating logic 0.

RESULT :
Truth table of gates and implementation has been verified.

PRECAUTIONS :
3. Connections should be proper & tight.
4. Check the connections checked before switching on kit.
 EXPERIMENT NO 3

AIM: a) To design and verify the truth table of Half Adder using gates.
(b) To design and verify the truth table of Full Adder using gates.

APPARATUS USED :
Trainer kit , 7486,7432,7408,Connecting Wires.

THEORY :

Half Adder : A logic used for the addition of two one bit signals is known as a half
adder

Full Adder : A half adder has only 2 input terminals and there is no provision to add
a carry coming from the lower order bits when binary numbers are added. For this
purpose a third input terminal is added and this circuit is used to add An,Bn& Cn-1
where An & Bn are the nth order bits of the numbers.

CIRCUIT DIAGRAM:
PROCEDURE:

For Half Adder:

1. Connect the circuit as shown in fig.1 using patch cords i.e. connect A & B
inputs to logic inputs. Also connect SUM (S) and CARRY (C) outputs to
output indicators.
2. For different combinations of ‘A’ and ‘B’ inputs verify the truth table shown.
For Full Adder:
1. Connect the circuit as shown in fig. 2 using patch cords i.e. An, Bn & Cn-1
inputs to logic inputs. Also connect SUM (S) and CARRY (C) outputs to
output indicators.
2. For different combinations of An, Bn & Cn-1 inputs verify the truth table as
shown in fig.2.
OBSERVATIONS :
Truth Table for Half Adder and Full Adder are as shown
RESULT: The truth tables for half and full adder have been verified.

PRECAUTIONS:
1. Check the connections before switching On the kit.
2. Connections should be done properly.
3. Observations should be taken properly.
 EXPERIMENT NO 4

AIM: (a) To design and verify the truth table of Half Subtractor using gates.
(b) To design and verify the truth table of Full Subtractor using gates.

APPARATUS USED:
Trainer kit, 7486,7408,7432,7404 & Connecting Wires

THEORY:

SUBTRACTION:

In a similar fashion subtraction can be performed using binary numbers. The truth
table for a single bit or half-subtractor with inputs A and B is given below along with
its circuit diagram (Fig.1). A full subtractor circuit accepts a minuend (A) and the
subtrahend (B) and a borrow (BIN) as inputs from a previous circuit. A full subtractor
circuit can be realized by combining two half subtractor circuits and an OR gate as
shown in (Fig.2).

CIRCUIT DIAGRAM:

Fig. 1: Schematics for half subtractor circuit

Fig. 2: Schematics for full subtractor circuit

PROCEDURE:

For Half Subtractor:

A. Connect the circuit as shown in fig.1 using patch cords i.e. connect A &
B inputs to logic inputs. Also connect DIFFERENCE (Q) and
BORROW (Bin) outputs to output indicators.
B. For different combinations of ‘A’ and ‘B’ inputs verify the truth table
shown below.
For Full Subtractor:
A. Connect the circuit as shown in fig. 2 using patch cords i.e. Bn-1, A &
B inputs to logic inputs. Also connect DIFFERENCE (Q) and
BORROW (Bn) outputs to output indicators.
B. For different combinations of Bn-1, A & B inputs verify the truth table
as shown below.

OBSERVATIONS:
Truth Table for Half Subtractor and Full Subtractor are as shown

1-bit Subtractor with Borrow

A B Q BI
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
1-bit Full Subtractor with BN-1& BN

BN-1 A B Q BN
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
RESULT: The truth tables for half and full Subtractor have been verified.

PRECAUTIONS:
1. Check the connections before switching on the kit.
2. Connections should be done properly.
3. Observations should be taken properly.
 EXPERIMENT NO 5

AIM: To design and implement the 4:1 Multiplexer using gates.

APPARATUS USED:
  Mini Digital Training and Digital Electronic Sets. 
 IC 7404, IC 7408, IC 7432, IC 74153 & connecting wires. 

THEORY:

MULTIPLEXER: - A multiplexer (MUX) is a many to one device. It allows input

from many different sources to be transmitted to a common destination. The
destination to which a particular source connects depends on the select/ control lines.
Thus MUX is a device that accepts data from one of many input sources for
transmission over a common shared line. To achieve this MUX has several data lines
and a single output along with data-select inputs, which permit digital data on any of
the inputs to be switched to the output line. The logic symbol for a 1- to-4 data
selector/multiplexer is shown in Figure below.

Fig. IC of MUX
PROCEDURE:-

1. Connections are made as per circuit diagram.

2. Also connect Vcc and Ground then performed experiment.

OBSERVATION:-

The truth table for a Multiplexer:-

The logic equation for the output can be written as:

Output= I0.S1'.S0' + I1.S1'.S0 + I2.S1.S0' + I3.S1.S0

RESULT: The truth table for 4:1 Multiplexer has been verified.

PRECAUTIONS:
a. All ICs should be checked before starting the experiment.
b. All the connection should be tight.
c. Always connect ground first and then connect Vcc.
d. Suitable type wire should be used for different types of circuit.
e. The kit should be off before change the connections.
f. After completed the experiments switch off the supply of the apparatus.
 EXPERIMENT NO 6

AIM: To design and implement the 1:4 Demultiplexer using gates.

APPARATUS USED:
Digital trainer kit, 7432 IC, 7404 IC, 74139 and Connecting wires, LEDs, 220Ohm
resistor, Power supply.

THEORY:

De- multiplexer:-
A de-multiplexer is a circuit that has one input and more than one output. A de-
multiplexer is often abbreviated as d-mux. It is used when a circuit wishes to send a
signal to one of many devices. The output line to which the input gets connected
depends on the selection/control lines. This description sounds similar to the
description given for a decoder, but a decoder is used to select among many devices
while a demultiplexer is used to send a signal among many devices.

Each one of them has 2 entries of selection A and B, an input G and 4

exits (Y0 with Y3).

Fig. Demux IC
Procedure:-
1. Connect the supply from the trainer kit through patch chords; also connect circuit
as per circuit diagram.
2. Give input connections at I, and at selection line.
3. Observe the output D0, D1 on the trainer kit through LED’s.
The logic diagram for the de-Multiplexer is given below:-

OBSERVATION:-

The truth table for a Demultiplexer:-

The logic equation for the output can be written as:-

O3= I.S1'.S0'
O2= I.S1'S0
O1= I.S1.S0'
O0 = I.S1.S0

RESULT: The truth table for 1:4 Demultiplexer has been verified.
PRECAUTIONS:
a. All ICs should be checked before starting the experiment.
b. All the connection should be tight.
c. Always connect ground first and then connect Vcc.
d. Suitable type wire should be used for different types of circuit.
e. The kit should be off before change the connections.
f. After completed the experiments switch off the supply of the apparatus.

EXPERIMENT NO 7

AIM: To design and implement the Binary code to BCD converter.

APPARATUS USED:
IC's of Hex-Inverters, 2-input AND, 2-input AND, 2-input XOR gates, IC 74184,
logic trainer kit and connecting leads.

THEORY:

BCD is binary coded decimal number, where each digit of a decimal number is
respected by its equivalent binary number. That means, LSB of a decimal number is
represented by its equivalent binary number and similarly other higher significant
bits of decimal number are also represented by their equivalent binary numbers.

For example, BCD Code of 14 is-

Procedure:
1. Use data sheets to get pins description for the IC are used in the circuit as shown
in the logic diagram.
2. Connect the inputs of the circuit to the corresponding logical switches A, B, C and
D.
3. Connect the outputs of the circuit to the logical LEDs.
4. Connect the ground and Vcc of for all IC's used in the circuit through the logical
trainer kit.

Fig. IC of Binary to BCD Converter

The logic diagram

OBSERVATION:-

The truth table:-

RESULT: The truth table for Binary to BCD converter has been verified.

PRECAUTIONS:
a. All ICs should be checked before starting the experiment.
b. All the connection should be tight.
c. Always connect ground first and then connect Vcc.
d. Suitable type wire should be used for different types of circuit.
e. The kit should be off before change the connections.
f. After completed the experiments switch off the supply of the apparatus.
 EXPERIMENT NO 8

AIM: To design and implement the 2-bit Magnitude Comparator.

APPARATUS USED:
2-input AND, 2-input AND, 2-input XOR gates, Not gates logic trainer kit and
connecting leads.

THEORY:

2-Bit Comparator
A 2-bit comparator compares two binary numbers, each of two bits and produces
their relation such as one number is equal or greater than or less than the other. The
figure below shows the block diagram of a two-bit comparator which has four inputs
and three outputs.

The first number A is designated as A = A1A0 and the second number is designated
as B = B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1,
if A = B) and L (L = 1 if A<B).
Procedure:
1. Use data sheets to get pins description for the IC are used in the circuit as shown
in the logic diagram.
2. Connect the inputs of the circuit to the corresponding logical switches A, B, C and
D.
3. Connect the outputs of the circuit to the logical LEDs.
4. Connect the ground and Vcc of for all IC's used in the circuit through the logical
trainer kit.

The figure below shows the logic diagram of a 2-bit comparator using basic logic
gates. It is also possible to construct this comparator by cascading of two 1-bit
comparators.
OBSERVATION:-

The truth table:-

The logic equation for the output can be written as:-

RESULT: The truth table for 2-bit Magnitude Comparator has been verified.

PRECAUTIONS:
a. All ICs should be checked before starting the experiment.
b. All the connection should be tight.
c. Always connect ground first and then connect Vcc.
d. Suitable type wire should be used for different types of circuit.
e. The kit should be off before change the connections.
f. After completed the experiments switch off the supply of the apparatus.
 EXPERIMENT NO 9

AIM: (a) To verify the truth tables of Flip Flops 7476 (J-K) and 7474 (D)
(b) To design and implement the S-R flip flop using NAND / NOR gates.

APPARATUS USED :
1. Logic Trainer kit.
2. flip flop kit 7476 & 7474,7400&7402
3. Connecting Wires.

CIRCUIT DIAGRAM:
THEORY :

For S-R Flip Flop:

In the SR flip-flop there are two inputs S and R (called Set and Reset), two outputs Q
and Q. The two outputs are complementary, if Q=0, Q=1 and if Q=1, Q=0. The truth
table is as shown in Observation Table No. 1. A low R and high S results in set state,
while high R and low S results in reset state. If both R & S are high the output is
indeterminate. The fig.1 shows the S-R flip-flop using NAND/NOR gates.

For J-K Flip Flop:

The J-K flip-flop is a flip flop with inputs J and K. The uncertainty in the state of an
S-R flip flop when S= R= 1, can be eliminated by converting it into a J-K flip flop.
The data inputs are J and K which are anded with Q & Q respectively to obtain S &
R inputs, i.e. S=J.Q & R=K.Q. A J-K flip flop thus obtained is shown above in figure
2. The truth table has been prepared for all possible combinations of J & K inputs
and is shown as shown in Observation Table No. 2.
For D Flip Flop:
This flip flop stores a 1 or a 0 depending on the data input (D) applied to it. When
the clock is absent, there is no affect on the output if D input is changed. However,
when the clock arrives, a data bit will be stored in the flip flop depending upon the D
input. The truth table is as shown in Observation Table No.3.

PROCEDURE:

For S-R flip flop:

1. Make connections as shown in figure 1 using connecting wires.
2. First use NAND gates and takes reading to verify truth table by giving
different inputs to S and R.
3. Now make connections with NOR gates and take reading and verify the truth
table by giving different inputs to S and R.

For J-K flip flop:

1. Make connections as shown in figure using connecting wires.
2. Verify the truth table by giving different inputs and take the readings.
3. Provide the external input to the IC-7476 clock by connecting 1 Hz square
wave signal.
4. Keep preset and clear input to high, i.e. at logic ‘1’ state one by one and note
the output.
5. Apply the inputs according to the truth table keeping the clock at high position
and giving it a pulse.
6. Note the output carefully. Verify for each input with the theoretical outputs.
For D flip flop:
1. Connect the dotted lines through patch cords i.e. connect three logic inputs to
preset (Pr), clear (Clr) and D inputs of the flip flop. Also connect Q and Q
outputs indication.
2. Connect 1 Hz Clock output to clock ‘clk’ input of flip flop.
3. Switch ON the instrument using ON/OFF toggle switch provided on front
panel.
4. Verify the truth table for various sets of input combinations.

OBSERVATIONS:
Truth tables are as shown:
RESULT:
Design and verification of S-R flip flop, verification of truth tables of J-K and D flip
flop have been done.

PRECAUTIONS:
1. Check the connections before switching on the kit.
2. Connections should be done properly.
3. Observations should be taken properly.

EXPERIMENT NO 10
AIM: To design and implement the Shift Register using D Flip Flops, for various modes: SISO,
SIPO, PISO, PIPO.

APPARATUS USED :
1. Logic Trainer kit.
2. flip flop kit 7474,7400&7402
3. Connecting Wires.

CIRCUIT DIAGRAM:

THEORY:

1. Serial in serial out shift register:-A basic 4-bit shift register can be
constructed using four D flip-flops, as shown in a figure. The register is
first cleared, forcing all four outputs to zero. The input data is then
applied sequentially to the D input of the first flip-flop from the left
(FF0). During each clock pulse, one bit is transmitted from left to right.
The least significant bit (LSB) of the data is the first to be shifted
through the registers i.e. From FF0 to FF3.

2. Serial in parallel out shift register: In this kind of register, data bits are
 entered serially in the same manner as discussed above. The difference
is the way in which the data bits are taken out of the register. Once the
data are stored, each bit appears on its respective output line, and all bits
are available simultaneously. A construction of a 4-bit serial in parallel
out register is shown below.

3. Parallel in serial out shift register: A 4-bit parallel in serial out shift
register is shown below. The circuit uses D flip- flops and NAND gates
for entering or loading data (i.e. writing) to the register.D0, D1, D2 and
D3 are the parallel inputs, where D0 is the most significant bit and D3 is
the least significant bit. To load or write data, the mode control line is
taken LOW and the data is clocked in. The data can be shifted when the
mode control line is HIGH as SHIFT is active high. The register
performs right shift operation on the application of clock pulse.
 4. Parallel in parallel out shift register: The following circuit is a four-bit
Parallel in parallel out shift register constructed by D flip-flops. In case of
parallel in parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits.

Procedure:

1. Connect +5 V adaptors to its indicated position on the trainer board for

power supply but do not switch it ‘ON’.
2. Connect the inputs D1-D3 of 3-bit parallel in serial out shift register
section to I2-I4 of input section.
3. Connect serial data output Q3 to O0 of output section. Toggle it to
any position as you want.
4. Connect the CLK socket using patch cords to socket A of CLK IN.

5. Connect the CLK INH input to I1 of input section. Toggle it to any

position as you want.
6. Connect the SHIFT/LOAD’ input to I0 of input section. Toggle it to logic
1level.
7. Switch ‘ON’ the power supply.
8. Now load whatever input you want (e.g. 011 as per the truth table ) at the
 CHANDIGARH UNIVERSITY,GHARUAN(MOHALI)

four inputs. For this, you have to toggle the switches corresponding to the inputs
D1–D3 at the respective logic levels.
 For serial shift of inputs
9. Toggle the switch corresponding to CLK INH input i.e. I1 to logic 0 level.
10. Toggle the switch corresponding to SHIFT/LOAD’ input i.e. I0 to logic1level.
11. Connect the CLK socket using patch cords to socket A of CLK IN. Give
logic 0 to 1 transitions to CLK input.
12. Observe outputs on LED display of the output section. It will be reverse of what
you had loaded earlier. The LSB or input at D3 will be shifted and displayed first
(i.e. if your input was 011, the output will first display 1, then 1and then 0).
13. Verify the truth table.

OBSERVATIONS:

Truth table is as shown

(Logic 1= +5 V & Logic 0= GND; 0  1 = positive edge trigger)

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RESULT:-Truth table is verified

Precautions:

1. Digital lab kits should be handled with utmost care.

2. While making connections main voltage should be kept switched off.

3. Never touch live and naked wires.

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 CHANDIGARH UNIVERSITY,GHARUAN(MOHALI)

EXPERIMENT NO 11

AIM: To design and implement the 4-bit Asynchronous Counters using J-K Flip Flops.

APPARATUS USED:
1. Logic Trainer kit.
2. flip flop kit 7474,7400&7402
3. Connecting Wires.

CIRCUIT DIAGRAM:

THEORY:

Asynchronous Counter: The events do not have a fixed time relationship with each
other and do not occur at the same time. Counters are classified according to the way they
are clocked. In asynchronous counters, the first flip-flop is clocked by the external clock
pulse and then each successive flip-flop is by clocked the output of the preceding flip-
flop. The main characteristic of an asynchronous counter is each flip-flop derives its own
clock from other flip-flops and is therefore independent of the input clock. Consequently,
the output of each flip-flop may change at different time, hence the term asynchronous.
From the asynchronous counter diagram above, we observed that the output of the first
flip-flop becomes the clock input for the second flip-flop, and the output of the second
flip-flop becomes the clock input for the third flip-flop etc.

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 CHANDIGARH UNIVERSITY,GHARUAN(MOHALI)
Procedure:
1. The external clock is connected to the clock input of the first flip-flop (FF0) only.
So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only
when triggered by the falling edge of the Q output of FF0. Because of the inherent
propagation delay through a flip-flop, the transition of the input clock pulse and a
transition of the Q output of FF0 can never occur at exactly the same time.
Therefore, the flip-flops cannot be triggered simultaneously, producing an
asynchronous operation.

2. Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram
above are shown as simultaneous even though this is an asynchronous counter.
Actually, there is some small delay between the CLK, Q0 and Q1 transitions.

3. Usually, all the CLEAR inputs are connected together, so that a single pulse can
clear all the flip-flops before counting starts. The clock pulse fed into FF0 is
rippled through the other counters after propagation delays, like a ripple on water,
hence the name Ripple Counter.

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 CHANDIGARH UNIVERSITY,GHARUAN(MOHALI)
OBSERVATIONS:
Note that each bit in this four-bit sequence toggles when the bit before it (the bit having a
lesser significance, or place-weight), toggles in a particular direction: from 1 to 0. Small
arrows indicate those points in the sequence where a bit toggles, the head of the arrow
pointing to the previous bit transitioning from a “high” (1) state to a “low” (0) state:-

RESULT:-Truth table is verified

Precautions:

1. Digital lab kits should be handled with utmost care.

2. While making connections main voltage should be kept switched off.

3. Never touch live and naked wires.

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