IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO.

4, APRIL 2012 1023

Effect of Band-to-Band Tunneling

on Junctionless Transistors
Suresh Gundapaneni, Graduate Student Member, IEEE, Mohit Bajaj, Rajan K. Pandey, Member, IEEE,
Kota V. R. M. Murali, Member, IEEE, Swaroop Ganguly, Member, IEEE, and
Anil Kottantharayil, Senior Member, IEEE

Abstract—We evaluate the impact of band-to-band tunneling
(BTBT) on the characteristics of n-channel junctionless transistors
(JLTs). A JLT that has a heavily doped channel, which is fully
depleted in the OFF state, results in a significant band overlap
between the channel and drain regions. This overlap leads to a
large BTBT of electrons from the channel to the drain in n-channel
JLTs. This BTBT leads to a nonnegligible increase in the OFF-state
leakage current, which needs to be understood and alleviated. In
the case of n-channel JLTs, tunneling of electrons from the valence
band of the channel to the conduction band of the drain leaves
behind holes in the channel, which would raise the channel poten-
tial. This triggers a parasitic bipolar junction transistor formed
by the source, channel, and drain regions induced in a JLT in the
OFF state. Tunneling current is observed to be a strong function
of the silicon body thickness and doping of a JLT. We present
guidelines to optimize the device for high ON-to-OFF current ratio.
Finally, we compare the OFF-state leakage of bulk JLTs with that
of silicon-on-insulator JLTs.
Index Terms—Gated resistor, junctionless transistor (JLT),
scaling, tunneling.
I. I NTRODUCTION
EALIZING metallurgical junctions beyond 32-nm node
R for a metal–oxide–semiconductor field-effect transistor
(MOSFET) has become extremely challenging due to the need
of ultrasteep doping profiles [1]. Recently, new kind of device
designs, based on Lilienfeld’s first transistor architecture [2],
which does not have any metallurgical junctions, have been
proposed [3]–[7] and successfully fabricated in silicon [1],
[8], [9]. New JLT designs include nanowire gate-all-around
(GAA) architectures [4], [8], trigated nanowire architectures
with a silicon-on-insulator (SOI) [1], and bulk substrates [5].
Planar JLT architectures on bulk substrates were also proposed
to further simplify the fabrication process [6]. Junctionless
transistors (JLTs) have an ultrathin device layer of a highly
doped semiconductor, which is volume depleted in the OFF state
Manuscript received August 30, 2011; revised November 23, 2011;
accepted January 13, 2012. Date of publication February 17, 2012; date of
current version March 23, 2012. The review of this paper was arranged by
Editor G. Jeong.
S. Gundapaneni is with the Indian Institute of Technology Bombay, Mumbai
400076, India, and also with the IBM Semiconductor Research and Develop-
ment Center, Bangalore 560045, India (e-mail: gunsuresh@ee.iitb.ac.in).
M. Bajaj, R. K. Pandey, and K. V. R. M. Murali are with the IBM Semicon-
ductor Research and Development Center, Bangalore 560045, India.
S. Ganguly and A. Kottantharayil are with the Department of Electrical
Engineering and Centre of Excellence in Nanoelectronics, Indian Institute of
Technology Bombay, Mumbai 400076, India (e-mail: anilkg@ee.iitb.ac.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2185800
(at zero gate bias) due to effective work-function difference
with that of the gate electrode. This results in very low currents
in the OFF state [1]. A positive gate bias forces the JLT layer
to flatband and then into accumulation, resulting in an increase
in the drain-to-source current [1]. The gate of JLT modulates
the resistance of the heavily doped semiconductor; hence, the
device behaves like a gated resistor [1].
Trigate JLTs with channel length of 1 μm were demonstrated
in the case of SOI substrates [1]. Recently, performance of
50- [8] and 26-nm- [10] gate-length JLTs has been reported. p-
channel JLTs on germanium-on-insulator (GeOI) substrates
[11] and n-channel JLTs with poly-Si nanowire channels have
been also reported [9]. It has been shown that a JLT can be
a good candidate for Flash [12], dynamic, and static random
access memory devices [13], [14]. Recent studies have also
include temperature dependence of electrical characteristics
[15], effects of strain on JLT performance [16], ballistic trans-
port at short channel lengths [17], and radio-frequency perfor-
mance analysis [18]. These devices are known to offer several
advantages over the conventional MOSFETs, viz., 1) better
scalability; 2) reduced fabrication process complexity [6];
3) low electric field during the ON state of the device [6]; 4) im-
pact ionization induced sharp subthreshold slope at a drain bias
of 1.5 V, which is better than that of conventional MOSFETs
[19]; and 5) mobility enhancement due to bulk conduction [16].
However, it has been reported that the JLT suffers large thresh-
old voltage variability with channel length and silicon body
thickness, as compared to inversion-mode devices [8], [10].
Although there are many studies that explore the physics of
JLTs [1], [3], the effect of band-to-band tunneling (BTBT) on
their characteristics is yet to be well understood. The current in
the OFF state of a thin-body SOI-MOSFET (due to BTBT) is
known to turn ON the parasitic bipolar junction transistor (BJT)
formed by the source, channel, and drain [20]–[22]. While
BTBT [22]–[24] and parasitic transistor actions in MOSFETs
are well known [20]–[22], these are yet to be understood
in JLTs.
We study, in detail, the OFF-state behavior of JLTs. We
show that the JLT operating in volume depletion in OFF state
has a significant overlap between the valence and conduction
bands in the channel and drain, respectively. As doping of the
source–channel–drain regions of JLT is high, the band overlap
during OFF state triggers tunneling of electrons from the valence
band of the channel to the conduction band of the drain (for n-
channel JLT operation). JLTs with a thicker device layer (or
nanowire diameter of a GAA JLT) make the OFF-state BTBT

0018-9383/$31.00 © 2012 IEEE

1024
Fig. 1. Structure of (a) n-channel JLT and (b) BPJLT.
TABLE I
PARAMETERS USED FOR THE DEVICE SIMULATION
current very high. We show that the OFF-state leakage current is
significantly lower in the bulk planar JLT (BPJLT). We further
carefully investigate the current components in the OFF state
and report the constraints on an optimal design of JLT. Our
analysis explains the OFF-state leakage trends experimentally
observed [8].
II. D EVICE S TRUCTURE AND S IMULATION S ETUP
The device structures of the SOI-JLT and BPJLT used for the
simulations are shown in Fig. 1. Parameters used for the device
simulation of the structures shown in Fig. 1 are listed in Table I.
The models used for the simulations are calibrated against a
long-channel experimentally demonstrated JLT, as described
in [6]. We use a nonlocal BTBT model in Sentaurus release E-
2010.12 [25] that is well calibrated to the experimental data,
and this model is being used in the literature to predict the
performance of tunnel FETs [26]. The nonlocal BTBT model
is included in the simulation to take into account tunneling
along the lateral direction (i.e., tunneling of carriers between
the source, channel, and drain regions) and in the vertical
direction (i.e., tunneling of carriers between the n-type device
layer and the substrate). The direct tunneling model for gate
leakage calculations is turned OFF assuming high-κ metal gate
stack. For thin device layers used in this paper, significant
quantization (due to field and size) can be expected. This can be
modeled as an effective increase in the band gap. The effective
band gap for the ultrathin-body SOI devices simulated here is
obtained from [27]. Band-gap narrowing (BGN) due to high
doping is modeled using Old Slotboom BGN model [25].
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012
Fig. 2. ID–VG plot for a JLT with and without the BTBT model. In addition,
shown is the ID–VG plot when SRH recombination rate is made high in
order to keep the diffusion length of the carriers less than the channel length.
Lg = 20 nm, TSi = 6 nm, Nd = 1019 cm−3, φm = 5.1 eV, Tox = 1 nm,
and VD = 1 V. Carrier lifetimes are set to 10−7 s; these are corresponding to
the lifetimes at a doping of∼1019 cm−3 and are set to 10−15 s for the high
SRH recombination case.
III. OFF-STATE B EHAVIOR OF JLT
While the inversion of the channel in conventional
MOSFETs keeps the channel series resistance low during the
ON state, the JLT operates around flatband during the ON state.
This requires the channel to have a high doping concentration
on the order of 1019 cm−3 to ensure that the series resistance
of the channel is low. While the flatband operation in the ON
state of JLTs has several advantages, the heavily doped channel
needs to be volume depleted in the OFF state. The channel
potential is lowered for the volume depletion to happen; this
results in a large potential barrier between the source and
channel, with band overlap between the channel and drain. On
the other hand, the gate overlap over the drain extension of
inversion-mode MOSFETs has a band bending in the vertical
direction (perpendicular to the channel) [22] and the drain bias
results in a band overlap in the lateral direction (along the
channel) [23], resulting in BTBT current, well known as a
gate-induced drain leakage. However, we show the existence
of BTBT current in the lateral direction for JLTs, i.e., due to the
band overlap between the channel and the drain.
Fig. 2 shows the typical ID–VG characteristics of a 20-nm-
gate-length JLT. We can see that the OFF-state current computed
by taking BTBT into account is several orders higher compared
with the OFF-state current when the BTBT model is absent.
Hence, it is important to minimize the OFF-state current to
obtain high ON-to-OFF ratio. A lateral band diagram of the JLT
at different gate voltages [see Fig. 3(a)] shows a significant
band overlap between the channel and drain regions for gate
voltages less than 0 V. The minimum tunneling width between
the channel and drain regions at VG = 0 V is measured to be
approximately 7 nm. This initiates tunneling of electrons from
the valence band of the channel to the conduction band of the
drain, leaving behind holes in the channel region. However,
from the band diagram in the y-direction [see Fig. 3(b)], at the
point of maximum tunneling rate (i.e., 5 Å away from the drain
and into the channel), shows no band overlap in the vertical
direction. This suggests that BTBT is dominant in the lateral
direction.
GUNDAPANENI et al.: EFFECT OF BTBT ON JUNCTIONLESS TRANSISTORS
Fig. 3. (a) Band diagram in the lateral direction for a JLT at several gate
voltages with the BTBT model included in the simulation. We have included
the band diagram at VG = 0.5
−V when the BTBT model is not included.
(b) Vertical band diagram (in the y-direction) at the point of maximum
tunneling rate (5 Å away from the drain and into the channel). Lg = 20 nm,
TSi = 6 nm, Nd = 1019 cm−3, φm = 5.1 eV, Tox = 1 nm, and VD = 1 V.
Holes generated in the channel because of electrons tunnel-
ing from the channel to the drain are seen to be accumulated in
the channel, as there exists a barrier for holes to flow from the
channel to the source. The hole accumulation in the channel is
illustrated in Fig. 4, where we show the hole concentration in
the channel region of JLT when simulated with and without the
BTBT model at a gate bias of 0 V. We observe a large difference
in the hole concentration in the channel due to tunneling of elec-
trons from the channel to the drain. The band diagrams of the
n-type source, depleted channel, and n-type drain regions look
similar to that of an n-p-n BJT. Hence, we expect a parasitic BJT
action taking place in the lateral direction. Holes accumulated
in the floating-body channel of the JLT lead to a forward bias
at the source–channel junction, which is the emitter–base of the
lateral parasitic n-p-n BJT. The forward-biased source–channel
junction eventually turns ON the parasitic n-p-n BJT, resulting
in a large drain current (collector current of the BJT). Once
the BJT is triggered ON, any further decrease in gate bias will
increase hole concentration and thereby increases the floating-
body potential (observed as a slight downward shift of bands in
Fig. 3(b), when BTBT is included). This saturates the source-
to-channel barrier height and the band overlap between the
channel and drain regions. It is observed, from the lateral band
diagram in Fig. 3, that the BJT is triggered ON at 0 V of gate
bias due to a small tunneling width and further decrease in gate
bias to −0.5 V does not increase the source-to-channel barrier
height. This is reflected in the ID–VG plot (see Fig. 2) as a
1025
Fig. 4. Two-dimensional contour plot for hole concentration in the channel
region when the BTBT model is (a) included and (b) not included.
(c) Schematic representing the parasitic BJT formed in the lateral direction.
Lg = 20 nm, TSi = 6 nm, Nd = 1019 cm−3, φm = 5.1 eV, Tox = 1 nm,
VG = 0 V, and VD = 1 V.
saturating drain current at a gate bias of 0 V and lower. On the
other hand, in simulations without the BTBT model, decreasing
the gate voltage from 0 to −0.5 V would increase the barrier by
∼0.5 V supporting the hole buildup and parasitic BJT model
described above, resulting in an ∼5 order decrease in drain
current.
To further explore the parasitic transistor action, the gain
of the lateral parasitic BJT is reduced by reducing the dif-
fusion length of carriers in silicon i.e., by increasing the
Shockley–Read–Hall (SRH) recombination rate. Lifetime en-
gineering is widely used to obtain fast switching performance
in bipolar power devices [28]. In practice, the carrier lifetime
is lowered by introducing deep levels in silicon; this includes
adding noble metal impurities such as gold or platinum and
low-dose irradiation of electron, proton, or helium in silicon
[28]. In our simulations, the lifetime of carriers is reduced to
10−15 s to shorten the diffusion length of carriers to∼2 nm,
i.e., ∼
10 times shorter than the gate length of the simulated
device. We notice in Fig. 2 that the OFF-state leakage current is
lowered by orders of magnitude when the SRH recombination
rate is high, i.e., OFF-state tunneling is lower when the diffusion
length is shorter than the channel length of JLT.
IV. O PTIMIZATION OF THE ON -TO -OFF RATIO OF JLT
As established in the previous section, BTBT has a large
impact on the OFF-state current for a JLT. A careful design
is essential to achieve a reasonable ION-to-IOFF ratio. In this
section, we discuss various options for reducing the effect of
BTBT current in the OFF-state characteristics.
1026 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012

Fig. 5. ID–VG plot for a JLT with several device layer thicknesses. Lg =
20 nm; TSi = 4, 5, and 6 nm; Nd = 1019 cm−3; φm = 5.1 eV; Tox = 1 nm;
and VD = 1 V.

A. Dependence of OFF-State Current on Channel Thickness

In Fig. 5, we show the ID–VG plot of JLT for device layer
thicknesses (T Si )= 4, 5, and 6 nm. It is observed that the JLT
with thin device layer (TSi) has a higher threshold voltage and
a lower OFF current compared with the device with thicker TSi.
Reduction in OFF current with decreased TSi is due to the fact
that lateral BTBT from the channel to the drain is lower for JLT
with thin device layer. This can be further explained as follows.
Fig. 6. (a) Band diagram along the lateral direction (x-direction, source–
1) The device with a thick TSi has a higher drain-induced channel–drain) of the device taken 5 Å away from the gate dielectric with the
BTBT model included in the simulation. (b) Tunneling width along the channel
barrier lowering (DIBL) at the source/channel edge. It is of the device. (c) Bandgap versus silicon body thickness obtained from [27]. Lg
observed in Fig. 6(a) that the source-to-channel barrier = 20 nm; TSi = 4, 5, and 6 nm; Nd = 1019 cm−3; φm = 5.1 eV; Tox = 1
height at 0 V is lower for the JLT with thicker TSi. This is nm; VD = 1 V; and VG = 0 V.
reflected as a high OFF-state leakage current even without
tunneling. In addition, triggering of the parasitic BJT
would become easier with a lower barrier between the
source and the channel.
2) As the JLT with thick TSi suffers higher drain control
over the channel, the tunneling barrier width between
the channel and the drain would be slightly lower in
comparison to devices with thin TSi. Tunneling width is
measured as a minimum distance between the valence
band maxima at a given point in the channel to the
conduction band minima in the drain. In Fig. 6(b), we
plot the tunneling width versus the distance along the
channel for devices with TSi = 4 and 6 nm. We observe
the tunneling width to be lower by∼1 nm at all points
along the channel for devices with TSi = 6 nm compared Fig. 7. ID–VG plot for a JLT with channel lengths of 20, 50, and 100 nm.
with devices with TSi = 4 nm. TSi = 6 nm, Nd = 1019 cm−3, φm = 5.1 eV, Tox = 1 nm, and VD = 1 V.
3) The higher effective band gap of silicon for extremely
thin silicon films [as shown in Fig. 6(c)], due to energy
B. Dependence of OFF-State Current on the Channel
quantization, results in the reduced BTBT current. Al-
Length of JLT
though this effect is nominal in the range of TSi, as shown
in Fig. 6(a) (∼60 meV increase in effective bandgap for In Fig. 7, we show the ID–VG plot for a JLT with 20-, 50-,
TSi = 4 nm), it will be very important while predicting and 100-nm channel lengths and TSi = 6 nm. We observe that
the OFF-state current of JLTs for TSi < 4 nm. the OFF current is higher for a 20-nm-channel-length JLT when
Our observations of the OFF-state current leakage current compared with that for 50- and 100-nm-channel-length JLTs.
dependence on silicon body thickness could explain the trend The reasons for this are as follows.
reported from experiments [8] (reader may refer to [8]). On 1) For a given TSi, the device with shorter channel length
the other hand, BTBT in the inversion-mode transistor does not suffers higher DIBL in comparison with a long-channel
depend much on silicon body thickness [8], [24]. JLT. It was mentioned in Section IV-A that higher DIBL
GUNDAPANENI et al.: EFFECT OF BTBT ON JUNCTIONLESS TRANSISTORS
Fig. 8. (a) OFF-state current at VG = 0 V. (b) ON-state current at VG =
1 V for a JLT. Lg = 20 nm, TSi = 3 to 8 nm, Nd = 6 × 1018 cm−3 to
5 × 1019 cm−3, φm = 5.1 eV, Tox = 1 nm, and VD = 1 V, with the BTBT
model.
lowers the tunneling width and would facilitate easy turn
ON of the parasitic BJT, hence, a higher OFF current for a
short-channel JLT.
2) In addition to the DIBL effect, a base of the parasitic BJT
is wider for a long-channel JLT. A wider base has more
recombinations happening in it; this results a reduced
gain of the BJT and, hence, a lower OFF current.
For channel lengths up to 1 μm, DIBL would be almost
negligible, and also, the diffusion length comes in comparison
with the channel length. Hence, in a very long channel length
(∼1 μm) device, it is not expected that any parasitic BJT action
takes place [1].
C. Dependence of OFF-State Current on Channel Doping
Fig. 8 shows the OFF current and ION/IOFF as a function
of TSi for several channel dopings. Fully depleting the channel
would be difficult for a thick TSi or for a high channel doping
(Nd); hence, DIBL and BTBT are higher in these cases, leading
to a high OFF-state current [see Fig. 8(b)]. A careful choice
of TSi and Nd should be made for an optimum value of
ON current, OFF current, and their ratio. In Fig. 8(b), we show
the ratio of ON-to-OFF current as a function of TSi and Nd. An
ON-to-OFF ratio of at least on the order of∼104 can be achieved
with Nd of ∼1019 along with a TSi of ∼5 nm. Although
we have shown the channel design space [see Fig. 8(b)] for
a drain voltage of 1 V with normal silicon carrier lifetimes,
reducing the lifetime of carriers or reducing the operating
drain voltage can further increase the room for optimization
of the JLT.
V. OFF-STATE B EHAVIOR OF BPJLT
In this section, we evaluate the OFF-state behavior of the
bulk device that was proposed earlier [6]. In Fig. 9, we show
the ID–VG plot for a typical BPJLT when simulated with and
without the BTBT model included. The device is designed so
that its OFF current is similar to that of the SOI-JLT with TSi =
1027
Fig. 9. ID–VG plot for a BPJLT with and without the tunnel model. Lg =
20 nm; Xj = 12 nm; TSi = 6 nm; Nd = 1019 (1.5 × 1019) cm−3, i.e.,
uniform doping (peak doping) for SOI-JLT (BPJLT); φm = 5.1 eV; Tox =
1 nm; and VD = 1 V.
6 nm (see Fig. 2). We observe that the OFF-state tunneling
leakage dominates the drift–diffusion current approximately at
−0.3 V (this is 1.3 V lower than the flatband voltage). On the
other hand, the BTBT current in the SOI-JLT with TSi = 6 nm
starts to be dominant at +0.1 V (this is 0.9 V lower than the
flatband voltage). This indicates that the tunneling current and,
hence, the parasitic BJT action in the BPJLT are less dominant
than those in the SOI-JLT, i.e., the gain of the parasitic BJT
is less in the BPJLT. The reason for reduced parasitic BJT
action in the BPJLT compared with the SOI-JLT is explained
as follows.
It was explained in Section III that the hole accumulation
in the channel region turns ON the parasitic BJT, increasing
the leakage current. However, in a BPJLT, the holes gen-
erated due to BTBT are also near the depletion region of
the substrate–channel junction. The built-in field of the ver-
tical junction would sweep away the holes to the substrate.
We observe from the schematic of the parasitic BJT shown
in Fig. 4(c) that there is no such provision for the SOI-JLT.
Hence, there would be less accumulation of holes in the
channel region and, hence, the reduced BJT action and re-
duced OFF-state leakage in BPJLT. We show in Fig. 10
the 2-D plot for hole concentration in the channel regions of
SOI-JLT and BPJLT at a gate bias of 0 V. It is observed that
the hole accumulation in the channel of the bulk device is much
lower when compared to its SOI counterpart. We also observe
that the magnitude of current at 0 V of gate bias for BPJLT is
unaffected by the tunneling leakage. Hence, the design space
for BPJLT reported in [6] is still valid when BTBT is taken into
account.
For the JLT to offer a proper switching behavior, the BTBT
in the OFF state needs to be minimized. This can be done either
by reducing the body thickness or the channel doping. While
lower silicon doping offers several advantages such as increased
channel mobility [10] and lower BTBT, the contact resistance
at source and drain will increase due to low doping. On the
other hand, reducing the body thickness demands an extremely
controlled process. Other ways to improve the JLT characteris-
tics include the work-function engineering and recombination
lifetime engineering [28].
1028
Fig. 10. Two-dimensional contour plot for hole concentration in the channel
region of (a) BPJLT and (b) JLT during OFF state. Lg = 20 nm; Xj = 12 nm;
TSi = 6 nm; Nd = 1019 (1.5×1019) cm−3, i.e., uniform doping (peak
doping) for SOI-JLT (BPJLT); φm = 5.1 eV; Tox = 1 nm; and VD = 1 V.
VI. C ONCLUSION
We have evaluated the impact of BTBT on the OFF-state
behavior of SOI-JLT and BPJLT. BTBT current is observed to
be significant in SOI-JLTs due to the high doping in the channel.
A careful device design is necessary to keep the tunneling leak-
age current under control and to achieve a reasonable ON/OFF
ratio of JLT. Various device parameters viz., channel thickness,
channel length, and channel doping, have been evaluated to
optimize the ON-to-OFF ratio of JLTs.
ACKNOWLEDGMENT
A part of this paper was done during the internship of one
of the authors S. Gundapaneni at the Semiconductor Research
and Development Center, IBM India, and a part of this paper
was carried out at the Centre of Excellence in Nanoelectronics,
Indian Institute of Technology Bombay, India.
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GUNDAPANENI et al.: EFFECT OF BTBT ON JUNCTIONLESS TRANSISTORS
Suresh Gundapaneni (S’11) is currently working
toward the Ph.D. degree on the physics of nanoscale
metal–oxide–semiconductor devices at the Indian
Institute of Technology Bombay, Mumbai, India.
Since January 2011, he has been an Intern at
the IBM Semiconductor Research and Development
Center, Bangalore, India.
Mohit Bajaj received the M.S. degree in chemical
engineering from the Indian Institute of Science,
Bangalore, India, in 2002 and Ph.D. degree in
chemical engineering from Monash University,
Melbourne, Australia, in 2006, working on the dy-
namics of polymer molecules in complex flows.
After the postdoctoral research with Monash Uni-
versity, he was with Australian Marine & Offshore
Group Consulting, Melbourne. Currently, he is a
member of the IBM Semiconductor Research and
Development Center, Bangalore, where he is work-
ing on the development of physical models for future-generation comple-
mentary metal–oxide–semiconductor devices and the software development of
semiconductor device simulation tools.
Rajan K. Pandey (M’11) received the M.Sc. degree
in physics from Banaras Hindu University, Varanasi,
India, in 1998 and the Ph.D. degree from the Indian
Institute of Technology Kanpur, Kanpur, India, in
2006, working on the electronic structure of semi-
conductor quantum dots.
After a postdoctoral research at the University of
California, Irvine, he worked with Motorola Labora-
tories, Bangalore, India. In 2008, he joined the IBM
Semiconductor Research and Development Center,
Bangalore, where he is working on multiscale
modeling of next-generation CMOS devices.
1029
Kota V. R. M. Murali (M’11) received the M.S.
and Ph.D. degrees from Massachusetts Institute of
Technology, Cambridge.
He is the Lead Scientist and Senior Manager
of Nanodevice Modeling Group at the IBM
Semiconductor Research and Development Center,
Bangalore, India. He has been a Visitor in IBM
Watson and Almaden Research centers and is also
an Adjunct Faculty Member at the Indian Institute of
Technology Bombay, Mumbai, India. His interests
are in nanoscale and quantum-scale device physics,
and he is currently leading efforts on 22/14 nm and beyond materials and device
modeling.
Swaroop Ganguly (S’00–M’06) received
the B.Tech. degree in electronics and electrical
communication engineering from the Indian Institute
of Technology, Kharagpur, India, in 1999 and the
M.S.E. and Ph.D. degrees from the University
of Texas, Austin, in 2001 and 2005, for work on
complementary metal–oxide–semiconductor source/
drain engineering and semiconductor spintronics,
respectively.
He also worked on device–circuit interaction with
Freescale and on semiconductor spintronics as a
Tokyo Electron Assignee with the Interuniversity Microelectronics Centre.
Since 2009, he has been with the Indian Institute of Technology, Bombay, India,
where he is currently an Assistant Professor. His research interests are in the
physics and the technology of novel devices. His teaching interest is in physical
electronics.
Anil Kottantharayil (M’97–SM’08)
received the B.Tech. degree in electronics
and communication engineering from
Calicut Regional Engineering College,
University of Calicut, Malappuram, India, in
1993, the M.Tech. degree in electrical engineering
from the Indian Institute of Technology Bombay,
Mumbai, India, in 1997, and the Dr.Ing. degree
(summa cum laude) from the Universität der
Bundeswehr, Munich, Germany, in 2002.
From 2001 to 2006, he was with the Interuniver-
sity Microelectronics Centre, Leuven, Belgium, where he worked on FinFETs,
metal gate, and high-κ integration in logic technologies. Since 2006, he
has been with the Department of Electrical Engineering, Indian Institute of
Technology Bombay, where he is currently an Associate Professor. His research
interests are in the areas of novel MOS devices, memory technologies, and
silicon-based solar cells.